projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
[media] au8522 Remove 0x4 bit for register reads
[linux-2.6-block.git] / drivers / media / dvb-frontends / au8522_decoder.c
CommitLineData
968cf782
DH		 1/*
2 * Auvitek AU8522 QAM/8VSB demodulator driver and video decoder
3 *
4 * Copyright (C) 2009 Devin Heitmueller <dheitmueller@linuxtv.org>
5 * Copyright (C) 2005-2008 Auvitek International, Ltd.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * As published by the Free Software Foundation; either version 2
10 * of the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
968cf782
DH		 16 */
17
18/* Developer notes:
19 *
968cf782
DH		 20 * Enough is implemented here for CVBS and S-Video inputs, but the actual
21 * analog demodulator code isn't implemented (not needed for xc5000 since it
22 * has its own demodulator and outputs CVBS)
23 *
24 */
25
26#include <linux/kernel.h>
27#include <linux/slab.h>
28#include <linux/videodev2.h>
29#include <linux/i2c.h>
30#include <linux/delay.h>
31#include <media/v4l2-common.h>
968cf782
DH		 32#include <media/v4l2-device.h>
33#include "au8522.h"
34#include "au8522_priv.h"
35
36MODULE_AUTHOR("Devin Heitmueller");
37MODULE_LICENSE("GPL");
38
39static int au8522_analog_debug;
40
968cf782
DH		 41
42module_param_named(analog_debug, au8522_analog_debug, int, 0644);
43
44MODULE_PARM_DESC(analog_debug,
45 "Analog debugging messages [0=Off (default) 1=On]");
46
968cf782
DH		 47struct au8522_register_config {
48 u16 reg_name;
49 u8 reg_val[8];
50};
51
52
53/* Video Decoder Filter Coefficients
54 The values are as follows from left to right
55 0="ATV RF" 1="ATV RF13" 2="CVBS" 3="S-Video" 4="PAL" 5=CVBS13" 6="SVideo13"
56*/
c86a3c37 57static const struct au8522_register_config filter_coef[] = {
62899a28
DH		 58 {AU8522_FILTER_COEF_R410, {0x25, 0x00, 0x25, 0x25, 0x00, 0x00, 0x00} },
59 {AU8522_FILTER_COEF_R411, {0x20, 0x00, 0x20, 0x20, 0x00, 0x00, 0x00} },
60 {AU8522_FILTER_COEF_R412, {0x03, 0x00, 0x03, 0x03, 0x00, 0x00, 0x00} },
61 {AU8522_FILTER_COEF_R413, {0xe6, 0x00, 0xe6, 0xe6, 0x00, 0x00, 0x00} },
62 {AU8522_FILTER_COEF_R414, {0x40, 0x00, 0x40, 0x40, 0x00, 0x00, 0x00} },
63 {AU8522_FILTER_COEF_R415, {0x1b, 0x00, 0x1b, 0x1b, 0x00, 0x00, 0x00} },
64 {AU8522_FILTER_COEF_R416, {0xc0, 0x00, 0xc0, 0x04, 0x00, 0x00, 0x00} },
65 {AU8522_FILTER_COEF_R417, {0x04, 0x00, 0x04, 0x04, 0x00, 0x00, 0x00} },
66 {AU8522_FILTER_COEF_R418, {0x8c, 0x00, 0x8c, 0x8c, 0x00, 0x00, 0x00} },
67 {AU8522_FILTER_COEF_R419, {0xa0, 0x40, 0xa0, 0xa0, 0x40, 0x40, 0x40} },
68 {AU8522_FILTER_COEF_R41A, {0x21, 0x09, 0x21, 0x21, 0x09, 0x09, 0x09} },
69 {AU8522_FILTER_COEF_R41B, {0x6c, 0x38, 0x6c, 0x6c, 0x38, 0x38, 0x38} },
70 {AU8522_FILTER_COEF_R41C, {0x03, 0xff, 0x03, 0x03, 0xff, 0xff, 0xff} },
71 {AU8522_FILTER_COEF_R41D, {0xbf, 0xc7, 0xbf, 0xbf, 0xc7, 0xc7, 0xc7} },
72 {AU8522_FILTER_COEF_R41E, {0xa0, 0xdf, 0xa0, 0xa0, 0xdf, 0xdf, 0xdf} },
73 {AU8522_FILTER_COEF_R41F, {0x10, 0x06, 0x10, 0x10, 0x06, 0x06, 0x06} },
74 {AU8522_FILTER_COEF_R420, {0xae, 0x30, 0xae, 0xae, 0x30, 0x30, 0x30} },
75 {AU8522_FILTER_COEF_R421, {0xc4, 0x01, 0xc4, 0xc4, 0x01, 0x01, 0x01} },
76 {AU8522_FILTER_COEF_R422, {0x54, 0xdd, 0x54, 0x54, 0xdd, 0xdd, 0xdd} },
77 {AU8522_FILTER_COEF_R423, {0xd0, 0xaf, 0xd0, 0xd0, 0xaf, 0xaf, 0xaf} },
78 {AU8522_FILTER_COEF_R424, {0x1c, 0xf7, 0x1c, 0x1c, 0xf7, 0xf7, 0xf7} },
79 {AU8522_FILTER_COEF_R425, {0x76, 0xdb, 0x76, 0x76, 0xdb, 0xdb, 0xdb} },
80 {AU8522_FILTER_COEF_R426, {0x61, 0xc0, 0x61, 0x61, 0xc0, 0xc0, 0xc0} },
81 {AU8522_FILTER_COEF_R427, {0xd1, 0x2f, 0xd1, 0xd1, 0x2f, 0x2f, 0x2f} },
82 {AU8522_FILTER_COEF_R428, {0x84, 0xd8, 0x84, 0x84, 0xd8, 0xd8, 0xd8} },
83 {AU8522_FILTER_COEF_R429, {0x06, 0xfb, 0x06, 0x06, 0xfb, 0xfb, 0xfb} },
84 {AU8522_FILTER_COEF_R42A, {0x21, 0xd5, 0x21, 0x21, 0xd5, 0xd5, 0xd5} },
85 {AU8522_FILTER_COEF_R42B, {0x0a, 0x3e, 0x0a, 0x0a, 0x3e, 0x3e, 0x3e} },
86 {AU8522_FILTER_COEF_R42C, {0xe6, 0x15, 0xe6, 0xe6, 0x15, 0x15, 0x15} },
87 {AU8522_FILTER_COEF_R42D, {0x01, 0x34, 0x01, 0x01, 0x34, 0x34, 0x34} },
968cf782
DH		 88
89};
62899a28
DH		 90#define NUM_FILTER_COEF (sizeof(filter_coef)\
91 / sizeof(struct au8522_register_config))
968cf782
DH		 92
93
94/* Registers 0x060b through 0x0652 are the LP Filter coefficients
95 The values are as follows from left to right
96 0="SIF" 1="ATVRF/ATVRF13"
97 Note: the "ATVRF/ATVRF13" mode has never been tested
98*/
c86a3c37 99static const struct au8522_register_config lpfilter_coef[] = {
62899a28
DH		 100 {0x060b, {0x21, 0x0b} },
101 {0x060c, {0xad, 0xad} },
102 {0x060d, {0x70, 0xf0} },
103 {0x060e, {0xea, 0xe9} },
104 {0x060f, {0xdd, 0xdd} },
105 {0x0610, {0x08, 0x64} },
106 {0x0611, {0x60, 0x60} },
107 {0x0612, {0xf8, 0xb2} },
108 {0x0613, {0x01, 0x02} },
109 {0x0614, {0xe4, 0xb4} },
110 {0x0615, {0x19, 0x02} },
111 {0x0616, {0xae, 0x2e} },
112 {0x0617, {0xee, 0xc5} },
113 {0x0618, {0x56, 0x56} },
114 {0x0619, {0x30, 0x58} },
115 {0x061a, {0xf9, 0xf8} },
116 {0x061b, {0x24, 0x64} },
117 {0x061c, {0x07, 0x07} },
118 {0x061d, {0x30, 0x30} },
119 {0x061e, {0xa9, 0xed} },
120 {0x061f, {0x09, 0x0b} },
121 {0x0620, {0x42, 0xc2} },
122 {0x0621, {0x1d, 0x2a} },
123 {0x0622, {0xd6, 0x56} },
124 {0x0623, {0x95, 0x8b} },
125 {0x0624, {0x2b, 0x2b} },
126 {0x0625, {0x30, 0x24} },
127 {0x0626, {0x3e, 0x3e} },
128 {0x0627, {0x62, 0xe2} },
129 {0x0628, {0xe9, 0xf5} },
130 {0x0629, {0x99, 0x19} },
131 {0x062a, {0xd4, 0x11} },
132 {0x062b, {0x03, 0x04} },
133 {0x062c, {0xb5, 0x85} },
134 {0x062d, {0x1e, 0x20} },
135 {0x062e, {0x2a, 0xea} },
136 {0x062f, {0xd7, 0xd2} },
137 {0x0630, {0x15, 0x15} },
138 {0x0631, {0xa3, 0xa9} },
139 {0x0632, {0x1f, 0x1f} },
140 {0x0633, {0xf9, 0xd1} },
141 {0x0634, {0xc0, 0xc3} },
142 {0x0635, {0x4d, 0x8d} },
143 {0x0636, {0x21, 0x31} },
144 {0x0637, {0x83, 0x83} },
145 {0x0638, {0x08, 0x8c} },
146 {0x0639, {0x19, 0x19} },
147 {0x063a, {0x45, 0xa5} },
148 {0x063b, {0xef, 0xec} },
149 {0x063c, {0x8a, 0x8a} },
150 {0x063d, {0xf4, 0xf6} },
151 {0x063e, {0x8f, 0x8f} },
152 {0x063f, {0x44, 0x0c} },
153 {0x0640, {0xef, 0xf0} },
154 {0x0641, {0x66, 0x66} },
155 {0x0642, {0xcc, 0xd2} },
156 {0x0643, {0x41, 0x41} },
157 {0x0644, {0x63, 0x93} },
158 {0x0645, {0x8e, 0x8e} },
159 {0x0646, {0xa2, 0x42} },
160 {0x0647, {0x7b, 0x7b} },
161 {0x0648, {0x04, 0x04} },
162 {0x0649, {0x00, 0x00} },
163 {0x064a, {0x40, 0x40} },
164 {0x064b, {0x8c, 0x98} },
165 {0x064c, {0x00, 0x00} },
166 {0x064d, {0x63, 0xc3} },
167 {0x064e, {0x04, 0x04} },
168 {0x064f, {0x20, 0x20} },
169 {0x0650, {0x00, 0x00} },
170 {0x0651, {0x40, 0x40} },
171 {0x0652, {0x01, 0x01} },
968cf782 172};
62899a28
DH		 173#define NUM_LPFILTER_COEF (sizeof(lpfilter_coef)\
174 / sizeof(struct au8522_register_config))
968cf782
DH		 175
176static inline struct au8522_state *to_state(struct v4l2_subdev *sd)
177{
178 return container_of(sd, struct au8522_state, sd);
179}
180
65c88209 181static void setup_decoder_defaults(struct au8522_state *state, bool is_svideo)
968cf782
DH		 182{
183 int i;
184 int filter_coef_type;
185
186 /* Provide reasonable defaults for picture tuning values */
187 au8522_writereg(state, AU8522_TVDEC_SHARPNESSREG009H, 0x07);
188 au8522_writereg(state, AU8522_TVDEC_BRIGHTNESS_REG00AH, 0xed);
968cf782 189 au8522_writereg(state, AU8522_TVDEC_CONTRAST_REG00BH, 0x79);
968cf782
DH		 190 au8522_writereg(state, AU8522_TVDEC_SATURATION_CB_REG00CH, 0x80);
191 au8522_writereg(state, AU8522_TVDEC_SATURATION_CR_REG00DH, 0x80);
192 au8522_writereg(state, AU8522_TVDEC_HUE_H_REG00EH, 0x00);
193 au8522_writereg(state, AU8522_TVDEC_HUE_L_REG00FH, 0x00);
194
195 /* Other decoder registers */
196 au8522_writereg(state, AU8522_TVDEC_INT_MASK_REG010H, 0x00);
197
65c88209 198 if (is_svideo)
968cf782 199 au8522_writereg(state, AU8522_VIDEO_MODE_REG011H, 0x04);
65c88209 200 else
968cf782 201 au8522_writereg(state, AU8522_VIDEO_MODE_REG011H, 0x00);
968cf782
DH		 202
203 au8522_writereg(state, AU8522_TVDEC_PGA_REG012H,
204 AU8522_TVDEC_PGA_REG012H_CVBS);
205 au8522_writereg(state, AU8522_TVDEC_COMB_MODE_REG015H,
206 AU8522_TVDEC_COMB_MODE_REG015H_CVBS);
207 au8522_writereg(state, AU8522_TVDED_DBG_MODE_REG060H,
208 AU8522_TVDED_DBG_MODE_REG060H_CVBS);
f2fd7ce6
MCC		 209
210 if (state->std == V4L2_STD_PAL_M) {
211 au8522_writereg(state, AU8522_TVDEC_FORMAT_CTRL1_REG061H,
212 AU8522_TVDEC_FORMAT_CTRL1_REG061H_FIELD_LEN_525 |
213 AU8522_TVDEC_FORMAT_CTRL1_REG061H_LINE_LEN_63_492 |
214 AU8522_TVDEC_FORMAT_CTRL1_REG061H_SUBCARRIER_NTSC_AUTO);
215 au8522_writereg(state, AU8522_TVDEC_FORMAT_CTRL2_REG062H,
216 AU8522_TVDEC_FORMAT_CTRL2_REG062H_STD_PAL_M);
217 } else {
218 /* NTSC */
219 au8522_writereg(state, AU8522_TVDEC_FORMAT_CTRL1_REG061H,
220 AU8522_TVDEC_FORMAT_CTRL1_REG061H_FIELD_LEN_525 |
221 AU8522_TVDEC_FORMAT_CTRL1_REG061H_LINE_LEN_63_492 |
222 AU8522_TVDEC_FORMAT_CTRL1_REG061H_SUBCARRIER_NTSC_MN);
223 au8522_writereg(state, AU8522_TVDEC_FORMAT_CTRL2_REG062H,
224 AU8522_TVDEC_FORMAT_CTRL2_REG062H_STD_NTSC);
225 }
968cf782
DH		 226 au8522_writereg(state, AU8522_TVDEC_VCR_DET_LLIM_REG063H,
227 AU8522_TVDEC_VCR_DET_LLIM_REG063H_CVBS);
228 au8522_writereg(state, AU8522_TVDEC_VCR_DET_HLIM_REG064H,
229 AU8522_TVDEC_VCR_DET_HLIM_REG064H_CVBS);
230 au8522_writereg(state, AU8522_TVDEC_COMB_VDIF_THR1_REG065H,
231 AU8522_TVDEC_COMB_VDIF_THR1_REG065H_CVBS);
232 au8522_writereg(state, AU8522_TVDEC_COMB_VDIF_THR2_REG066H,
233 AU8522_TVDEC_COMB_VDIF_THR2_REG066H_CVBS);
234 au8522_writereg(state, AU8522_TVDEC_COMB_VDIF_THR3_REG067H,
235 AU8522_TVDEC_COMB_VDIF_THR3_REG067H_CVBS);
236 au8522_writereg(state, AU8522_TVDEC_COMB_NOTCH_THR_REG068H,
237 AU8522_TVDEC_COMB_NOTCH_THR_REG068H_CVBS);
238 au8522_writereg(state, AU8522_TVDEC_COMB_HDIF_THR1_REG069H,
239 AU8522_TVDEC_COMB_HDIF_THR1_REG069H_CVBS);
240 au8522_writereg(state, AU8522_TVDEC_COMB_HDIF_THR2_REG06AH,
241 AU8522_TVDEC_COMB_HDIF_THR2_REG06AH_CVBS);
242 au8522_writereg(state, AU8522_TVDEC_COMB_HDIF_THR3_REG06BH,
243 AU8522_TVDEC_COMB_HDIF_THR3_REG06BH_CVBS);
65c88209 244 if (is_svideo) {
301c9f26
DH		 245 au8522_writereg(state, AU8522_TVDEC_COMB_DCDIF_THR1_REG06CH,
246 AU8522_TVDEC_COMB_DCDIF_THR1_REG06CH_SVIDEO);
247 au8522_writereg(state, AU8522_TVDEC_COMB_DCDIF_THR2_REG06DH,
248 AU8522_TVDEC_COMB_DCDIF_THR2_REG06DH_SVIDEO);
249 } else {
250 au8522_writereg(state, AU8522_TVDEC_COMB_DCDIF_THR1_REG06CH,
251 AU8522_TVDEC_COMB_DCDIF_THR1_REG06CH_CVBS);
252 au8522_writereg(state, AU8522_TVDEC_COMB_DCDIF_THR2_REG06DH,
253 AU8522_TVDEC_COMB_DCDIF_THR2_REG06DH_CVBS);
254 }
968cf782
DH		 255 au8522_writereg(state, AU8522_TVDEC_COMB_DCDIF_THR3_REG06EH,
256 AU8522_TVDEC_COMB_DCDIF_THR3_REG06EH_CVBS);
257 au8522_writereg(state, AU8522_TVDEC_UV_SEP_THR_REG06FH,
258 AU8522_TVDEC_UV_SEP_THR_REG06FH_CVBS);
259 au8522_writereg(state, AU8522_TVDEC_COMB_DC_THR1_NTSC_REG070H,
260 AU8522_TVDEC_COMB_DC_THR1_NTSC_REG070H_CVBS);
261 au8522_writereg(state, AU8522_REG071H, AU8522_REG071H_CVBS);
262 au8522_writereg(state, AU8522_REG072H, AU8522_REG072H_CVBS);
263 au8522_writereg(state, AU8522_TVDEC_COMB_DC_THR2_NTSC_REG073H,
264 AU8522_TVDEC_COMB_DC_THR2_NTSC_REG073H_CVBS);
265 au8522_writereg(state, AU8522_REG074H, AU8522_REG074H_CVBS);
266 au8522_writereg(state, AU8522_REG075H, AU8522_REG075H_CVBS);
267 au8522_writereg(state, AU8522_TVDEC_DCAGC_CTRL_REG077H,
268 AU8522_TVDEC_DCAGC_CTRL_REG077H_CVBS);
269 au8522_writereg(state, AU8522_TVDEC_PIC_START_ADJ_REG078H,
270 AU8522_TVDEC_PIC_START_ADJ_REG078H_CVBS);
271 au8522_writereg(state, AU8522_TVDEC_AGC_HIGH_LIMIT_REG079H,
272 AU8522_TVDEC_AGC_HIGH_LIMIT_REG079H_CVBS);
273 au8522_writereg(state, AU8522_TVDEC_MACROVISION_SYNC_THR_REG07AH,
274 AU8522_TVDEC_MACROVISION_SYNC_THR_REG07AH_CVBS);
275 au8522_writereg(state, AU8522_TVDEC_INTRP_CTRL_REG07BH,
276 AU8522_TVDEC_INTRP_CTRL_REG07BH_CVBS);
277 au8522_writereg(state, AU8522_TVDEC_AGC_LOW_LIMIT_REG0E4H,
278 AU8522_TVDEC_AGC_LOW_LIMIT_REG0E4H_CVBS);
279 au8522_writereg(state, AU8522_TOREGAAGC_REG0E5H,
280 AU8522_TOREGAAGC_REG0E5H_CVBS);
281 au8522_writereg(state, AU8522_REG016H, AU8522_REG016H_CVBS);
282
65c88209 283 if (is_svideo) {
968cf782 284 /* Despite what the table says, for the HVR-950q we still need
af901ca1 285 to be in CVBS mode for the S-Video input (reason unknown). */
968cf782
DH		 286 /* filter_coef_type = 3; */
287 filter_coef_type = 5;
288 } else {
289 filter_coef_type = 5;
290 }
291
292 /* Load the Video Decoder Filter Coefficients */
293 for (i = 0; i < NUM_FILTER_COEF; i++) {
294 au8522_writereg(state, filter_coef[i].reg_name,
295 filter_coef[i].reg_val[filter_coef_type]);
296 }
297
298 /* It's not clear what these registers are for, but they are always
299 set to the same value regardless of what mode we're in */
300 au8522_writereg(state, AU8522_REG42EH, 0x87);
301 au8522_writereg(state, AU8522_REG42FH, 0xa2);
302 au8522_writereg(state, AU8522_REG430H, 0xbf);
303 au8522_writereg(state, AU8522_REG431H, 0xcb);
304 au8522_writereg(state, AU8522_REG432H, 0xa1);
305 au8522_writereg(state, AU8522_REG433H, 0x41);
306 au8522_writereg(state, AU8522_REG434H, 0x88);
307 au8522_writereg(state, AU8522_REG435H, 0xc2);
308 au8522_writereg(state, AU8522_REG436H, 0x3c);
309}
310
36469316 311static void au8522_setup_cvbs_mode(struct au8522_state *state, u8 input_mode)
968cf782
DH		 312{
313 /* here we're going to try the pre-programmed route */
314 au8522_writereg(state, AU8522_MODULE_CLOCK_CONTROL_REG0A3H,
315 AU8522_MODULE_CLOCK_CONTROL_REG0A3H_CVBS);
316
d2c194ce 317 /* PGA in automatic mode */
968cf782 318 au8522_writereg(state, AU8522_PGA_CONTROL_REG082H, 0x00);
d2c194ce
DH		 319
320 /* Enable clamping control */
321 au8522_writereg(state, AU8522_CLAMPING_CONTROL_REG083H, 0x00);
968cf782 322
36469316 323 au8522_writereg(state, AU8522_INPUT_CONTROL_REG081H, input_mode);
968cf782 324
65c88209 325 setup_decoder_defaults(state, false);
968cf782
DH		 326
327 au8522_writereg(state, AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H,
328 AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H_CVBS);
329}
330
36469316
MCC		 331static void au8522_setup_cvbs_tuner_mode(struct au8522_state *state,
332 u8 input_mode)
968cf782
DH		 333{
334 /* here we're going to try the pre-programmed route */
335 au8522_writereg(state, AU8522_MODULE_CLOCK_CONTROL_REG0A3H,
336 AU8522_MODULE_CLOCK_CONTROL_REG0A3H_CVBS);
337
d2c194ce
DH		 338 /* It's not clear why we have to have the PGA in automatic mode while
339 enabling clamp control, but it's what Windows does */
968cf782
DH		 340 au8522_writereg(state, AU8522_PGA_CONTROL_REG082H, 0x00);
341
342 /* Enable clamping control */
343 au8522_writereg(state, AU8522_CLAMPING_CONTROL_REG083H, 0x0e);
344
d2c194ce 345 /* Disable automatic PGA (since the CVBS is coming from the tuner) */
968cf782
DH		 346 au8522_writereg(state, AU8522_PGA_CONTROL_REG082H, 0x10);
347
348 /* Set input mode to CVBS on channel 4 with SIF audio input enabled */
36469316 349 au8522_writereg(state, AU8522_INPUT_CONTROL_REG081H, input_mode);
968cf782 350
65c88209 351 setup_decoder_defaults(state, false);
968cf782
DH		 352
353 au8522_writereg(state, AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H,
354 AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H_CVBS);
355}
356
36469316
MCC		 357static void au8522_setup_svideo_mode(struct au8522_state *state,
358 u8 input_mode)
968cf782
DH		 359{
360 au8522_writereg(state, AU8522_MODULE_CLOCK_CONTROL_REG0A3H,
361 AU8522_MODULE_CLOCK_CONTROL_REG0A3H_SVIDEO);
362
363 /* Set input to Y on Channe1, C on Channel 3 */
36469316 364 au8522_writereg(state, AU8522_INPUT_CONTROL_REG081H, input_mode);
968cf782 365
d2c194ce
DH		 366 /* PGA in automatic mode */
367 au8522_writereg(state, AU8522_PGA_CONTROL_REG082H, 0x00);
368
369 /* Enable clamping control */
968cf782
DH		 370 au8522_writereg(state, AU8522_CLAMPING_CONTROL_REG083H, 0x00);
371
65c88209 372 setup_decoder_defaults(state, true);
968cf782
DH		 373
374 au8522_writereg(state, AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H,
375 AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H_CVBS);
376}
377
378/* ----------------------------------------------------------------------- */
379
380static void disable_audio_input(struct au8522_state *state)
381{
968cf782
DH		 382 au8522_writereg(state, AU8522_AUDIO_VOLUME_L_REG0F2H, 0x00);
383 au8522_writereg(state, AU8522_AUDIO_VOLUME_R_REG0F3H, 0x00);
384 au8522_writereg(state, AU8522_AUDIO_VOLUME_REG0F4H, 0x00);
968cf782
DH		 385
386 au8522_writereg(state, AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H, 0x04);
968cf782
DH		 387 au8522_writereg(state, AU8522_I2S_CTRL_2_REG112H, 0x02);
388
389 au8522_writereg(state, AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H,
2428a2ed 390 AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H_SVIDEO);
968cf782
DH		 391}
392
393/* 0=disable, 1=SIF */
d289cdf0 394static void set_audio_input(struct au8522_state *state)
968cf782 395{
d289cdf0 396 int aud_input = state->aud_input;
968cf782
DH		 397 int i;
398
399 /* Note that this function needs to be used in conjunction with setting
400 the input routing via register 0x81 */
401
402 if (aud_input == AU8522_AUDIO_NONE) {
403 disable_audio_input(state);
404 return;
405 }
406
407 if (aud_input != AU8522_AUDIO_SIF) {
408 /* The caller asked for a mode we don't currently support */
62899a28 409 printk(KERN_ERR "Unsupported audio mode requested! mode=%d\n",
968cf782
DH		 410 aud_input);
411 return;
412 }
413
414 /* Load the Audio Decoder Filter Coefficients */
415 for (i = 0; i < NUM_LPFILTER_COEF; i++) {
416 au8522_writereg(state, lpfilter_coef[i].reg_name,
417 lpfilter_coef[i].reg_val[0]);
418 }
419
427de05c 420 /* Set the volume */
968cf782
DH		 421 au8522_writereg(state, AU8522_AUDIO_VOLUME_L_REG0F2H, 0x7F);
422 au8522_writereg(state, AU8522_AUDIO_VOLUME_R_REG0F3H, 0x7F);
423 au8522_writereg(state, AU8522_AUDIO_VOLUME_REG0F4H, 0xff);
427de05c
DH		 424
425 /* Not sure what this does */
968cf782 426 au8522_writereg(state, AU8522_REG0F9H, AU8522_REG0F9H_AUDIO);
427de05c
DH		 427
428 /* Setup the audio mode to stereo DBX */
968cf782
DH		 429 au8522_writereg(state, AU8522_AUDIO_MODE_REG0F1H, 0x82);
430 msleep(70);
427de05c
DH		 431
432 /* Start the audio processing module */
433 au8522_writereg(state, AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H, 0x9d);
434
435 /* Set the audio frequency to 48 KHz */
968cf782 436 au8522_writereg(state, AU8522_AUDIOFREQ_REG606H, 0x03);
427de05c
DH		 437
438 /* Set the I2S parameters (WS, LSB, mode, sample rate */
968cf782 439 au8522_writereg(state, AU8522_I2S_CTRL_2_REG112H, 0xc2);
427de05c
DH		 440
441 /* Enable the I2S output */
442 au8522_writereg(state, AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H, 0x09);
968cf782
DH		 443}
444
445/* ----------------------------------------------------------------------- */
446
5a4bdb4b 447static int au8522_s_ctrl(struct v4l2_ctrl *ctrl)
968cf782 448{
5a4bdb4b
HV		 449 struct au8522_state *state =
450 container_of(ctrl->handler, struct au8522_state, hdl);
968cf782
DH		 451
452 switch (ctrl->id) {
453 case V4L2_CID_BRIGHTNESS:
968cf782 454 au8522_writereg(state, AU8522_TVDEC_BRIGHTNESS_REG00AH,
5a4bdb4b 455 ctrl->val - 128);
968cf782
DH		 456 break;
457 case V4L2_CID_CONTRAST:
968cf782 458 au8522_writereg(state, AU8522_TVDEC_CONTRAST_REG00BH,
5a4bdb4b 459 ctrl->val);
968cf782
DH		 460 break;
461 case V4L2_CID_SATURATION:
36a91879 462 au8522_writereg(state, AU8522_TVDEC_SATURATION_CB_REG00CH,
5a4bdb4b 463 ctrl->val);
36a91879 464 au8522_writereg(state, AU8522_TVDEC_SATURATION_CR_REG00DH,
5a4bdb4b 465 ctrl->val);
36a91879 466 break;
968cf782 467 case V4L2_CID_HUE:
36a91879 468 au8522_writereg(state, AU8522_TVDEC_HUE_H_REG00EH,
5a4bdb4b 469 ctrl->val >> 8);
36a91879 470 au8522_writereg(state, AU8522_TVDEC_HUE_L_REG00FH,
5a4bdb4b 471 ctrl->val & 0xFF);
36a91879 472 break;
968cf782
DH		 473 default:
474 return -EINVAL;
475 }
476
477 return 0;
478}
479
480/* ----------------------------------------------------------------------- */
481
968cf782
DH		 482#ifdef CONFIG_VIDEO_ADV_DEBUG
483static int au8522_g_register(struct v4l2_subdev *sd,
484 struct v4l2_dbg_register *reg)
485{
968cf782
DH		 486 struct au8522_state *state = to_state(sd);
487
968cf782
DH		 488 reg->val = au8522_readreg(state, reg->reg & 0xffff);
489 return 0;
490}
491
492static int au8522_s_register(struct v4l2_subdev *sd,
977ba3b1 493 const struct v4l2_dbg_register *reg)
968cf782 494{
968cf782
DH		 495 struct au8522_state *state = to_state(sd);
496
968cf782
DH		 497 au8522_writereg(state, reg->reg, reg->val & 0xff);
498 return 0;
499}
500#endif
501
36469316 502static void au8522_video_set(struct au8522_state *state)
36469316
MCC		 503{
504 u8 input_mode;
505
38fe3510 506 au8522_writereg(state, 0xa4, 1 << 5);
36469316
MCC		 507
508 switch (state->vid_input) {
509 case AU8522_COMPOSITE_CH1:
510 input_mode = AU8522_INPUT_CONTROL_REG081H_CVBS_CH1;
511 au8522_setup_cvbs_mode(state, input_mode);
512 break;
513 case AU8522_COMPOSITE_CH2:
514 input_mode = AU8522_INPUT_CONTROL_REG081H_CVBS_CH2;
515 au8522_setup_cvbs_mode(state, input_mode);
516 break;
517 case AU8522_COMPOSITE_CH3:
518 input_mode = AU8522_INPUT_CONTROL_REG081H_CVBS_CH3;
519 au8522_setup_cvbs_mode(state, input_mode);
520 break;
521 case AU8522_COMPOSITE_CH4:
522 input_mode = AU8522_INPUT_CONTROL_REG081H_CVBS_CH4;
523 au8522_setup_cvbs_mode(state, input_mode);
524 break;
525 case AU8522_SVIDEO_CH13:
526 input_mode = AU8522_INPUT_CONTROL_REG081H_SVIDEO_CH13;
527 au8522_setup_svideo_mode(state, input_mode);
528 break;
529 case AU8522_SVIDEO_CH24:
530 input_mode = AU8522_INPUT_CONTROL_REG081H_SVIDEO_CH24;
531 au8522_setup_svideo_mode(state, input_mode);
532 break;
533 default:
534 case AU8522_COMPOSITE_CH4_SIF:
535 input_mode = AU8522_INPUT_CONTROL_REG081H_CVBS_CH4_SIF;
536 au8522_setup_cvbs_tuner_mode(state, input_mode);
537 break;
538 }
539}
540
38fe3510
MCC		 541static int au8522_s_stream(struct v4l2_subdev *sd, int enable)
542{
543 struct au8522_state *state = to_state(sd);
544
545 if (enable) {
38fe3510
MCC		 546 /*
547 * Clear out any state associated with the digital side of the
548 * chip, so that when it gets powered back up it won't think
549 * that it is already tuned
550 */
551 state->current_frequency = 0;
552
553 au8522_writereg(state, AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H,
554 0x01);
c9f5ccc2 555 msleep(10);
38fe3510
MCC		 556
557 au8522_video_set(state);
d289cdf0
MCC		 558 set_audio_input(state);
559
560 state->operational_mode = AU8522_ANALOG_MODE;
38fe3510
MCC		 561 } else {
562 /* This does not completely power down the device
563 (it only reduces it from around 140ma to 80ma) */
564 au8522_writereg(state, AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H,
565 1 << 5);
566 state->operational_mode = AU8522_SUSPEND_MODE;
567 }
568 return 0;
569}
570
968cf782 571static int au8522_s_video_routing(struct v4l2_subdev *sd,
5325b427 572 u32 input, u32 output, u32 config)
968cf782
DH		 573{
574 struct au8522_state *state = to_state(sd);
575
36469316
MCC		 576 switch(input) {
577 case AU8522_COMPOSITE_CH1:
578 case AU8522_SVIDEO_CH13:
579 case AU8522_COMPOSITE_CH4_SIF:
580 state->vid_input = input;
581 break;
582 default:
62899a28 583 printk(KERN_ERR "au8522 mode not currently supported\n");
968cf782
DH		 584 return -EINVAL;
585 }
38fe3510
MCC		 586
587 if (state->operational_mode == AU8522_ANALOG_MODE)
588 au8522_video_set(state);
589
968cf782
DH		 590 return 0;
591}
592
f2fd7ce6
MCC		 593static int au8522_s_std(struct v4l2_subdev *sd, v4l2_std_id std)
594{
595 struct au8522_state *state = to_state(sd);
596
597 if ((std & (V4L2_STD_PAL_M | V4L2_STD_NTSC_M)) == 0)
598 return -EINVAL;
599
600 state->std = std;
601
602 if (state->operational_mode == AU8522_ANALOG_MODE)
603 au8522_video_set(state);
604
605 return 0;
606}
607
968cf782 608static int au8522_s_audio_routing(struct v4l2_subdev *sd,
5325b427 609 u32 input, u32 output, u32 config)
968cf782
DH		 610{
611 struct au8522_state *state = to_state(sd);
d289cdf0
MCC		 612
613 state->aud_input = input;
614
615 if (state->operational_mode == AU8522_ANALOG_MODE)
616 set_audio_input(state);
617
968cf782
DH		 618 return 0;
619}
620
621static int au8522_g_tuner(struct v4l2_subdev *sd, struct v4l2_tuner *vt)
622{
623 int val = 0;
624 struct au8522_state *state = to_state(sd);
625 u8 lock_status;
626
627 /* Interrogate the decoder to see if we are getting a real signal */
628 lock_status = au8522_readreg(state, 0x00);
629 if (lock_status == 0xa2)
d749fb66 630 vt->signal = 0xffff;
968cf782
DH		 631 else
632 vt->signal = 0x00;
633
634 vt->capability |=
635 V4L2_TUNER_CAP_STEREO | V4L2_TUNER_CAP_LANG1 |
636 V4L2_TUNER_CAP_LANG2 | V4L2_TUNER_CAP_SAP;
637
638 val = V4L2_TUNER_SUB_MONO;
639 vt->rxsubchans = val;
640 vt->audmode = V4L2_TUNER_MODE_STEREO;
641 return 0;
642}
643
968cf782
DH		 644/* ----------------------------------------------------------------------- */
645
646static const struct v4l2_subdev_core_ops au8522_core_ops = {
5a4bdb4b 647 .log_status = v4l2_ctrl_subdev_log_status,
968cf782
DH		 648#ifdef CONFIG_VIDEO_ADV_DEBUG
649 .g_register = au8522_g_register,
650 .s_register = au8522_s_register,
651#endif
652};
653
654static const struct v4l2_subdev_tuner_ops au8522_tuner_ops = {
655 .g_tuner = au8522_g_tuner,
656};
657
658static const struct v4l2_subdev_audio_ops au8522_audio_ops = {
659 .s_routing = au8522_s_audio_routing,
660};
661
662static const struct v4l2_subdev_video_ops au8522_video_ops = {
663 .s_routing = au8522_s_video_routing,
968cf782 664 .s_stream = au8522_s_stream,
f2fd7ce6 665 .s_std = au8522_s_std,
968cf782
DH		 666};
667
668static const struct v4l2_subdev_ops au8522_ops = {
669 .core = &au8522_core_ops,
670 .tuner = &au8522_tuner_ops,
671 .audio = &au8522_audio_ops,
672 .video = &au8522_video_ops,
673};
674
5a4bdb4b
HV		 675static const struct v4l2_ctrl_ops au8522_ctrl_ops = {
676 .s_ctrl = au8522_s_ctrl,
677};
678
968cf782
DH		 679/* ----------------------------------------------------------------------- */
680
681static int au8522_probe(struct i2c_client *client,
682 const struct i2c_device_id *did)
683{
684 struct au8522_state *state;
5a4bdb4b 685 struct v4l2_ctrl_handler *hdl;
968cf782
DH		 686 struct v4l2_subdev *sd;
687 int instance;
bed69196
RLLC		 688#ifdef CONFIG_MEDIA_CONTROLLER
689 int ret;
690#endif
968cf782
DH		 691
692 /* Check if the adapter supports the needed features */
693 if (!i2c_check_functionality(client->adapter,
694 I2C_FUNC_SMBUS_BYTE_DATA)) {
695 return -EIO;
696 }
697
698 /* allocate memory for the internal state */
699 instance = au8522_get_state(&state, client->adapter, client->addr);
700 switch (instance) {
701 case 0:
62899a28 702 printk(KERN_ERR "au8522_decoder allocation failed\n");
968cf782
DH		 703 return -EIO;
704 case 1:
705 /* new demod instance */
62899a28 706 printk(KERN_INFO "au8522_decoder creating new instance...\n");
968cf782
DH		 707 break;
708 default:
709 /* existing demod instance */
62899a28 710 printk(KERN_INFO "au8522_decoder attach existing instance.\n");
968cf782
DH		 711 break;
712 }
713
aa37763f 714 state->config.demod_address = 0x8e >> 1;
968cf782
DH		 715 state->i2c = client->adapter;
716
717 sd = &state->sd;
718 v4l2_i2c_subdev_init(sd, client, &au8522_ops);
bed69196
RLLC		 719#if defined(CONFIG_MEDIA_CONTROLLER)
720
bddc4187
MCC		 721 state->pads[DEMOD_PAD_IF_INPUT].flags = MEDIA_PAD_FL_SINK;
722 state->pads[DEMOD_PAD_VID_OUT].flags = MEDIA_PAD_FL_SOURCE;
723 state->pads[DEMOD_PAD_VBI_OUT].flags = MEDIA_PAD_FL_SOURCE;
724 state->pads[DEMOD_PAD_AUDIO_OUT].flags = MEDIA_PAD_FL_SOURCE;
4ca72efa 725 sd->entity.function = MEDIA_ENT_F_ATV_DECODER;
bed69196 726
ab22e77c 727 ret = media_entity_pads_init(&sd->entity, ARRAY_SIZE(state->pads),
18095107 728 state->pads);
bed69196
RLLC		 729 if (ret < 0) {
730 v4l_info(client, "failed to initialize media entity!\n");
731 return ret;
732 }
733#endif
968cf782 734
5a4bdb4b
HV		 735 hdl = &state->hdl;
736 v4l2_ctrl_handler_init(hdl, 4);
737 v4l2_ctrl_new_std(hdl, &au8522_ctrl_ops,
738 V4L2_CID_BRIGHTNESS, 0, 255, 1, 109);
739 v4l2_ctrl_new_std(hdl, &au8522_ctrl_ops,
740 V4L2_CID_CONTRAST, 0, 255, 1,
741 AU8522_TVDEC_CONTRAST_REG00BH_CVBS);
742 v4l2_ctrl_new_std(hdl, &au8522_ctrl_ops,
743 V4L2_CID_SATURATION, 0, 255, 1, 128);
744 v4l2_ctrl_new_std(hdl, &au8522_ctrl_ops,
745 V4L2_CID_HUE, -32768, 32767, 1, 0);
746 sd->ctrl_handler = hdl;
747 if (hdl->error) {
748 int err = hdl->error;
749
750 v4l2_ctrl_handler_free(hdl);
aa37763f 751 au8522_release_state(state);
5a4bdb4b
HV		 752 return err;
753 }
754
968cf782 755 state->c = client;
f2fd7ce6 756 state->std = V4L2_STD_NTSC_M;
968cf782
DH		 757 state->vid_input = AU8522_COMPOSITE_CH1;
758 state->aud_input = AU8522_AUDIO_NONE;
759 state->id = 8522;
760 state->rev = 0;
761
762 /* Jam open the i2c gate to the tuner */
763 au8522_writereg(state, 0x106, 1);
764
765 return 0;
766}
767
768static int au8522_remove(struct i2c_client *client)
769{
770 struct v4l2_subdev *sd = i2c_get_clientdata(client);
771 v4l2_device_unregister_subdev(sd);
5a4bdb4b 772 v4l2_ctrl_handler_free(sd->ctrl_handler);
968cf782
DH		 773 au8522_release_state(to_state(sd));
774 return 0;
775}
776
777static const struct i2c_device_id au8522_id[] = {
778 {"au8522", 0},
779 {}
780};
781
782MODULE_DEVICE_TABLE(i2c, au8522_id);
783
978cff6b
HV		 784static struct i2c_driver au8522_driver = {
785 .driver = {
978cff6b
HV		 786 .name = "au8522",
787 },
788 .probe = au8522_probe,
789 .remove = au8522_remove,
790 .id_table = au8522_id,
968cf782 791};
978cff6b 792
c6e8d86f 793module_i2c_driver(au8522_driver);
Linux 6.x block layer and io_uring tree(s)