[linux-2.6-block.git] / drivers / media / dvb-frontends / as102_fe_types.h

/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
 * Abilis Systems Single DVB-T Receiver
 * Copyright (C) 2008 Pierrick Hascoet <pierrick.hascoet@abilis.com>
 */
#ifndef _AS10X_TYPES_H_
#define _AS10X_TYPES_H_

/*********************************/
/*       MACRO DEFINITIONS       */
/*********************************/

/* bandwidth constant values */
#define BW_5_MHZ		0x00
#define BW_6_MHZ		0x01
#define BW_7_MHZ		0x02
#define BW_8_MHZ		0x03

/* hierarchy priority selection values */
#define HIER_NO_PRIORITY	0x00
#define HIER_LOW_PRIORITY	0x01
#define HIER_HIGH_PRIORITY	0x02

/* constellation available values */
#define CONST_QPSK		0x00
#define CONST_QAM16		0x01
#define CONST_QAM64		0x02
#define CONST_UNKNOWN		0xFF

/* hierarchy available values */
#define HIER_NONE		0x00
#define HIER_ALPHA_1		0x01
#define HIER_ALPHA_2		0x02
#define HIER_ALPHA_4		0x03
#define HIER_UNKNOWN		0xFF

/* interleaving available values */
#define INTLV_NATIVE		0x00
#define INTLV_IN_DEPTH		0x01
#define INTLV_UNKNOWN		0xFF

/* code rate available values */
#define CODE_RATE_1_2		0x00
#define CODE_RATE_2_3		0x01
#define CODE_RATE_3_4		0x02
#define CODE_RATE_5_6		0x03
#define CODE_RATE_7_8		0x04
#define CODE_RATE_UNKNOWN	0xFF

/* guard interval available values */
#define GUARD_INT_1_32		0x00
#define GUARD_INT_1_16		0x01
#define GUARD_INT_1_8		0x02
#define GUARD_INT_1_4		0x03
#define GUARD_UNKNOWN		0xFF

/* transmission mode available values */
#define TRANS_MODE_2K		0x00
#define TRANS_MODE_8K		0x01
#define TRANS_MODE_4K		0x02
#define TRANS_MODE_UNKNOWN	0xFF

/* DVBH signalling available values */
#define TIMESLICING_PRESENT	0x01
#define MPE_FEC_PRESENT		0x02

/* tune state available */
#define TUNE_STATUS_NOT_TUNED		0x00
#define TUNE_STATUS_IDLE		0x01
#define TUNE_STATUS_LOCKING		0x02
#define TUNE_STATUS_SIGNAL_DVB_OK	0x03
#define TUNE_STATUS_STREAM_DETECTED	0x04
#define TUNE_STATUS_STREAM_TUNED	0x05
#define TUNE_STATUS_ERROR		0xFF

/* available TS FID filter types */
#define TS_PID_TYPE_TS		0
#define TS_PID_TYPE_PSI_SI	1
#define TS_PID_TYPE_MPE		2

/* number of echos available */
#define MAX_ECHOS	15

/* Context types */
#define CONTEXT_LNA			1010
#define CONTEXT_ELNA_HYSTERESIS		4003
#define CONTEXT_ELNA_GAIN		4004
#define CONTEXT_MER_THRESHOLD		5005
#define CONTEXT_MER_OFFSET		5006
#define CONTEXT_IR_STATE		7000
#define CONTEXT_TSOUT_MSB_FIRST		7004
#define CONTEXT_TSOUT_FALLING_EDGE	7005

/* Configuration modes */
#define CFG_MODE_ON	0
#define CFG_MODE_OFF	1
#define CFG_MODE_AUTO	2

struct as10x_tps {
	uint8_t modulation;
	uint8_t hierarchy;
	uint8_t interleaving_mode;
	uint8_t code_rate_HP;
	uint8_t code_rate_LP;
	uint8_t guard_interval;
	uint8_t transmission_mode;
	uint8_t DVBH_mask_HP;
	uint8_t DVBH_mask_LP;
	uint16_t cell_ID;
} __packed;

struct as10x_tune_args {
	/* frequency */
	uint32_t freq;
	/* bandwidth */
	uint8_t bandwidth;
	/* hierarchy selection */
	uint8_t hier_select;
	/* constellation */
	uint8_t modulation;
	/* hierarchy */
	uint8_t hierarchy;
	/* interleaving mode */
	uint8_t interleaving_mode;
	/* code rate */
	uint8_t code_rate;
	/* guard interval */
	uint8_t guard_interval;
	/* transmission mode */
	uint8_t transmission_mode;
} __packed;

struct as10x_tune_status {
	/* tune status */
	uint8_t tune_state;
	/* signal strength */
	int16_t signal_strength;
	/* packet error rate 10^-4 */
	uint16_t PER;
	/* bit error rate 10^-4 */
	uint16_t BER;
} __packed;

struct as10x_demod_stats {
	/* frame counter */
	uint32_t frame_count;
	/* Bad frame counter */
	uint32_t bad_frame_count;
	/* Number of wrong bytes fixed by Reed-Solomon */
	uint32_t bytes_fixed_by_rs;
	/* Averaged MER */
	uint16_t mer;
	/* statistics calculation state indicator (started or not) */
	uint8_t has_started;
} __packed;

struct as10x_ts_filter {
	uint16_t pid;  /* valid PID value 0x00 : 0x2000 */
	uint8_t  type; /* Red TS_PID_TYPE_<N> values */
	uint8_t  idx;  /* index in filtering table */
} __packed;

struct as10x_register_value {
	uint8_t mode;
	union {
		uint8_t  value8;   /* 8 bit value */
		uint16_t value16;  /* 16 bit value */
		uint32_t value32;  /* 32 bit value */
	} __packed u;
} __packed;

struct as10x_register_addr {
	/* register addr */
	uint32_t addr;
	/* register mode access */
	uint8_t mode;
};

#endif
Commit	Line	Data
3e0a4e85	1	/* SPDX-License-Identifier: GPL-2.0-or-later */
41b44e04 PH	2	/*
	3	* Abilis Systems Single DVB-T Receiver
	4	* Copyright (C) 2008 Pierrick Hascoet <pierrick.hascoet@abilis.com>
41b44e04 PH	5	*/
	6	#ifndef _AS10X_TYPES_H_
	7	#define _AS10X_TYPES_H_
	8
41b44e04 PH	9	/*********************************/
	10	/* MACRO DEFINITIONS */
	11	/*********************************/
	12
	13	/* bandwidth constant values */
14e0e4bf SN	14	#define BW_5_MHZ 0x00
	15	#define BW_6_MHZ 0x01
	16	#define BW_7_MHZ 0x02
	17	#define BW_8_MHZ 0x03
41b44e04 PH	18
41b44e04 PH	19	/* hierarchy priority selection values */
14e0e4bf SN	20	#define HIER_NO_PRIORITY 0x00
	21	#define HIER_LOW_PRIORITY 0x01
	22	#define HIER_HIGH_PRIORITY 0x02
41b44e04 PH	23
41b44e04 PH	24	/* constellation available values */
14e0e4bf SN	25	#define CONST_QPSK 0x00
	26	#define CONST_QAM16 0x01
	27	#define CONST_QAM64 0x02
	28	#define CONST_UNKNOWN 0xFF
41b44e04 PH	29
41b44e04 PH	30	/* hierarchy available values */
14e0e4bf SN	31	#define HIER_NONE 0x00
	32	#define HIER_ALPHA_1 0x01
	33	#define HIER_ALPHA_2 0x02
	34	#define HIER_ALPHA_4 0x03
	35	#define HIER_UNKNOWN 0xFF
41b44e04 PH	36
41b44e04 PH	37	/* interleaving available values */
14e0e4bf SN	38	#define INTLV_NATIVE 0x00
	39	#define INTLV_IN_DEPTH 0x01
	40	#define INTLV_UNKNOWN 0xFF
41b44e04 PH	41
41b44e04 PH	42	/* code rate available values */
14e0e4bf SN	43	#define CODE_RATE_1_2 0x00
	44	#define CODE_RATE_2_3 0x01
	45	#define CODE_RATE_3_4 0x02
	46	#define CODE_RATE_5_6 0x03
	47	#define CODE_RATE_7_8 0x04
	48	#define CODE_RATE_UNKNOWN 0xFF
41b44e04 PH	49
41b44e04 PH	50	/* guard interval available values */
14e0e4bf SN	51	#define GUARD_INT_1_32 0x00
	52	#define GUARD_INT_1_16 0x01
	53	#define GUARD_INT_1_8 0x02
	54	#define GUARD_INT_1_4 0x03
	55	#define GUARD_UNKNOWN 0xFF
41b44e04 PH	56
41b44e04 PH	57	/* transmission mode available values */
14e0e4bf SN	58	#define TRANS_MODE_2K 0x00
	59	#define TRANS_MODE_8K 0x01
	60	#define TRANS_MODE_4K 0x02
	61	#define TRANS_MODE_UNKNOWN 0xFF
41b44e04 PH	62
41b44e04 PH	63	/* DVBH signalling available values */
14e0e4bf SN	64	#define TIMESLICING_PRESENT 0x01
14e0e4bf SN	65	#define MPE_FEC_PRESENT 0x02
41b44e04 PH	66
41b44e04 PH	67	/* tune state available */
14e0e4bf SN	68	#define TUNE_STATUS_NOT_TUNED 0x00
	69	#define TUNE_STATUS_IDLE 0x01
	70	#define TUNE_STATUS_LOCKING 0x02
	71	#define TUNE_STATUS_SIGNAL_DVB_OK 0x03
	72	#define TUNE_STATUS_STREAM_DETECTED 0x04
	73	#define TUNE_STATUS_STREAM_TUNED 0x05
	74	#define TUNE_STATUS_ERROR 0xFF
41b44e04 PH	75
41b44e04 PH	76	/* available TS FID filter types */
14e0e4bf SN	77	#define TS_PID_TYPE_TS 0
	78	#define TS_PID_TYPE_PSI_SI 1
	79	#define TS_PID_TYPE_MPE 2
41b44e04 PH	80
41b44e04 PH	81	/* number of echos available */
14e0e4bf	82	#define MAX_ECHOS 15
41b44e04 PH	83
41b44e04 PH	84	/* Context types */
14e0e4bf SN	85	#define CONTEXT_LNA 1010
	86	#define CONTEXT_ELNA_HYSTERESIS 4003
	87	#define CONTEXT_ELNA_GAIN 4004
	88	#define CONTEXT_MER_THRESHOLD 5005
	89	#define CONTEXT_MER_OFFSET 5006
	90	#define CONTEXT_IR_STATE 7000
	91	#define CONTEXT_TSOUT_MSB_FIRST 7004
	92	#define CONTEXT_TSOUT_FALLING_EDGE 7005
41b44e04 PH	93
41b44e04 PH	94	/* Configuration modes */
14e0e4bf SN	95	#define CFG_MODE_ON 0
	96	#define CFG_MODE_OFF 1
	97	#define CFG_MODE_AUTO 2
41b44e04	98
41b44e04	99	struct as10x_tps {
dfc64384	100	uint8_t modulation;
14e0e4bf SN	101	uint8_t hierarchy;
	102	uint8_t interleaving_mode;
	103	uint8_t code_rate_HP;
	104	uint8_t code_rate_LP;
	105	uint8_t guard_interval;
	106	uint8_t transmission_mode;
	107	uint8_t DVBH_mask_HP;
	108	uint8_t DVBH_mask_LP;
	109	uint16_t cell_ID;
fa1a13f6	110	} __packed;
41b44e04 PH	111
41b44e04 PH	112	struct as10x_tune_args {
14e0e4bf SN	113	/* frequency */
	114	uint32_t freq;
	115	/* bandwidth */
	116	uint8_t bandwidth;
	117	/* hierarchy selection */
	118	uint8_t hier_select;
	119	/* constellation */
dfc64384	120	uint8_t modulation;
14e0e4bf SN	121	/* hierarchy */
	122	uint8_t hierarchy;
	123	/* interleaving mode */
	124	uint8_t interleaving_mode;
	125	/* code rate */
	126	uint8_t code_rate;
	127	/* guard interval */
	128	uint8_t guard_interval;
	129	/* transmission mode */
	130	uint8_t transmission_mode;
fa1a13f6	131	} __packed;
41b44e04 PH	132
41b44e04 PH	133	struct as10x_tune_status {
14e0e4bf SN	134	/* tune status */
	135	uint8_t tune_state;
	136	/* signal strength */
	137	int16_t signal_strength;
	138	/* packet error rate 10^-4 */
	139	uint16_t PER;
	140	/* bit error rate 10^-4 */
	141	uint16_t BER;
fa1a13f6	142	} __packed;
41b44e04 PH	143
41b44e04 PH	144	struct as10x_demod_stats {
14e0e4bf SN	145	/* frame counter */
	146	uint32_t frame_count;
	147	/* Bad frame counter */
	148	uint32_t bad_frame_count;
	149	/* Number of wrong bytes fixed by Reed-Solomon */
	150	uint32_t bytes_fixed_by_rs;
	151	/* Averaged MER */
	152	uint16_t mer;
	153	/* statistics calculation state indicator (started or not) */
	154	uint8_t has_started;
fa1a13f6	155	} __packed;
41b44e04 PH	156
41b44e04 PH	157	struct as10x_ts_filter {
14e0e4bf SN	158	uint16_t pid; /* valid PID value 0x00 : 0x2000 */
	159	uint8_t type; /* Red TS_PID_TYPE_<N> values */
	160	uint8_t idx; /* index in filtering table */
fa1a13f6	161	} __packed;
41b44e04 PH	162
41b44e04 PH	163	struct as10x_register_value {
14e0e4bf SN	164	uint8_t mode;
	165	union {
	166	uint8_t value8; /* 8 bit value */
	167	uint16_t value16; /* 16 bit value */
	168	uint32_t value32; /* 32 bit value */
abf9d005	169	} __packed u;
fa1a13f6	170	} __packed;
41b44e04 PH	171
41b44e04 PH	172	struct as10x_register_addr {
14e0e4bf SN	173	/* register addr */
	174	uint32_t addr;
	175	/* register mode access */
	176	uint8_t mode;
41b44e04 PH	177	};
41b44e04 PH	178
41b44e04	179	#endif