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[media] af9035: correct demod i2c addresses
[linux-2.6-block.git] / drivers / media / dvb-frontends / af9033.c
CommitLineData
4b64bb26
AP		 1/*
2 * Afatech AF9033 demodulator driver
3 *
4 * Copyright (C) 2009 Antti Palosaari <crope@iki.fi>
5 * Copyright (C) 2012 Antti Palosaari <crope@iki.fi>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
4b64bb26
AP		 16 */
17
18#include "af9033_priv.h"
19
09611caa 20struct af9033_dev {
f5b00a76 21 struct i2c_client *client;
bc85d5e2 22 struct regmap *regmap;
4b64bb26
AP		 23 struct dvb_frontend fe;
24 struct af9033_config cfg;
83f11619
AP		 25 bool is_af9035;
26 bool is_it9135;
4b64bb26
AP		 27
28 u32 bandwidth_hz;
29 bool ts_mode_parallel;
30 bool ts_mode_serial;
47eafa54 31
0df289a2 32 enum fe_status fe_status;
e53c4744 33 u64 post_bit_error_prev; /* for old read_ber we return (curr - prev) */
6bb096c9
AP		 34 u64 post_bit_error;
35 u64 post_bit_count;
204f4319
AP		 36 u64 error_block_count;
37 u64 total_block_count;
4b64bb26
AP		 38};
39
81e19912 40/* Write reg val table using reg addr auto increment */
09611caa 41static int af9033_wr_reg_val_tab(struct af9033_dev *dev,
81e19912 42 const struct reg_val *tab, int tab_len)
3bf5e552 43{
81e19912 44 struct i2c_client *client = dev->client;
d18a88b1 45#define MAX_TAB_LEN 212
3bf5e552 46 int ret, i, j;
d18a88b1
AP		 47 u8 buf[1 + MAX_TAB_LEN];
48
81e19912 49 dev_dbg(&client->dev, "tab_len=%d\n", tab_len);
37ebaf68
MCC		 50
51 if (tab_len > sizeof(buf)) {
81e19912 52 dev_warn(&client->dev, "tab len %d is too big\n", tab_len);
37ebaf68
MCC		 53 return -EINVAL;
54 }
3bf5e552 55
3bf5e552
AP		 56 for (i = 0, j = 0; i < tab_len; i++) {
57 buf[j] = tab[i].val;
58
59 if (i == tab_len - 1 || tab[i].reg != tab[i + 1].reg - 1) {
bc85d5e2
AP		 60 ret = regmap_bulk_write(dev->regmap, tab[i].reg - j,
61 buf, j + 1);
62 if (ret)
3bf5e552
AP		 63 goto err;
64
65 j = 0;
66 } else {
67 j++;
68 }
69 }
70
71 return 0;
3bf5e552 72err:
81e19912 73 dev_dbg(&client->dev, "failed=%d\n", ret);
3bf5e552
AP		 74 return ret;
75}
76
4b64bb26
AP		 77static int af9033_init(struct dvb_frontend *fe)
78{
09611caa 79 struct af9033_dev *dev = fe->demodulator_priv;
81e19912 80 struct i2c_client *client = dev->client;
2db4d179 81 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
4b64bb26 82 int ret, i, len;
c2feb9ff 83 unsigned int utmp;
4b64bb26
AP		 84 const struct reg_val *init;
85 u8 buf[4];
4b64bb26
AP		 86 struct reg_val_mask tab[] = {
87 { 0x80fb24, 0x00, 0x08 },
88 { 0x80004c, 0x00, 0xff },
09611caa 89 { 0x00f641, dev->cfg.tuner, 0xff },
4b64bb26
AP		 90 { 0x80f5ca, 0x01, 0x01 },
91 { 0x80f715, 0x01, 0x01 },
92 { 0x00f41f, 0x04, 0x04 },
93 { 0x00f41a, 0x01, 0x01 },
94 { 0x80f731, 0x00, 0x01 },
95 { 0x00d91e, 0x00, 0x01 },
96 { 0x00d919, 0x00, 0x01 },
97 { 0x80f732, 0x00, 0x01 },
98 { 0x00d91f, 0x00, 0x01 },
99 { 0x00d91a, 0x00, 0x01 },
100 { 0x80f730, 0x00, 0x01 },
101 { 0x80f778, 0x00, 0xff },
102 { 0x80f73c, 0x01, 0x01 },
103 { 0x80f776, 0x00, 0x01 },
104 { 0x00d8fd, 0x01, 0xff },
105 { 0x00d830, 0x01, 0xff },
106 { 0x00d831, 0x00, 0xff },
107 { 0x00d832, 0x00, 0xff },
09611caa
AP		 108 { 0x80f985, dev->ts_mode_serial, 0x01 },
109 { 0x80f986, dev->ts_mode_parallel, 0x01 },
4b64bb26
AP		 110 { 0x00d827, 0x00, 0xff },
111 { 0x00d829, 0x00, 0xff },
09611caa 112 { 0x800045, dev->cfg.adc_multiplier, 0xff },
4b64bb26
AP		 113 };
114
81e19912
AP		 115 dev_dbg(&client->dev, "\n");
116
117 /* Main clk control */
c2feb9ff
AP		 118 utmp = div_u64((u64)dev->cfg.clock * 0x80000, 1000000);
119 buf[0] = (utmp >> 0) & 0xff;
120 buf[1] = (utmp >> 8) & 0xff;
121 buf[2] = (utmp >> 16) & 0xff;
122 buf[3] = (utmp >> 24) & 0xff;
bc85d5e2
AP		 123 ret = regmap_bulk_write(dev->regmap, 0x800025, buf, 4);
124 if (ret)
4b64bb26
AP		 125 goto err;
126
81e19912 127 dev_dbg(&client->dev, "clk=%u clk_cw=%08x\n", dev->cfg.clock, utmp);
c2feb9ff 128
81e19912 129 /* ADC clk control */
4b64bb26 130 for (i = 0; i < ARRAY_SIZE(clock_adc_lut); i++) {
09611caa 131 if (clock_adc_lut[i].clock == dev->cfg.clock)
4b64bb26
AP		 132 break;
133 }
060f79d5 134 if (i == ARRAY_SIZE(clock_adc_lut)) {
81e19912 135 dev_err(&client->dev, "Couldn't find ADC config for clock %d\n",
060f79d5
MCC		 136 dev->cfg.clock);
137 goto err;
138 }
4b64bb26 139
c2feb9ff
AP		 140 utmp = div_u64((u64)clock_adc_lut[i].adc * 0x80000, 1000000);
141 buf[0] = (utmp >> 0) & 0xff;
142 buf[1] = (utmp >> 8) & 0xff;
143 buf[2] = (utmp >> 16) & 0xff;
bc85d5e2
AP		 144 ret = regmap_bulk_write(dev->regmap, 0x80f1cd, buf, 3);
145 if (ret)
4b64bb26
AP		 146 goto err;
147
81e19912 148 dev_dbg(&client->dev, "adc=%u adc_cw=%06x\n",
c2feb9ff
AP		 149 clock_adc_lut[i].adc, utmp);
150
81e19912 151 /* Config register table */
4b64bb26 152 for (i = 0; i < ARRAY_SIZE(tab); i++) {
bc85d5e2
AP		 153 ret = regmap_update_bits(dev->regmap, tab[i].reg, tab[i].mask,
154 tab[i].val);
155 if (ret)
4b64bb26
AP		 156 goto err;
157 }
158
81e19912 159 /* Demod clk output */
09611caa 160 if (dev->cfg.dyn0_clk) {
bc85d5e2
AP		 161 ret = regmap_write(dev->regmap, 0x80fba8, 0x00);
162 if (ret)
9dc0f3fe
AP		 163 goto err;
164 }
165
81e19912 166 /* TS interface */
09611caa 167 if (dev->cfg.ts_mode == AF9033_TS_MODE_USB) {
bc85d5e2
AP		 168 ret = regmap_update_bits(dev->regmap, 0x80f9a5, 0x01, 0x00);
169 if (ret)
4b64bb26 170 goto err;
bc85d5e2
AP		 171 ret = regmap_update_bits(dev->regmap, 0x80f9b5, 0x01, 0x01);
172 if (ret)
4b64bb26
AP		 173 goto err;
174 } else {
bc85d5e2
AP		 175 ret = regmap_update_bits(dev->regmap, 0x80f990, 0x01, 0x00);
176 if (ret)
4b64bb26 177 goto err;
bc85d5e2
AP		 178 ret = regmap_update_bits(dev->regmap, 0x80f9b5, 0x01, 0x00);
179 if (ret)
4b64bb26
AP		 180 goto err;
181 }
182
81e19912
AP		 183 /* Demod core settings */
184 dev_dbg(&client->dev, "load ofsm settings\n");
09611caa 185 switch (dev->cfg.tuner) {
fe8eece1
AP		 186 case AF9033_TUNER_IT9135_38:
187 case AF9033_TUNER_IT9135_51:
188 case AF9033_TUNER_IT9135_52:
463c399c
AP		 189 len = ARRAY_SIZE(ofsm_init_it9135_v1);
190 init = ofsm_init_it9135_v1;
191 break;
fe8eece1
AP		 192 case AF9033_TUNER_IT9135_60:
193 case AF9033_TUNER_IT9135_61:
194 case AF9033_TUNER_IT9135_62:
463c399c
AP		 195 len = ARRAY_SIZE(ofsm_init_it9135_v2);
196 init = ofsm_init_it9135_v2;
fe8eece1
AP		 197 break;
198 default:
199 len = ARRAY_SIZE(ofsm_init);
200 init = ofsm_init;
201 break;
202 }
203
09611caa 204 ret = af9033_wr_reg_val_tab(dev, init, len);
bc85d5e2 205 if (ret)
3bf5e552 206 goto err;
4b64bb26 207
81e19912
AP		 208 /* Demod tuner specific settings */
209 dev_dbg(&client->dev, "load tuner specific settings\n");
09611caa 210 switch (dev->cfg.tuner) {
4b64bb26
AP		 211 case AF9033_TUNER_TUA9001:
212 len = ARRAY_SIZE(tuner_init_tua9001);
213 init = tuner_init_tua9001;
214 break;
ffc501f6
MB		 215 case AF9033_TUNER_FC0011:
216 len = ARRAY_SIZE(tuner_init_fc0011);
217 init = tuner_init_fc0011;
218 break;
540fd4ba
HFV		 219 case AF9033_TUNER_MXL5007T:
220 len = ARRAY_SIZE(tuner_init_mxl5007t);
221 init = tuner_init_mxl5007t;
222 break;
ce1fe379
GG		 223 case AF9033_TUNER_TDA18218:
224 len = ARRAY_SIZE(tuner_init_tda18218);
225 init = tuner_init_tda18218;
226 break;
d67ceb33
OS		 227 case AF9033_TUNER_FC2580:
228 len = ARRAY_SIZE(tuner_init_fc2580);
229 init = tuner_init_fc2580;
230 break;
e713ad15
AP		 231 case AF9033_TUNER_FC0012:
232 len = ARRAY_SIZE(tuner_init_fc0012);
233 init = tuner_init_fc0012;
234 break;
4902bb39 235 case AF9033_TUNER_IT9135_38:
a72cbb77
AP		 236 len = ARRAY_SIZE(tuner_init_it9135_38);
237 init = tuner_init_it9135_38;
238 break;
4902bb39 239 case AF9033_TUNER_IT9135_51:
bb2e12a6
AP		 240 len = ARRAY_SIZE(tuner_init_it9135_51);
241 init = tuner_init_it9135_51;
242 break;
4902bb39 243 case AF9033_TUNER_IT9135_52:
22d729f3
AP		 244 len = ARRAY_SIZE(tuner_init_it9135_52);
245 init = tuner_init_it9135_52;
246 break;
4902bb39 247 case AF9033_TUNER_IT9135_60:
a49f53a0
AP		 248 len = ARRAY_SIZE(tuner_init_it9135_60);
249 init = tuner_init_it9135_60;
250 break;
4902bb39 251 case AF9033_TUNER_IT9135_61:
85211323
AP		 252 len = ARRAY_SIZE(tuner_init_it9135_61);
253 init = tuner_init_it9135_61;
254 break;
4902bb39 255 case AF9033_TUNER_IT9135_62:
dc4a2c40
AP		 256 len = ARRAY_SIZE(tuner_init_it9135_62);
257 init = tuner_init_it9135_62;
4902bb39 258 break;
4b64bb26 259 default:
81e19912
AP		 260 dev_dbg(&client->dev, "unsupported tuner ID=%d\n",
261 dev->cfg.tuner);
4b64bb26
AP		 262 ret = -ENODEV;
263 goto err;
264 }
265
09611caa 266 ret = af9033_wr_reg_val_tab(dev, init, len);
bc85d5e2 267 if (ret)
3bf5e552 268 goto err;
4b64bb26 269
09611caa 270 if (dev->cfg.ts_mode == AF9033_TS_MODE_SERIAL) {
bc85d5e2
AP		 271 ret = regmap_update_bits(dev->regmap, 0x00d91c, 0x01, 0x01);
272 if (ret)
9805992f 273 goto err;
bc85d5e2
AP		 274 ret = regmap_update_bits(dev->regmap, 0x00d917, 0x01, 0x00);
275 if (ret)
9805992f 276 goto err;
bc85d5e2
AP		 277 ret = regmap_update_bits(dev->regmap, 0x00d916, 0x01, 0x00);
278 if (ret)
9805992f
JAR		 279 goto err;
280 }
281
09611caa 282 switch (dev->cfg.tuner) {
086991dd
AP		 283 case AF9033_TUNER_IT9135_60:
284 case AF9033_TUNER_IT9135_61:
285 case AF9033_TUNER_IT9135_62:
bc85d5e2
AP		 286 ret = regmap_write(dev->regmap, 0x800000, 0x01);
287 if (ret)
086991dd
AP		 288 goto err;
289 }
290
81e19912
AP		 291 dev->bandwidth_hz = 0; /* Force to program all parameters */
292 /* Init stats here in order signal app which stats are supported */
2db4d179
AP		 293 c->strength.len = 1;
294 c->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
295 c->cnr.len = 1;
296 c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
297 c->block_count.len = 1;
298 c->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
299 c->block_error.len = 1;
300 c->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
301 c->post_bit_count.len = 1;
302 c->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
303 c->post_bit_error.len = 1;
304 c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
4b64bb26
AP		 305
306 return 0;
4b64bb26 307err:
81e19912 308 dev_dbg(&client->dev, "failed=%d\n", ret);
4b64bb26
AP		 309 return ret;
310}
311
312static int af9033_sleep(struct dvb_frontend *fe)
313{
09611caa 314 struct af9033_dev *dev = fe->demodulator_priv;
81e19912 315 struct i2c_client *client = dev->client;
bc85d5e2
AP		 316 int ret;
317 unsigned int utmp;
4b64bb26 318
81e19912
AP		 319 dev_dbg(&client->dev, "\n");
320
bc85d5e2
AP		 321 ret = regmap_write(dev->regmap, 0x80004c, 0x01);
322 if (ret)
4b64bb26 323 goto err;
bc85d5e2
AP		 324 ret = regmap_write(dev->regmap, 0x800000, 0x00);
325 if (ret)
4b64bb26 326 goto err;
bc85d5e2
AP		 327 ret = regmap_read_poll_timeout(dev->regmap, 0x80004c, utmp, utmp == 0,
328 5000, 1000000);
329 if (ret)
4b64bb26 330 goto err;
bc85d5e2
AP		 331 ret = regmap_update_bits(dev->regmap, 0x80fb24, 0x08, 0x08);
332 if (ret)
4b64bb26
AP		 333 goto err;
334
81e19912 335 /* Prevent current leak by setting TS interface to parallel mode */
09611caa 336 if (dev->cfg.ts_mode == AF9033_TS_MODE_SERIAL) {
81e19912 337 /* Enable parallel TS */
bc85d5e2
AP		 338 ret = regmap_update_bits(dev->regmap, 0x00d917, 0x01, 0x00);
339 if (ret)
4b64bb26 340 goto err;
bc85d5e2
AP		 341 ret = regmap_update_bits(dev->regmap, 0x00d916, 0x01, 0x01);
342 if (ret)
4b64bb26
AP		 343 goto err;
344 }
345
346 return 0;
4b64bb26 347err:
81e19912 348 dev_dbg(&client->dev, "failed=%d\n", ret);
4b64bb26
AP		 349 return ret;
350}
351
352static int af9033_get_tune_settings(struct dvb_frontend *fe,
81e19912 353 struct dvb_frontend_tune_settings *fesettings)
4b64bb26 354{
fe8eece1
AP		 355 /* 800 => 2000 because IT9135 v2 is slow to gain lock */
356 fesettings->min_delay_ms = 2000;
4b64bb26
AP		 357 fesettings->step_size = 0;
358 fesettings->max_drift = 0;
359
360 return 0;
361}
362
363static int af9033_set_frontend(struct dvb_frontend *fe)
364{
09611caa 365 struct af9033_dev *dev = fe->demodulator_priv;
81e19912 366 struct i2c_client *client = dev->client;
4b64bb26 367 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
c2feb9ff
AP		 368 int ret, i;
369 unsigned int utmp, adc_freq;
4b64bb26 370 u8 tmp, buf[3], bandwidth_reg_val;
c2feb9ff 371 u32 if_frequency;
4b64bb26 372
81e19912
AP		 373 dev_dbg(&client->dev, "frequency=%u bandwidth_hz=%u\n",
374 c->frequency, c->bandwidth_hz);
4b64bb26 375
81e19912 376 /* Check bandwidth */
4b64bb26
AP		 377 switch (c->bandwidth_hz) {
378 case 6000000:
379 bandwidth_reg_val = 0x00;
380 break;
381 case 7000000:
382 bandwidth_reg_val = 0x01;
383 break;
384 case 8000000:
385 bandwidth_reg_val = 0x02;
386 break;
387 default:
81e19912 388 dev_dbg(&client->dev, "invalid bandwidth_hz\n");
4b64bb26
AP		 389 ret = -EINVAL;
390 goto err;
391 }
392
81e19912 393 /* Program tuner */
4b64bb26
AP		 394 if (fe->ops.tuner_ops.set_params)
395 fe->ops.tuner_ops.set_params(fe);
396
81e19912 397 /* Coefficients */
09611caa 398 if (c->bandwidth_hz != dev->bandwidth_hz) {
4b64bb26 399 for (i = 0; i < ARRAY_SIZE(coeff_lut); i++) {
09611caa 400 if (coeff_lut[i].clock == dev->cfg.clock &&
81e19912 401 coeff_lut[i].bandwidth_hz == c->bandwidth_hz) {
4b64bb26
AP		 402 break;
403 }
404 }
060f79d5 405 if (i == ARRAY_SIZE(coeff_lut)) {
81e19912
AP		 406 dev_err(&client->dev,
407 "Couldn't find config for clock %u\n",
060f79d5
MCC		 408 dev->cfg.clock);
409 ret = -EINVAL;
410 goto err;
411 }
412
bc85d5e2
AP		 413 ret = regmap_bulk_write(dev->regmap, 0x800001, coeff_lut[i].val,
414 sizeof(coeff_lut[i].val));
415 if (ret)
416 goto err;
4b64bb26
AP		 417 }
418
81e19912 419 /* IF frequency control */
09611caa 420 if (c->bandwidth_hz != dev->bandwidth_hz) {
540fd4ba 421 for (i = 0; i < ARRAY_SIZE(clock_adc_lut); i++) {
09611caa 422 if (clock_adc_lut[i].clock == dev->cfg.clock)
540fd4ba
HFV		 423 break;
424 }
060f79d5 425 if (i == ARRAY_SIZE(clock_adc_lut)) {
81e19912
AP		 426 dev_err(&client->dev,
427 "Couldn't find ADC clock for clock %u\n",
060f79d5
MCC		 428 dev->cfg.clock);
429 ret = -EINVAL;
430 goto err;
431 }
540fd4ba
HFV		 432 adc_freq = clock_adc_lut[i].adc;
433
c2feb9ff
AP		 434 if (dev->cfg.adc_multiplier == AF9033_ADC_MULTIPLIER_2X)
435 adc_freq = 2 * adc_freq;
436
81e19912 437 /* Get used IF frequency */
4b64bb26
AP		 438 if (fe->ops.tuner_ops.get_if_frequency)
439 fe->ops.tuner_ops.get_if_frequency(fe, &if_frequency);
440 else
441 if_frequency = 0;
442
c2feb9ff
AP		 443 utmp = DIV_ROUND_CLOSEST_ULL((u64)if_frequency * 0x800000,
444 adc_freq);
4b64bb26 445
c2feb9ff
AP		 446 if (!dev->cfg.spec_inv && if_frequency)
447 utmp = 0x800000 - utmp;
fe8eece1 448
c2feb9ff
AP		 449 buf[0] = (utmp >> 0) & 0xff;
450 buf[1] = (utmp >> 8) & 0xff;
451 buf[2] = (utmp >> 16) & 0xff;
bc85d5e2
AP		 452 ret = regmap_bulk_write(dev->regmap, 0x800029, buf, 3);
453 if (ret)
4b64bb26
AP		 454 goto err;
455
81e19912 456 dev_dbg(&client->dev, "if_frequency_cw=%06x\n", utmp);
c2feb9ff 457
09611caa 458 dev->bandwidth_hz = c->bandwidth_hz;
4b64bb26
AP		 459 }
460
bc85d5e2
AP		 461 ret = regmap_update_bits(dev->regmap, 0x80f904, 0x03,
462 bandwidth_reg_val);
463 if (ret)
4b64bb26 464 goto err;
bc85d5e2
AP		 465 ret = regmap_write(dev->regmap, 0x800040, 0x00);
466 if (ret)
4b64bb26 467 goto err;
bc85d5e2
AP		 468 ret = regmap_write(dev->regmap, 0x800047, 0x00);
469 if (ret)
4b64bb26 470 goto err;
bc85d5e2
AP		 471 ret = regmap_update_bits(dev->regmap, 0x80f999, 0x01, 0x00);
472 if (ret)
4b64bb26
AP		 473 goto err;
474
475 if (c->frequency <= 230000000)
476 tmp = 0x00; /* VHF */
477 else
478 tmp = 0x01; /* UHF */
479
bc85d5e2
AP		 480 ret = regmap_write(dev->regmap, 0x80004b, tmp);
481 if (ret)
4b64bb26 482 goto err;
81e19912 483 /* Reset FSM */
bc85d5e2
AP		 484 ret = regmap_write(dev->regmap, 0x800000, 0x00);
485 if (ret)
4b64bb26
AP		 486 goto err;
487
488 return 0;
4b64bb26 489err:
81e19912 490 dev_dbg(&client->dev, "failed=%d\n", ret);
4b64bb26
AP		 491 return ret;
492}
493
7e3e68bc
MCC		 494static int af9033_get_frontend(struct dvb_frontend *fe,
495 struct dtv_frontend_properties *c)
0a4df239 496{
09611caa 497 struct af9033_dev *dev = fe->demodulator_priv;
81e19912 498 struct i2c_client *client = dev->client;
0a4df239
GG		 499 int ret;
500 u8 buf[8];
501
81e19912 502 dev_dbg(&client->dev, "\n");
0a4df239 503
81e19912 504 /* Read all needed TPS registers */
bc85d5e2
AP		 505 ret = regmap_bulk_read(dev->regmap, 0x80f900, buf, 8);
506 if (ret)
de7f14fc 507 goto err;
0a4df239
GG		 508
509 switch ((buf[0] >> 0) & 3) {
510 case 0:
de7f14fc 511 c->transmission_mode = TRANSMISSION_MODE_2K;
0a4df239
GG		 512 break;
513 case 1:
de7f14fc 514 c->transmission_mode = TRANSMISSION_MODE_8K;
0a4df239
GG		 515 break;
516 }
517
518 switch ((buf[1] >> 0) & 3) {
519 case 0:
de7f14fc 520 c->guard_interval = GUARD_INTERVAL_1_32;
0a4df239
GG		 521 break;
522 case 1:
de7f14fc 523 c->guard_interval = GUARD_INTERVAL_1_16;
0a4df239
GG		 524 break;
525 case 2:
de7f14fc 526 c->guard_interval = GUARD_INTERVAL_1_8;
0a4df239
GG		 527 break;
528 case 3:
de7f14fc 529 c->guard_interval = GUARD_INTERVAL_1_4;
0a4df239
GG		 530 break;
531 }
532
533 switch ((buf[2] >> 0) & 7) {
534 case 0:
de7f14fc 535 c->hierarchy = HIERARCHY_NONE;
0a4df239
GG		 536 break;
537 case 1:
de7f14fc 538 c->hierarchy = HIERARCHY_1;
0a4df239
GG		 539 break;
540 case 2:
de7f14fc 541 c->hierarchy = HIERARCHY_2;
0a4df239
GG		 542 break;
543 case 3:
de7f14fc 544 c->hierarchy = HIERARCHY_4;
0a4df239
GG		 545 break;
546 }
547
548 switch ((buf[3] >> 0) & 3) {
549 case 0:
de7f14fc 550 c->modulation = QPSK;
0a4df239
GG		 551 break;
552 case 1:
de7f14fc 553 c->modulation = QAM_16;
0a4df239
GG		 554 break;
555 case 2:
de7f14fc 556 c->modulation = QAM_64;
0a4df239
GG		 557 break;
558 }
559
560 switch ((buf[4] >> 0) & 3) {
561 case 0:
de7f14fc 562 c->bandwidth_hz = 6000000;
0a4df239
GG		 563 break;
564 case 1:
de7f14fc 565 c->bandwidth_hz = 7000000;
0a4df239
GG		 566 break;
567 case 2:
de7f14fc 568 c->bandwidth_hz = 8000000;
0a4df239
GG		 569 break;
570 }
571
572 switch ((buf[6] >> 0) & 7) {
573 case 0:
de7f14fc 574 c->code_rate_HP = FEC_1_2;
0a4df239
GG		 575 break;
576 case 1:
de7f14fc 577 c->code_rate_HP = FEC_2_3;
0a4df239
GG		 578 break;
579 case 2:
de7f14fc 580 c->code_rate_HP = FEC_3_4;
0a4df239
GG		 581 break;
582 case 3:
de7f14fc 583 c->code_rate_HP = FEC_5_6;
0a4df239
GG		 584 break;
585 case 4:
de7f14fc 586 c->code_rate_HP = FEC_7_8;
0a4df239
GG		 587 break;
588 case 5:
de7f14fc 589 c->code_rate_HP = FEC_NONE;
0a4df239
GG		 590 break;
591 }
592
593 switch ((buf[7] >> 0) & 7) {
594 case 0:
de7f14fc 595 c->code_rate_LP = FEC_1_2;
0a4df239
GG		 596 break;
597 case 1:
de7f14fc 598 c->code_rate_LP = FEC_2_3;
0a4df239
GG		 599 break;
600 case 2:
de7f14fc 601 c->code_rate_LP = FEC_3_4;
0a4df239
GG		 602 break;
603 case 3:
de7f14fc 604 c->code_rate_LP = FEC_5_6;
0a4df239
GG		 605 break;
606 case 4:
de7f14fc 607 c->code_rate_LP = FEC_7_8;
0a4df239
GG		 608 break;
609 case 5:
de7f14fc 610 c->code_rate_LP = FEC_NONE;
0a4df239
GG		 611 break;
612 }
613
de7f14fc 614 return 0;
de7f14fc 615err:
81e19912 616 dev_dbg(&client->dev, "failed=%d\n", ret);
0a4df239
GG		 617 return ret;
618}
619
0df289a2 620static int af9033_read_status(struct dvb_frontend *fe, enum fe_status *status)
4b64bb26 621{
09611caa 622 struct af9033_dev *dev = fe->demodulator_priv;
81e19912 623 struct i2c_client *client = dev->client;
659a0999 624 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
c93350a6 625 int ret, i, tmp = 0;
bc85d5e2
AP		 626 u8 buf[7];
627 unsigned int utmp;
659a0999 628
81e19912 629 dev_dbg(&client->dev, "\n");
4b64bb26
AP		 630
631 *status = 0;
632
81e19912 633 /* Radio channel status: 0=no result, 1=has signal, 2=no signal */
bc85d5e2
AP		 634 ret = regmap_read(dev->regmap, 0x800047, &utmp);
635 if (ret)
4b64bb26
AP		 636 goto err;
637
81e19912 638 /* Has signal */
bc85d5e2 639 if (utmp == 0x01)
4b64bb26
AP		 640 *status |= FE_HAS_SIGNAL;
641
bc85d5e2 642 if (utmp != 0x02) {
4b64bb26 643 /* TPS lock */
bc85d5e2
AP		 644 ret = regmap_read(dev->regmap, 0x80f5a9, &utmp);
645 if (ret)
4b64bb26
AP		 646 goto err;
647
bc85d5e2 648 if ((utmp >> 0) & 0x01)
4b64bb26
AP		 649 *status |= FE_HAS_SIGNAL | FE_HAS_CARRIER |
650 FE_HAS_VITERBI;
651
81e19912 652 /* Full lock */
bc85d5e2
AP		 653 ret = regmap_read(dev->regmap, 0x80f999, &utmp);
654 if (ret)
4b64bb26
AP		 655 goto err;
656
bc85d5e2 657 if ((utmp >> 0) & 0x01)
4b64bb26
AP		 658 *status |= FE_HAS_SIGNAL | FE_HAS_CARRIER |
659 FE_HAS_VITERBI | FE_HAS_SYNC |
660 FE_HAS_LOCK;
661 }
662
83f11619
AP		 663 dev->fe_status = *status;
664
81e19912 665 /* Signal strength */
659a0999
AP		 666 if (dev->fe_status & FE_HAS_SIGNAL) {
667 if (dev->is_af9035) {
bc85d5e2 668 ret = regmap_read(dev->regmap, 0x80004a, &utmp);
659a0999
AP		 669 if (ret)
670 goto err;
bc85d5e2 671 tmp = -utmp * 1000;
659a0999 672 } else {
bc85d5e2 673 ret = regmap_read(dev->regmap, 0x8000f7, &utmp);
659a0999
AP		 674 if (ret)
675 goto err;
bc85d5e2 676 tmp = (utmp - 100) * 1000;
659a0999
AP		 677 }
678
679 c->strength.len = 1;
680 c->strength.stat[0].scale = FE_SCALE_DECIBEL;
681 c->strength.stat[0].svalue = tmp;
682 } else {
683 c->strength.len = 1;
684 c->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
685 }
686
687 /* CNR */
688 if (dev->fe_status & FE_HAS_VITERBI) {
689 u32 snr_val, snr_lut_size;
c93350a6 690 const struct val_snr *snr_lut = NULL;
659a0999 691
81e19912 692 /* Read raw SNR value */
bc85d5e2 693 ret = regmap_bulk_read(dev->regmap, 0x80002c, buf, 3);
659a0999
AP		 694 if (ret)
695 goto err;
696
697 snr_val = (buf[2] << 16) | (buf[1] << 8) | (buf[0] << 0);
698
81e19912 699 /* Read superframe number */
bc85d5e2 700 ret = regmap_read(dev->regmap, 0x80f78b, &utmp);
659a0999
AP		 701 if (ret)
702 goto err;
703
bc85d5e2
AP		 704 if (utmp)
705 snr_val /= utmp;
659a0999 706
81e19912 707 /* Read current transmission mode */
bc85d5e2 708 ret = regmap_read(dev->regmap, 0x80f900, &utmp);
659a0999
AP		 709 if (ret)
710 goto err;
711
bc85d5e2 712 switch ((utmp >> 0) & 3) {
659a0999
AP		 713 case 0:
714 snr_val *= 4;
715 break;
716 case 1:
717 snr_val *= 1;
718 break;
719 case 2:
720 snr_val *= 2;
721 break;
722 default:
723 snr_val *= 0;
724 break;
725 }
726
81e19912 727 /* Read current modulation */
bc85d5e2 728 ret = regmap_read(dev->regmap, 0x80f903, &utmp);
659a0999
AP		 729 if (ret)
730 goto err;
731
bc85d5e2 732 switch ((utmp >> 0) & 3) {
659a0999
AP		 733 case 0:
734 snr_lut_size = ARRAY_SIZE(qpsk_snr_lut);
735 snr_lut = qpsk_snr_lut;
736 break;
737 case 1:
738 snr_lut_size = ARRAY_SIZE(qam16_snr_lut);
739 snr_lut = qam16_snr_lut;
740 break;
741 case 2:
742 snr_lut_size = ARRAY_SIZE(qam64_snr_lut);
743 snr_lut = qam64_snr_lut;
744 break;
745 default:
746 snr_lut_size = 0;
747 tmp = 0;
748 break;
749 }
750
751 for (i = 0; i < snr_lut_size; i++) {
752 tmp = snr_lut[i].snr * 1000;
753 if (snr_val < snr_lut[i].val)
754 break;
755 }
756
757 c->cnr.len = 1;
758 c->cnr.stat[0].scale = FE_SCALE_DECIBEL;
759 c->cnr.stat[0].svalue = tmp;
760 } else {
761 c->cnr.len = 1;
762 c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
763 }
764
765 /* UCB/PER/BER */
766 if (dev->fe_status & FE_HAS_LOCK) {
81e19912 767 /* Outer FEC, 204 byte packets */
659a0999 768 u16 abort_packet_count, rsd_packet_count;
81e19912 769 /* Inner FEC, bits */
659a0999
AP		 770 u32 rsd_bit_err_count;
771
772 /*
773 * Packet count used for measurement is 10000
774 * (rsd_packet_count). Maybe it should be increased?
775 */
776
bc85d5e2 777 ret = regmap_bulk_read(dev->regmap, 0x800032, buf, 7);
659a0999
AP		 778 if (ret)
779 goto err;
780
781 abort_packet_count = (buf[1] << 8) | (buf[0] << 0);
782 rsd_bit_err_count = (buf[4] << 16) | (buf[3] << 8) | buf[2];
783 rsd_packet_count = (buf[6] << 8) | (buf[5] << 0);
784
785 dev->error_block_count += abort_packet_count;
786 dev->total_block_count += rsd_packet_count;
787 dev->post_bit_error += rsd_bit_err_count;
788 dev->post_bit_count += rsd_packet_count * 204 * 8;
789
790 c->block_count.len = 1;
791 c->block_count.stat[0].scale = FE_SCALE_COUNTER;
792 c->block_count.stat[0].uvalue = dev->total_block_count;
793
794 c->block_error.len = 1;
795 c->block_error.stat[0].scale = FE_SCALE_COUNTER;
796 c->block_error.stat[0].uvalue = dev->error_block_count;
797
798 c->post_bit_count.len = 1;
799 c->post_bit_count.stat[0].scale = FE_SCALE_COUNTER;
800 c->post_bit_count.stat[0].uvalue = dev->post_bit_count;
801
802 c->post_bit_error.len = 1;
803 c->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;
804 c->post_bit_error.stat[0].uvalue = dev->post_bit_error;
805 }
806
4b64bb26 807 return 0;
4b64bb26 808err:
81e19912 809 dev_dbg(&client->dev, "failed=%d\n", ret);
4b64bb26
AP		 810 return ret;
811}
812
813static int af9033_read_snr(struct dvb_frontend *fe, u16 *snr)
814{
09611caa 815 struct af9033_dev *dev = fe->demodulator_priv;
81e19912 816 struct i2c_client *client = dev->client;
6b457786 817 struct dtv_frontend_properties *c = &dev->fe.dtv_property_cache;
6d03f6a8 818 int ret;
bc85d5e2 819 unsigned int utmp;
e898ef62 820
81e19912
AP		 821 dev_dbg(&client->dev, "\n");
822
823 /* Use DVBv5 CNR */
6d03f6a8 824 if (c->cnr.stat[0].scale == FE_SCALE_DECIBEL) {
c3a80cd0
AP		 825 /* Return 0.1 dB for AF9030 and 0-0xffff for IT9130. */
826 if (dev->is_af9035) {
827 /* 1000x => 10x (0.1 dB) */
828 *snr = div_s64(c->cnr.stat[0].svalue, 100);
829 } else {
830 /* 1000x => 1x (1 dB) */
831 *snr = div_s64(c->cnr.stat[0].svalue, 1000);
6d03f6a8 832
81e19912 833 /* Read current modulation */
bc85d5e2 834 ret = regmap_read(dev->regmap, 0x80f903, &utmp);
c3a80cd0
AP		 835 if (ret)
836 goto err;
6d03f6a8 837
c3a80cd0 838 /* scale value to 0x0000-0xffff */
bc85d5e2 839 switch ((utmp >> 0) & 3) {
c3a80cd0
AP		 840 case 0:
841 *snr = *snr * 0xffff / 23;
842 break;
843 case 1:
844 *snr = *snr * 0xffff / 26;
845 break;
846 case 2:
847 *snr = *snr * 0xffff / 32;
848 break;
849 default:
850 goto err;
851 }
6d03f6a8
BC		 852 }
853 } else {
6b457786 854 *snr = 0;
6d03f6a8 855 }
4b64bb26
AP		 856
857 return 0;
6d03f6a8 858err:
81e19912 859 dev_dbg(&client->dev, "failed=%d\n", ret);
6d03f6a8 860 return ret;
4b64bb26
AP		 861}
862
863static int af9033_read_signal_strength(struct dvb_frontend *fe, u16 *strength)
864{
09611caa 865 struct af9033_dev *dev = fe->demodulator_priv;
81e19912 866 struct i2c_client *client = dev->client;
3adec272
BC		 867 struct dtv_frontend_properties *c = &dev->fe.dtv_property_cache;
868 int ret, tmp, power_real;
bc85d5e2
AP		 869 unsigned int utmp;
870 u8 gain_offset, buf[7];
4b64bb26 871
81e19912
AP		 872 dev_dbg(&client->dev, "\n");
873
3adec272 874 if (dev->is_af9035) {
81e19912 875 /* Read signal strength of 0-100 scale */
bc85d5e2
AP		 876 ret = regmap_read(dev->regmap, 0x800048, &utmp);
877 if (ret)
0b0d9628
AP		 878 goto err;
879
81e19912 880 /* Scale value to 0x0000-0xffff */
bc85d5e2 881 *strength = utmp * 0xffff / 100;
3adec272 882 } else {
bc85d5e2
AP		 883 ret = regmap_read(dev->regmap, 0x8000f7, &utmp);
884 if (ret)
1620d221
AP		 885 goto err;
886
bc85d5e2
AP		 887 ret = regmap_bulk_read(dev->regmap, 0x80f900, buf, 7);
888 if (ret)
1620d221 889 goto err;
3adec272
BC		 890
891 if (c->frequency <= 300000000)
892 gain_offset = 7; /* VHF */
893 else
894 gain_offset = 4; /* UHF */
895
bc85d5e2 896 power_real = (utmp - 100 - gain_offset) -
3adec272
BC		 897 power_reference[((buf[3] >> 0) & 3)][((buf[6] >> 0) & 7)];
898
899 if (power_real < -15)
900 tmp = 0;
901 else if ((power_real >= -15) && (power_real < 0))
902 tmp = (2 * (power_real + 15)) / 3;
903 else if ((power_real >= 0) && (power_real < 20))
904 tmp = 4 * power_real + 10;
905 else if ((power_real >= 20) && (power_real < 35))
906 tmp = (2 * (power_real - 20)) / 3 + 90;
907 else
908 tmp = 100;
909
81e19912 910 /* Scale value to 0x0000-0xffff */
3adec272
BC		 911 *strength = tmp * 0xffff / 100;
912 }
4b64bb26 913
4b64bb26 914 return 0;
4b64bb26 915err:
81e19912 916 dev_dbg(&client->dev, "failed=%d\n", ret);
4b64bb26
AP		 917 return ret;
918}
919
920static int af9033_read_ber(struct dvb_frontend *fe, u32 *ber)
921{
09611caa 922 struct af9033_dev *dev = fe->demodulator_priv;
47eafa54 923
e53c4744
AP		 924 *ber = (dev->post_bit_error - dev->post_bit_error_prev);
925 dev->post_bit_error_prev = dev->post_bit_error;
4b64bb26
AP		 926
927 return 0;
928}
929
930static int af9033_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
931{
09611caa 932 struct af9033_dev *dev = fe->demodulator_priv;
4b64bb26 933
1d0ceae4 934 *ucblocks = dev->error_block_count;
81e19912 935
4b64bb26
AP		 936 return 0;
937}
938
939static int af9033_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
940{
09611caa 941 struct af9033_dev *dev = fe->demodulator_priv;
81e19912 942 struct i2c_client *client = dev->client;
4b64bb26
AP		 943 int ret;
944
81e19912 945 dev_dbg(&client->dev, "enable=%d\n", enable);
4b64bb26 946
bc85d5e2
AP		 947 ret = regmap_update_bits(dev->regmap, 0x00fa04, 0x01, enable);
948 if (ret)
4b64bb26
AP		 949 goto err;
950
951 return 0;
4b64bb26 952err:
81e19912 953 dev_dbg(&client->dev, "failed=%d\n", ret);
4b64bb26
AP		 954 return ret;
955}
956
ed97a6fe 957static int af9033_pid_filter_ctrl(struct dvb_frontend *fe, int onoff)
040cf86c 958{
09611caa 959 struct af9033_dev *dev = fe->demodulator_priv;
81e19912 960 struct i2c_client *client = dev->client;
040cf86c
AP		 961 int ret;
962
81e19912 963 dev_dbg(&client->dev, "onoff=%d\n", onoff);
040cf86c 964
bc85d5e2
AP		 965 ret = regmap_update_bits(dev->regmap, 0x80f993, 0x01, onoff);
966 if (ret)
040cf86c
AP		 967 goto err;
968
969 return 0;
040cf86c 970err:
81e19912 971 dev_dbg(&client->dev, "failed=%d\n", ret);
040cf86c
AP		 972 return ret;
973}
040cf86c 974
24e419a0 975static int af9033_pid_filter(struct dvb_frontend *fe, int index, u16 pid,
81e19912 976 int onoff)
040cf86c 977{
09611caa 978 struct af9033_dev *dev = fe->demodulator_priv;
81e19912 979 struct i2c_client *client = dev->client;
040cf86c
AP		 980 int ret;
981 u8 wbuf[2] = {(pid >> 0) & 0xff, (pid >> 8) & 0xff};
982
81e19912
AP		 983 dev_dbg(&client->dev, "index=%d pid=%04x onoff=%d\n",
984 index, pid, onoff);
040cf86c
AP		 985
986 if (pid > 0x1fff)
987 return 0;
988
bc85d5e2
AP		 989 ret = regmap_bulk_write(dev->regmap, 0x80f996, wbuf, 2);
990 if (ret)
040cf86c 991 goto err;
bc85d5e2
AP		 992 ret = regmap_write(dev->regmap, 0x80f994, onoff);
993 if (ret)
040cf86c 994 goto err;
bc85d5e2
AP		 995 ret = regmap_write(dev->regmap, 0x80f995, index);
996 if (ret)
040cf86c
AP		 997 goto err;
998
999 return 0;
040cf86c 1000err:
81e19912 1001 dev_dbg(&client->dev, "failed=%d\n", ret);
040cf86c
AP		 1002 return ret;
1003}
040cf86c 1004
bd336e63 1005static const struct dvb_frontend_ops af9033_ops = {
81e19912 1006 .delsys = {SYS_DVBT},
f5b00a76
AP		 1007 .info = {
1008 .name = "Afatech AF9033 (DVB-T)",
1009 .frequency_min = 174000000,
1010 .frequency_max = 862000000,
1011 .frequency_stepsize = 250000,
1012 .frequency_tolerance = 0,
1013 .caps = FE_CAN_FEC_1_2 |
1014 FE_CAN_FEC_2_3 |
1015 FE_CAN_FEC_3_4 |
1016 FE_CAN_FEC_5_6 |
1017 FE_CAN_FEC_7_8 |
1018 FE_CAN_FEC_AUTO |
1019 FE_CAN_QPSK |
1020 FE_CAN_QAM_16 |
1021 FE_CAN_QAM_64 |
1022 FE_CAN_QAM_AUTO |
1023 FE_CAN_TRANSMISSION_MODE_AUTO |
1024 FE_CAN_GUARD_INTERVAL_AUTO |
1025 FE_CAN_HIERARCHY_AUTO |
1026 FE_CAN_RECOVER |
1027 FE_CAN_MUTE_TS
1028 },
1029
1030 .init = af9033_init,
1031 .sleep = af9033_sleep,
1032
1033 .get_tune_settings = af9033_get_tune_settings,
1034 .set_frontend = af9033_set_frontend,
1035 .get_frontend = af9033_get_frontend,
1036
1037 .read_status = af9033_read_status,
1038 .read_snr = af9033_read_snr,
1039 .read_signal_strength = af9033_read_signal_strength,
1040 .read_ber = af9033_read_ber,
1041 .read_ucblocks = af9033_read_ucblocks,
1042
1043 .i2c_gate_ctrl = af9033_i2c_gate_ctrl,
1044};
4b64bb26 1045
f5b00a76 1046static int af9033_probe(struct i2c_client *client,
81e19912 1047 const struct i2c_device_id *id)
4b64bb26 1048{
f5b00a76 1049 struct af9033_config *cfg = client->dev.platform_data;
09611caa 1050 struct af9033_dev *dev;
f5b00a76 1051 int ret;
4b64bb26 1052 u8 buf[8];
ef5211fd 1053 u32 reg;
bc85d5e2
AP		 1054 static const struct regmap_config regmap_config = {
1055 .reg_bits = 24,
1056 .val_bits = 8,
1057 };
1058
81e19912
AP		 1059 /* Allocate memory for the internal state */
1060 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
1061 if (!dev) {
f5b00a76 1062 ret = -ENOMEM;
4b64bb26 1063 goto err;
f5b00a76 1064 }
4b64bb26 1065
81e19912 1066 /* Setup the state */
f5b00a76 1067 dev->client = client;
81e19912
AP		 1068 memcpy(&dev->cfg, cfg, sizeof(dev->cfg));
1069 switch (dev->cfg.ts_mode) {
1070 case AF9033_TS_MODE_PARALLEL:
1071 dev->ts_mode_parallel = true;
1072 break;
1073 case AF9033_TS_MODE_SERIAL:
1074 dev->ts_mode_serial = true;
1075 break;
1076 case AF9033_TS_MODE_USB:
1077 /* USB mode for AF9035 */
1078 default:
1079 break;
1080 }
4b64bb26 1081
09611caa 1082 if (dev->cfg.clock != 12000000) {
f5b00a76 1083 ret = -ENODEV;
81e19912
AP		 1084 dev_err(&client->dev,
1085 "Unsupported clock %u Hz. Only 12000000 Hz is supported currently\n",
1086 dev->cfg.clock);
f5b00a76 1087 goto err_kfree;
8e8a5ac7
AP		 1088 }
1089
bc85d5e2
AP		 1090 /* Create regmap */
1091 dev->regmap = regmap_init_i2c(client, &regmap_config);
1092 if (IS_ERR(dev->regmap)) {
1093 ret = PTR_ERR(dev->regmap);
1094 goto err_kfree;
1095 }
1096
81e19912 1097 /* Firmware version */
09611caa 1098 switch (dev->cfg.tuner) {
ef5211fd
AP		 1099 case AF9033_TUNER_IT9135_38:
1100 case AF9033_TUNER_IT9135_51:
1101 case AF9033_TUNER_IT9135_52:
1102 case AF9033_TUNER_IT9135_60:
1103 case AF9033_TUNER_IT9135_61:
1104 case AF9033_TUNER_IT9135_62:
83f11619 1105 dev->is_it9135 = true;
ef5211fd
AP		 1106 reg = 0x004bfc;
1107 break;
1108 default:
83f11619 1109 dev->is_af9035 = true;
ef5211fd
AP		 1110 reg = 0x0083e9;
1111 break;
1112 }
1113
bc85d5e2
AP		 1114 ret = regmap_bulk_read(dev->regmap, reg, &buf[0], 4);
1115 if (ret)
1116 goto err_regmap_exit;
1117 ret = regmap_bulk_read(dev->regmap, 0x804191, &buf[4], 4);
1118 if (ret)
1119 goto err_regmap_exit;
4b64bb26 1120
81e19912
AP		 1121 dev_info(&client->dev,
1122 "firmware version: LINK %d.%d.%d.%d - OFDM %d.%d.%d.%d\n",
1123 buf[0], buf[1], buf[2], buf[3],
1124 buf[4], buf[5], buf[6], buf[7]);
4b64bb26 1125
81e19912 1126 /* Sleep as chip seems to be partly active by default */
09611caa 1127 switch (dev->cfg.tuner) {
0c13c54d
AP		 1128 case AF9033_TUNER_IT9135_38:
1129 case AF9033_TUNER_IT9135_51:
1130 case AF9033_TUNER_IT9135_52:
1131 case AF9033_TUNER_IT9135_60:
1132 case AF9033_TUNER_IT9135_61:
1133 case AF9033_TUNER_IT9135_62:
1134 /* IT9135 did not like to sleep at that early */
1135 break;
1136 default:
bc85d5e2
AP		 1137 ret = regmap_write(dev->regmap, 0x80004c, 0x01);
1138 if (ret)
1139 goto err_regmap_exit;
1140 ret = regmap_write(dev->regmap, 0x800000, 0x00);
1141 if (ret)
1142 goto err_regmap_exit;
4902bb39 1143 }
12897dc3 1144
81e19912
AP		 1145 /* Create dvb frontend */
1146 memcpy(&dev->fe.ops, &af9033_ops, sizeof(dev->fe.ops));
09611caa 1147 dev->fe.demodulator_priv = dev;
f5b00a76
AP		 1148 *cfg->fe = &dev->fe;
1149 if (cfg->ops) {
1150 cfg->ops->pid_filter = af9033_pid_filter;
1151 cfg->ops->pid_filter_ctrl = af9033_pid_filter_ctrl;
ed97a6fe 1152 }
3461831a 1153 cfg->regmap = dev->regmap;
f5b00a76 1154 i2c_set_clientdata(client, dev);
ed97a6fe 1155
81e19912
AP		 1156 dev_info(&client->dev, "Afatech AF9033 successfully attached\n");
1157
f5b00a76 1158 return 0;
bc85d5e2
AP		 1159err_regmap_exit:
1160 regmap_exit(dev->regmap);
f5b00a76 1161err_kfree:
09611caa 1162 kfree(dev);
f5b00a76 1163err:
6a087f1f 1164 dev_dbg(&client->dev, "failed=%d\n", ret);
f5b00a76 1165 return ret;
4b64bb26 1166}
4b64bb26 1167
f5b00a76
AP		 1168static int af9033_remove(struct i2c_client *client)
1169{
1170 struct af9033_dev *dev = i2c_get_clientdata(client);
4b64bb26 1171
81e19912 1172 dev_dbg(&client->dev, "\n");
4b64bb26 1173
bc85d5e2 1174 regmap_exit(dev->regmap);
f5b00a76 1175 kfree(dev);
4b64bb26 1176
f5b00a76
AP		 1177 return 0;
1178}
4b64bb26 1179
f5b00a76
AP		 1180static const struct i2c_device_id af9033_id_table[] = {
1181 {"af9033", 0},
1182 {}
1183};
1184MODULE_DEVICE_TABLE(i2c, af9033_id_table);
4b64bb26 1185
f5b00a76
AP		 1186static struct i2c_driver af9033_driver = {
1187 .driver = {
f5b00a76 1188 .name = "af9033",
72812175 1189 .suppress_bind_attrs = true,
f5b00a76
AP		 1190 },
1191 .probe = af9033_probe,
1192 .remove = af9033_remove,
1193 .id_table = af9033_id_table,
4b64bb26
AP		 1194};
1195
f5b00a76
AP		 1196module_i2c_driver(af9033_driver);
1197
4b64bb26
AP		 1198MODULE_AUTHOR("Antti Palosaari <crope@iki.fi>");
1199MODULE_DESCRIPTION("Afatech AF9033 DVB-T demodulator driver");
1200MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)