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Merge tag 'for-linus-5.4-rc1-tag' of git://git.kernel.org/pub/scm/linux/kernel/git...
[linux-2.6-block.git] / drivers / media / dvb-frontends / af9033.c
CommitLineData
c942fddf 1// SPDX-License-Identifier: GPL-2.0-or-later
4b64bb26
AP		 2/*
3 * Afatech AF9033 demodulator driver
4 *
5 * Copyright (C) 2009 Antti Palosaari <crope@iki.fi>
6 * Copyright (C) 2012 Antti Palosaari <crope@iki.fi>
4b64bb26
AP		 7 */
8
9#include "af9033_priv.h"
10
09611caa 11struct af9033_dev {
f5b00a76 12 struct i2c_client *client;
bc85d5e2 13 struct regmap *regmap;
4b64bb26
AP		 14 struct dvb_frontend fe;
15 struct af9033_config cfg;
83f11619
AP		 16 bool is_af9035;
17 bool is_it9135;
4b64bb26
AP		 18
19 u32 bandwidth_hz;
20 bool ts_mode_parallel;
21 bool ts_mode_serial;
47eafa54 22
0df289a2 23 enum fe_status fe_status;
e53c4744 24 u64 post_bit_error_prev; /* for old read_ber we return (curr - prev) */
6bb096c9
AP		 25 u64 post_bit_error;
26 u64 post_bit_count;
204f4319
AP		 27 u64 error_block_count;
28 u64 total_block_count;
4b64bb26
AP		 29};
30
81e19912 31/* Write reg val table using reg addr auto increment */
09611caa 32static int af9033_wr_reg_val_tab(struct af9033_dev *dev,
81e19912 33 const struct reg_val *tab, int tab_len)
3bf5e552 34{
81e19912 35 struct i2c_client *client = dev->client;
d18a88b1 36#define MAX_TAB_LEN 212
3bf5e552 37 int ret, i, j;
d18a88b1
AP		 38 u8 buf[1 + MAX_TAB_LEN];
39
81e19912 40 dev_dbg(&client->dev, "tab_len=%d\n", tab_len);
37ebaf68
MCC		 41
42 if (tab_len > sizeof(buf)) {
81e19912 43 dev_warn(&client->dev, "tab len %d is too big\n", tab_len);
37ebaf68
MCC		 44 return -EINVAL;
45 }
3bf5e552 46
3bf5e552
AP		 47 for (i = 0, j = 0; i < tab_len; i++) {
48 buf[j] = tab[i].val;
49
50 if (i == tab_len - 1 || tab[i].reg != tab[i + 1].reg - 1) {
bc85d5e2
AP		 51 ret = regmap_bulk_write(dev->regmap, tab[i].reg - j,
52 buf, j + 1);
53 if (ret)
3bf5e552
AP		 54 goto err;
55
56 j = 0;
57 } else {
58 j++;
59 }
60 }
61
62 return 0;
3bf5e552 63err:
81e19912 64 dev_dbg(&client->dev, "failed=%d\n", ret);
3bf5e552
AP		 65 return ret;
66}
67
4b64bb26
AP		 68static int af9033_init(struct dvb_frontend *fe)
69{
09611caa 70 struct af9033_dev *dev = fe->demodulator_priv;
81e19912 71 struct i2c_client *client = dev->client;
2db4d179 72 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
4b64bb26 73 int ret, i, len;
c2feb9ff 74 unsigned int utmp;
4b64bb26
AP		 75 const struct reg_val *init;
76 u8 buf[4];
4b64bb26
AP		 77 struct reg_val_mask tab[] = {
78 { 0x80fb24, 0x00, 0x08 },
79 { 0x80004c, 0x00, 0xff },
09611caa 80 { 0x00f641, dev->cfg.tuner, 0xff },
4b64bb26
AP		 81 { 0x80f5ca, 0x01, 0x01 },
82 { 0x80f715, 0x01, 0x01 },
83 { 0x00f41f, 0x04, 0x04 },
84 { 0x00f41a, 0x01, 0x01 },
85 { 0x80f731, 0x00, 0x01 },
86 { 0x00d91e, 0x00, 0x01 },
87 { 0x00d919, 0x00, 0x01 },
88 { 0x80f732, 0x00, 0x01 },
89 { 0x00d91f, 0x00, 0x01 },
90 { 0x00d91a, 0x00, 0x01 },
91 { 0x80f730, 0x00, 0x01 },
92 { 0x80f778, 0x00, 0xff },
93 { 0x80f73c, 0x01, 0x01 },
94 { 0x80f776, 0x00, 0x01 },
95 { 0x00d8fd, 0x01, 0xff },
96 { 0x00d830, 0x01, 0xff },
97 { 0x00d831, 0x00, 0xff },
98 { 0x00d832, 0x00, 0xff },
09611caa
AP		 99 { 0x80f985, dev->ts_mode_serial, 0x01 },
100 { 0x80f986, dev->ts_mode_parallel, 0x01 },
4b64bb26
AP		 101 { 0x00d827, 0x00, 0xff },
102 { 0x00d829, 0x00, 0xff },
09611caa 103 { 0x800045, dev->cfg.adc_multiplier, 0xff },
4b64bb26
AP		 104 };
105
81e19912
AP		 106 dev_dbg(&client->dev, "\n");
107
108 /* Main clk control */
c2feb9ff
AP		 109 utmp = div_u64((u64)dev->cfg.clock * 0x80000, 1000000);
110 buf[0] = (utmp >> 0) & 0xff;
111 buf[1] = (utmp >> 8) & 0xff;
112 buf[2] = (utmp >> 16) & 0xff;
113 buf[3] = (utmp >> 24) & 0xff;
bc85d5e2
AP		 114 ret = regmap_bulk_write(dev->regmap, 0x800025, buf, 4);
115 if (ret)
4b64bb26
AP		 116 goto err;
117
81e19912 118 dev_dbg(&client->dev, "clk=%u clk_cw=%08x\n", dev->cfg.clock, utmp);
c2feb9ff 119
81e19912 120 /* ADC clk control */
4b64bb26 121 for (i = 0; i < ARRAY_SIZE(clock_adc_lut); i++) {
09611caa 122 if (clock_adc_lut[i].clock == dev->cfg.clock)
4b64bb26
AP		 123 break;
124 }
060f79d5 125 if (i == ARRAY_SIZE(clock_adc_lut)) {
81e19912 126 dev_err(&client->dev, "Couldn't find ADC config for clock %d\n",
060f79d5
MCC		 127 dev->cfg.clock);
128 goto err;
129 }
4b64bb26 130
c2feb9ff
AP		 131 utmp = div_u64((u64)clock_adc_lut[i].adc * 0x80000, 1000000);
132 buf[0] = (utmp >> 0) & 0xff;
133 buf[1] = (utmp >> 8) & 0xff;
134 buf[2] = (utmp >> 16) & 0xff;
bc85d5e2
AP		 135 ret = regmap_bulk_write(dev->regmap, 0x80f1cd, buf, 3);
136 if (ret)
4b64bb26
AP		 137 goto err;
138
81e19912 139 dev_dbg(&client->dev, "adc=%u adc_cw=%06x\n",
c2feb9ff
AP		 140 clock_adc_lut[i].adc, utmp);
141
81e19912 142 /* Config register table */
4b64bb26 143 for (i = 0; i < ARRAY_SIZE(tab); i++) {
bc85d5e2
AP		 144 ret = regmap_update_bits(dev->regmap, tab[i].reg, tab[i].mask,
145 tab[i].val);
146 if (ret)
4b64bb26
AP		 147 goto err;
148 }
149
81e19912 150 /* Demod clk output */
09611caa 151 if (dev->cfg.dyn0_clk) {
bc85d5e2
AP		 152 ret = regmap_write(dev->regmap, 0x80fba8, 0x00);
153 if (ret)
9dc0f3fe
AP		 154 goto err;
155 }
156
81e19912 157 /* TS interface */
09611caa 158 if (dev->cfg.ts_mode == AF9033_TS_MODE_USB) {
bc85d5e2
AP		 159 ret = regmap_update_bits(dev->regmap, 0x80f9a5, 0x01, 0x00);
160 if (ret)
4b64bb26 161 goto err;
bc85d5e2
AP		 162 ret = regmap_update_bits(dev->regmap, 0x80f9b5, 0x01, 0x01);
163 if (ret)
4b64bb26
AP		 164 goto err;
165 } else {
bc85d5e2
AP		 166 ret = regmap_update_bits(dev->regmap, 0x80f990, 0x01, 0x00);
167 if (ret)
4b64bb26 168 goto err;
bc85d5e2
AP		 169 ret = regmap_update_bits(dev->regmap, 0x80f9b5, 0x01, 0x00);
170 if (ret)
4b64bb26
AP		 171 goto err;
172 }
173
81e19912
AP		 174 /* Demod core settings */
175 dev_dbg(&client->dev, "load ofsm settings\n");
09611caa 176 switch (dev->cfg.tuner) {
fe8eece1
AP		 177 case AF9033_TUNER_IT9135_38:
178 case AF9033_TUNER_IT9135_51:
179 case AF9033_TUNER_IT9135_52:
463c399c
AP		 180 len = ARRAY_SIZE(ofsm_init_it9135_v1);
181 init = ofsm_init_it9135_v1;
182 break;
fe8eece1
AP		 183 case AF9033_TUNER_IT9135_60:
184 case AF9033_TUNER_IT9135_61:
185 case AF9033_TUNER_IT9135_62:
463c399c
AP		 186 len = ARRAY_SIZE(ofsm_init_it9135_v2);
187 init = ofsm_init_it9135_v2;
fe8eece1
AP		 188 break;
189 default:
190 len = ARRAY_SIZE(ofsm_init);
191 init = ofsm_init;
192 break;
193 }
194
09611caa 195 ret = af9033_wr_reg_val_tab(dev, init, len);
bc85d5e2 196 if (ret)
3bf5e552 197 goto err;
4b64bb26 198
81e19912
AP		 199 /* Demod tuner specific settings */
200 dev_dbg(&client->dev, "load tuner specific settings\n");
09611caa 201 switch (dev->cfg.tuner) {
4b64bb26
AP		 202 case AF9033_TUNER_TUA9001:
203 len = ARRAY_SIZE(tuner_init_tua9001);
204 init = tuner_init_tua9001;
205 break;
ffc501f6
MB		 206 case AF9033_TUNER_FC0011:
207 len = ARRAY_SIZE(tuner_init_fc0011);
208 init = tuner_init_fc0011;
209 break;
540fd4ba
HFV		 210 case AF9033_TUNER_MXL5007T:
211 len = ARRAY_SIZE(tuner_init_mxl5007t);
212 init = tuner_init_mxl5007t;
213 break;
ce1fe379
GG		 214 case AF9033_TUNER_TDA18218:
215 len = ARRAY_SIZE(tuner_init_tda18218);
216 init = tuner_init_tda18218;
217 break;
d67ceb33
OS		 218 case AF9033_TUNER_FC2580:
219 len = ARRAY_SIZE(tuner_init_fc2580);
220 init = tuner_init_fc2580;
221 break;
e713ad15
AP		 222 case AF9033_TUNER_FC0012:
223 len = ARRAY_SIZE(tuner_init_fc0012);
224 init = tuner_init_fc0012;
225 break;
4902bb39 226 case AF9033_TUNER_IT9135_38:
a72cbb77
AP		 227 len = ARRAY_SIZE(tuner_init_it9135_38);
228 init = tuner_init_it9135_38;
229 break;
4902bb39 230 case AF9033_TUNER_IT9135_51:
bb2e12a6
AP		 231 len = ARRAY_SIZE(tuner_init_it9135_51);
232 init = tuner_init_it9135_51;
233 break;
4902bb39 234 case AF9033_TUNER_IT9135_52:
22d729f3
AP		 235 len = ARRAY_SIZE(tuner_init_it9135_52);
236 init = tuner_init_it9135_52;
237 break;
4902bb39 238 case AF9033_TUNER_IT9135_60:
a49f53a0
AP		 239 len = ARRAY_SIZE(tuner_init_it9135_60);
240 init = tuner_init_it9135_60;
241 break;
4902bb39 242 case AF9033_TUNER_IT9135_61:
85211323
AP		 243 len = ARRAY_SIZE(tuner_init_it9135_61);
244 init = tuner_init_it9135_61;
245 break;
4902bb39 246 case AF9033_TUNER_IT9135_62:
dc4a2c40
AP		 247 len = ARRAY_SIZE(tuner_init_it9135_62);
248 init = tuner_init_it9135_62;
4902bb39 249 break;
4b64bb26 250 default:
81e19912
AP		 251 dev_dbg(&client->dev, "unsupported tuner ID=%d\n",
252 dev->cfg.tuner);
4b64bb26
AP		 253 ret = -ENODEV;
254 goto err;
255 }
256
09611caa 257 ret = af9033_wr_reg_val_tab(dev, init, len);
bc85d5e2 258 if (ret)
3bf5e552 259 goto err;
4b64bb26 260
09611caa 261 if (dev->cfg.ts_mode == AF9033_TS_MODE_SERIAL) {
bc85d5e2
AP		 262 ret = regmap_update_bits(dev->regmap, 0x00d91c, 0x01, 0x01);
263 if (ret)
9805992f 264 goto err;
bc85d5e2
AP		 265 ret = regmap_update_bits(dev->regmap, 0x00d917, 0x01, 0x00);
266 if (ret)
9805992f 267 goto err;
bc85d5e2
AP		 268 ret = regmap_update_bits(dev->regmap, 0x00d916, 0x01, 0x00);
269 if (ret)
9805992f
JAR		 270 goto err;
271 }
272
09611caa 273 switch (dev->cfg.tuner) {
086991dd
AP		 274 case AF9033_TUNER_IT9135_60:
275 case AF9033_TUNER_IT9135_61:
276 case AF9033_TUNER_IT9135_62:
bc85d5e2
AP		 277 ret = regmap_write(dev->regmap, 0x800000, 0x01);
278 if (ret)
086991dd
AP		 279 goto err;
280 }
281
81e19912
AP		 282 dev->bandwidth_hz = 0; /* Force to program all parameters */
283 /* Init stats here in order signal app which stats are supported */
2db4d179
AP		 284 c->strength.len = 1;
285 c->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
286 c->cnr.len = 1;
287 c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
288 c->block_count.len = 1;
289 c->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
290 c->block_error.len = 1;
291 c->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
292 c->post_bit_count.len = 1;
293 c->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
294 c->post_bit_error.len = 1;
295 c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
4b64bb26
AP		 296
297 return 0;
4b64bb26 298err:
81e19912 299 dev_dbg(&client->dev, "failed=%d\n", ret);
4b64bb26
AP		 300 return ret;
301}
302
303static int af9033_sleep(struct dvb_frontend *fe)
304{
09611caa 305 struct af9033_dev *dev = fe->demodulator_priv;
81e19912 306 struct i2c_client *client = dev->client;
bc85d5e2
AP		 307 int ret;
308 unsigned int utmp;
4b64bb26 309
81e19912
AP		 310 dev_dbg(&client->dev, "\n");
311
bc85d5e2
AP		 312 ret = regmap_write(dev->regmap, 0x80004c, 0x01);
313 if (ret)
4b64bb26 314 goto err;
bc85d5e2
AP		 315 ret = regmap_write(dev->regmap, 0x800000, 0x00);
316 if (ret)
4b64bb26 317 goto err;
bc85d5e2
AP		 318 ret = regmap_read_poll_timeout(dev->regmap, 0x80004c, utmp, utmp == 0,
319 5000, 1000000);
320 if (ret)
4b64bb26 321 goto err;
bc85d5e2
AP		 322 ret = regmap_update_bits(dev->regmap, 0x80fb24, 0x08, 0x08);
323 if (ret)
4b64bb26
AP		 324 goto err;
325
81e19912 326 /* Prevent current leak by setting TS interface to parallel mode */
09611caa 327 if (dev->cfg.ts_mode == AF9033_TS_MODE_SERIAL) {
81e19912 328 /* Enable parallel TS */
bc85d5e2
AP		 329 ret = regmap_update_bits(dev->regmap, 0x00d917, 0x01, 0x00);
330 if (ret)
4b64bb26 331 goto err;
bc85d5e2
AP		 332 ret = regmap_update_bits(dev->regmap, 0x00d916, 0x01, 0x01);
333 if (ret)
4b64bb26
AP		 334 goto err;
335 }
336
337 return 0;
4b64bb26 338err:
81e19912 339 dev_dbg(&client->dev, "failed=%d\n", ret);
4b64bb26
AP		 340 return ret;
341}
342
343static int af9033_get_tune_settings(struct dvb_frontend *fe,
81e19912 344 struct dvb_frontend_tune_settings *fesettings)
4b64bb26 345{
fe8eece1
AP		 346 /* 800 => 2000 because IT9135 v2 is slow to gain lock */
347 fesettings->min_delay_ms = 2000;
4b64bb26
AP		 348 fesettings->step_size = 0;
349 fesettings->max_drift = 0;
350
351 return 0;
352}
353
354static int af9033_set_frontend(struct dvb_frontend *fe)
355{
09611caa 356 struct af9033_dev *dev = fe->demodulator_priv;
81e19912 357 struct i2c_client *client = dev->client;
4b64bb26 358 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
c2feb9ff
AP		 359 int ret, i;
360 unsigned int utmp, adc_freq;
4b64bb26 361 u8 tmp, buf[3], bandwidth_reg_val;
c2feb9ff 362 u32 if_frequency;
4b64bb26 363
81e19912
AP		 364 dev_dbg(&client->dev, "frequency=%u bandwidth_hz=%u\n",
365 c->frequency, c->bandwidth_hz);
4b64bb26 366
81e19912 367 /* Check bandwidth */
4b64bb26
AP		 368 switch (c->bandwidth_hz) {
369 case 6000000:
370 bandwidth_reg_val = 0x00;
371 break;
372 case 7000000:
373 bandwidth_reg_val = 0x01;
374 break;
375 case 8000000:
376 bandwidth_reg_val = 0x02;
377 break;
378 default:
81e19912 379 dev_dbg(&client->dev, "invalid bandwidth_hz\n");
4b64bb26
AP		 380 ret = -EINVAL;
381 goto err;
382 }
383
81e19912 384 /* Program tuner */
4b64bb26
AP		 385 if (fe->ops.tuner_ops.set_params)
386 fe->ops.tuner_ops.set_params(fe);
387
81e19912 388 /* Coefficients */
09611caa 389 if (c->bandwidth_hz != dev->bandwidth_hz) {
4b64bb26 390 for (i = 0; i < ARRAY_SIZE(coeff_lut); i++) {
09611caa 391 if (coeff_lut[i].clock == dev->cfg.clock &&
81e19912 392 coeff_lut[i].bandwidth_hz == c->bandwidth_hz) {
4b64bb26
AP		 393 break;
394 }
395 }
060f79d5 396 if (i == ARRAY_SIZE(coeff_lut)) {
81e19912
AP		 397 dev_err(&client->dev,
398 "Couldn't find config for clock %u\n",
060f79d5
MCC		 399 dev->cfg.clock);
400 ret = -EINVAL;
401 goto err;
402 }
403
bc85d5e2
AP		 404 ret = regmap_bulk_write(dev->regmap, 0x800001, coeff_lut[i].val,
405 sizeof(coeff_lut[i].val));
406 if (ret)
407 goto err;
4b64bb26
AP		 408 }
409
81e19912 410 /* IF frequency control */
09611caa 411 if (c->bandwidth_hz != dev->bandwidth_hz) {
540fd4ba 412 for (i = 0; i < ARRAY_SIZE(clock_adc_lut); i++) {
09611caa 413 if (clock_adc_lut[i].clock == dev->cfg.clock)
540fd4ba
HFV		 414 break;
415 }
060f79d5 416 if (i == ARRAY_SIZE(clock_adc_lut)) {
81e19912
AP		 417 dev_err(&client->dev,
418 "Couldn't find ADC clock for clock %u\n",
060f79d5
MCC		 419 dev->cfg.clock);
420 ret = -EINVAL;
421 goto err;
422 }
540fd4ba
HFV		 423 adc_freq = clock_adc_lut[i].adc;
424
c2feb9ff
AP		 425 if (dev->cfg.adc_multiplier == AF9033_ADC_MULTIPLIER_2X)
426 adc_freq = 2 * adc_freq;
427
81e19912 428 /* Get used IF frequency */
4b64bb26
AP		 429 if (fe->ops.tuner_ops.get_if_frequency)
430 fe->ops.tuner_ops.get_if_frequency(fe, &if_frequency);
431 else
432 if_frequency = 0;
433
c2feb9ff
AP		 434 utmp = DIV_ROUND_CLOSEST_ULL((u64)if_frequency * 0x800000,
435 adc_freq);
4b64bb26 436
c2feb9ff
AP		 437 if (!dev->cfg.spec_inv && if_frequency)
438 utmp = 0x800000 - utmp;
fe8eece1 439
c2feb9ff
AP		 440 buf[0] = (utmp >> 0) & 0xff;
441 buf[1] = (utmp >> 8) & 0xff;
442 buf[2] = (utmp >> 16) & 0xff;
bc85d5e2
AP		 443 ret = regmap_bulk_write(dev->regmap, 0x800029, buf, 3);
444 if (ret)
4b64bb26
AP		 445 goto err;
446
81e19912 447 dev_dbg(&client->dev, "if_frequency_cw=%06x\n", utmp);
c2feb9ff 448
09611caa 449 dev->bandwidth_hz = c->bandwidth_hz;
4b64bb26
AP		 450 }
451
bc85d5e2
AP		 452 ret = regmap_update_bits(dev->regmap, 0x80f904, 0x03,
453 bandwidth_reg_val);
454 if (ret)
4b64bb26 455 goto err;
bc85d5e2
AP		 456 ret = regmap_write(dev->regmap, 0x800040, 0x00);
457 if (ret)
4b64bb26 458 goto err;
bc85d5e2
AP		 459 ret = regmap_write(dev->regmap, 0x800047, 0x00);
460 if (ret)
4b64bb26 461 goto err;
bc85d5e2
AP		 462 ret = regmap_update_bits(dev->regmap, 0x80f999, 0x01, 0x00);
463 if (ret)
4b64bb26
AP		 464 goto err;
465
466 if (c->frequency <= 230000000)
467 tmp = 0x00; /* VHF */
468 else
469 tmp = 0x01; /* UHF */
470
bc85d5e2
AP		 471 ret = regmap_write(dev->regmap, 0x80004b, tmp);
472 if (ret)
4b64bb26 473 goto err;
81e19912 474 /* Reset FSM */
bc85d5e2
AP		 475 ret = regmap_write(dev->regmap, 0x800000, 0x00);
476 if (ret)
4b64bb26
AP		 477 goto err;
478
479 return 0;
4b64bb26 480err:
81e19912 481 dev_dbg(&client->dev, "failed=%d\n", ret);
4b64bb26
AP		 482 return ret;
483}
484
7e3e68bc
MCC		 485static int af9033_get_frontend(struct dvb_frontend *fe,
486 struct dtv_frontend_properties *c)
0a4df239 487{
09611caa 488 struct af9033_dev *dev = fe->demodulator_priv;
81e19912 489 struct i2c_client *client = dev->client;
0a4df239
GG		 490 int ret;
491 u8 buf[8];
492
81e19912 493 dev_dbg(&client->dev, "\n");
0a4df239 494
81e19912 495 /* Read all needed TPS registers */
bc85d5e2
AP		 496 ret = regmap_bulk_read(dev->regmap, 0x80f900, buf, 8);
497 if (ret)
de7f14fc 498 goto err;
0a4df239
GG		 499
500 switch ((buf[0] >> 0) & 3) {
501 case 0:
de7f14fc 502 c->transmission_mode = TRANSMISSION_MODE_2K;
0a4df239
GG		 503 break;
504 case 1:
de7f14fc 505 c->transmission_mode = TRANSMISSION_MODE_8K;
0a4df239
GG		 506 break;
507 }
508
509 switch ((buf[1] >> 0) & 3) {
510 case 0:
de7f14fc 511 c->guard_interval = GUARD_INTERVAL_1_32;
0a4df239
GG		 512 break;
513 case 1:
de7f14fc 514 c->guard_interval = GUARD_INTERVAL_1_16;
0a4df239
GG		 515 break;
516 case 2:
de7f14fc 517 c->guard_interval = GUARD_INTERVAL_1_8;
0a4df239
GG		 518 break;
519 case 3:
de7f14fc 520 c->guard_interval = GUARD_INTERVAL_1_4;
0a4df239
GG		 521 break;
522 }
523
524 switch ((buf[2] >> 0) & 7) {
525 case 0:
de7f14fc 526 c->hierarchy = HIERARCHY_NONE;
0a4df239
GG		 527 break;
528 case 1:
de7f14fc 529 c->hierarchy = HIERARCHY_1;
0a4df239
GG		 530 break;
531 case 2:
de7f14fc 532 c->hierarchy = HIERARCHY_2;
0a4df239
GG		 533 break;
534 case 3:
de7f14fc 535 c->hierarchy = HIERARCHY_4;
0a4df239
GG		 536 break;
537 }
538
539 switch ((buf[3] >> 0) & 3) {
540 case 0:
de7f14fc 541 c->modulation = QPSK;
0a4df239
GG		 542 break;
543 case 1:
de7f14fc 544 c->modulation = QAM_16;
0a4df239
GG		 545 break;
546 case 2:
de7f14fc 547 c->modulation = QAM_64;
0a4df239
GG		 548 break;
549 }
550
551 switch ((buf[4] >> 0) & 3) {
552 case 0:
de7f14fc 553 c->bandwidth_hz = 6000000;
0a4df239
GG		 554 break;
555 case 1:
de7f14fc 556 c->bandwidth_hz = 7000000;
0a4df239
GG		 557 break;
558 case 2:
de7f14fc 559 c->bandwidth_hz = 8000000;
0a4df239
GG		 560 break;
561 }
562
563 switch ((buf[6] >> 0) & 7) {
564 case 0:
de7f14fc 565 c->code_rate_HP = FEC_1_2;
0a4df239
GG		 566 break;
567 case 1:
de7f14fc 568 c->code_rate_HP = FEC_2_3;
0a4df239
GG		 569 break;
570 case 2:
de7f14fc 571 c->code_rate_HP = FEC_3_4;
0a4df239
GG		 572 break;
573 case 3:
de7f14fc 574 c->code_rate_HP = FEC_5_6;
0a4df239
GG		 575 break;
576 case 4:
de7f14fc 577 c->code_rate_HP = FEC_7_8;
0a4df239
GG		 578 break;
579 case 5:
de7f14fc 580 c->code_rate_HP = FEC_NONE;
0a4df239
GG		 581 break;
582 }
583
584 switch ((buf[7] >> 0) & 7) {
585 case 0:
de7f14fc 586 c->code_rate_LP = FEC_1_2;
0a4df239
GG		 587 break;
588 case 1:
de7f14fc 589 c->code_rate_LP = FEC_2_3;
0a4df239
GG		 590 break;
591 case 2:
de7f14fc 592 c->code_rate_LP = FEC_3_4;
0a4df239
GG		 593 break;
594 case 3:
de7f14fc 595 c->code_rate_LP = FEC_5_6;
0a4df239
GG		 596 break;
597 case 4:
de7f14fc 598 c->code_rate_LP = FEC_7_8;
0a4df239
GG		 599 break;
600 case 5:
de7f14fc 601 c->code_rate_LP = FEC_NONE;
0a4df239
GG		 602 break;
603 }
604
de7f14fc 605 return 0;
de7f14fc 606err:
81e19912 607 dev_dbg(&client->dev, "failed=%d\n", ret);
0a4df239
GG		 608 return ret;
609}
610
0df289a2 611static int af9033_read_status(struct dvb_frontend *fe, enum fe_status *status)
4b64bb26 612{
09611caa 613 struct af9033_dev *dev = fe->demodulator_priv;
81e19912 614 struct i2c_client *client = dev->client;
659a0999 615 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
239dd616 616 int ret, tmp = 0;
bc85d5e2 617 u8 buf[7];
239dd616 618 unsigned int utmp, utmp1;
659a0999 619
81e19912 620 dev_dbg(&client->dev, "\n");
4b64bb26
AP		 621
622 *status = 0;
623
81e19912 624 /* Radio channel status: 0=no result, 1=has signal, 2=no signal */
bc85d5e2
AP		 625 ret = regmap_read(dev->regmap, 0x800047, &utmp);
626 if (ret)
4b64bb26
AP		 627 goto err;
628
81e19912 629 /* Has signal */
bc85d5e2 630 if (utmp == 0x01)
4b64bb26
AP		 631 *status |= FE_HAS_SIGNAL;
632
bc85d5e2 633 if (utmp != 0x02) {
4b64bb26 634 /* TPS lock */
bc85d5e2
AP		 635 ret = regmap_read(dev->regmap, 0x80f5a9, &utmp);
636 if (ret)
4b64bb26
AP		 637 goto err;
638
bc85d5e2 639 if ((utmp >> 0) & 0x01)
4b64bb26
AP		 640 *status |= FE_HAS_SIGNAL | FE_HAS_CARRIER |
641 FE_HAS_VITERBI;
642
81e19912 643 /* Full lock */
bc85d5e2
AP		 644 ret = regmap_read(dev->regmap, 0x80f999, &utmp);
645 if (ret)
4b64bb26
AP		 646 goto err;
647
bc85d5e2 648 if ((utmp >> 0) & 0x01)
4b64bb26
AP		 649 *status |= FE_HAS_SIGNAL | FE_HAS_CARRIER |
650 FE_HAS_VITERBI | FE_HAS_SYNC |
651 FE_HAS_LOCK;
652 }
653
83f11619
AP		 654 dev->fe_status = *status;
655
81e19912 656 /* Signal strength */
659a0999
AP		 657 if (dev->fe_status & FE_HAS_SIGNAL) {
658 if (dev->is_af9035) {
bc85d5e2 659 ret = regmap_read(dev->regmap, 0x80004a, &utmp);
659a0999
AP		 660 if (ret)
661 goto err;
bc85d5e2 662 tmp = -utmp * 1000;
659a0999 663 } else {
bc85d5e2 664 ret = regmap_read(dev->regmap, 0x8000f7, &utmp);
659a0999
AP		 665 if (ret)
666 goto err;
bc85d5e2 667 tmp = (utmp - 100) * 1000;
659a0999
AP		 668 }
669
670 c->strength.len = 1;
671 c->strength.stat[0].scale = FE_SCALE_DECIBEL;
672 c->strength.stat[0].svalue = tmp;
673 } else {
674 c->strength.len = 1;
675 c->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
676 }
677
678 /* CNR */
679 if (dev->fe_status & FE_HAS_VITERBI) {
81e19912 680 /* Read raw SNR value */
bc85d5e2 681 ret = regmap_bulk_read(dev->regmap, 0x80002c, buf, 3);
659a0999
AP		 682 if (ret)
683 goto err;
684
239dd616 685 utmp1 = buf[2] << 16 | buf[1] << 8 | buf[0] << 0;
659a0999 686
81e19912 687 /* Read superframe number */
bc85d5e2 688 ret = regmap_read(dev->regmap, 0x80f78b, &utmp);
659a0999
AP		 689 if (ret)
690 goto err;
691
bc85d5e2 692 if (utmp)
239dd616 693 utmp1 /= utmp;
659a0999 694
81e19912 695 /* Read current transmission mode */
bc85d5e2 696 ret = regmap_read(dev->regmap, 0x80f900, &utmp);
659a0999
AP		 697 if (ret)
698 goto err;
699
bc85d5e2 700 switch ((utmp >> 0) & 3) {
659a0999 701 case 0:
239dd616
AP		 702 /* 2k */
703 utmp1 *= 4;
659a0999
AP		 704 break;
705 case 1:
239dd616
AP		 706 /* 8k */
707 utmp1 *= 1;
659a0999
AP		 708 break;
709 case 2:
239dd616
AP		 710 /* 4k */
711 utmp1 *= 2;
659a0999
AP		 712 break;
713 default:
239dd616 714 utmp1 *= 0;
659a0999
AP		 715 break;
716 }
717
81e19912 718 /* Read current modulation */
bc85d5e2 719 ret = regmap_read(dev->regmap, 0x80f903, &utmp);
659a0999
AP		 720 if (ret)
721 goto err;
722
bc85d5e2 723 switch ((utmp >> 0) & 3) {
659a0999 724 case 0:
239dd616
AP		 725 /*
726 * QPSK
727 * CNR[dB] 13 * -log10((1690000 - value) / value) + 2.6
728 * value [653799, 1689999], 2.6 / 13 = 3355443
729 */
730 utmp1 = clamp(utmp1, 653799U, 1689999U);
731 utmp1 = ((u64)(intlog10(utmp1)
732 - intlog10(1690000 - utmp1)
733 + 3355443) * 13 * 1000) >> 24;
659a0999
AP		 734 break;
735 case 1:
239dd616
AP		 736 /*
737 * QAM-16
738 * CNR[dB] 6 * log10((value - 370000) / (828000 - value)) + 15.7
739 * value [371105, 827999], 15.7 / 6 = 43900382
740 */
741 utmp1 = clamp(utmp1, 371105U, 827999U);
742 utmp1 = ((u64)(intlog10(utmp1 - 370000)
743 - intlog10(828000 - utmp1)
744 + 43900382) * 6 * 1000) >> 24;
659a0999
AP		 745 break;
746 case 2:
239dd616
AP		 747 /*
748 * QAM-64
749 * CNR[dB] 8 * log10((value - 193000) / (425000 - value)) + 23.8
750 * value [193246, 424999], 23.8 / 8 = 49912218
751 */
752 utmp1 = clamp(utmp1, 193246U, 424999U);
753 utmp1 = ((u64)(intlog10(utmp1 - 193000)
754 - intlog10(425000 - utmp1)
755 + 49912218) * 8 * 1000) >> 24;
659a0999
AP		 756 break;
757 default:
239dd616 758 utmp1 = 0;
659a0999
AP		 759 break;
760 }
761
239dd616 762 dev_dbg(&client->dev, "cnr=%u\n", utmp1);
659a0999 763
659a0999 764 c->cnr.stat[0].scale = FE_SCALE_DECIBEL;
239dd616 765 c->cnr.stat[0].svalue = utmp1;
659a0999 766 } else {
659a0999
AP		 767 c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
768 }
769
770 /* UCB/PER/BER */
771 if (dev->fe_status & FE_HAS_LOCK) {
81e19912 772 /* Outer FEC, 204 byte packets */
659a0999 773 u16 abort_packet_count, rsd_packet_count;
81e19912 774 /* Inner FEC, bits */
659a0999
AP		 775 u32 rsd_bit_err_count;
776
777 /*
778 * Packet count used for measurement is 10000
779 * (rsd_packet_count). Maybe it should be increased?
780 */
781
bc85d5e2 782 ret = regmap_bulk_read(dev->regmap, 0x800032, buf, 7);
659a0999
AP		 783 if (ret)
784 goto err;
785
786 abort_packet_count = (buf[1] << 8) | (buf[0] << 0);
787 rsd_bit_err_count = (buf[4] << 16) | (buf[3] << 8) | buf[2];
788 rsd_packet_count = (buf[6] << 8) | (buf[5] << 0);
789
790 dev->error_block_count += abort_packet_count;
791 dev->total_block_count += rsd_packet_count;
792 dev->post_bit_error += rsd_bit_err_count;
793 dev->post_bit_count += rsd_packet_count * 204 * 8;
794
795 c->block_count.len = 1;
796 c->block_count.stat[0].scale = FE_SCALE_COUNTER;
797 c->block_count.stat[0].uvalue = dev->total_block_count;
798
799 c->block_error.len = 1;
800 c->block_error.stat[0].scale = FE_SCALE_COUNTER;
801 c->block_error.stat[0].uvalue = dev->error_block_count;
802
803 c->post_bit_count.len = 1;
804 c->post_bit_count.stat[0].scale = FE_SCALE_COUNTER;
805 c->post_bit_count.stat[0].uvalue = dev->post_bit_count;
806
807 c->post_bit_error.len = 1;
808 c->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;
809 c->post_bit_error.stat[0].uvalue = dev->post_bit_error;
810 }
811
4b64bb26 812 return 0;
4b64bb26 813err:
81e19912 814 dev_dbg(&client->dev, "failed=%d\n", ret);
4b64bb26
AP		 815 return ret;
816}
817
818static int af9033_read_snr(struct dvb_frontend *fe, u16 *snr)
819{
09611caa 820 struct af9033_dev *dev = fe->demodulator_priv;
81e19912 821 struct i2c_client *client = dev->client;
6b457786 822 struct dtv_frontend_properties *c = &dev->fe.dtv_property_cache;
6d03f6a8 823 int ret;
bc85d5e2 824 unsigned int utmp;
e898ef62 825
81e19912
AP		 826 dev_dbg(&client->dev, "\n");
827
828 /* Use DVBv5 CNR */
6d03f6a8 829 if (c->cnr.stat[0].scale == FE_SCALE_DECIBEL) {
c3a80cd0
AP		 830 /* Return 0.1 dB for AF9030 and 0-0xffff for IT9130. */
831 if (dev->is_af9035) {
832 /* 1000x => 10x (0.1 dB) */
833 *snr = div_s64(c->cnr.stat[0].svalue, 100);
834 } else {
835 /* 1000x => 1x (1 dB) */
836 *snr = div_s64(c->cnr.stat[0].svalue, 1000);
6d03f6a8 837
81e19912 838 /* Read current modulation */
bc85d5e2 839 ret = regmap_read(dev->regmap, 0x80f903, &utmp);
c3a80cd0
AP		 840 if (ret)
841 goto err;
6d03f6a8 842
c3a80cd0 843 /* scale value to 0x0000-0xffff */
bc85d5e2 844 switch ((utmp >> 0) & 3) {
c3a80cd0
AP		 845 case 0:
846 *snr = *snr * 0xffff / 23;
847 break;
848 case 1:
849 *snr = *snr * 0xffff / 26;
850 break;
851 case 2:
852 *snr = *snr * 0xffff / 32;
853 break;
854 default:
855 goto err;
856 }
6d03f6a8
BC		 857 }
858 } else {
6b457786 859 *snr = 0;
6d03f6a8 860 }
4b64bb26
AP		 861
862 return 0;
6d03f6a8 863err:
81e19912 864 dev_dbg(&client->dev, "failed=%d\n", ret);
6d03f6a8 865 return ret;
4b64bb26
AP		 866}
867
868static int af9033_read_signal_strength(struct dvb_frontend *fe, u16 *strength)
869{
09611caa 870 struct af9033_dev *dev = fe->demodulator_priv;
81e19912 871 struct i2c_client *client = dev->client;
3adec272
BC		 872 struct dtv_frontend_properties *c = &dev->fe.dtv_property_cache;
873 int ret, tmp, power_real;
bc85d5e2
AP		 874 unsigned int utmp;
875 u8 gain_offset, buf[7];
4b64bb26 876
81e19912
AP		 877 dev_dbg(&client->dev, "\n");
878
3adec272 879 if (dev->is_af9035) {
81e19912 880 /* Read signal strength of 0-100 scale */
bc85d5e2
AP		 881 ret = regmap_read(dev->regmap, 0x800048, &utmp);
882 if (ret)
0b0d9628
AP		 883 goto err;
884
81e19912 885 /* Scale value to 0x0000-0xffff */
bc85d5e2 886 *strength = utmp * 0xffff / 100;
3adec272 887 } else {
bc85d5e2
AP		 888 ret = regmap_read(dev->regmap, 0x8000f7, &utmp);
889 if (ret)
1620d221
AP		 890 goto err;
891
bc85d5e2
AP		 892 ret = regmap_bulk_read(dev->regmap, 0x80f900, buf, 7);
893 if (ret)
1620d221 894 goto err;
3adec272
BC		 895
896 if (c->frequency <= 300000000)
897 gain_offset = 7; /* VHF */
898 else
899 gain_offset = 4; /* UHF */
900
bc85d5e2 901 power_real = (utmp - 100 - gain_offset) -
3adec272
BC		 902 power_reference[((buf[3] >> 0) & 3)][((buf[6] >> 0) & 7)];
903
904 if (power_real < -15)
905 tmp = 0;
906 else if ((power_real >= -15) && (power_real < 0))
907 tmp = (2 * (power_real + 15)) / 3;
908 else if ((power_real >= 0) && (power_real < 20))
909 tmp = 4 * power_real + 10;
910 else if ((power_real >= 20) && (power_real < 35))
911 tmp = (2 * (power_real - 20)) / 3 + 90;
912 else
913 tmp = 100;
914
81e19912 915 /* Scale value to 0x0000-0xffff */
3adec272
BC		 916 *strength = tmp * 0xffff / 100;
917 }
4b64bb26 918
4b64bb26 919 return 0;
4b64bb26 920err:
81e19912 921 dev_dbg(&client->dev, "failed=%d\n", ret);
4b64bb26
AP		 922 return ret;
923}
924
925static int af9033_read_ber(struct dvb_frontend *fe, u32 *ber)
926{
09611caa 927 struct af9033_dev *dev = fe->demodulator_priv;
47eafa54 928
e53c4744
AP		 929 *ber = (dev->post_bit_error - dev->post_bit_error_prev);
930 dev->post_bit_error_prev = dev->post_bit_error;
4b64bb26
AP		 931
932 return 0;
933}
934
935static int af9033_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
936{
09611caa 937 struct af9033_dev *dev = fe->demodulator_priv;
4b64bb26 938
1d0ceae4 939 *ucblocks = dev->error_block_count;
81e19912 940
4b64bb26
AP		 941 return 0;
942}
943
944static int af9033_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
945{
09611caa 946 struct af9033_dev *dev = fe->demodulator_priv;
81e19912 947 struct i2c_client *client = dev->client;
4b64bb26
AP		 948 int ret;
949
81e19912 950 dev_dbg(&client->dev, "enable=%d\n", enable);
4b64bb26 951
bc85d5e2
AP		 952 ret = regmap_update_bits(dev->regmap, 0x00fa04, 0x01, enable);
953 if (ret)
4b64bb26
AP		 954 goto err;
955
956 return 0;
4b64bb26 957err:
81e19912 958 dev_dbg(&client->dev, "failed=%d\n", ret);
4b64bb26
AP		 959 return ret;
960}
961
ed97a6fe 962static int af9033_pid_filter_ctrl(struct dvb_frontend *fe, int onoff)
040cf86c 963{
09611caa 964 struct af9033_dev *dev = fe->demodulator_priv;
81e19912 965 struct i2c_client *client = dev->client;
040cf86c
AP		 966 int ret;
967
81e19912 968 dev_dbg(&client->dev, "onoff=%d\n", onoff);
040cf86c 969
bc85d5e2
AP		 970 ret = regmap_update_bits(dev->regmap, 0x80f993, 0x01, onoff);
971 if (ret)
040cf86c
AP		 972 goto err;
973
974 return 0;
040cf86c 975err:
81e19912 976 dev_dbg(&client->dev, "failed=%d\n", ret);
040cf86c
AP		 977 return ret;
978}
040cf86c 979
24e419a0 980static int af9033_pid_filter(struct dvb_frontend *fe, int index, u16 pid,
81e19912 981 int onoff)
040cf86c 982{
09611caa 983 struct af9033_dev *dev = fe->demodulator_priv;
81e19912 984 struct i2c_client *client = dev->client;
040cf86c
AP		 985 int ret;
986 u8 wbuf[2] = {(pid >> 0) & 0xff, (pid >> 8) & 0xff};
987
81e19912
AP		 988 dev_dbg(&client->dev, "index=%d pid=%04x onoff=%d\n",
989 index, pid, onoff);
040cf86c
AP		 990
991 if (pid > 0x1fff)
992 return 0;
993
bc85d5e2
AP		 994 ret = regmap_bulk_write(dev->regmap, 0x80f996, wbuf, 2);
995 if (ret)
040cf86c 996 goto err;
bc85d5e2
AP		 997 ret = regmap_write(dev->regmap, 0x80f994, onoff);
998 if (ret)
040cf86c 999 goto err;
bc85d5e2
AP		 1000 ret = regmap_write(dev->regmap, 0x80f995, index);
1001 if (ret)
040cf86c
AP		 1002 goto err;
1003
1004 return 0;
040cf86c 1005err:
81e19912 1006 dev_dbg(&client->dev, "failed=%d\n", ret);
040cf86c
AP		 1007 return ret;
1008}
040cf86c 1009
bd336e63 1010static const struct dvb_frontend_ops af9033_ops = {
81e19912 1011 .delsys = {SYS_DVBT},
f5b00a76
AP		 1012 .info = {
1013 .name = "Afatech AF9033 (DVB-T)",
f1b1eabf
MCC		 1014 .frequency_min_hz = 174 * MHz,
1015 .frequency_max_hz = 862 * MHz,
1016 .frequency_stepsize_hz = 250 * kHz,
f5b00a76
AP		 1017 .caps = FE_CAN_FEC_1_2 |
1018 FE_CAN_FEC_2_3 |
1019 FE_CAN_FEC_3_4 |
1020 FE_CAN_FEC_5_6 |
1021 FE_CAN_FEC_7_8 |
1022 FE_CAN_FEC_AUTO |
1023 FE_CAN_QPSK |
1024 FE_CAN_QAM_16 |
1025 FE_CAN_QAM_64 |
1026 FE_CAN_QAM_AUTO |
1027 FE_CAN_TRANSMISSION_MODE_AUTO |
1028 FE_CAN_GUARD_INTERVAL_AUTO |
1029 FE_CAN_HIERARCHY_AUTO |
1030 FE_CAN_RECOVER |
1031 FE_CAN_MUTE_TS
1032 },
1033
1034 .init = af9033_init,
1035 .sleep = af9033_sleep,
1036
1037 .get_tune_settings = af9033_get_tune_settings,
1038 .set_frontend = af9033_set_frontend,
1039 .get_frontend = af9033_get_frontend,
1040
1041 .read_status = af9033_read_status,
1042 .read_snr = af9033_read_snr,
1043 .read_signal_strength = af9033_read_signal_strength,
1044 .read_ber = af9033_read_ber,
1045 .read_ucblocks = af9033_read_ucblocks,
1046
1047 .i2c_gate_ctrl = af9033_i2c_gate_ctrl,
1048};
4b64bb26 1049
f5b00a76 1050static int af9033_probe(struct i2c_client *client,
81e19912 1051 const struct i2c_device_id *id)
4b64bb26 1052{
f5b00a76 1053 struct af9033_config *cfg = client->dev.platform_data;
09611caa 1054 struct af9033_dev *dev;
f5b00a76 1055 int ret;
4b64bb26 1056 u8 buf[8];
ef5211fd 1057 u32 reg;
bc85d5e2
AP		 1058 static const struct regmap_config regmap_config = {
1059 .reg_bits = 24,
1060 .val_bits = 8,
1061 };
1062
81e19912
AP		 1063 /* Allocate memory for the internal state */
1064 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
1065 if (!dev) {
f5b00a76 1066 ret = -ENOMEM;
4b64bb26 1067 goto err;
f5b00a76 1068 }
4b64bb26 1069
81e19912 1070 /* Setup the state */
f5b00a76 1071 dev->client = client;
81e19912
AP		 1072 memcpy(&dev->cfg, cfg, sizeof(dev->cfg));
1073 switch (dev->cfg.ts_mode) {
1074 case AF9033_TS_MODE_PARALLEL:
1075 dev->ts_mode_parallel = true;
1076 break;
1077 case AF9033_TS_MODE_SERIAL:
1078 dev->ts_mode_serial = true;
1079 break;
1080 case AF9033_TS_MODE_USB:
1081 /* USB mode for AF9035 */
1082 default:
1083 break;
1084 }
4b64bb26 1085
09611caa 1086 if (dev->cfg.clock != 12000000) {
f5b00a76 1087 ret = -ENODEV;
81e19912
AP		 1088 dev_err(&client->dev,
1089 "Unsupported clock %u Hz. Only 12000000 Hz is supported currently\n",
1090 dev->cfg.clock);
f5b00a76 1091 goto err_kfree;
8e8a5ac7
AP		 1092 }
1093
bc85d5e2
AP		 1094 /* Create regmap */
1095 dev->regmap = regmap_init_i2c(client, &regmap_config);
1096 if (IS_ERR(dev->regmap)) {
1097 ret = PTR_ERR(dev->regmap);
1098 goto err_kfree;
1099 }
1100
81e19912 1101 /* Firmware version */
09611caa 1102 switch (dev->cfg.tuner) {
ef5211fd
AP		 1103 case AF9033_TUNER_IT9135_38:
1104 case AF9033_TUNER_IT9135_51:
1105 case AF9033_TUNER_IT9135_52:
1106 case AF9033_TUNER_IT9135_60:
1107 case AF9033_TUNER_IT9135_61:
1108 case AF9033_TUNER_IT9135_62:
83f11619 1109 dev->is_it9135 = true;
ef5211fd
AP		 1110 reg = 0x004bfc;
1111 break;
1112 default:
83f11619 1113 dev->is_af9035 = true;
ef5211fd
AP		 1114 reg = 0x0083e9;
1115 break;
1116 }
1117
bc85d5e2
AP		 1118 ret = regmap_bulk_read(dev->regmap, reg, &buf[0], 4);
1119 if (ret)
1120 goto err_regmap_exit;
1121 ret = regmap_bulk_read(dev->regmap, 0x804191, &buf[4], 4);
1122 if (ret)
1123 goto err_regmap_exit;
4b64bb26 1124
81e19912
AP		 1125 dev_info(&client->dev,
1126 "firmware version: LINK %d.%d.%d.%d - OFDM %d.%d.%d.%d\n",
1127 buf[0], buf[1], buf[2], buf[3],
1128 buf[4], buf[5], buf[6], buf[7]);
4b64bb26 1129
81e19912 1130 /* Sleep as chip seems to be partly active by default */
09a446d2
VT		 1131 /* IT9135 did not like to sleep at that early */
1132 if (dev->is_af9035) {
bc85d5e2
AP		 1133 ret = regmap_write(dev->regmap, 0x80004c, 0x01);
1134 if (ret)
1135 goto err_regmap_exit;
1136 ret = regmap_write(dev->regmap, 0x800000, 0x00);
1137 if (ret)
1138 goto err_regmap_exit;
4902bb39 1139 }
12897dc3 1140
81e19912
AP		 1141 /* Create dvb frontend */
1142 memcpy(&dev->fe.ops, &af9033_ops, sizeof(dev->fe.ops));
09611caa 1143 dev->fe.demodulator_priv = dev;
f5b00a76
AP		 1144 *cfg->fe = &dev->fe;
1145 if (cfg->ops) {
1146 cfg->ops->pid_filter = af9033_pid_filter;
1147 cfg->ops->pid_filter_ctrl = af9033_pid_filter_ctrl;
ed97a6fe 1148 }
3461831a 1149 cfg->regmap = dev->regmap;
f5b00a76 1150 i2c_set_clientdata(client, dev);
ed97a6fe 1151
81e19912
AP		 1152 dev_info(&client->dev, "Afatech AF9033 successfully attached\n");
1153
f5b00a76 1154 return 0;
bc85d5e2
AP		 1155err_regmap_exit:
1156 regmap_exit(dev->regmap);
f5b00a76 1157err_kfree:
09611caa 1158 kfree(dev);
f5b00a76 1159err:
6a087f1f 1160 dev_dbg(&client->dev, "failed=%d\n", ret);
f5b00a76 1161 return ret;
4b64bb26 1162}
4b64bb26 1163
f5b00a76
AP		 1164static int af9033_remove(struct i2c_client *client)
1165{
1166 struct af9033_dev *dev = i2c_get_clientdata(client);
4b64bb26 1167
81e19912 1168 dev_dbg(&client->dev, "\n");
4b64bb26 1169
bc85d5e2 1170 regmap_exit(dev->regmap);
f5b00a76 1171 kfree(dev);
4b64bb26 1172
f5b00a76
AP		 1173 return 0;
1174}
4b64bb26 1175
f5b00a76
AP		 1176static const struct i2c_device_id af9033_id_table[] = {
1177 {"af9033", 0},
1178 {}
1179};
1180MODULE_DEVICE_TABLE(i2c, af9033_id_table);
4b64bb26 1181
f5b00a76
AP		 1182static struct i2c_driver af9033_driver = {
1183 .driver = {
f5b00a76 1184 .name = "af9033",
72812175 1185 .suppress_bind_attrs = true,
f5b00a76
AP		 1186 },
1187 .probe = af9033_probe,
1188 .remove = af9033_remove,
1189 .id_table = af9033_id_table,
4b64bb26
AP		 1190};
1191
f5b00a76
AP		 1192module_i2c_driver(af9033_driver);
1193
4b64bb26
AP		 1194MODULE_AUTHOR("Antti Palosaari <crope@iki.fi>");
1195MODULE_DESCRIPTION("Afatech AF9033 DVB-T demodulator driver");
1196MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)