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V4L/DVB: ngene: Implement support for MSI
[linux-2.6-block.git] / drivers / media / dvb / ngene / ngene-core.c
CommitLineData
dae52d00
MB		 1/*
2 * ngene.c: nGene PCIe bridge driver
3 *
4 * Copyright (C) 2005-2007 Micronas
5 *
6 * Copyright (C) 2008-2009 Ralph Metzler <rjkm@metzlerbros.de>
7 * Modifications for new nGene firmware,
8 * support for EEPROM-copying,
9 * support for new dual DVB-S2 card prototype
10 *
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * version 2 only, as published by the Free Software Foundation.
15 *
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
26 * 02110-1301, USA
27 * Or, point your browser to http://www.gnu.org/copyleft/gpl.html
28 */
29
30#include <linux/module.h>
31#include <linux/init.h>
32#include <linux/delay.h>
dae52d00 33#include <linux/poll.h>
684688d8 34#include <linux/io.h>
dae52d00
MB		 35#include <asm/div64.h>
36#include <linux/pci.h>
dae52d00
MB		 37#include <linux/smp_lock.h>
38#include <linux/timer.h>
dae52d00
MB		 39#include <linux/byteorder/generic.h>
40#include <linux/firmware.h>
6fd2d0f9 41#include <linux/vmalloc.h>
dae52d00
MB		 42
43#include "ngene.h"
44
cf1b12f2
MB		 45static int one_adapter = 1;
46module_param(one_adapter, int, 0444);
47MODULE_PARM_DESC(one_adapter, "Use only one adapter.");
48
dae52d00 49
dae52d00
MB		 50static int debug;
51module_param(debug, int, 0444);
52MODULE_PARM_DESC(debug, "Print debugging information.");
53
83f3c715
OE		 54DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr);
55
b1ec9532
OE		 56#define COMMAND_TIMEOUT_WORKAROUND
57
dae52d00
MB		 58#define dprintk if (debug) printk
59
dae52d00
MB		 60#define ngwriteb(dat, adr) writeb((dat), (char *)(dev->iomem + (adr)))
61#define ngwritel(dat, adr) writel((dat), (char *)(dev->iomem + (adr)))
62#define ngwriteb(dat, adr) writeb((dat), (char *)(dev->iomem + (adr)))
63#define ngreadl(adr) readl(dev->iomem + (adr))
64#define ngreadb(adr) readb(dev->iomem + (adr))
65#define ngcpyto(adr, src, count) memcpy_toio((char *) \
66 (dev->iomem + (adr)), (src), (count))
67#define ngcpyfrom(dst, adr, count) memcpy_fromio((dst), (char *) \
68 (dev->iomem + (adr)), (count))
69
dae52d00
MB		 70/****************************************************************************/
71/* nGene interrupt handler **************************************************/
72/****************************************************************************/
73
74static void event_tasklet(unsigned long data)
75{
76 struct ngene *dev = (struct ngene *)data;
77
78 while (dev->EventQueueReadIndex != dev->EventQueueWriteIndex) {
79 struct EVENT_BUFFER Event =
80 dev->EventQueue[dev->EventQueueReadIndex];
81 dev->EventQueueReadIndex =
82 (dev->EventQueueReadIndex + 1) & (EVENT_QUEUE_SIZE - 1);
83
84 if ((Event.UARTStatus & 0x01) && (dev->TxEventNotify))
85 dev->TxEventNotify(dev, Event.TimeStamp);
86 if ((Event.UARTStatus & 0x02) && (dev->RxEventNotify))
87 dev->RxEventNotify(dev, Event.TimeStamp,
88 Event.RXCharacter);
89 }
90}
91
92static void demux_tasklet(unsigned long data)
93{
94 struct ngene_channel *chan = (struct ngene_channel *)data;
95 struct SBufferHeader *Cur = chan->nextBuffer;
96
97 spin_lock_irq(&chan->state_lock);
98
99 while (Cur->ngeneBuffer.SR.Flags & 0x80) {
100 if (chan->mode & NGENE_IO_TSOUT) {
101 u32 Flags = chan->DataFormatFlags;
102 if (Cur->ngeneBuffer.SR.Flags & 0x20)
103 Flags |= BEF_OVERFLOW;
104 if (chan->pBufferExchange) {
105 if (!chan->pBufferExchange(chan,
106 Cur->Buffer1,
107 chan->Capture1Length,
108 Cur->ngeneBuffer.SR.
109 Clock, Flags)) {
110 /*
111 We didn't get data
112 Clear in service flag to make sure we
113 get called on next interrupt again.
114 leave fill/empty (0x80) flag alone
115 to avoid hardware running out of
116 buffers during startup, we hold only
117 in run state ( the source may be late
118 delivering data )
119 */
120
121 if (chan->HWState == HWSTATE_RUN) {
122 Cur->ngeneBuffer.SR.Flags &=
123 ~0x40;
124 break;
125 /* Stop proccessing stream */
126 }
127 } else {
128 /* We got a valid buffer,
129 so switch to run state */
130 chan->HWState = HWSTATE_RUN;
131 }
132 } else {
133 printk(KERN_ERR DEVICE_NAME ": OOPS\n");
134 if (chan->HWState == HWSTATE_RUN) {
135 Cur->ngeneBuffer.SR.Flags &= ~0x40;
136 break; /* Stop proccessing stream */
137 }
138 }
139 if (chan->AudioDTOUpdated) {
140 printk(KERN_INFO DEVICE_NAME
141 ": Update AudioDTO = %d\n",
142 chan->AudioDTOValue);
143 Cur->ngeneBuffer.SR.DTOUpdate =
144 chan->AudioDTOValue;
145 chan->AudioDTOUpdated = 0;
146 }
147 } else {
148 if (chan->HWState == HWSTATE_RUN) {
149 u32 Flags = 0;
eb05d155
OE		 150 IBufferExchange *exch1 = chan->pBufferExchange;
151 IBufferExchange *exch2 = chan->pBufferExchange2;
dae52d00
MB		 152 if (Cur->ngeneBuffer.SR.Flags & 0x01)
153 Flags |= BEF_EVEN_FIELD;
154 if (Cur->ngeneBuffer.SR.Flags & 0x20)
155 Flags |= BEF_OVERFLOW;
eb05d155
OE		 156 spin_unlock_irq(&chan->state_lock);
157 if (exch1)
158 exch1(chan, Cur->Buffer1,
159 chan->Capture1Length,
160 Cur->ngeneBuffer.SR.Clock,
161 Flags);
162 if (exch2)
163 exch2(chan, Cur->Buffer2,
164 chan->Capture2Length,
165 Cur->ngeneBuffer.SR.Clock,
166 Flags);
167 spin_lock_irq(&chan->state_lock);
dae52d00
MB		 168 } else if (chan->HWState != HWSTATE_STOP)
169 chan->HWState = HWSTATE_RUN;
170 }
171 Cur->ngeneBuffer.SR.Flags = 0x00;
172 Cur = Cur->Next;
173 }
174 chan->nextBuffer = Cur;
175
176 spin_unlock_irq(&chan->state_lock);
177}
178
179static irqreturn_t irq_handler(int irq, void *dev_id)
180{
181 struct ngene *dev = (struct ngene *)dev_id;
182 u32 icounts = 0;
183 irqreturn_t rc = IRQ_NONE;
184 u32 i = MAX_STREAM;
185 u8 *tmpCmdDoneByte;
186
187 if (dev->BootFirmware) {
188 icounts = ngreadl(NGENE_INT_COUNTS);
189 if (icounts != dev->icounts) {
190 ngwritel(0, FORCE_NMI);
191 dev->cmd_done = 1;
192 wake_up(&dev->cmd_wq);
193 dev->icounts = icounts;
194 rc = IRQ_HANDLED;
195 }
196 return rc;
197 }
198
199 ngwritel(0, FORCE_NMI);
200
201 spin_lock(&dev->cmd_lock);
202 tmpCmdDoneByte = dev->CmdDoneByte;
203 if (tmpCmdDoneByte &&
204 (*tmpCmdDoneByte ||
205 (dev->ngenetohost[0] == 1 && dev->ngenetohost[1] != 0))) {
206 dev->CmdDoneByte = NULL;
207 dev->cmd_done = 1;
208 wake_up(&dev->cmd_wq);
209 rc = IRQ_HANDLED;
210 }
211 spin_unlock(&dev->cmd_lock);
212
213 if (dev->EventBuffer->EventStatus & 0x80) {
214 u8 nextWriteIndex =
215 (dev->EventQueueWriteIndex + 1) &
216 (EVENT_QUEUE_SIZE - 1);
217 if (nextWriteIndex != dev->EventQueueReadIndex) {
218 dev->EventQueue[dev->EventQueueWriteIndex] =
219 *(dev->EventBuffer);
220 dev->EventQueueWriteIndex = nextWriteIndex;
221 } else {
222 printk(KERN_ERR DEVICE_NAME ": event overflow\n");
223 dev->EventQueueOverflowCount += 1;
224 dev->EventQueueOverflowFlag = 1;
225 }
226 dev->EventBuffer->EventStatus &= ~0x80;
227 tasklet_schedule(&dev->event_tasklet);
228 rc = IRQ_HANDLED;
229 }
230
231 while (i > 0) {
232 i--;
233 spin_lock(&dev->channel[i].state_lock);
234 /* if (dev->channel[i].State>=KSSTATE_RUN) { */
235 if (dev->channel[i].nextBuffer) {
236 if ((dev->channel[i].nextBuffer->
237 ngeneBuffer.SR.Flags & 0xC0) == 0x80) {
238 dev->channel[i].nextBuffer->
239 ngeneBuffer.SR.Flags |= 0x40;
240 tasklet_schedule(
241 &dev->channel[i].demux_tasklet);
242 rc = IRQ_HANDLED;
243 }
244 }
245 spin_unlock(&dev->channel[i].state_lock);
246 }
247
ace30f74
OE		 248 /* Request might have been processed by a previous call. */
249 return IRQ_HANDLED;
dae52d00
MB		 250}
251
252/****************************************************************************/
253/* nGene command interface **************************************************/
254/****************************************************************************/
255
b1ec9532
OE		 256static void dump_command_io(struct ngene *dev)
257{
258 u8 buf[8], *b;
259
260 ngcpyfrom(buf, HOST_TO_NGENE, 8);
261 printk(KERN_ERR "host_to_ngene (%04x): %02x %02x %02x %02x %02x %02x %02x %02x\n",
684688d8
OE		 262 HOST_TO_NGENE, buf[0], buf[1], buf[2], buf[3],
263 buf[4], buf[5], buf[6], buf[7]);
b1ec9532
OE		 264
265 ngcpyfrom(buf, NGENE_TO_HOST, 8);
266 printk(KERN_ERR "ngene_to_host (%04x): %02x %02x %02x %02x %02x %02x %02x %02x\n",
684688d8
OE		 267 NGENE_TO_HOST, buf[0], buf[1], buf[2], buf[3],
268 buf[4], buf[5], buf[6], buf[7]);
b1ec9532
OE		 269
270 b = dev->hosttongene;
271 printk(KERN_ERR "dev->hosttongene (%p): %02x %02x %02x %02x %02x %02x %02x %02x\n",
272 b, b[0], b[1], b[2], b[3], b[4], b[5], b[6], b[7]);
273
274 b = dev->ngenetohost;
275 printk(KERN_ERR "dev->ngenetohost (%p): %02x %02x %02x %02x %02x %02x %02x %02x\n",
276 b, b[0], b[1], b[2], b[3], b[4], b[5], b[6], b[7]);
277}
278
dae52d00
MB		 279static int ngene_command_mutex(struct ngene *dev, struct ngene_command *com)
280{
281 int ret;
282 u8 *tmpCmdDoneByte;
283
284 dev->cmd_done = 0;
285
286 if (com->cmd.hdr.Opcode == CMD_FWLOAD_PREPARE) {
287 dev->BootFirmware = 1;
288 dev->icounts = ngreadl(NGENE_INT_COUNTS);
289 ngwritel(0, NGENE_COMMAND);
290 ngwritel(0, NGENE_COMMAND_HI);
291 ngwritel(0, NGENE_STATUS);
292 ngwritel(0, NGENE_STATUS_HI);
293 ngwritel(0, NGENE_EVENT);
294 ngwritel(0, NGENE_EVENT_HI);
295 } else if (com->cmd.hdr.Opcode == CMD_FWLOAD_FINISH) {
296 u64 fwio = dev->PAFWInterfaceBuffer;
297
298 ngwritel(fwio & 0xffffffff, NGENE_COMMAND);
299 ngwritel(fwio >> 32, NGENE_COMMAND_HI);
300 ngwritel((fwio + 256) & 0xffffffff, NGENE_STATUS);
301 ngwritel((fwio + 256) >> 32, NGENE_STATUS_HI);
302 ngwritel((fwio + 512) & 0xffffffff, NGENE_EVENT);
303 ngwritel((fwio + 512) >> 32, NGENE_EVENT_HI);
304 }
305
306 memcpy(dev->FWInterfaceBuffer, com->cmd.raw8, com->in_len + 2);
307
308 if (dev->BootFirmware)
309 ngcpyto(HOST_TO_NGENE, com->cmd.raw8, com->in_len + 2);
310
311 spin_lock_irq(&dev->cmd_lock);
312 tmpCmdDoneByte = dev->ngenetohost + com->out_len;
313 if (!com->out_len)
314 tmpCmdDoneByte++;
315 *tmpCmdDoneByte = 0;
316 dev->ngenetohost[0] = 0;
317 dev->ngenetohost[1] = 0;
318 dev->CmdDoneByte = tmpCmdDoneByte;
319 spin_unlock_irq(&dev->cmd_lock);
320
321 /* Notify 8051. */
322 ngwritel(1, FORCE_INT);
323
324 ret = wait_event_timeout(dev->cmd_wq, dev->cmd_done == 1, 2 * HZ);
325 if (!ret) {
326 /*ngwritel(0, FORCE_NMI);*/
327
328 printk(KERN_ERR DEVICE_NAME
329 ": Command timeout cmd=%02x prev=%02x\n",
330 com->cmd.hdr.Opcode, dev->prev_cmd);
b1ec9532 331 dump_command_io(dev);
dae52d00
MB		 332 return -1;
333 }
334 if (com->cmd.hdr.Opcode == CMD_FWLOAD_FINISH)
335 dev->BootFirmware = 0;
336
337 dev->prev_cmd = com->cmd.hdr.Opcode;
dae52d00
MB		 338
339 if (!com->out_len)
340 return 0;
341
342 memcpy(com->cmd.raw8, dev->ngenetohost, com->out_len);
343
344 return 0;
345}
346
cb1c0f8e 347int ngene_command(struct ngene *dev, struct ngene_command *com)
dae52d00
MB		 348{
349 int result;
350
351 down(&dev->cmd_mutex);
352 result = ngene_command_mutex(dev, com);
353 up(&dev->cmd_mutex);
354 return result;
355}
356
dae52d00 357
dae52d00
MB		 358static int ngene_command_load_firmware(struct ngene *dev,
359 u8 *ngene_fw, u32 size)
360{
361#define FIRSTCHUNK (1024)
362 u32 cleft;
363 struct ngene_command com;
364
365 com.cmd.hdr.Opcode = CMD_FWLOAD_PREPARE;
366 com.cmd.hdr.Length = 0;
367 com.in_len = 0;
368 com.out_len = 0;
369
370 ngene_command(dev, &com);
371
372 cleft = (size + 3) & ~3;
373 if (cleft > FIRSTCHUNK) {
374 ngcpyto(PROGRAM_SRAM + FIRSTCHUNK, ngene_fw + FIRSTCHUNK,
375 cleft - FIRSTCHUNK);
376 cleft = FIRSTCHUNK;
377 }
dae52d00
MB		 378 ngcpyto(DATA_FIFO_AREA, ngene_fw, cleft);
379
380 memset(&com, 0, sizeof(struct ngene_command));
381 com.cmd.hdr.Opcode = CMD_FWLOAD_FINISH;
382 com.cmd.hdr.Length = 4;
383 com.cmd.FWLoadFinish.Address = DATA_FIFO_AREA;
384 com.cmd.FWLoadFinish.Length = (unsigned short)cleft;
385 com.in_len = 4;
386 com.out_len = 0;
387
388 return ngene_command(dev, &com);
389}
390
dae52d00
MB		 391
392static int ngene_command_config_buf(struct ngene *dev, u8 config)
393{
394 struct ngene_command com;
395
396 com.cmd.hdr.Opcode = CMD_CONFIGURE_BUFFER;
397 com.cmd.hdr.Length = 1;
398 com.cmd.ConfigureBuffers.config = config;
399 com.in_len = 1;
400 com.out_len = 0;
401
402 if (ngene_command(dev, &com) < 0)
403 return -EIO;
404 return 0;
405}
406
407static int ngene_command_config_free_buf(struct ngene *dev, u8 *config)
408{
409 struct ngene_command com;
410
411 com.cmd.hdr.Opcode = CMD_CONFIGURE_FREE_BUFFER;
412 com.cmd.hdr.Length = 6;
413 memcpy(&com.cmd.ConfigureBuffers.config, config, 6);
414 com.in_len = 6;
415 com.out_len = 0;
416
417 if (ngene_command(dev, &com) < 0)
418 return -EIO;
419
420 return 0;
421}
422
cb1c0f8e 423int ngene_command_gpio_set(struct ngene *dev, u8 select, u8 level)
dae52d00
MB		 424{
425 struct ngene_command com;
426
427 com.cmd.hdr.Opcode = CMD_SET_GPIO_PIN;
428 com.cmd.hdr.Length = 1;
429 com.cmd.SetGpioPin.select = select | (level << 7);
430 com.in_len = 1;
431 com.out_len = 0;
432
433 return ngene_command(dev, &com);
434}
435
dae52d00
MB		 436
437/*
438 02000640 is sample on rising edge.
439 02000740 is sample on falling edge.
440 02000040 is ignore "valid" signal
441
442 0: FD_CTL1 Bit 7,6 must be 0,1
443 7 disable(fw controlled)
444 6 0-AUX,1-TS
445 5 0-par,1-ser
446 4 0-lsb/1-msb
447 3,2 reserved
448 1,0 0-no sync, 1-use ext. start, 2-use 0x47, 3-both
449 1: FD_CTL2 has 3-valid must be hi, 2-use valid, 1-edge
450 2: FD_STA is read-only. 0-sync
451 3: FD_INSYNC is number of 47s to trigger "in sync".
452 4: FD_OUTSYNC is number of 47s to trigger "out of sync".
453 5: FD_MAXBYTE1 is low-order of bytes per packet.
454 6: FD_MAXBYTE2 is high-order of bytes per packet.
455 7: Top byte is unused.
456*/
457
458/****************************************************************************/
459
0abf2629 460static u8 TSFeatureDecoderSetup[8 * 5] = {
dae52d00
MB		 461 0x42, 0x00, 0x00, 0x02, 0x02, 0xbc, 0x00, 0x00,
462 0x40, 0x06, 0x00, 0x02, 0x02, 0xbc, 0x00, 0x00, /* DRXH */
463 0x71, 0x07, 0x00, 0x02, 0x02, 0xbc, 0x00, 0x00, /* DRXHser */
464 0x72, 0x06, 0x00, 0x02, 0x02, 0xbc, 0x00, 0x00, /* S2ser */
0abf2629 465 0x40, 0x07, 0x00, 0x02, 0x02, 0xbc, 0x00, 0x00, /* LGDT3303 */
dae52d00
MB		 466};
467
468/* Set NGENE I2S Config to 16 bit packed */
469static u8 I2SConfiguration[] = {
470 0x00, 0x10, 0x00, 0x00,
471 0x80, 0x10, 0x00, 0x00,
472};
473
474static u8 SPDIFConfiguration[10] = {
475 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
476};
477
478/* Set NGENE I2S Config to transport stream compatible mode */
479
480static u8 TS_I2SConfiguration[4] = { 0x3E, 0x1A, 0x00, 0x00 }; /*3e 18 00 00 ?*/
481
482static u8 TS_I2SOutConfiguration[4] = { 0x80, 0x20, 0x00, 0x00 };
483
484static u8 ITUDecoderSetup[4][16] = {
485 {0x1c, 0x13, 0x01, 0x68, 0x3d, 0x90, 0x14, 0x20, /* SDTV */
486 0x00, 0x00, 0x01, 0xb0, 0x9c, 0x00, 0x00, 0x00},
487 {0x9c, 0x03, 0x23, 0xC0, 0x60, 0x0E, 0x13, 0x00,
488 0x00, 0x00, 0x00, 0x01, 0xB0, 0x00, 0x00, 0x00},
489 {0x9f, 0x00, 0x23, 0xC0, 0x60, 0x0F, 0x13, 0x00, /* HDTV 1080i50 */
490 0x00, 0x00, 0x00, 0x01, 0xB0, 0x00, 0x00, 0x00},
491 {0x9c, 0x01, 0x23, 0xC0, 0x60, 0x0E, 0x13, 0x00, /* HDTV 1080i60 */
492 0x00, 0x00, 0x00, 0x01, 0xB0, 0x00, 0x00, 0x00},
493};
494
495/*
496 * 50 48 60 gleich
497 * 27p50 9f 00 22 80 42 69 18 ...
498 * 27p60 93 00 22 80 82 69 1c ...
499 */
500
501/* Maxbyte to 1144 (for raw data) */
502static u8 ITUFeatureDecoderSetup[8] = {
503 0x00, 0x00, 0x00, 0x00, 0x00, 0x78, 0x04, 0x00
504};
505
1899e97c 506void FillTSBuffer(void *Buffer, int Length, u32 Flags)
dae52d00
MB		 507{
508 u32 *ptr = Buffer;
509
fd9be0dc 510 memset(Buffer, 0xff, Length);
dae52d00
MB		 511 while (Length > 0) {
512 if (Flags & DF_SWAP32)
513 *ptr = 0x471FFF10;
514 else
515 *ptr = 0x10FF1F47;
516 ptr += (188 / 4);
517 Length -= 188;
518 }
519}
520
dae52d00
MB		 521
522static void flush_buffers(struct ngene_channel *chan)
523{
524 u8 val;
525
526 do {
527 msleep(1);
528 spin_lock_irq(&chan->state_lock);
529 val = chan->nextBuffer->ngeneBuffer.SR.Flags & 0x80;
530 spin_unlock_irq(&chan->state_lock);
531 } while (val);
532}
533
534static void clear_buffers(struct ngene_channel *chan)
535{
536 struct SBufferHeader *Cur = chan->nextBuffer;
537
538 do {
539 memset(&Cur->ngeneBuffer.SR, 0, sizeof(Cur->ngeneBuffer.SR));
540 if (chan->mode & NGENE_IO_TSOUT)
541 FillTSBuffer(Cur->Buffer1,
542 chan->Capture1Length,
543 chan->DataFormatFlags);
544 Cur = Cur->Next;
545 } while (Cur != chan->nextBuffer);
546
547 if (chan->mode & NGENE_IO_TSOUT) {
548 chan->nextBuffer->ngeneBuffer.SR.DTOUpdate =
549 chan->AudioDTOValue;
550 chan->AudioDTOUpdated = 0;
551
552 Cur = chan->TSIdleBuffer.Head;
553
554 do {
555 memset(&Cur->ngeneBuffer.SR, 0,
556 sizeof(Cur->ngeneBuffer.SR));
557 FillTSBuffer(Cur->Buffer1,
558 chan->Capture1Length,
559 chan->DataFormatFlags);
560 Cur = Cur->Next;
561 } while (Cur != chan->TSIdleBuffer.Head);
562 }
563}
564
9fdd7976
OE		 565static int ngene_command_stream_control(struct ngene *dev, u8 stream,
566 u8 control, u8 mode, u8 flags)
dae52d00
MB		 567{
568 struct ngene_channel *chan = &dev->channel[stream];
569 struct ngene_command com;
570 u16 BsUVI = ((stream & 1) ? 0x9400 : 0x9300);
571 u16 BsSDI = ((stream & 1) ? 0x9600 : 0x9500);
572 u16 BsSPI = ((stream & 1) ? 0x9800 : 0x9700);
573 u16 BsSDO = 0x9B00;
574
575 /* down(&dev->stream_mutex); */
576 while (down_trylock(&dev->stream_mutex)) {
577 printk(KERN_INFO DEVICE_NAME ": SC locked\n");
578 msleep(1);
579 }
580 memset(&com, 0, sizeof(com));
581 com.cmd.hdr.Opcode = CMD_CONTROL;
582 com.cmd.hdr.Length = sizeof(struct FW_STREAM_CONTROL) - 2;
583 com.cmd.StreamControl.Stream = stream | (control ? 8 : 0);
584 if (chan->mode & NGENE_IO_TSOUT)
585 com.cmd.StreamControl.Stream |= 0x07;
586 com.cmd.StreamControl.Control = control |
587 (flags & SFLAG_ORDER_LUMA_CHROMA);
588 com.cmd.StreamControl.Mode = mode;
589 com.in_len = sizeof(struct FW_STREAM_CONTROL);
590 com.out_len = 0;
591
44cdd064
OE		 592 dprintk(KERN_INFO DEVICE_NAME
593 ": Stream=%02x, Control=%02x, Mode=%02x\n",
594 com.cmd.StreamControl.Stream, com.cmd.StreamControl.Control,
595 com.cmd.StreamControl.Mode);
596
dae52d00
MB		 597 chan->Mode = mode;
598
599 if (!(control & 0x80)) {
600 spin_lock_irq(&chan->state_lock);
601 if (chan->State == KSSTATE_RUN) {
602 chan->State = KSSTATE_ACQUIRE;
603 chan->HWState = HWSTATE_STOP;
604 spin_unlock_irq(&chan->state_lock);
605 if (ngene_command(dev, &com) < 0) {
606 up(&dev->stream_mutex);
607 return -1;
608 }
609 /* clear_buffers(chan); */
610 flush_buffers(chan);
611 up(&dev->stream_mutex);
612 return 0;
613 }
614 spin_unlock_irq(&chan->state_lock);
615 up(&dev->stream_mutex);
616 return 0;
617 }
618
619 if (mode & SMODE_AUDIO_CAPTURE) {
620 com.cmd.StreamControl.CaptureBlockCount =
621 chan->Capture1Length / AUDIO_BLOCK_SIZE;
622 com.cmd.StreamControl.Buffer_Address = chan->RingBuffer.PAHead;
623 } else if (mode & SMODE_TRANSPORT_STREAM) {
624 com.cmd.StreamControl.CaptureBlockCount =
625 chan->Capture1Length / TS_BLOCK_SIZE;
626 com.cmd.StreamControl.MaxLinesPerField =
627 chan->Capture1Length / TS_BLOCK_SIZE;
628 com.cmd.StreamControl.Buffer_Address =
629 chan->TSRingBuffer.PAHead;
630 if (chan->mode & NGENE_IO_TSOUT) {
631 com.cmd.StreamControl.BytesPerVBILine =
632 chan->Capture1Length / TS_BLOCK_SIZE;
633 com.cmd.StreamControl.Stream |= 0x07;
634 }
635 } else {
636 com.cmd.StreamControl.BytesPerVideoLine = chan->nBytesPerLine;
637 com.cmd.StreamControl.MaxLinesPerField = chan->nLines;
638 com.cmd.StreamControl.MinLinesPerField = 100;
639 com.cmd.StreamControl.Buffer_Address = chan->RingBuffer.PAHead;
640
641 if (mode & SMODE_VBI_CAPTURE) {
642 com.cmd.StreamControl.MaxVBILinesPerField =
643 chan->nVBILines;
644 com.cmd.StreamControl.MinVBILinesPerField = 0;
645 com.cmd.StreamControl.BytesPerVBILine =
646 chan->nBytesPerVBILine;
647 }
648 if (flags & SFLAG_COLORBAR)
649 com.cmd.StreamControl.Stream |= 0x04;
650 }
651
652 spin_lock_irq(&chan->state_lock);
653 if (mode & SMODE_AUDIO_CAPTURE) {
654 chan->nextBuffer = chan->RingBuffer.Head;
655 if (mode & SMODE_AUDIO_SPDIF) {
656 com.cmd.StreamControl.SetupDataLen =
657 sizeof(SPDIFConfiguration);
658 com.cmd.StreamControl.SetupDataAddr = BsSPI;
659 memcpy(com.cmd.StreamControl.SetupData,
660 SPDIFConfiguration, sizeof(SPDIFConfiguration));
661 } else {
662 com.cmd.StreamControl.SetupDataLen = 4;
663 com.cmd.StreamControl.SetupDataAddr = BsSDI;
664 memcpy(com.cmd.StreamControl.SetupData,
665 I2SConfiguration +
666 4 * dev->card_info->i2s[stream], 4);
667 }
668 } else if (mode & SMODE_TRANSPORT_STREAM) {
669 chan->nextBuffer = chan->TSRingBuffer.Head;
670 if (stream >= STREAM_AUDIOIN1) {
671 if (chan->mode & NGENE_IO_TSOUT) {
672 com.cmd.StreamControl.SetupDataLen =
673 sizeof(TS_I2SOutConfiguration);
674 com.cmd.StreamControl.SetupDataAddr = BsSDO;
675 memcpy(com.cmd.StreamControl.SetupData,
676 TS_I2SOutConfiguration,
677 sizeof(TS_I2SOutConfiguration));
678 } else {
679 com.cmd.StreamControl.SetupDataLen =
680 sizeof(TS_I2SConfiguration);
681 com.cmd.StreamControl.SetupDataAddr = BsSDI;
682 memcpy(com.cmd.StreamControl.SetupData,
683 TS_I2SConfiguration,
684 sizeof(TS_I2SConfiguration));
685 }
686 } else {
687 com.cmd.StreamControl.SetupDataLen = 8;
688 com.cmd.StreamControl.SetupDataAddr = BsUVI + 0x10;
689 memcpy(com.cmd.StreamControl.SetupData,
690 TSFeatureDecoderSetup +
691 8 * dev->card_info->tsf[stream], 8);
692 }
693 } else {
694 chan->nextBuffer = chan->RingBuffer.Head;
695 com.cmd.StreamControl.SetupDataLen =
696 16 + sizeof(ITUFeatureDecoderSetup);
697 com.cmd.StreamControl.SetupDataAddr = BsUVI;
698 memcpy(com.cmd.StreamControl.SetupData,
699 ITUDecoderSetup[chan->itumode], 16);
700 memcpy(com.cmd.StreamControl.SetupData + 16,
701 ITUFeatureDecoderSetup, sizeof(ITUFeatureDecoderSetup));
702 }
703 clear_buffers(chan);
704 chan->State = KSSTATE_RUN;
705 if (mode & SMODE_TRANSPORT_STREAM)
706 chan->HWState = HWSTATE_RUN;
707 else
708 chan->HWState = HWSTATE_STARTUP;
709 spin_unlock_irq(&chan->state_lock);
710
711 if (ngene_command(dev, &com) < 0) {
712 up(&dev->stream_mutex);
713 return -1;
714 }
715 up(&dev->stream_mutex);
716 return 0;
717}
718
1899e97c 719void set_transfer(struct ngene_channel *chan, int state)
dae52d00
MB		 720{
721 u8 control = 0, mode = 0, flags = 0;
722 struct ngene *dev = chan->dev;
723 int ret;
724
dae52d00
MB		 725 /*
726 printk(KERN_INFO DEVICE_NAME ": st %d\n", state);
727 msleep(100);
728 */
729
730 if (state) {
731 if (chan->running) {
732 printk(KERN_INFO DEVICE_NAME ": already running\n");
733 return;
734 }
735 } else {
736 if (!chan->running) {
737 printk(KERN_INFO DEVICE_NAME ": already stopped\n");
738 return;
739 }
740 }
741
742 if (dev->card_info->switch_ctrl)
743 dev->card_info->switch_ctrl(chan, 1, state ^ 1);
744
745 if (state) {
746 spin_lock_irq(&chan->state_lock);
747
748 /* printk(KERN_INFO DEVICE_NAME ": lock=%08x\n",
749 ngreadl(0x9310)); */
126cd4bc 750 dvb_ringbuffer_flush(&dev->tsout_rbuf);
dae52d00
MB		 751 control = 0x80;
752 if (chan->mode & (NGENE_IO_TSIN | NGENE_IO_TSOUT)) {
753 chan->Capture1Length = 512 * 188;
754 mode = SMODE_TRANSPORT_STREAM;
755 }
756 if (chan->mode & NGENE_IO_TSOUT) {
757 chan->pBufferExchange = tsout_exchange;
758 /* 0x66666666 = 50MHz *2^33 /250MHz */
759 chan->AudioDTOValue = 0x66666666;
760 /* set_dto(chan, 38810700+1000); */
761 /* set_dto(chan, 19392658); */
762 }
763 if (chan->mode & NGENE_IO_TSIN)
764 chan->pBufferExchange = tsin_exchange;
765 /* ngwritel(0, 0x9310); */
766 spin_unlock_irq(&chan->state_lock);
767 } else
768 ;/* printk(KERN_INFO DEVICE_NAME ": lock=%08x\n",
769 ngreadl(0x9310)); */
770
771 ret = ngene_command_stream_control(dev, chan->number,
772 control, mode, flags);
773 if (!ret)
774 chan->running = state;
775 else
776 printk(KERN_ERR DEVICE_NAME ": set_transfer %d failed\n",
777 state);
778 if (!state) {
779 spin_lock_irq(&chan->state_lock);
7b1fc72c 780 chan->pBufferExchange = NULL;
126cd4bc 781 dvb_ringbuffer_flush(&dev->tsout_rbuf);
dae52d00
MB		 782 spin_unlock_irq(&chan->state_lock);
783 }
784}
785
dae52d00
MB		 786
787/****************************************************************************/
788/* nGene hardware init and release functions ********************************/
789/****************************************************************************/
790
9fdd7976 791static void free_ringbuffer(struct ngene *dev, struct SRingBufferDescriptor *rb)
dae52d00
MB		 792{
793 struct SBufferHeader *Cur = rb->Head;
794 u32 j;
795
796 if (!Cur)
797 return;
798
799 for (j = 0; j < rb->NumBuffers; j++, Cur = Cur->Next) {
800 if (Cur->Buffer1)
801 pci_free_consistent(dev->pci_dev,
802 rb->Buffer1Length,
803 Cur->Buffer1,
804 Cur->scList1->Address);
805
806 if (Cur->Buffer2)
807 pci_free_consistent(dev->pci_dev,
808 rb->Buffer2Length,
809 Cur->Buffer2,
810 Cur->scList2->Address);
811 }
812
813 if (rb->SCListMem)
814 pci_free_consistent(dev->pci_dev, rb->SCListMemSize,
815 rb->SCListMem, rb->PASCListMem);
816
817 pci_free_consistent(dev->pci_dev, rb->MemSize, rb->Head, rb->PAHead);
818}
819
9fdd7976 820static void free_idlebuffer(struct ngene *dev,
dae52d00
MB		 821 struct SRingBufferDescriptor *rb,
822 struct SRingBufferDescriptor *tb)
823{
824 int j;
825 struct SBufferHeader *Cur = tb->Head;
826
827 if (!rb->Head)
828 return;
829 free_ringbuffer(dev, rb);
830 for (j = 0; j < tb->NumBuffers; j++, Cur = Cur->Next) {
7b1fc72c
MN		 831 Cur->Buffer2 = NULL;
832 Cur->scList2 = NULL;
dae52d00
MB		 833 Cur->ngeneBuffer.Address_of_first_entry_2 = 0;
834 Cur->ngeneBuffer.Number_of_entries_2 = 0;
835 }
836}
837
9fdd7976 838static void free_common_buffers(struct ngene *dev)
dae52d00
MB		 839{
840 u32 i;
841 struct ngene_channel *chan;
842
843 for (i = STREAM_VIDEOIN1; i < MAX_STREAM; i++) {
844 chan = &dev->channel[i];
845 free_idlebuffer(dev, &chan->TSIdleBuffer, &chan->TSRingBuffer);
846 free_ringbuffer(dev, &chan->RingBuffer);
847 free_ringbuffer(dev, &chan->TSRingBuffer);
848 }
849
850 if (dev->OverflowBuffer)
851 pci_free_consistent(dev->pci_dev,
852 OVERFLOW_BUFFER_SIZE,
853 dev->OverflowBuffer, dev->PAOverflowBuffer);
854
855 if (dev->FWInterfaceBuffer)
856 pci_free_consistent(dev->pci_dev,
857 4096,
858 dev->FWInterfaceBuffer,
859 dev->PAFWInterfaceBuffer);
860}
861
862/****************************************************************************/
863/* Ring buffer handling *****************************************************/
864/****************************************************************************/
865
9fdd7976 866static int create_ring_buffer(struct pci_dev *pci_dev,
dae52d00
MB		 867 struct SRingBufferDescriptor *descr, u32 NumBuffers)
868{
869 dma_addr_t tmp;
870 struct SBufferHeader *Head;
871 u32 i;
872 u32 MemSize = SIZEOF_SBufferHeader * NumBuffers;
873 u64 PARingBufferHead;
874 u64 PARingBufferCur;
875 u64 PARingBufferNext;
876 struct SBufferHeader *Cur, *Next;
877
7b1fc72c 878 descr->Head = NULL;
dae52d00
MB		 879 descr->MemSize = 0;
880 descr->PAHead = 0;
881 descr->NumBuffers = 0;
882
883 if (MemSize < 4096)
884 MemSize = 4096;
885
886 Head = pci_alloc_consistent(pci_dev, MemSize, &tmp);
887 PARingBufferHead = tmp;
888
889 if (!Head)
890 return -ENOMEM;
891
892 memset(Head, 0, MemSize);
893
894 PARingBufferCur = PARingBufferHead;
895 Cur = Head;
896
897 for (i = 0; i < NumBuffers - 1; i++) {
898 Next = (struct SBufferHeader *)
899 (((u8 *) Cur) + SIZEOF_SBufferHeader);
900 PARingBufferNext = PARingBufferCur + SIZEOF_SBufferHeader;
901 Cur->Next = Next;
902 Cur->ngeneBuffer.Next = PARingBufferNext;
903 Cur = Next;
904 PARingBufferCur = PARingBufferNext;
905 }
906 /* Last Buffer points back to first one */
907 Cur->Next = Head;
908 Cur->ngeneBuffer.Next = PARingBufferHead;
909
910 descr->Head = Head;
911 descr->MemSize = MemSize;
912 descr->PAHead = PARingBufferHead;
913 descr->NumBuffers = NumBuffers;
914
915 return 0;
916}
917
918static int AllocateRingBuffers(struct pci_dev *pci_dev,
919 dma_addr_t of,
920 struct SRingBufferDescriptor *pRingBuffer,
921 u32 Buffer1Length, u32 Buffer2Length)
922{
923 dma_addr_t tmp;
924 u32 i, j;
925 int status = 0;
926 u32 SCListMemSize = pRingBuffer->NumBuffers
927 * ((Buffer2Length != 0) ? (NUM_SCATTER_GATHER_ENTRIES * 2) :
928 NUM_SCATTER_GATHER_ENTRIES)
929 * sizeof(struct HW_SCATTER_GATHER_ELEMENT);
930
931 u64 PASCListMem;
684688d8 932 struct HW_SCATTER_GATHER_ELEMENT *SCListEntry;
dae52d00
MB		 933 u64 PASCListEntry;
934 struct SBufferHeader *Cur;
935 void *SCListMem;
936
937 if (SCListMemSize < 4096)
938 SCListMemSize = 4096;
939
940 SCListMem = pci_alloc_consistent(pci_dev, SCListMemSize, &tmp);
941
942 PASCListMem = tmp;
943 if (SCListMem == NULL)
944 return -ENOMEM;
945
946 memset(SCListMem, 0, SCListMemSize);
947
948 pRingBuffer->SCListMem = SCListMem;
949 pRingBuffer->PASCListMem = PASCListMem;
950 pRingBuffer->SCListMemSize = SCListMemSize;
951 pRingBuffer->Buffer1Length = Buffer1Length;
952 pRingBuffer->Buffer2Length = Buffer2Length;
953
684688d8 954 SCListEntry = SCListMem;
dae52d00
MB		 955 PASCListEntry = PASCListMem;
956 Cur = pRingBuffer->Head;
957
958 for (i = 0; i < pRingBuffer->NumBuffers; i += 1, Cur = Cur->Next) {
959 u64 PABuffer;
960
961 void *Buffer = pci_alloc_consistent(pci_dev, Buffer1Length,
962 &tmp);
963 PABuffer = tmp;
964
965 if (Buffer == NULL)
966 return -ENOMEM;
967
968 Cur->Buffer1 = Buffer;
969
970 SCListEntry->Address = PABuffer;
971 SCListEntry->Length = Buffer1Length;
972
973 Cur->scList1 = SCListEntry;
974 Cur->ngeneBuffer.Address_of_first_entry_1 = PASCListEntry;
975 Cur->ngeneBuffer.Number_of_entries_1 =
976 NUM_SCATTER_GATHER_ENTRIES;
977
978 SCListEntry += 1;
979 PASCListEntry += sizeof(struct HW_SCATTER_GATHER_ELEMENT);
980
981#if NUM_SCATTER_GATHER_ENTRIES > 1
982 for (j = 0; j < NUM_SCATTER_GATHER_ENTRIES - 1; j += 1) {
983 SCListEntry->Address = of;
984 SCListEntry->Length = OVERFLOW_BUFFER_SIZE;
985 SCListEntry += 1;
986 PASCListEntry +=
987 sizeof(struct HW_SCATTER_GATHER_ELEMENT);
988 }
989#endif
990
991 if (!Buffer2Length)
992 continue;
993
994 Buffer = pci_alloc_consistent(pci_dev, Buffer2Length, &tmp);
995 PABuffer = tmp;
996
997 if (Buffer == NULL)
998 return -ENOMEM;
999
1000 Cur->Buffer2 = Buffer;
1001
1002 SCListEntry->Address = PABuffer;
1003 SCListEntry->Length = Buffer2Length;
1004
1005 Cur->scList2 = SCListEntry;
1006 Cur->ngeneBuffer.Address_of_first_entry_2 = PASCListEntry;
1007 Cur->ngeneBuffer.Number_of_entries_2 =
1008 NUM_SCATTER_GATHER_ENTRIES;
1009
1010 SCListEntry += 1;
1011 PASCListEntry += sizeof(struct HW_SCATTER_GATHER_ELEMENT);
1012
1013#if NUM_SCATTER_GATHER_ENTRIES > 1
1014 for (j = 0; j < NUM_SCATTER_GATHER_ENTRIES - 1; j++) {
1015 SCListEntry->Address = of;
1016 SCListEntry->Length = OVERFLOW_BUFFER_SIZE;
1017 SCListEntry += 1;
1018 PASCListEntry +=
1019 sizeof(struct HW_SCATTER_GATHER_ELEMENT);
1020 }
1021#endif
1022
1023 }
1024
1025 return status;
1026}
1027
1028static int FillTSIdleBuffer(struct SRingBufferDescriptor *pIdleBuffer,
1029 struct SRingBufferDescriptor *pRingBuffer)
1030{
1031 int status = 0;
1032
1033 /* Copy pointer to scatter gather list in TSRingbuffer
1034 structure for buffer 2
1035 Load number of buffer
1036 */
1037 u32 n = pRingBuffer->NumBuffers;
1038
1039 /* Point to first buffer entry */
1040 struct SBufferHeader *Cur = pRingBuffer->Head;
1041 int i;
1042 /* Loop thru all buffer and set Buffer 2 pointers to TSIdlebuffer */
1043 for (i = 0; i < n; i++) {
1044 Cur->Buffer2 = pIdleBuffer->Head->Buffer1;
1045 Cur->scList2 = pIdleBuffer->Head->scList1;
1046 Cur->ngeneBuffer.Address_of_first_entry_2 =
1047 pIdleBuffer->Head->ngeneBuffer.
1048 Address_of_first_entry_1;
1049 Cur->ngeneBuffer.Number_of_entries_2 =
1050 pIdleBuffer->Head->ngeneBuffer.Number_of_entries_1;
1051 Cur = Cur->Next;
1052 }
1053 return status;
1054}
1055
1056static u32 RingBufferSizes[MAX_STREAM] = {
1057 RING_SIZE_VIDEO,
1058 RING_SIZE_VIDEO,
1059 RING_SIZE_AUDIO,
1060 RING_SIZE_AUDIO,
1061 RING_SIZE_AUDIO,
1062};
1063
1064static u32 Buffer1Sizes[MAX_STREAM] = {
1065 MAX_VIDEO_BUFFER_SIZE,
1066 MAX_VIDEO_BUFFER_SIZE,
1067 MAX_AUDIO_BUFFER_SIZE,
1068 MAX_AUDIO_BUFFER_SIZE,
1069 MAX_AUDIO_BUFFER_SIZE
1070};
1071
1072static u32 Buffer2Sizes[MAX_STREAM] = {
1073 MAX_VBI_BUFFER_SIZE,
1074 MAX_VBI_BUFFER_SIZE,
1075 0,
1076 0,
1077 0
1078};
1079
dae52d00
MB		 1080
1081static int AllocCommonBuffers(struct ngene *dev)
1082{
1083 int status = 0, i;
1084
1085 dev->FWInterfaceBuffer = pci_alloc_consistent(dev->pci_dev, 4096,
1086 &dev->PAFWInterfaceBuffer);
1087 if (!dev->FWInterfaceBuffer)
1088 return -ENOMEM;
1089 dev->hosttongene = dev->FWInterfaceBuffer;
1090 dev->ngenetohost = dev->FWInterfaceBuffer + 256;
1091 dev->EventBuffer = dev->FWInterfaceBuffer + 512;
1092
1093 dev->OverflowBuffer = pci_alloc_consistent(dev->pci_dev,
1094 OVERFLOW_BUFFER_SIZE,
1095 &dev->PAOverflowBuffer);
1096 if (!dev->OverflowBuffer)
1097 return -ENOMEM;
1098 memset(dev->OverflowBuffer, 0, OVERFLOW_BUFFER_SIZE);
1099
1100 for (i = STREAM_VIDEOIN1; i < MAX_STREAM; i++) {
1101 int type = dev->card_info->io_type[i];
1102
1103 dev->channel[i].State = KSSTATE_STOP;
1104
1105 if (type & (NGENE_IO_TV | NGENE_IO_HDTV | NGENE_IO_AIN)) {
1106 status = create_ring_buffer(dev->pci_dev,
1107 &dev->channel[i].RingBuffer,
1108 RingBufferSizes[i]);
1109 if (status < 0)
1110 break;
1111
1112 if (type & (NGENE_IO_TV | NGENE_IO_AIN)) {
1113 status = AllocateRingBuffers(dev->pci_dev,
1114 dev->
1115 PAOverflowBuffer,
1116 &dev->channel[i].
1117 RingBuffer,
1118 Buffer1Sizes[i],
1119 Buffer2Sizes[i]);
1120 if (status < 0)
1121 break;
1122 } else if (type & NGENE_IO_HDTV) {
1123 status = AllocateRingBuffers(dev->pci_dev,
1124 dev->
1125 PAOverflowBuffer,
1126 &dev->channel[i].
1127 RingBuffer,
1128 MAX_HDTV_BUFFER_SIZE,
1129 0);
1130 if (status < 0)
1131 break;
1132 }
1133 }
1134
1135 if (type & (NGENE_IO_TSIN | NGENE_IO_TSOUT)) {
1136
1137 status = create_ring_buffer(dev->pci_dev,
1138 &dev->channel[i].
1139 TSRingBuffer, RING_SIZE_TS);
1140 if (status < 0)
1141 break;
1142
1143 status = AllocateRingBuffers(dev->pci_dev,
1144 dev->PAOverflowBuffer,
1145 &dev->channel[i].
1146 TSRingBuffer,
1147 MAX_TS_BUFFER_SIZE, 0);
1148 if (status)
1149 break;
1150 }
1151
1152 if (type & NGENE_IO_TSOUT) {
1153 status = create_ring_buffer(dev->pci_dev,
1154 &dev->channel[i].
1155 TSIdleBuffer, 1);
1156 if (status < 0)
1157 break;
1158 status = AllocateRingBuffers(dev->pci_dev,
1159 dev->PAOverflowBuffer,
1160 &dev->channel[i].
1161 TSIdleBuffer,
1162 MAX_TS_BUFFER_SIZE, 0);
1163 if (status)
1164 break;
1165 FillTSIdleBuffer(&dev->channel[i].TSIdleBuffer,
1166 &dev->channel[i].TSRingBuffer);
1167 }
1168 }
1169 return status;
1170}
1171
1172static void ngene_release_buffers(struct ngene *dev)
1173{
1174 if (dev->iomem)
1175 iounmap(dev->iomem);
1176 free_common_buffers(dev);
1177 vfree(dev->tsout_buf);
1178 vfree(dev->ain_buf);
1179 vfree(dev->vin_buf);
1180 vfree(dev);
1181}
1182
1183static int ngene_get_buffers(struct ngene *dev)
1184{
1185 if (AllocCommonBuffers(dev))
1186 return -ENOMEM;
1187 if (dev->card_info->io_type[4] & NGENE_IO_TSOUT) {
1188 dev->tsout_buf = vmalloc(TSOUT_BUF_SIZE);
1189 if (!dev->tsout_buf)
1190 return -ENOMEM;
1191 dvb_ringbuffer_init(&dev->tsout_rbuf,
1192 dev->tsout_buf, TSOUT_BUF_SIZE);
1193 }
1194 if (dev->card_info->io_type[2] & NGENE_IO_AIN) {
1195 dev->ain_buf = vmalloc(AIN_BUF_SIZE);
1196 if (!dev->ain_buf)
1197 return -ENOMEM;
1198 dvb_ringbuffer_init(&dev->ain_rbuf, dev->ain_buf, AIN_BUF_SIZE);
1199 }
1200 if (dev->card_info->io_type[0] & NGENE_IO_HDTV) {
1201 dev->vin_buf = vmalloc(VIN_BUF_SIZE);
1202 if (!dev->vin_buf)
1203 return -ENOMEM;
1204 dvb_ringbuffer_init(&dev->vin_rbuf, dev->vin_buf, VIN_BUF_SIZE);
1205 }
1206 dev->iomem = ioremap(pci_resource_start(dev->pci_dev, 0),
1207 pci_resource_len(dev->pci_dev, 0));
1208 if (!dev->iomem)
1209 return -ENOMEM;
1210
1211 return 0;
1212}
1213
1214static void ngene_init(struct ngene *dev)
1215{
1216 int i;
1217
1218 tasklet_init(&dev->event_tasklet, event_tasklet, (unsigned long)dev);
1219
1220 memset_io(dev->iomem + 0xc000, 0x00, 0x220);
1221 memset_io(dev->iomem + 0xc400, 0x00, 0x100);
1222
1223 for (i = 0; i < MAX_STREAM; i++) {
1224 dev->channel[i].dev = dev;
1225 dev->channel[i].number = i;
1226 }
1227
1228 dev->fw_interface_version = 0;
1229
1230 ngwritel(0, NGENE_INT_ENABLE);
1231
1232 dev->icounts = ngreadl(NGENE_INT_COUNTS);
1233
1234 dev->device_version = ngreadl(DEV_VER) & 0x0f;
1235 printk(KERN_INFO DEVICE_NAME ": Device version %d\n",
1236 dev->device_version);
1237}
1238
1239static int ngene_load_firm(struct ngene *dev)
1240{
1241 u32 size;
1242 const struct firmware *fw = NULL;
1243 u8 *ngene_fw;
1244 char *fw_name;
1245 int err, version;
1246
1247 version = dev->card_info->fw_version;
1248
1249 switch (version) {
1250 default:
1251 case 15:
1252 version = 15;
0027ebb7 1253 size = 23466;
dae52d00
MB		 1254 fw_name = "ngene_15.fw";
1255 break;
1256 case 16:
0027ebb7 1257 size = 23498;
dae52d00
MB		 1258 fw_name = "ngene_16.fw";
1259 break;
1260 case 17:
0027ebb7 1261 size = 24446;
dae52d00
MB		 1262 fw_name = "ngene_17.fw";
1263 break;
1264 }
dae52d00 1265
dae52d00
MB		 1266 if (request_firmware(&fw, fw_name, &dev->pci_dev->dev) < 0) {
1267 printk(KERN_ERR DEVICE_NAME
0027ebb7 1268 ": Could not load firmware file %s.\n", fw_name);
dae52d00
MB		 1269 printk(KERN_INFO DEVICE_NAME
1270 ": Copy %s to your hotplug directory!\n", fw_name);
1271 return -1;
1272 }
0027ebb7
OE		 1273 if (size != fw->size) {
1274 printk(KERN_ERR DEVICE_NAME
1275 ": Firmware %s has invalid size!", fw_name);
1276 err = -1;
1277 } else {
1278 printk(KERN_INFO DEVICE_NAME
1279 ": Loading firmware file %s.\n", fw_name);
1280 ngene_fw = (u8 *) fw->data;
1281 err = ngene_command_load_firmware(dev, ngene_fw, size);
1282 }
1283
dae52d00 1284 release_firmware(fw);
0027ebb7 1285
dae52d00
MB		 1286 return err;
1287}
1288
1289static void ngene_stop(struct ngene *dev)
1290{
1291 down(&dev->cmd_mutex);
1292 i2c_del_adapter(&(dev->channel[0].i2c_adapter));
1293 i2c_del_adapter(&(dev->channel[1].i2c_adapter));
1294 ngwritel(0, NGENE_INT_ENABLE);
1295 ngwritel(0, NGENE_COMMAND);
1296 ngwritel(0, NGENE_COMMAND_HI);
1297 ngwritel(0, NGENE_STATUS);
1298 ngwritel(0, NGENE_STATUS_HI);
1299 ngwritel(0, NGENE_EVENT);
1300 ngwritel(0, NGENE_EVENT_HI);
1301 free_irq(dev->pci_dev->irq, dev);
43874181
OE		 1302 if (dev->msi_enabled)
1303 pci_disable_msi(dev->pci_dev);
dae52d00
MB		 1304}
1305
1306static int ngene_start(struct ngene *dev)
1307{
1308 int stat;
43874181 1309 unsigned long flags;
dae52d00
MB		 1310 int i;
1311
1312 pci_set_master(dev->pci_dev);
1313 ngene_init(dev);
1314
1315 stat = request_irq(dev->pci_dev->irq, irq_handler,
1316 IRQF_SHARED, "nGene",
1317 (void *)dev);
1318 if (stat < 0)
1319 return stat;
1320
1321 init_waitqueue_head(&dev->cmd_wq);
1322 init_waitqueue_head(&dev->tx_wq);
1323 init_waitqueue_head(&dev->rx_wq);
1324 sema_init(&dev->cmd_mutex, 1);
1325 sema_init(&dev->stream_mutex, 1);
1326 sema_init(&dev->pll_mutex, 1);
1327 sema_init(&dev->i2c_switch_mutex, 1);
1328 spin_lock_init(&dev->cmd_lock);
1329 for (i = 0; i < MAX_STREAM; i++)
1330 spin_lock_init(&dev->channel[i].state_lock);
1331 ngwritel(1, TIMESTAMPS);
1332
1333 ngwritel(1, NGENE_INT_ENABLE);
1334
1335 stat = ngene_load_firm(dev);
1336 if (stat < 0)
1337 goto fail;
1338
43874181
OE		 1339#ifdef CONFIG_PCI_MSI
1340 /* enable MSI if kernel and card support it */
1341 if (dev->card_info->msi_supported) {
1342 ngwritel(0, NGENE_INT_ENABLE);
1343 free_irq(dev->pci_dev->irq, dev);
1344 stat = pci_enable_msi(dev->pci_dev);
1345 if (stat) {
1346 printk(KERN_INFO DEVICE_NAME
1347 ": MSI not available\n");
1348 flags = IRQF_SHARED;
1349 } else {
1350 flags = 0;
1351 dev->msi_enabled = true;
1352 }
1353 stat = request_irq(dev->pci_dev->irq, irq_handler,
1354 flags, "nGene", dev);
1355 if (stat < 0)
1356 goto fail2;
1357 ngwritel(1, NGENE_INT_ENABLE);
1358 }
1359#endif
1360
dae52d00
MB		 1361 stat = ngene_i2c_init(dev, 0);
1362 if (stat < 0)
1363 goto fail;
1364
1365 stat = ngene_i2c_init(dev, 1);
1366 if (stat < 0)
1367 goto fail;
1368
1369 if (dev->card_info->fw_version == 17) {
684688d8
OE		 1370 u8 tsin4_config[6] = {
1371 3072 / 64, 3072 / 64, 0, 3072 / 64, 3072 / 64, 0};
1372 u8 default_config[6] = {
1373 4096 / 64, 4096 / 64, 0, 2048 / 64, 2048 / 64, 0};
dae52d00
MB		 1374 u8 *bconf = default_config;
1375
1376 if (dev->card_info->io_type[3] == NGENE_IO_TSIN)
1377 bconf = tsin4_config;
44cdd064 1378 dprintk(KERN_DEBUG DEVICE_NAME ": FW 17 buffer config\n");
dae52d00
MB		 1379 stat = ngene_command_config_free_buf(dev, bconf);
1380 } else {
1381 int bconf = BUFFER_CONFIG_4422;
dae52d00
MB		 1382 if (dev->card_info->io_type[3] == NGENE_IO_TSIN)
1383 bconf = BUFFER_CONFIG_3333;
1384 stat = ngene_command_config_buf(dev, bconf);
1385 }
43874181
OE		 1386 if (!stat)
1387 return stat;
1388
1389 /* otherwise error: fall through */
dae52d00
MB		 1390fail:
1391 ngwritel(0, NGENE_INT_ENABLE);
1392 free_irq(dev->pci_dev->irq, dev);
43874181
OE		 1393fail2:
1394 if (dev->msi_enabled)
1395 pci_disable_msi(dev->pci_dev);
dae52d00
MB		 1396 return stat;
1397}
1398
83f3c715
OE		 1399
1400
0abf2629 1401
83f3c715
OE		 1402/****************************************************************************/
1403/****************************************************************************/
1404/****************************************************************************/
1405
1406static void release_channel(struct ngene_channel *chan)
dae52d00
MB		 1407{
1408 struct dvb_demux *dvbdemux = &chan->demux;
1409 struct ngene *dev = chan->dev;
1410 struct ngene_info *ni = dev->card_info;
1411 int io = ni->io_type[chan->number];
1412
b1ec9532
OE		 1413#ifdef COMMAND_TIMEOUT_WORKAROUND
1414 if (chan->running)
1415 set_transfer(chan, 0);
1416#endif
1417
dae52d00
MB		 1418 tasklet_kill(&chan->demux_tasklet);
1419
1420 if (io & (NGENE_IO_TSIN | NGENE_IO_TSOUT)) {
dae52d00
MB		 1421 if (chan->fe) {
1422 dvb_unregister_frontend(chan->fe);
dc35c9ae 1423 dvb_frontend_detach(chan->fe);
7b1fc72c 1424 chan->fe = NULL;
dae52d00
MB		 1425 }
1426 dvbdemux->dmx.close(&dvbdemux->dmx);
1427 dvbdemux->dmx.remove_frontend(&dvbdemux->dmx,
1428 &chan->hw_frontend);
1429 dvbdemux->dmx.remove_frontend(&dvbdemux->dmx,
1430 &chan->mem_frontend);
1431 dvb_dmxdev_release(&chan->dmxdev);
1432 dvb_dmx_release(&chan->demux);
cf1b12f2
MB		 1433
1434 if (chan->number == 0 || !one_adapter)
1435 dvb_unregister_adapter(&dev->adapter[chan->number]);
dae52d00 1436 }
dae52d00
MB		 1437}
1438
1439static int init_channel(struct ngene_channel *chan)
1440{
1441 int ret = 0, nr = chan->number;
948a1195 1442 struct dvb_adapter *adapter = NULL;
dae52d00
MB		 1443 struct dvb_demux *dvbdemux = &chan->demux;
1444 struct ngene *dev = chan->dev;
1445 struct ngene_info *ni = dev->card_info;
1446 int io = ni->io_type[nr];
1447
1448 tasklet_init(&chan->demux_tasklet, demux_tasklet, (unsigned long)chan);
1449 chan->users = 0;
1450 chan->type = io;
1451 chan->mode = chan->type; /* for now only one mode */
1452
1453 if (io & (NGENE_IO_TSIN | NGENE_IO_TSOUT)) {
1454 if (nr >= STREAM_AUDIOIN1)
1455 chan->DataFormatFlags = DF_SWAP32;
fdafc96c 1456 if (nr == 0 || !one_adapter || dev->first_adapter == NULL) {
cf1b12f2
MB		 1457 adapter = &dev->adapter[nr];
1458 ret = dvb_register_adapter(adapter, "nGene",
1459 THIS_MODULE,
1460 &chan->dev->pci_dev->dev,
1461 adapter_nr);
1462 if (ret < 0)
1463 return ret;
fdafc96c
DH		 1464 if (dev->first_adapter == NULL)
1465 dev->first_adapter = adapter;
cf1b12f2 1466 } else {
fdafc96c 1467 adapter = dev->first_adapter;
cf1b12f2
MB		 1468 }
1469
dae52d00
MB		 1470 ret = my_dvb_dmx_ts_card_init(dvbdemux, "SW demux",
1471 ngene_start_feed,
1472 ngene_stop_feed, chan);
1473 ret = my_dvb_dmxdev_ts_card_init(&chan->dmxdev, &chan->demux,
1474 &chan->hw_frontend,
1475 &chan->mem_frontend, adapter);
dae52d00
MB		 1476 }
1477
1478 if (io & NGENE_IO_TSIN) {
1479 chan->fe = NULL;
1480 if (ni->demod_attach[nr])
1481 ni->demod_attach[nr](chan);
1482 if (chan->fe) {
1483 if (dvb_register_frontend(adapter, chan->fe) < 0) {
1484 if (chan->fe->ops.release)
1485 chan->fe->ops.release(chan->fe);
1486 chan->fe = NULL;
1487 }
1488 }
1489 if (chan->fe && ni->tuner_attach[nr])
1490 if (ni->tuner_attach[nr] (chan) < 0) {
1491 printk(KERN_ERR DEVICE_NAME
1492 ": Tuner attach failed on channel %d!\n",
1493 nr);
1494 }
1495 }
dae52d00
MB		 1496 return ret;
1497}
1498
1499static int init_channels(struct ngene *dev)
1500{
1501 int i, j;
1502
1503 for (i = 0; i < MAX_STREAM; i++) {
fdafc96c 1504 dev->channel[i].number = i;
dae52d00 1505 if (init_channel(&dev->channel[i]) < 0) {
cf1b12f2 1506 for (j = i - 1; j >= 0; j--)
dae52d00
MB		 1507 release_channel(&dev->channel[j]);
1508 return -1;
1509 }
1510 }
1511 return 0;
1512}
1513
1514/****************************************************************************/
1515/* device probe/remove calls ************************************************/
1516/****************************************************************************/
1517
cbddcba6 1518void __devexit ngene_remove(struct pci_dev *pdev)
dae52d00
MB		 1519{
1520 struct ngene *dev = (struct ngene *)pci_get_drvdata(pdev);
1521 int i;
1522
1523 tasklet_kill(&dev->event_tasklet);
cf1b12f2 1524 for (i = MAX_STREAM - 1; i >= 0; i--)
dae52d00 1525 release_channel(&dev->channel[i]);
dae52d00
MB		 1526 ngene_stop(dev);
1527 ngene_release_buffers(dev);
7b1fc72c 1528 pci_set_drvdata(pdev, NULL);
dae52d00
MB		 1529 pci_disable_device(pdev);
1530}
1531
cbddcba6
DH		 1532int __devinit ngene_probe(struct pci_dev *pci_dev,
1533 const struct pci_device_id *id)
dae52d00
MB		 1534{
1535 struct ngene *dev;
1536 int stat = 0;
1537
1538 if (pci_enable_device(pci_dev) < 0)
1539 return -ENODEV;
1540
1541 dev = vmalloc(sizeof(struct ngene));
dc35c9ae
RP		 1542 if (dev == NULL) {
1543 stat = -ENOMEM;
1544 goto fail0;
1545 }
dae52d00
MB		 1546 memset(dev, 0, sizeof(struct ngene));
1547
1548 dev->pci_dev = pci_dev;
1549 dev->card_info = (struct ngene_info *)id->driver_data;
1550 printk(KERN_INFO DEVICE_NAME ": Found %s\n", dev->card_info->name);
1551
1552 pci_set_drvdata(pci_dev, dev);
1553
1554 /* Alloc buffers and start nGene */
1555 stat = ngene_get_buffers(dev);
1556 if (stat < 0)
1557 goto fail1;
1558 stat = ngene_start(dev);
1559 if (stat < 0)
1560 goto fail1;
1561
1562 dev->i2c_current_bus = -1;
dae52d00
MB		 1563
1564 /* Register DVB adapters and devices for both channels */
dae52d00
MB		 1565 if (init_channels(dev) < 0)
1566 goto fail2;
1567
1568 return 0;
1569
1570fail2:
1571 ngene_stop(dev);
1572fail1:
1573 ngene_release_buffers(dev);
dc35c9ae
RP		 1574fail0:
1575 pci_disable_device(pci_dev);
7b1fc72c 1576 pci_set_drvdata(pci_dev, NULL);
dae52d00
MB		 1577 return stat;
1578}
Linux 6.x block layer and io_uring tree(s)