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V4L/DVB (9457): Optimization, Fix a Bug
[linux-block.git] / drivers / media / dvb / frontends / stb0899_algo.c
CommitLineData
8bd135ba
MA		 1/*
2 STB0899 Multistandard Frontend driver
3 Copyright (C) Manu Abraham (abraham.manu@gmail.com)
4
5 Copyright (C) ST Microelectronics
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20*/
21
22#include "stb0899_drv.h"
23#include "stb0899_priv.h"
24#include "stb0899_reg.h"
25
27713c8b 26inline u32 stb0899_do_div(u64 n, u32 d)
8bd135ba 27{
27713c8b
RN		 28 /* wrap do_div() for ease of use */
29
30 do_div(n, d);
31 return n;
8bd135ba
MA		 32}
33
34/*
35 * stb0899_calc_srate
36 * Compute symbol rate
37 */
38static u32 stb0899_calc_srate(u32 master_clk, u8 *sfr)
39{
27713c8b 40 u64 tmp;
8bd135ba 41
27713c8b 42 /* srate = (SFR * master_clk) >> 20 */
8bd135ba 43
27713c8b
RN		 44 /* sfr is of size 20 bit, stored with an offset of 4 bit */
45 tmp = (((u32)sfr[0]) << 16) | (((u32)sfr[1]) << 8) | sfr[2];
46 tmp &= ~0xf;
47 tmp *= master_clk;
48 tmp >>= 24;
8bd135ba
MA		 49
50 return tmp;
51}
52
53/*
54 * stb0899_get_srate
55 * Get the current symbol rate
56 */
57u32 stb0899_get_srate(struct stb0899_state *state)
58{
59 struct stb0899_internal *internal = &state->internal;
27713c8b 60 u8 sfr[3];
8bd135ba
MA		 61
62 stb0899_read_regs(state, STB0899_SFRH, sfr, 3);
63
64 return stb0899_calc_srate(internal->master_clk, sfr);
65}
66
67/*
68 * stb0899_set_srate
69 * Set symbol frequency
70 * MasterClock: master clock frequency (hz)
71 * SymbolRate: symbol rate (bauds)
72 * return symbol frequency
73 */
74static u32 stb0899_set_srate(struct stb0899_state *state, u32 master_clk, u32 srate)
75{
b359325d
MA		 76 u32 tmp;
77 u8 sfr[3];
8bd135ba 78
8bd135ba
MA		 79 dprintk(state->verbose, FE_DEBUG, 1, "-->");
80 /*
81 * in order to have the maximum precision, the symbol rate entered into
82 * the chip is computed as the closest value of the "true value".
83 * In this purpose, the symbol rate value is rounded (1 is added on the bit
84 * below the LSB )
b359325d 85 *
27713c8b
RN		 86 * srate = (SFR * master_clk) >> 20
87 * <=>
88 * SFR = srate << 20 / master_clk
89 *
90 * rounded:
91 * SFR = (srate << 21 + master_clk) / (2 * master_clk)
92 *
93 * stored as 20 bit number with an offset of 4 bit:
94 * sfr = SFR << 4;
95 */
27713c8b
RN		 96
97 tmp = stb0899_do_div((((u64)srate) << 21) + master_clk, 2 * master_clk);
98 tmp <<= 4;
8bd135ba 99
27713c8b
RN		 100 sfr[0] = tmp >> 16;
101 sfr[1] = tmp >> 8;
102 sfr[2] = tmp;
8bd135ba 103
8bd135ba
MA		 104 stb0899_write_regs(state, STB0899_SFRH, sfr, 3);
105
106 return srate;
107}
108
8bd135ba
MA		 109/*
110 * stb0899_calc_derot_time
111 * Compute the amount of time needed by the derotator to lock
112 * SymbolRate: Symbol rate
113 * return: derotator time constant (ms)
114 */
115static long stb0899_calc_derot_time(long srate)
116{
117 if (srate > 0)
118 return (100000 / (srate / 1000));
119 else
120 return 0;
121}
122
123/*
124 * stb0899_carr_width
125 * Compute the width of the carrier
126 * return: width of carrier (kHz or Mhz)
127 */
128long stb0899_carr_width(struct stb0899_state *state)
129{
130 struct stb0899_internal *internal = &state->internal;
131
132 return (internal->srate + (internal->srate * internal->rolloff) / 100);
133}
134
135/*
136 * stb0899_first_subrange
137 * Compute the first subrange of the search
138 */
139static void stb0899_first_subrange(struct stb0899_state *state)
140{
141 struct stb0899_internal *internal = &state->internal;
142 struct stb0899_params *params = &state->params;
143 struct stb0899_config *config = state->config;
144
145 int range = 0;
146 u32 bandwidth = 0;
147
148 if (config->tuner_get_bandwidth) {
149 config->tuner_get_bandwidth(&state->frontend, &bandwidth);
150 range = bandwidth - stb0899_carr_width(state) / 2;
151 }
152
153 if (range > 0)
154 internal->sub_range = MIN(internal->srch_range, range);
155 else
156 internal->sub_range = 0;
157
158 internal->freq = params->freq;
159 internal->tuner_offst = 0L;
160 internal->sub_dir = 1;
161}
162
163/*
164 * stb0899_check_tmg
165 * check for timing lock
166 * internal.Ttiming: time to wait for loop lock
167 */
168static enum stb0899_status stb0899_check_tmg(struct stb0899_state *state)
169{
170 struct stb0899_internal *internal = &state->internal;
eadf29b9 171 int lock;
8bd135ba 172 u8 reg;
eadf29b9 173 s8 timing;
8bd135ba 174
b359325d 175 msleep(internal->t_derot);
8bd135ba 176
85eabac4 177 stb0899_write_reg(state, STB0899_RTF, 0xf2);
8bd135ba
MA		 178 reg = stb0899_read_reg(state, STB0899_TLIR);
179 lock = STB0899_GETFIELD(TLIR_TMG_LOCK_IND, reg);
180 timing = stb0899_read_reg(state, STB0899_RTF);
181
182 if (lock >= 42) {
eadf29b9 183 if ((lock > 48) && (ABS(timing) >= 110)) {
8bd135ba
MA		 184 internal->status = ANALOGCARRIER;
185 dprintk(state->verbose, FE_DEBUG, 1, "-->ANALOG Carrier !");
186 } else {
187 internal->status = TIMINGOK;
188 dprintk(state->verbose, FE_DEBUG, 1, "------->TIMING OK !");
189 }
190 } else {
191 internal->status = NOTIMING;
192 dprintk(state->verbose, FE_DEBUG, 1, "-->NO TIMING !");
193 }
194 return internal->status;
195}
196
197/*
198 * stb0899_search_tmg
199 * perform a fs/2 zig-zag to find timing
200 */
201static enum stb0899_status stb0899_search_tmg(struct stb0899_state *state)
202{
203 struct stb0899_internal *internal = &state->internal;
204 struct stb0899_params *params = &state->params;
205
206 short int derot_step, derot_freq = 0, derot_limit, next_loop = 3;
207 int index = 0;
208 u8 cfr[2];
209
210 internal->status = NOTIMING;
211
212 /* timing loop computation & symbol rate optimisation */
213 derot_limit = (internal->sub_range / 2L) / internal->mclk;
214 derot_step = (params->srate / 2L) / internal->mclk;
215
216 while ((stb0899_check_tmg(state) != TIMINGOK) && next_loop) {
217 index++;
218 derot_freq += index * internal->direction * derot_step; /* next derot zig zag position */
219
220 if (ABS(derot_freq) > derot_limit)
221 next_loop--;
222
223 if (next_loop) {
224 STB0899_SETFIELD_VAL(CFRM, cfr[0], MSB(state->config->inversion * derot_freq));
225 STB0899_SETFIELD_VAL(CFRL, cfr[1], LSB(state->config->inversion * derot_freq));
226 stb0899_write_regs(state, STB0899_CFRM, cfr, 2); /* derotator frequency */
227 }
228 internal->direction = -internal->direction; /* Change zigzag direction */
229 }
230
231 if (internal->status == TIMINGOK) {
232 stb0899_read_regs(state, STB0899_CFRM, cfr, 2); /* get derotator frequency */
233 internal->derot_freq = state->config->inversion * MAKEWORD16(cfr[0], cfr[1]);
234 dprintk(state->verbose, FE_DEBUG, 1, "------->TIMING OK ! Derot Freq = %d", internal->derot_freq);
235 }
236
237 return internal->status;
238}
239
240/*
241 * stb0899_check_carrier
242 * Check for carrier found
243 */
244static enum stb0899_status stb0899_check_carrier(struct stb0899_state *state)
245{
246 struct stb0899_internal *internal = &state->internal;
247 u8 reg;
248
249 msleep(internal->t_derot); /* wait for derotator ok */
250
251 reg = stb0899_read_reg(state, STB0899_CFD);
252 STB0899_SETFIELD_VAL(CFD_ON, reg, 1);
57ad94a6 253 stb0899_write_reg(state, STB0899_CFD, reg);
8bd135ba
MA		 254
255 reg = stb0899_read_reg(state, STB0899_DSTATUS);
256 dprintk(state->verbose, FE_DEBUG, 1, "--------------------> STB0899_DSTATUS=[0x%02x]", reg);
257 if (STB0899_GETFIELD(CARRIER_FOUND, reg)) {
258 internal->status = CARRIEROK;
259 dprintk(state->verbose, FE_DEBUG, 1, "-------------> CARRIEROK !");
260 } else {
261 internal->status = NOCARRIER;
262 dprintk(state->verbose, FE_DEBUG, 1, "-------------> NOCARRIER !");
263 }
264
265 return internal->status;
266}
267
268/*
269 * stb0899_search_carrier
270 * Search for a QPSK carrier with the derotator
271 */
272static enum stb0899_status stb0899_search_carrier(struct stb0899_state *state)
273{
274 struct stb0899_internal *internal = &state->internal;
275
276 short int derot_freq = 0, last_derot_freq = 0, derot_limit, next_loop = 3;
277 int index = 0;
278 u8 cfr[2];
279 u8 reg;
280
281 internal->status = NOCARRIER;
282 derot_limit = (internal->sub_range / 2L) / internal->mclk;
283 derot_freq = internal->derot_freq;
284
285 reg = stb0899_read_reg(state, STB0899_CFD);
286 STB0899_SETFIELD_VAL(CFD_ON, reg, 1);
57ad94a6 287 stb0899_write_reg(state, STB0899_CFD, reg);
8bd135ba
MA		 288
289 do {
290 dprintk(state->verbose, FE_DEBUG, 1, "Derot Freq=%d, mclk=%d", derot_freq, internal->mclk);
291 if (stb0899_check_carrier(state) == NOCARRIER) {
292 index++;
293 last_derot_freq = derot_freq;
294 derot_freq += index * internal->direction * internal->derot_step; /* next zig zag derotator position */
295
296 if(ABS(derot_freq) > derot_limit)
297 next_loop--;
298
299 if (next_loop) {
300 reg = stb0899_read_reg(state, STB0899_CFD);
301 STB0899_SETFIELD_VAL(CFD_ON, reg, 1);
57ad94a6 302 stb0899_write_reg(state, STB0899_CFD, reg);
8bd135ba
MA		 303
304 STB0899_SETFIELD_VAL(CFRM, cfr[0], MSB(state->config->inversion * derot_freq));
305 STB0899_SETFIELD_VAL(CFRL, cfr[1], LSB(state->config->inversion * derot_freq));
306 stb0899_write_regs(state, STB0899_CFRM, cfr, 2); /* derotator frequency */
307 }
308 }
309
310 internal->direction = -internal->direction; /* Change zigzag direction */
311 } while ((internal->status != CARRIEROK) && next_loop);
312
313 if (internal->status == CARRIEROK) {
314 stb0899_read_regs(state, STB0899_CFRM, cfr, 2); /* get derotator frequency */
315 internal->derot_freq = state->config->inversion * MAKEWORD16(cfr[0], cfr[1]);
316 dprintk(state->verbose, FE_DEBUG, 1, "----> CARRIER OK !, Derot Freq=%d", internal->derot_freq);
317 } else {
318 internal->derot_freq = last_derot_freq;
319 }
320
321 return internal->status;
322}
323
324/*
325 * stb0899_check_data
326 * Check for data found
327 */
328static enum stb0899_status stb0899_check_data(struct stb0899_state *state)
329{
330 struct stb0899_internal *internal = &state->internal;
331 struct stb0899_params *params = &state->params;
332
333 int lock = 0, index = 0, dataTime = 500, loop;
334 u8 reg;
335
336 internal->status = NODATA;
337
338 /* RESET FEC */
339 reg = stb0899_read_reg(state, STB0899_TSTRES);
340 STB0899_SETFIELD_VAL(FRESACS, reg, 1);
341 stb0899_write_reg(state, STB0899_TSTRES, reg);
342 msleep(1);
343 reg = stb0899_read_reg(state, STB0899_TSTRES);
344 STB0899_SETFIELD_VAL(FRESACS, reg, 0);
345 stb0899_write_reg(state, STB0899_TSTRES, reg);
346
347 if (params->srate <= 2000000)
348 dataTime = 2000;
349 else if (params->srate <= 5000000)
350 dataTime = 1500;
351 else if (params->srate <= 15000000)
352 dataTime = 1000;
353 else
354 dataTime = 500;
355
356 stb0899_write_reg(state, STB0899_DSTATUS2, 0x00); /* force search loop */
357 while (1) {
358 /* WARNING! VIT LOCKED has to be tested before VIT_END_LOOOP */
359 reg = stb0899_read_reg(state, STB0899_VSTATUS);
360 lock = STB0899_GETFIELD(VSTATUS_LOCKEDVIT, reg);
361 loop = STB0899_GETFIELD(VSTATUS_END_LOOPVIT, reg);
362
363 if (lock || loop || (index > dataTime))
364 break;
365 index++;
366 }
367
368 if (lock) { /* DATA LOCK indicator */
369 internal->status = DATAOK;
370 dprintk(state->verbose, FE_DEBUG, 1, "-----------------> DATA OK !");
371 }
372
373 return internal->status;
374}
375
376/*
377 * stb0899_search_data
378 * Search for a QPSK carrier with the derotator
379 */
380static enum stb0899_status stb0899_search_data(struct stb0899_state *state)
381{
382 short int derot_freq, derot_step, derot_limit, next_loop = 3;
383 u8 cfr[2];
384 u8 reg;
385 int index = 1;
386
387 struct stb0899_internal *internal = &state->internal;
388 struct stb0899_params *params = &state->params;
389
390 derot_step = (params->srate / 4L) / internal->mclk;
391 derot_limit = (internal->sub_range / 2L) / internal->mclk;
392 derot_freq = internal->derot_freq;
393
394 do {
395 if ((internal->status != CARRIEROK) || (stb0899_check_data(state) != DATAOK)) {
396
397 derot_freq += index * internal->direction * derot_step; /* next zig zag derotator position */
398 if (ABS(derot_freq) > derot_limit)
399 next_loop--;
400
401 if (next_loop) {
402 dprintk(state->verbose, FE_DEBUG, 1, "Derot freq=%d, mclk=%d", derot_freq, internal->mclk);
403 reg = stb0899_read_reg(state, STB0899_CFD);
404 STB0899_SETFIELD_VAL(CFD_ON, reg, 1);
57ad94a6 405 stb0899_write_reg(state, STB0899_CFD, reg);
8bd135ba
MA		 406
407 STB0899_SETFIELD_VAL(CFRM, cfr[0], MSB(state->config->inversion * derot_freq));
408 STB0899_SETFIELD_VAL(CFRL, cfr[1], LSB(state->config->inversion * derot_freq));
409 stb0899_write_regs(state, STB0899_CFRM, cfr, 2); /* derotator frequency */
410
411 stb0899_check_carrier(state);
412 index++;
413 }
414 }
415 internal->direction = -internal->direction; /* change zig zag direction */
416 } while ((internal->status != DATAOK) && next_loop);
417
418 if (internal->status == DATAOK) {
419 stb0899_read_regs(state, STB0899_CFRM, cfr, 2); /* get derotator frequency */
420 internal->derot_freq = state->config->inversion * MAKEWORD16(cfr[0], cfr[1]);
421 dprintk(state->verbose, FE_DEBUG, 1, "------> DATAOK ! Derot Freq=%d", internal->derot_freq);
422 }
423
424 return internal->status;
425}
426
427/*
428 * stb0899_check_range
429 * check if the found frequency is in the correct range
430 */
431static enum stb0899_status stb0899_check_range(struct stb0899_state *state)
432{
433 struct stb0899_internal *internal = &state->internal;
434 struct stb0899_params *params = &state->params;
435
436 int range_offst, tp_freq;
437
438 range_offst = internal->srch_range / 2000;
439 tp_freq = internal->freq + (internal->derot_freq * internal->mclk) / 1000;
440
441 if ((tp_freq >= params->freq - range_offst) && (tp_freq <= params->freq + range_offst)) {
442 internal->status = RANGEOK;
443 dprintk(state->verbose, FE_DEBUG, 1, "----> RANGEOK !");
444 } else {
445 internal->status = OUTOFRANGE;
446 dprintk(state->verbose, FE_DEBUG, 1, "----> OUT OF RANGE !");
447 }
448
449 return internal->status;
450}
451
452/*
453 * NextSubRange
454 * Compute the next subrange of the search
455 */
456static void next_sub_range(struct stb0899_state *state)
457{
458 struct stb0899_internal *internal = &state->internal;
459 struct stb0899_params *params = &state->params;
460
461 long old_sub_range;
462
463 if (internal->sub_dir > 0) {
464 old_sub_range = internal->sub_range;
465 internal->sub_range = MIN((internal->srch_range / 2) -
466 (internal->tuner_offst + internal->sub_range / 2),
467 internal->sub_range);
468
469 if (internal->sub_range < 0)
470 internal->sub_range = 0;
471
472 internal->tuner_offst += (old_sub_range + internal->sub_range) / 2;
473 }
474
475 internal->freq = params->freq + (internal->sub_dir * internal->tuner_offst) / 1000;
476 internal->sub_dir = -internal->sub_dir;
477}
478
479/*
480 * stb0899_dvbs_algo
481 * Search for a signal, timing, carrier and data for a
482 * given frequency in a given range
483 */
484enum stb0899_status stb0899_dvbs_algo(struct stb0899_state *state)
485{
486 struct stb0899_params *params = &state->params;
487 struct stb0899_internal *internal = &state->internal;
488 struct stb0899_config *config = state->config;
489
490 u8 bclc, reg;
7d8f1e57 491 u8 cfr[2];
8bd135ba
MA		 492 u8 eq_const[10];
493 s32 clnI = 3;
494 u32 bandwidth = 0;
495
496 /* BETA values rated @ 99MHz */
497 s32 betaTab[5][4] = {
498 /* 5 10 20 30MBps */
499 { 37, 34, 32, 31 }, /* QPSK 1/2 */
500 { 37, 35, 33, 31 }, /* QPSK 2/3 */
501 { 37, 35, 33, 31 }, /* QPSK 3/4 */
502 { 37, 36, 33, 32 }, /* QPSK 5/6 */
503 { 37, 36, 33, 32 } /* QPSK 7/8 */
504 };
505
506 internal->direction = 1;
507
508 stb0899_set_srate(state, internal->master_clk, params->srate);
509 /* Carrier loop optimization versus symbol rate for acquisition*/
510 if (params->srate <= 5000000) {
511 stb0899_write_reg(state, STB0899_ACLC, 0x89);
512 bclc = stb0899_read_reg(state, STB0899_BCLC);
513 STB0899_SETFIELD_VAL(BETA, bclc, 0x1c);
514 stb0899_write_reg(state, STB0899_BCLC, bclc);
515 clnI = 0;
516 } else if (params->srate <= 15000000) {
517 stb0899_write_reg(state, STB0899_ACLC, 0xc9);
518 bclc = stb0899_read_reg(state, STB0899_BCLC);
519 STB0899_SETFIELD_VAL(BETA, bclc, 0x22);
520 stb0899_write_reg(state, STB0899_BCLC, bclc);
521 clnI = 1;
522 } else if(params->srate <= 25000000) {
523 stb0899_write_reg(state, STB0899_ACLC, 0x89);
524 bclc = stb0899_read_reg(state, STB0899_BCLC);
525 STB0899_SETFIELD_VAL(BETA, bclc, 0x27);
526 stb0899_write_reg(state, STB0899_BCLC, bclc);
527 clnI = 2;
528 } else {
529 stb0899_write_reg(state, STB0899_ACLC, 0xc8);
530 bclc = stb0899_read_reg(state, STB0899_BCLC);
531 STB0899_SETFIELD_VAL(BETA, bclc, 0x29);
532 stb0899_write_reg(state, STB0899_BCLC, bclc);
533 clnI = 3;
534 }
535
536 dprintk(state->verbose, FE_DEBUG, 1, "Set the timing loop to acquisition");
537 /* Set the timing loop to acquisition */
538 stb0899_write_reg(state, STB0899_RTC, 0x46);
539 stb0899_write_reg(state, STB0899_CFD, 0xee);
540
541 /* !! WARNING !!
542 * Do not read any status variables while acquisition,
543 * If any needed, read before the acquisition starts
544 * querying status while acquiring causes the
545 * acquisition to go bad and hence no locks.
546 */
547 dprintk(state->verbose, FE_DEBUG, 1, "Derot Percent=%d Srate=%d mclk=%d",
548 internal->derot_percent, params->srate, internal->mclk);
549
550 /* Initial calculations */
551 internal->derot_step = internal->derot_percent * (params->srate / 1000L) / internal->mclk; /* DerotStep/1000 * Fsymbol */
8bd135ba
MA		 552 internal->t_derot = stb0899_calc_derot_time(params->srate);
553 internal->t_data = 500;
554
555 dprintk(state->verbose, FE_DEBUG, 1, "RESET stream merger");
556 /* RESET Stream merger */
557 reg = stb0899_read_reg(state, STB0899_TSTRES);
558 STB0899_SETFIELD_VAL(FRESRS, reg, 1);
559 stb0899_write_reg(state, STB0899_TSTRES, reg);
560
561 /*
562 * Set KDIVIDER to an intermediate value between
563 * 1/2 and 7/8 for acquisition
564 */
565 reg = stb0899_read_reg(state, STB0899_DEMAPVIT);
566 STB0899_SETFIELD_VAL(DEMAPVIT_KDIVIDER, reg, 60);
567 stb0899_write_reg(state, STB0899_DEMAPVIT, reg);
568
569 stb0899_write_reg(state, STB0899_EQON, 0x01); /* Equalizer OFF while acquiring */
570 stb0899_write_reg(state, STB0899_VITSYNC, 0x19);
571
572 stb0899_first_subrange(state);
573 do {
574 /* Initialisations */
575 cfr[0] = cfr[1] = 0;
576 stb0899_write_regs(state, STB0899_CFRM, cfr, 2); /* RESET derotator frequency */
577
85eabac4 578 stb0899_write_reg(state, STB0899_RTF, 0);
8bd135ba
MA		 579 reg = stb0899_read_reg(state, STB0899_CFD);
580 STB0899_SETFIELD_VAL(CFD_ON, reg, 1);
57ad94a6 581 stb0899_write_reg(state, STB0899_CFD, reg);
8bd135ba
MA		 582
583 internal->derot_freq = 0;
584 internal->status = NOAGC1;
585
40e8ce3d
MA		 586 /* enable tuner I/O */
587 stb0899_i2c_gate_ctrl(&state->frontend, 1);
588
8bd135ba
MA		 589 /* Move tuner to frequency */
590 dprintk(state->verbose, FE_DEBUG, 1, "Tuner set frequency");
591 if (state->config->tuner_set_frequency)
592 state->config->tuner_set_frequency(&state->frontend, internal->freq);
593
8bd135ba
MA		 594 if (state->config->tuner_get_frequency)
595 state->config->tuner_get_frequency(&state->frontend, &internal->freq);
596
b359325d 597 msleep(internal->t_agc1 + internal->t_agc2 + internal->t_derot); /* AGC1, AGC2 and timing loop */
8bd135ba
MA		 598 dprintk(state->verbose, FE_DEBUG, 1, "current derot freq=%d", internal->derot_freq);
599 internal->status = AGC1OK;
600
601 /* There is signal in the band */
602 if (config->tuner_get_bandwidth)
603 config->tuner_get_bandwidth(&state->frontend, &bandwidth);
40e8ce3d
MA		 604
605 /* disable tuner I/O */
606 stb0899_i2c_gate_ctrl(&state->frontend, 0);
607
8bd135ba
MA		 608 if (params->srate <= bandwidth / 2)
609 stb0899_search_tmg(state); /* For low rates (SCPC) */
610 else
611 stb0899_check_tmg(state); /* For high rates (MCPC) */
612
613 if (internal->status == TIMINGOK) {
614 dprintk(state->verbose, FE_DEBUG, 1,
615 "TIMING OK ! Derot freq=%d, mclk=%d",
616 internal->derot_freq, internal->mclk);
617
618 if (stb0899_search_carrier(state) == CARRIEROK) { /* Search for carrier */
619 dprintk(state->verbose, FE_DEBUG, 1,
620 "CARRIER OK ! Derot freq=%d, mclk=%d",
621 internal->derot_freq, internal->mclk);
622
623 if (stb0899_search_data(state) == DATAOK) { /* Check for data */
624 dprintk(state->verbose, FE_DEBUG, 1,
625 "DATA OK ! Derot freq=%d, mclk=%d",
626 internal->derot_freq, internal->mclk);
627
628 if (stb0899_check_range(state) == RANGEOK) {
629 dprintk(state->verbose, FE_DEBUG, 1,
630 "RANGE OK ! derot freq=%d, mclk=%d",
631 internal->derot_freq, internal->mclk);
632
633 internal->freq = params->freq + ((internal->derot_freq * internal->mclk) / 1000);
634 reg = stb0899_read_reg(state, STB0899_PLPARM);
635 internal->fecrate = STB0899_GETFIELD(VITCURPUN, reg);
636 dprintk(state->verbose, FE_DEBUG, 1,
637 "freq=%d, internal resultant freq=%d",
638 params->freq, internal->freq);
639
640 dprintk(state->verbose, FE_DEBUG, 1,
641 "internal puncture rate=%d",
642 internal->fecrate);
643 }
644 }
645 }
646 }
647 if (internal->status != RANGEOK)
648 next_sub_range(state);
649
650 } while (internal->sub_range && internal->status != RANGEOK);
651
652 /* Set the timing loop to tracking */
653 stb0899_write_reg(state, STB0899_RTC, 0x33);
654 stb0899_write_reg(state, STB0899_CFD, 0xf7);
8bd135ba
MA		 655 /* if locked and range ok, set Kdiv */
656 if (internal->status == RANGEOK) {
657 dprintk(state->verbose, FE_DEBUG, 1, "Locked & Range OK !");
658 stb0899_write_reg(state, STB0899_EQON, 0x41); /* Equalizer OFF while acquiring */
659 stb0899_write_reg(state, STB0899_VITSYNC, 0x39); /* SN to b'11 for acquisition */
660
661 /*
662 * Carrier loop optimization versus
663 * symbol Rate/Puncture Rate for Tracking
664 */
b655b6cb 665 reg = stb0899_read_reg(state, STB0899_BCLC);
8bd135ba
MA		 666 switch (internal->fecrate) {
667 case STB0899_FEC_1_2: /* 13 */
b655b6cb 668 stb0899_write_reg(state, STB0899_DEMAPVIT, 0x1a);
8bd135ba
MA		 669 STB0899_SETFIELD_VAL(BETA, reg, betaTab[0][clnI]);
670 stb0899_write_reg(state, STB0899_BCLC, reg);
671 break;
672 case STB0899_FEC_2_3: /* 18 */
b655b6cb 673 stb0899_write_reg(state, STB0899_DEMAPVIT, 44);
8bd135ba
MA		 674 STB0899_SETFIELD_VAL(BETA, reg, betaTab[1][clnI]);
675 stb0899_write_reg(state, STB0899_BCLC, reg);
676 break;
677 case STB0899_FEC_3_4: /* 21 */
b655b6cb 678 stb0899_write_reg(state, STB0899_DEMAPVIT, 60);
8bd135ba
MA		 679 STB0899_SETFIELD_VAL(BETA, reg, betaTab[2][clnI]);
680 stb0899_write_reg(state, STB0899_BCLC, reg);
681 break;
682 case STB0899_FEC_5_6: /* 24 */
b655b6cb 683 stb0899_write_reg(state, STB0899_DEMAPVIT, 75);
8bd135ba
MA		 684 STB0899_SETFIELD_VAL(BETA, reg, betaTab[3][clnI]);
685 stb0899_write_reg(state, STB0899_BCLC, reg);
686 break;
687 case STB0899_FEC_6_7: /* 25 */
b655b6cb 688 stb0899_write_reg(state, STB0899_DEMAPVIT, 88);
8bd135ba
MA		 689 stb0899_write_reg(state, STB0899_ACLC, 0x88);
690 stb0899_write_reg(state, STB0899_BCLC, 0x9a);
691 break;
692 case STB0899_FEC_7_8: /* 26 */
b655b6cb 693 stb0899_write_reg(state, STB0899_DEMAPVIT, 94);
8bd135ba
MA		 694 STB0899_SETFIELD_VAL(BETA, reg, betaTab[4][clnI]);
695 stb0899_write_reg(state, STB0899_BCLC, reg);
696 break;
697 default:
698 dprintk(state->verbose, FE_DEBUG, 1, "Unsupported Puncture Rate");
699 break;
700 }
701 /* release stream merger RESET */
702 reg = stb0899_read_reg(state, STB0899_TSTRES);
703 STB0899_SETFIELD_VAL(FRESRS, reg, 0);
704 stb0899_write_reg(state, STB0899_TSTRES, reg);
705
706 /* disable carrier detector */
707 reg = stb0899_read_reg(state, STB0899_CFD);
708 STB0899_SETFIELD_VAL(CFD_ON, reg, 0);
57ad94a6 709 stb0899_write_reg(state, STB0899_CFD, reg);
8bd135ba
MA		 710
711 stb0899_read_regs(state, STB0899_EQUAI1, eq_const, 10);
712 }
713
714 return internal->status;
715}
716
717/*
718 * stb0899_dvbs2_config_uwp
719 * Configure UWP state machine
720 */
721static void stb0899_dvbs2_config_uwp(struct stb0899_state *state)
722{
723 struct stb0899_internal *internal = &state->internal;
724 struct stb0899_config *config = state->config;
725 u32 uwp1, uwp2, uwp3, reg;
726
727 uwp1 = STB0899_READ_S2REG(STB0899_S2DEMOD, UWP_CNTRL1);
728 uwp2 = STB0899_READ_S2REG(STB0899_S2DEMOD, UWP_CNTRL2);
729 uwp3 = STB0899_READ_S2REG(STB0899_S2DEMOD, UWP_CNTRL3);
730
731 STB0899_SETFIELD_VAL(UWP_ESN0_AVE, uwp1, config->esno_ave);
732 STB0899_SETFIELD_VAL(UWP_ESN0_QUANT, uwp1, config->esno_quant);
733 STB0899_SETFIELD_VAL(UWP_TH_SOF, uwp1, config->uwp_threshold_sof);
734
735 STB0899_SETFIELD_VAL(FE_COARSE_TRK, uwp2, internal->av_frame_coarse);
736 STB0899_SETFIELD_VAL(FE_FINE_TRK, uwp2, internal->av_frame_fine);
737 STB0899_SETFIELD_VAL(UWP_MISS_TH, uwp2, config->miss_threshold);
738
739 STB0899_SETFIELD_VAL(UWP_TH_ACQ, uwp3, config->uwp_threshold_acq);
740 STB0899_SETFIELD_VAL(UWP_TH_TRACK, uwp3, config->uwp_threshold_track);
741
742 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_UWP_CNTRL1, STB0899_OFF0_UWP_CNTRL1, uwp1);
743 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_UWP_CNTRL2, STB0899_OFF0_UWP_CNTRL2, uwp2);
744 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_UWP_CNTRL3, STB0899_OFF0_UWP_CNTRL3, uwp3);
745
746 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, SOF_SRCH_TO);
747 STB0899_SETFIELD_VAL(SOF_SEARCH_TIMEOUT, reg, config->sof_search_timeout);
748 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_SOF_SRCH_TO, STB0899_OFF0_SOF_SRCH_TO, reg);
749}
750
751/*
752 * stb0899_dvbs2_config_csm_auto
753 * Set CSM to AUTO mode
754 */
755static void stb0899_dvbs2_config_csm_auto(struct stb0899_state *state)
756{
757 u32 reg;
758
759 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, CSM_CNTRL1);
760 STB0899_SETFIELD_VAL(CSM_AUTO_PARAM, reg, 1);
761 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CSM_CNTRL1, STB0899_OFF0_CSM_CNTRL1, reg);
762}
763
764long Log2Int(int number)
765{
766 int i;
767
768 i = 0;
769 while ((1 << i) <= ABS(number))
770 i++;
771
772 if (number == 0)
773 i = 1;
774
775 return i - 1;
776}
777
778/*
779 * stb0899_dvbs2_calc_srate
780 * compute BTR_NOM_FREQ for the symbol rate
781 */
782static u32 stb0899_dvbs2_calc_srate(struct stb0899_state *state)
783{
784 struct stb0899_internal *internal = &state->internal;
785 struct stb0899_config *config = state->config;
786
787 u32 dec_ratio, dec_rate, decim, remain, intval, btr_nom_freq;
788 u32 master_clk, srate;
789
790 dec_ratio = (internal->master_clk * 2) / (5 * internal->srate);
791 dec_ratio = (dec_ratio == 0) ? 1 : dec_ratio;
792 dec_rate = Log2Int(dec_ratio);
793 decim = 1 << dec_rate;
794 master_clk = internal->master_clk / 1000;
795 srate = internal->srate / 1000;
796
797 if (decim <= 4) {
798 intval = (decim * (1 << (config->btr_nco_bits - 1))) / master_clk;
799 remain = (decim * (1 << (config->btr_nco_bits - 1))) % master_clk;
800 } else {
801 intval = (1 << (config->btr_nco_bits - 1)) / (master_clk / 100) * decim / 100;
802 remain = (decim * (1 << (config->btr_nco_bits - 1))) % master_clk;
803 }
804 btr_nom_freq = (intval * srate) + ((remain * srate) / master_clk);
805
806 return btr_nom_freq;
807}
808
809/*
810 * stb0899_dvbs2_calc_dev
811 * compute the correction to be applied to symbol rate
812 */
813static u32 stb0899_dvbs2_calc_dev(struct stb0899_state *state)
814{
815 struct stb0899_internal *internal = &state->internal;
816 u32 dec_ratio, correction, master_clk, srate;
817
818 dec_ratio = (internal->master_clk * 2) / (5 * internal->srate);
819 dec_ratio = (dec_ratio == 0) ? 1 : dec_ratio;
820
821 master_clk = internal->master_clk / 1000; /* for integer Caculation*/
822 srate = internal->srate / 1000; /* for integer Caculation*/
823 correction = (512 * master_clk) / (2 * dec_ratio * srate);
824
825 return correction;
826}
827
828/*
829 * stb0899_dvbs2_set_srate
830 * Set DVBS2 symbol rate
831 */
832static void stb0899_dvbs2_set_srate(struct stb0899_state *state)
833{
834 struct stb0899_internal *internal = &state->internal;
835
836 u32 dec_ratio, dec_rate, win_sel, decim, f_sym, btr_nom_freq;
837 u32 correction, freq_adj, band_lim, decim_cntrl, reg;
838 u8 anti_alias;
839
840 /*set decimation to 1*/
841 dec_ratio = (internal->master_clk * 2) / (5 * internal->srate);
842 dec_ratio = (dec_ratio == 0) ? 1 : dec_ratio;
843 dec_rate = Log2Int(dec_ratio);
844
845 win_sel = 0;
846 if (dec_rate >= 5)
847 win_sel = dec_rate - 4;
848
849 decim = (1 << dec_rate);
850 /* (FSamp/Fsymbol *100) for integer Caculation */
851 f_sym = internal->master_clk / ((decim * internal->srate) / 1000);
852
853 if (f_sym <= 2250) /* don't band limit signal going into btr block*/
854 band_lim = 1;
855 else
856 band_lim = 0; /* band limit signal going into btr block*/
857
858 decim_cntrl = ((win_sel << 3) & 0x18) + ((band_lim << 5) & 0x20) + (dec_rate & 0x7);
859 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_DECIM_CNTRL, STB0899_OFF0_DECIM_CNTRL, decim_cntrl);
860
861 if (f_sym <= 3450)
862 anti_alias = 0;
863 else if (f_sym <= 4250)
864 anti_alias = 1;
865 else
866 anti_alias = 2;
867
868 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_ANTI_ALIAS_SEL, STB0899_OFF0_ANTI_ALIAS_SEL, anti_alias);
869 btr_nom_freq = stb0899_dvbs2_calc_srate(state);
870 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_BTR_NOM_FREQ, STB0899_OFF0_BTR_NOM_FREQ, btr_nom_freq);
871
872 correction = stb0899_dvbs2_calc_dev(state);
873 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, BTR_CNTRL);
874 STB0899_SETFIELD_VAL(BTR_FREQ_CORR, reg, correction);
875 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_BTR_CNTRL, STB0899_OFF0_BTR_CNTRL, reg);
876
877 /* scale UWP+CSM frequency to sample rate*/
878 freq_adj = internal->srate / (internal->master_clk / 4096);
879 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_FREQ_ADJ_SCALE, STB0899_OFF0_FREQ_ADJ_SCALE, freq_adj);
880}
881
882/*
883 * stb0899_dvbs2_set_btr_loopbw
884 * set bit timing loop bandwidth as a percentage of the symbol rate
885 */
886static void stb0899_dvbs2_set_btr_loopbw(struct stb0899_state *state)
887{
888 struct stb0899_internal *internal = &state->internal;
889 struct stb0899_config *config = state->config;
890
891 u32 sym_peak = 23, zeta = 707, loopbw_percent = 60;
892 s32 dec_ratio, dec_rate, k_btr1_rshft, k_btr1, k_btr0_rshft;
893 s32 k_btr0, k_btr2_rshft, k_direct_shift, k_indirect_shift;
894 u32 decim, K, wn, k_direct, k_indirect;
895 u32 reg;
896
897 dec_ratio = (internal->master_clk * 2) / (5 * internal->srate);
898 dec_ratio = (dec_ratio == 0) ? 1 : dec_ratio;
899 dec_rate = Log2Int(dec_ratio);
900 decim = (1 << dec_rate);
901
902 sym_peak *= 576000;
903 K = (1 << config->btr_nco_bits) / (internal->master_clk / 1000);
904 K *= (internal->srate / 1000000) * decim; /*k=k 10^-8*/
8bd135ba
MA		 905
906 if (K != 0) {
b797c206 907 K = sym_peak / K;
8bd135ba
MA		 908 wn = (4 * zeta * zeta) + 1000000;
909 wn = (2 * (loopbw_percent * 1000) * 40 * zeta) /wn; /*wn =wn 10^-8*/
910
911 k_indirect = (wn * wn) / K;
912 k_indirect = k_indirect; /*kindirect = kindirect 10^-6*/
913 k_direct = (2 * wn * zeta) / K; /*kDirect = kDirect 10^-2*/
914 k_direct *= 100;
915
916 k_direct_shift = Log2Int(k_direct) - Log2Int(10000) - 2;
917 k_btr1_rshft = (-1 * k_direct_shift) + config->btr_gain_shift_offset;
918 k_btr1 = k_direct / (1 << k_direct_shift);
919 k_btr1 /= 10000;
920
921 k_indirect_shift = Log2Int(k_indirect + 15) - 20 /*- 2*/;
922 k_btr0_rshft = (-1 * k_indirect_shift) + config->btr_gain_shift_offset;
923 k_btr0 = k_indirect * (1 << (-k_indirect_shift));
924 k_btr0 /= 1000000;
925
926 k_btr2_rshft = 0;
927 if (k_btr0_rshft > 15) {
928 k_btr2_rshft = k_btr0_rshft - 15;
929 k_btr0_rshft = 15;
930 }
931 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, BTR_LOOP_GAIN);
932 STB0899_SETFIELD_VAL(KBTR0_RSHFT, reg, k_btr0_rshft);
933 STB0899_SETFIELD_VAL(KBTR0, reg, k_btr0);
934 STB0899_SETFIELD_VAL(KBTR1_RSHFT, reg, k_btr1_rshft);
935 STB0899_SETFIELD_VAL(KBTR1, reg, k_btr1);
936 STB0899_SETFIELD_VAL(KBTR2_RSHFT, reg, k_btr2_rshft);
937 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_BTR_LOOP_GAIN, STB0899_OFF0_BTR_LOOP_GAIN, reg);
938 } else
939 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_BTR_LOOP_GAIN, STB0899_OFF0_BTR_LOOP_GAIN, 0xc4c4f);
940}
941
942/*
943 * stb0899_dvbs2_set_carr_freq
944 * set nominal frequency for carrier search
945 */
946static void stb0899_dvbs2_set_carr_freq(struct stb0899_state *state, s32 carr_freq, u32 master_clk)
947{
948 struct stb0899_config *config = state->config;
949 s32 crl_nom_freq;
950 u32 reg;
951
952 crl_nom_freq = (1 << config->crl_nco_bits) / master_clk;
953 crl_nom_freq *= carr_freq;
954 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, CRL_NOM_FREQ);
955 STB0899_SETFIELD_VAL(CRL_NOM_FREQ, reg, crl_nom_freq);
956 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CRL_NOM_FREQ, STB0899_OFF0_CRL_NOM_FREQ, reg);
957}
958
959/*
960 * stb0899_dvbs2_init_calc
961 * Initialize DVBS2 UWP, CSM, carrier and timing loops
962 */
963static void stb0899_dvbs2_init_calc(struct stb0899_state *state)
964{
965 struct stb0899_internal *internal = &state->internal;
966 s32 steps, step_size;
967 u32 range, reg;
968
969 /* config uwp and csm */
970 stb0899_dvbs2_config_uwp(state);
971 stb0899_dvbs2_config_csm_auto(state);
972
973 /* initialize BTR */
974 stb0899_dvbs2_set_srate(state);
975 stb0899_dvbs2_set_btr_loopbw(state);
976
977 if (internal->srate / 1000000 >= 15)
978 step_size = (1 << 17) / 5;
979 else if (internal->srate / 1000000 >= 10)
980 step_size = (1 << 17) / 7;
981 else if (internal->srate / 1000000 >= 5)
982 step_size = (1 << 17) / 10;
983 else
984 step_size = (1 << 17) / 4;
985
986 range = internal->srch_range / 1000000;
987 steps = (10 * range * (1 << 17)) / (step_size * (internal->srate / 1000000));
988 steps = (steps + 6) / 10;
989 steps = (steps == 0) ? 1 : steps;
990 if (steps % 2 == 0)
991 stb0899_dvbs2_set_carr_freq(state, internal->center_freq -
992 (internal->step_size * (internal->srate / 20000000)),
993 (internal->master_clk) / 1000000);
994 else
995 stb0899_dvbs2_set_carr_freq(state, internal->center_freq, (internal->master_clk) / 1000000);
996
997 /*Set Carrier Search params (zigzag, num steps and freq step size*/
998 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, ACQ_CNTRL2);
999 STB0899_SETFIELD_VAL(ZIGZAG, reg, 1);
1000 STB0899_SETFIELD_VAL(NUM_STEPS, reg, steps);
1001 STB0899_SETFIELD_VAL(FREQ_STEPSIZE, reg, step_size);
1002 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_ACQ_CNTRL2, STB0899_OFF0_ACQ_CNTRL2, reg);
1003}
1004
1005/*
1006 * stb0899_dvbs2_btr_init
1007 * initialize the timing loop
1008 */
1009static void stb0899_dvbs2_btr_init(struct stb0899_state *state)
1010{
1011 u32 reg;
1012
1013 /* set enable BTR loopback */
1014 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, BTR_CNTRL);
1015 STB0899_SETFIELD_VAL(INTRP_PHS_SENSE, reg, 1);
1016 STB0899_SETFIELD_VAL(BTR_ERR_ENA, reg, 1);
1017 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_BTR_CNTRL, STB0899_OFF0_BTR_CNTRL, reg);
1018
1019 /* fix btr freq accum at 0 */
1020 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_BTR_FREQ_INIT, STB0899_OFF0_BTR_FREQ_INIT, 0x10000000);
1021 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_BTR_FREQ_INIT, STB0899_OFF0_BTR_FREQ_INIT, 0x00000000);
1022
1023 /* fix btr freq accum at 0 */
1024 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_BTR_PHS_INIT, STB0899_OFF0_BTR_PHS_INIT, 0x10000000);
1025 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_BTR_PHS_INIT, STB0899_OFF0_BTR_PHS_INIT, 0x00000000);
1026}
1027
1028/*
1029 * stb0899_dvbs2_reacquire
1030 * trigger a DVB-S2 acquisition
1031 */
1032static void stb0899_dvbs2_reacquire(struct stb0899_state *state)
1033{
1034 u32 reg = 0;
1035
1036 /* demod soft reset */
1037 STB0899_SETFIELD_VAL(DVBS2_RESET, reg, 1);
1038 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_RESET_CNTRL, STB0899_OFF0_RESET_CNTRL, reg);
1039
1040 /*Reset Timing Loop */
1041 stb0899_dvbs2_btr_init(state);
1042
1043 /* reset Carrier loop */
1044 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CRL_FREQ_INIT, STB0899_OFF0_CRL_FREQ_INIT, (1 << 30));
1045 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CRL_FREQ_INIT, STB0899_OFF0_CRL_FREQ_INIT, 0);
1046 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CRL_LOOP_GAIN, STB0899_OFF0_CRL_LOOP_GAIN, 0);
1047 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CRL_PHS_INIT, STB0899_OFF0_CRL_PHS_INIT, (1 << 30));
1048 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CRL_PHS_INIT, STB0899_OFF0_CRL_PHS_INIT, 0);
1049
1050 /*release demod soft reset */
1051 reg = 0;
1052 STB0899_SETFIELD_VAL(DVBS2_RESET, reg, 0);
1053 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_RESET_CNTRL, STB0899_OFF0_RESET_CNTRL, reg);
1054
1055 /* start acquisition process */
1056 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_ACQUIRE_TRIG, STB0899_OFF0_ACQUIRE_TRIG, 1);
1057 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_LOCK_LOST, STB0899_OFF0_LOCK_LOST, 0);
1058
1059 /* equalizer Init */
1060 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_EQUALIZER_INIT, STB0899_OFF0_EQUALIZER_INIT, 1);
1061
1062 /*Start equilizer */
1063 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_EQUALIZER_INIT, STB0899_OFF0_EQUALIZER_INIT, 0);
1064
1065 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, EQ_CNTRL);
1066 STB0899_SETFIELD_VAL(EQ_SHIFT, reg, 0);
1067 STB0899_SETFIELD_VAL(EQ_DISABLE_UPDATE, reg, 0);
1068 STB0899_SETFIELD_VAL(EQ_DELAY, reg, 0x05);
1069 STB0899_SETFIELD_VAL(EQ_ADAPT_MODE, reg, 0x01);
1070 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_EQ_CNTRL, STB0899_OFF0_EQ_CNTRL, reg);
1071
1072 /* RESET Packet delineator */
1073 stb0899_write_reg(state, STB0899_PDELCTRL, 0x4a);
1074}
1075
1076/*
1077 * stb0899_dvbs2_get_dmd_status
1078 * get DVB-S2 Demod LOCK status
1079 */
1080static enum stb0899_status stb0899_dvbs2_get_dmd_status(struct stb0899_state *state, int timeout)
1081{
1082 int time = -10, lock = 0, uwp, csm;
1083 u32 reg;
1084
1085 do {
1086 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, DMD_STATUS);
1087 dprintk(state->verbose, FE_DEBUG, 1, "DMD_STATUS=[0x%02x]", reg);
1088 if (STB0899_GETFIELD(IF_AGC_LOCK, reg))
1089 dprintk(state->verbose, FE_DEBUG, 1, "------------->IF AGC LOCKED !");
1090 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, DMD_STAT2);
1091 dprintk(state->verbose, FE_DEBUG, 1, "----------->DMD STAT2=[0x%02x]", reg);
1092 uwp = STB0899_GETFIELD(UWP_LOCK, reg);
1093 csm = STB0899_GETFIELD(CSM_LOCK, reg);
1094 if (uwp && csm)
1095 lock = 1;
1096
1097 time += 10;
1098 msleep(10);
1099
1100 } while ((!lock) && (time <= timeout));
1101
1102 if (lock) {
1103 dprintk(state->verbose, FE_DEBUG, 1, "----------------> DVB-S2 LOCK !");
1104 return DVBS2_DEMOD_LOCK;
1105 } else {
1106 return DVBS2_DEMOD_NOLOCK;
1107 }
1108}
1109
1110/*
1111 * stb0899_dvbs2_get_data_lock
1112 * get FEC status
1113 */
1114static int stb0899_dvbs2_get_data_lock(struct stb0899_state *state, int timeout)
1115{
1116 int time = 0, lock = 0;
1117 u8 reg;
1118
1119 while ((!lock) && (time < timeout)) {
1120 reg = stb0899_read_reg(state, STB0899_CFGPDELSTATUS1);
1121 dprintk(state->verbose, FE_DEBUG, 1, "---------> CFGPDELSTATUS=[0x%02x]", reg);
1122 lock = STB0899_GETFIELD(CFGPDELSTATUS_LOCK, reg);
1123 time++;
1124 }
1125
1126 return lock;
1127}
1128
1129/*
1130 * stb0899_dvbs2_get_fec_status
1131 * get DVB-S2 FEC LOCK status
1132 */
1133static enum stb0899_status stb0899_dvbs2_get_fec_status(struct stb0899_state *state, int timeout)
1134{
1135 int time = 0, Locked;
1136
1137 do {
1138 Locked = stb0899_dvbs2_get_data_lock(state, 1);
1139 time++;
1140 msleep(1);
1141
1142 } while ((!Locked) && (time < timeout));
1143
1144 if (Locked) {
1145 dprintk(state->verbose, FE_DEBUG, 1, "---------->DVB-S2 FEC LOCK !");
1146 return DVBS2_FEC_LOCK;
1147 } else {
1148 return DVBS2_FEC_NOLOCK;
1149 }
1150}
1151
1152
1153/*
1154 * stb0899_dvbs2_init_csm
1155 * set parameters for manual mode
1156 */
1157static void stb0899_dvbs2_init_csm(struct stb0899_state *state, int pilots, enum stb0899_modcod modcod)
1158{
1159 struct stb0899_internal *internal = &state->internal;
1160
1161 s32 dvt_tbl = 1, two_pass = 0, agc_gain = 6, agc_shift = 0, loop_shift = 0, phs_diff_thr = 0x80;
1162 s32 gamma_acq, gamma_rho_acq, gamma_trk, gamma_rho_trk, lock_count_thr;
1163 u32 csm1, csm2, csm3, csm4;
1164
1165 if (((internal->master_clk / internal->srate) <= 4) && (modcod <= 11) && (pilots == 1)) {
1166 switch (modcod) {
1167 case STB0899_QPSK_12:
1168 gamma_acq = 25;
1169 gamma_rho_acq = 2700;
1170 gamma_trk = 12;
1171 gamma_rho_trk = 180;
1172 lock_count_thr = 8;
1173 break;
1174 case STB0899_QPSK_35:
1175 gamma_acq = 38;
1176 gamma_rho_acq = 7182;
1177 gamma_trk = 14;
1178 gamma_rho_trk = 308;
1179 lock_count_thr = 8;
1180 break;
1181 case STB0899_QPSK_23:
1182 gamma_acq = 42;
1183 gamma_rho_acq = 9408;
1184 gamma_trk = 17;
1185 gamma_rho_trk = 476;
1186 lock_count_thr = 8;
1187 break;
1188 case STB0899_QPSK_34:
1189 gamma_acq = 53;
1190 gamma_rho_acq = 16642;
1191 gamma_trk = 19;
1192 gamma_rho_trk = 646;
1193 lock_count_thr = 8;
1194 break;
1195 case STB0899_QPSK_45:
1196 gamma_acq = 53;
1197 gamma_rho_acq = 17119;
1198 gamma_trk = 22;
1199 gamma_rho_trk = 880;
1200 lock_count_thr = 8;
1201 break;
1202 case STB0899_QPSK_56:
1203 gamma_acq = 55;
1204 gamma_rho_acq = 19250;
1205 gamma_trk = 23;
1206 gamma_rho_trk = 989;
1207 lock_count_thr = 8;
1208 break;
1209 case STB0899_QPSK_89:
1210 gamma_acq = 60;
1211 gamma_rho_acq = 24240;
1212 gamma_trk = 24;
1213 gamma_rho_trk = 1176;
1214 lock_count_thr = 8;
1215 break;
1216 case STB0899_QPSK_910:
1217 gamma_acq = 66;
1218 gamma_rho_acq = 29634;
1219 gamma_trk = 24;
1220 gamma_rho_trk = 1176;
1221 lock_count_thr = 8;
1222 break;
1223 default:
1224 gamma_acq = 66;
1225 gamma_rho_acq = 29634;
1226 gamma_trk = 24;
1227 gamma_rho_trk = 1176;
1228 lock_count_thr = 8;
1229 break;
1230 }
1231
1232 csm1 = STB0899_READ_S2REG(STB0899_S2DEMOD, CSM_CNTRL1);
1233 STB0899_SETFIELD_VAL(CSM_AUTO_PARAM, csm1, 0);
1234 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CSM_CNTRL1, STB0899_OFF0_CSM_CNTRL1, csm1);
1235
1236 csm1 = STB0899_READ_S2REG(STB0899_S2DEMOD, CSM_CNTRL1);
1237 csm2 = STB0899_READ_S2REG(STB0899_S2DEMOD, CSM_CNTRL2);
1238 csm3 = STB0899_READ_S2REG(STB0899_S2DEMOD, CSM_CNTRL3);
1239 csm4 = STB0899_READ_S2REG(STB0899_S2DEMOD, CSM_CNTRL4);
1240
1241 STB0899_SETFIELD_VAL(CSM_DVT_TABLE, csm1, dvt_tbl);
1242 STB0899_SETFIELD_VAL(CSM_TWO_PASS, csm1, two_pass);
1243 STB0899_SETFIELD_VAL(CSM_AGC_GAIN, csm1, agc_gain);
1244 STB0899_SETFIELD_VAL(CSM_AGC_SHIFT, csm1, agc_shift);
1245 STB0899_SETFIELD_VAL(FE_LOOP_SHIFT, csm1, loop_shift);
1246 STB0899_SETFIELD_VAL(CSM_GAMMA_ACQ, csm2, gamma_acq);
1247 STB0899_SETFIELD_VAL(CSM_GAMMA_RHOACQ, csm2, gamma_rho_acq);
1248 STB0899_SETFIELD_VAL(CSM_GAMMA_TRACK, csm3, gamma_trk);
1249 STB0899_SETFIELD_VAL(CSM_GAMMA_RHOTRACK, csm3, gamma_rho_trk);
1250 STB0899_SETFIELD_VAL(CSM_LOCKCOUNT_THRESH, csm4, lock_count_thr);
1251 STB0899_SETFIELD_VAL(CSM_PHASEDIFF_THRESH, csm4, phs_diff_thr);
1252
1253 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CSM_CNTRL1, STB0899_OFF0_CSM_CNTRL1, csm1);
1254 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CSM_CNTRL2, STB0899_OFF0_CSM_CNTRL2, csm2);
1255 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CSM_CNTRL3, STB0899_OFF0_CSM_CNTRL3, csm3);
1256 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CSM_CNTRL4, STB0899_OFF0_CSM_CNTRL4, csm4);
1257 }
1258}
1259
1260/*
1261 * stb0899_dvbs2_get_srate
1262 * get DVB-S2 Symbol Rate
1263 */
1264static u32 stb0899_dvbs2_get_srate(struct stb0899_state *state)
1265{
1266 struct stb0899_internal *internal = &state->internal;
1267 struct stb0899_config *config = state->config;
1268
1269 u32 bTrNomFreq, srate, decimRate, intval1, intval2, reg;
1270 int div1, div2, rem1, rem2;
1271
1272 div1 = config->btr_nco_bits / 2;
1273 div2 = config->btr_nco_bits - div1 - 1;
1274
1275 bTrNomFreq = STB0899_READ_S2REG(STB0899_S2DEMOD, BTR_NOM_FREQ);
1276
1277 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, DECIM_CNTRL);
1278 decimRate = STB0899_GETFIELD(DECIM_RATE, reg);
1279 decimRate = (1 << decimRate);
1280
1281 intval1 = internal->master_clk / (1 << div1);
1282 intval2 = bTrNomFreq / (1 << div2);
1283
1284 rem1 = internal->master_clk % (1 << div1);
1285 rem2 = bTrNomFreq % (1 << div2);
1286 /* only for integer calculation */
1287 srate = (intval1 * intval2) + ((intval1 * rem2) / (1 << div2)) + ((intval2 * rem1) / (1 << div1));
1288 srate /= decimRate; /*symbrate = (btrnomfreq_register_val*MasterClock)/2^(27+decim_rate_field) */
1289
1290 return srate;
1291}
1292
1293/*
1294 * stb0899_dvbs2_algo
1295 * Search for signal, timing, carrier and data for a given
1296 * frequency in a given range
1297 */
1298enum stb0899_status stb0899_dvbs2_algo(struct stb0899_state *state)
1299{
1300 struct stb0899_internal *internal = &state->internal;
1301 enum stb0899_modcod modcod;
1302
1303 s32 offsetfreq, searchTime, FecLockTime, pilots, iqSpectrum;
1304 int i = 0;
1305 u32 reg, csm1;
1306
1307 if (internal->srate <= 2000000) {
1308 searchTime = 5000; /* 5000 ms max time to lock UWP and CSM, SYMB <= 2Mbs */
1309 FecLockTime = 350; /* 350 ms max time to lock FEC, SYMB <= 2Mbs */
1310 } else if (internal->srate <= 5000000) {
1311 searchTime = 2500; /* 2500 ms max time to lock UWP and CSM, 2Mbs < SYMB <= 5Mbs */
1312 FecLockTime = 170; /* 170 ms max time to lock FEC, 2Mbs< SYMB <= 5Mbs */
1313 } else if (internal->srate <= 10000000) {
1314 searchTime = 1500; /* 1500 ms max time to lock UWP and CSM, 5Mbs <SYMB <= 10Mbs */
1315 FecLockTime = 80; /* 80 ms max time to lock FEC, 5Mbs< SYMB <= 10Mbs */
1316 } else if (internal->srate <= 15000000) {
1317 searchTime = 500; /* 500 ms max time to lock UWP and CSM, 10Mbs <SYMB <= 15Mbs */
1318 FecLockTime = 50; /* 50 ms max time to lock FEC, 10Mbs< SYMB <= 15Mbs */
1319 } else if (internal->srate <= 20000000) {
1320 searchTime = 300; /* 300 ms max time to lock UWP and CSM, 15Mbs < SYMB <= 20Mbs */
1321 FecLockTime = 30; /* 50 ms max time to lock FEC, 15Mbs< SYMB <= 20Mbs */
1322 } else if (internal->srate <= 25000000) {
1323 searchTime = 250; /* 250 ms max time to lock UWP and CSM, 20 Mbs < SYMB <= 25Mbs */
1324 FecLockTime = 25; /* 25 ms max time to lock FEC, 20Mbs< SYMB <= 25Mbs */
1325 } else {
1326 searchTime = 150; /* 150 ms max time to lock UWP and CSM, SYMB > 25Mbs */
1327 FecLockTime = 20; /* 20 ms max time to lock FEC, 20Mbs< SYMB <= 25Mbs */
1328 }
1329
1330 /* Maintain Stream Merger in reset during acquisition */
1331 reg = stb0899_read_reg(state, STB0899_TSTRES);
1332 STB0899_SETFIELD_VAL(FRESRS, reg, 1);
1333 stb0899_write_reg(state, STB0899_TSTRES, reg);
1334
40e8ce3d
MA		 1335 /* enable tuner I/O */
1336 stb0899_i2c_gate_ctrl(&state->frontend, 1);
1337
8bd135ba
MA		 1338 /* Move tuner to frequency */
1339 if (state->config->tuner_set_frequency)
1340 state->config->tuner_set_frequency(&state->frontend, internal->freq);
1341 if (state->config->tuner_get_frequency)
1342 state->config->tuner_get_frequency(&state->frontend, &internal->freq);
1343
40e8ce3d
MA		 1344 /* disable tuner I/O */
1345 stb0899_i2c_gate_ctrl(&state->frontend, 0);
1346
8bd135ba
MA		 1347 /* Set IF AGC to acquisition */
1348 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, IF_AGC_CNTRL);
1349 STB0899_SETFIELD_VAL(IF_LOOP_GAIN, reg, 4);
1350 STB0899_SETFIELD_VAL(IF_AGC_REF, reg, 32);
1351 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_IF_AGC_CNTRL, STB0899_OFF0_IF_AGC_CNTRL, reg);
1352
1353 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, IF_AGC_CNTRL2);
1354 STB0899_SETFIELD_VAL(IF_AGC_DUMP_PER, reg, 0);
1355 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_IF_AGC_CNTRL2, STB0899_OFF0_IF_AGC_CNTRL2, reg);
1356
1357 /* Initialisation */
1358 stb0899_dvbs2_init_calc(state);
1359
1360 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, DMD_CNTRL2);
1361 switch (internal->inversion) {
1362 case IQ_SWAP_OFF:
1363 STB0899_SETFIELD_VAL(SPECTRUM_INVERT, reg, 0);
1364 break;
1365 case IQ_SWAP_ON:
1366 STB0899_SETFIELD_VAL(SPECTRUM_INVERT, reg, 1);
1367 break;
1368 case IQ_SWAP_AUTO: /* use last successful search first */
1369 STB0899_SETFIELD_VAL(SPECTRUM_INVERT, reg, 1);
1370 break;
1371 }
1372 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_DMD_CNTRL2, STB0899_OFF0_DMD_CNTRL2, reg);
1373 stb0899_dvbs2_reacquire(state);
1374
1375 /* Wait for demod lock (UWP and CSM) */
1376 internal->status = stb0899_dvbs2_get_dmd_status(state, searchTime);
1377
1378 if (internal->status == DVBS2_DEMOD_LOCK) {
1379 dprintk(state->verbose, FE_DEBUG, 1, "------------> DVB-S2 DEMOD LOCK !");
1380 i = 0;
1381 /* Demod Locked, check FEC status */
1382 internal->status = stb0899_dvbs2_get_fec_status(state, FecLockTime);
1383
1384 /*If false lock (UWP and CSM Locked but no FEC) try 3 time max*/
1385 while ((internal->status != DVBS2_FEC_LOCK) && (i < 3)) {
1386 /* Read the frequency offset*/
1387 offsetfreq = STB0899_READ_S2REG(STB0899_S2DEMOD, CRL_FREQ);
1388
1389 /* Set the Nominal frequency to the found frequency offset for the next reacquire*/
1390 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, CRL_NOM_FREQ);
1391 STB0899_SETFIELD_VAL(CRL_NOM_FREQ, reg, offsetfreq);
08bcdbec 1392 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CRL_NOM_FREQ, STB0899_OFF0_CRL_NOM_FREQ, reg);
8bd135ba
MA		 1393 stb0899_dvbs2_reacquire(state);
1394 internal->status = stb0899_dvbs2_get_fec_status(state, searchTime);
1395 i++;
1396 }
1397 }
1398
1399 if (internal->status != DVBS2_FEC_LOCK) {
1400 if (internal->inversion == IQ_SWAP_AUTO) {
1401 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, DMD_CNTRL2);
1402 iqSpectrum = STB0899_GETFIELD(SPECTRUM_INVERT, reg);
1403 /* IQ Spectrum Inversion */
1404 STB0899_SETFIELD_VAL(SPECTRUM_INVERT, reg, !iqSpectrum);
1405 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_DMD_CNTRL2, STB0899_OFF0_DMD_CNTRL2, reg);
1406 /* start acquistion process */
1407 stb0899_dvbs2_reacquire(state);
1408
1409 /* Wait for demod lock (UWP and CSM) */
1410 internal->status = stb0899_dvbs2_get_dmd_status(state, searchTime);
1411 if (internal->status == DVBS2_DEMOD_LOCK) {
1412 i = 0;
1413 /* Demod Locked, check FEC */
1414 internal->status = stb0899_dvbs2_get_fec_status(state, FecLockTime);
1415 /*try thrice for false locks, (UWP and CSM Locked but no FEC) */
1416 while ((internal->status != DVBS2_FEC_LOCK) && (i < 3)) {
1417 /* Read the frequency offset*/
1418 offsetfreq = STB0899_READ_S2REG(STB0899_S2DEMOD, CRL_FREQ);
1419
1420 /* Set the Nominal frequency to the found frequency offset for the next reacquire*/
1421 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, CRL_NOM_FREQ);
1422 STB0899_SETFIELD_VAL(CRL_NOM_FREQ, reg, offsetfreq);
08bcdbec 1423 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CRL_NOM_FREQ, STB0899_OFF0_CRL_NOM_FREQ, reg);
8bd135ba
MA		 1424
1425 stb0899_dvbs2_reacquire(state);
1426 internal->status = stb0899_dvbs2_get_fec_status(state, searchTime);
1427 i++;
1428 }
1429 }
1430/*
1431 if (pParams->DVBS2State == FE_DVBS2_FEC_LOCKED)
1432 pParams->IQLocked = !iqSpectrum;
1433*/
1434 }
1435 }
1436 if (internal->status == DVBS2_FEC_LOCK) {
1437 dprintk(state->verbose, FE_DEBUG, 1, "----------------> DVB-S2 FEC Lock !");
1438 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, UWP_STAT2);
1439 modcod = STB0899_GETFIELD(UWP_DECODE_MOD, reg) >> 2;
1440 pilots = STB0899_GETFIELD(UWP_DECODE_MOD, reg) & 0x01;
1441
1442 if ((((10 * internal->master_clk) / (internal->srate / 10)) <= 410) &&
1443 (INRANGE(STB0899_QPSK_23, modcod, STB0899_QPSK_910)) &&
1444 (pilots == 1)) {
1445
1446 stb0899_dvbs2_init_csm(state, pilots, modcod);
1447 /* Wait for UWP,CSM and data LOCK 20ms max */
1448 internal->status = stb0899_dvbs2_get_fec_status(state, FecLockTime);
1449
1450 i = 0;
1451 while ((internal->status != DVBS2_FEC_LOCK) && (i < 3)) {
1452 csm1 = STB0899_READ_S2REG(STB0899_S2DEMOD, CSM_CNTRL1);
1453 STB0899_SETFIELD_VAL(CSM_TWO_PASS, csm1, 1);
1454 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CSM_CNTRL1, STB0899_OFF0_CSM_CNTRL1, csm1);
1455 csm1 = STB0899_READ_S2REG(STB0899_S2DEMOD, CSM_CNTRL1);
1456 STB0899_SETFIELD_VAL(CSM_TWO_PASS, csm1, 0);
1457 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CSM_CNTRL1, STB0899_OFF0_CSM_CNTRL1, csm1);
1458
1459 internal->status = stb0899_dvbs2_get_fec_status(state, FecLockTime);
1460 i++;
1461 }
1462 }
1463
1464 if ((((10 * internal->master_clk) / (internal->srate / 10)) <= 410) &&
1465 (INRANGE(STB0899_QPSK_12, modcod, STB0899_QPSK_35)) &&
1466 (pilots == 1)) {
1467
1468 /* Equalizer Disable update */
1469 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, EQ_CNTRL);
1470 STB0899_SETFIELD_VAL(EQ_DISABLE_UPDATE, reg, 1);
1471 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_EQ_CNTRL, STB0899_OFF0_EQ_CNTRL, reg);
1472 }
1473
1474 /* slow down the Equalizer once locked */
1475 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, EQ_CNTRL);
1476 STB0899_SETFIELD_VAL(EQ_SHIFT, reg, 0x02);
1477 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_EQ_CNTRL, STB0899_OFF0_EQ_CNTRL, reg);
1478
1479 /* Store signal parameters */
1480 offsetfreq = STB0899_READ_S2REG(STB0899_S2DEMOD, CRL_FREQ);
1481
1482 offsetfreq = offsetfreq / ((1 << 30) / 1000);
1483 offsetfreq *= (internal->master_clk / 1000000);
1484 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, DMD_CNTRL2);
1485 if (STB0899_GETFIELD(SPECTRUM_INVERT, reg))
1486 offsetfreq *= -1;
1487
1488 internal->freq = internal->freq - offsetfreq;
1489 internal->srate = stb0899_dvbs2_get_srate(state);
1490
1491 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, UWP_STAT2);
1492 internal->modcod = STB0899_GETFIELD(UWP_DECODE_MOD, reg) >> 2;
1493 internal->pilots = STB0899_GETFIELD(UWP_DECODE_MOD, reg) & 0x01;
1494 internal->frame_length = (STB0899_GETFIELD(UWP_DECODE_MOD, reg) >> 1) & 0x01;
1495
1496 /* Set IF AGC to tracking */
1497 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, IF_AGC_CNTRL);
1498 STB0899_SETFIELD_VAL(IF_LOOP_GAIN, reg, 3);
1499
1500 /* if QPSK 1/2,QPSK 3/5 or QPSK 2/3 set IF AGC reference to 16 otherwise 32*/
1501 if (INRANGE(STB0899_QPSK_12, internal->modcod, STB0899_QPSK_23))
1502 STB0899_SETFIELD_VAL(IF_AGC_REF, reg, 16);
1503
1504 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_IF_AGC_CNTRL, STB0899_OFF0_IF_AGC_CNTRL, reg);
1505
1506 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, IF_AGC_CNTRL2);
1507 STB0899_SETFIELD_VAL(IF_AGC_DUMP_PER, reg, 7);
1508 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_IF_AGC_CNTRL2, STB0899_OFF0_IF_AGC_CNTRL2, reg);
1509 }
1510
1511 /* Release Stream Merger Reset */
1512 reg = stb0899_read_reg(state, STB0899_TSTRES);
1513 STB0899_SETFIELD_VAL(FRESRS, reg, 0);
1514 stb0899_write_reg(state, STB0899_TSTRES, reg);
1515
1516 return internal->status;
1517}
Linux 6.x block layer and io_uring tree(s)