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Merge branch 'omap-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel...
[linux-2.6-block.git] / drivers / media / dvb / frontends / mb86a16.c
CommitLineData
41e840b1
MA		 1/*
2 Fujitsu MB86A16 DVB-S/DSS DC Receiver driver
3
4cd191fb 4 Copyright (C) Manu Abraham (abraham.manu@gmail.com)
41e840b1
MA		 5
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2 of the License, or
9 (at your option) any later version.
10
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19*/
20
21#include <linux/init.h>
22#include <linux/kernel.h>
23#include <linux/module.h>
24#include <linux/moduleparam.h>
25
26#include "dvb_frontend.h"
27#include "mb86a16.h"
28#include "mb86a16_priv.h"
29
30unsigned int verbose = 5;
31module_param(verbose, int, 0644);
32
33#define ABS(x) ((x) < 0 ? (-x) : (x))
34
35struct mb86a16_state {
36 struct i2c_adapter *i2c_adap;
37 const struct mb86a16_config *config;
38 struct dvb_frontend frontend;
41e840b1 39
f5ae4f6f 40 /* tuning parameters */
41e840b1
MA		 41 int frequency;
42 int srate;
43
f5ae4f6f 44 /* Internal stuff */
41e840b1
MA		 45 int master_clk;
46 int deci;
47 int csel;
48 int rsel;
49};
50
51#define MB86A16_ERROR 0
52#define MB86A16_NOTICE 1
53#define MB86A16_INFO 2
54#define MB86A16_DEBUG 3
55
56#define dprintk(x, y, z, format, arg...) do { \
57 if (z) { \
58 if ((x > MB86A16_ERROR) && (x > y)) \
59 printk(KERN_ERR "%s: " format "\n", __func__, ##arg); \
60 else if ((x > MB86A16_NOTICE) && (x > y)) \
61 printk(KERN_NOTICE "%s: " format "\n", __func__, ##arg); \
62 else if ((x > MB86A16_INFO) && (x > y)) \
63 printk(KERN_INFO "%s: " format "\n", __func__, ##arg); \
64 else if ((x > MB86A16_DEBUG) && (x > y)) \
65 printk(KERN_DEBUG "%s: " format "\n", __func__, ##arg); \
66 } else { \
67 if (x > y) \
68 printk(format, ##arg); \
69 } \
70} while (0)
71
72#define TRACE_IN dprintk(verbose, MB86A16_DEBUG, 1, "-->()")
73#define TRACE_OUT dprintk(verbose, MB86A16_DEBUG, 1, "()-->")
74
75static int mb86a16_write(struct mb86a16_state *state, u8 reg, u8 val)
76{
77 int ret;
78 u8 buf[] = { reg, val };
79
80 struct i2c_msg msg = {
81 .addr = state->config->demod_address,
82 .flags = 0,
83 .buf = buf,
84 .len = 2
85 };
86
87 dprintk(verbose, MB86A16_DEBUG, 1,
88 "writing to [0x%02x],Reg[0x%02x],Data[0x%02x]",
89 state->config->demod_address, buf[0], buf[1]);
90
91 ret = i2c_transfer(state->i2c_adap, &msg, 1);
92
93 return (ret != 1) ? -EREMOTEIO : 0;
94}
95
96static int mb86a16_read(struct mb86a16_state *state, u8 reg, u8 *val)
97{
98 int ret;
99 u8 b0[] = { reg };
100 u8 b1[] = { 0 };
101
102 struct i2c_msg msg[] = {
103 {
104 .addr = state->config->demod_address,
105 .flags = 0,
106 .buf = b0,
107 .len = 1
f5ae4f6f 108 }, {
41e840b1
MA		 109 .addr = state->config->demod_address,
110 .flags = I2C_M_RD,
111 .buf = b1,
112 .len = 1
113 }
114 };
115 ret = i2c_transfer(state->i2c_adap, msg, 2);
116 if (ret != 2) {
117 dprintk(verbose, MB86A16_ERROR, 1, "read error(reg=0x%02x, ret=0x%i)",
118 reg, ret);
119
120 return -EREMOTEIO;
121 }
122 *val = b1[0];
123
124 return ret;
125}
126
127static int CNTM_set(struct mb86a16_state *state,
128 unsigned char timint1,
129 unsigned char timint2,
130 unsigned char cnext)
131{
132 unsigned char val;
133
134 val = (timint1 << 4) | (timint2 << 2) | cnext;
135 if (mb86a16_write(state, MB86A16_CNTMR, val) < 0)
136 goto err;
137
138 return 0;
139
140err:
141 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
142 return -EREMOTEIO;
143}
144
145static int smrt_set(struct mb86a16_state *state, int rate)
146{
147 int tmp ;
148 int m ;
149 unsigned char STOFS0, STOFS1;
150
151 m = 1 << state->deci;
152 tmp = (8192 * state->master_clk - 2 * m * rate * 8192 + state->master_clk / 2) / state->master_clk;
153
154 STOFS0 = tmp & 0x0ff;
155 STOFS1 = (tmp & 0xf00) >> 8;
156
157 if (mb86a16_write(state, MB86A16_SRATE1, (state->deci << 2) |
158 (state->csel << 1) |
159 state->rsel) < 0)
160 goto err;
161 if (mb86a16_write(state, MB86A16_SRATE2, STOFS0) < 0)
162 goto err;
163 if (mb86a16_write(state, MB86A16_SRATE3, STOFS1) < 0)
164 goto err;
165
166 return 0;
167err:
168 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
169 return -1;
170}
171
172static int srst(struct mb86a16_state *state)
173{
174 if (mb86a16_write(state, MB86A16_RESET, 0x04) < 0)
175 goto err;
176
177 return 0;
178err:
179 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
180 return -EREMOTEIO;
181
182}
183
184static int afcex_data_set(struct mb86a16_state *state,
185 unsigned char AFCEX_L,
186 unsigned char AFCEX_H)
187{
188 if (mb86a16_write(state, MB86A16_AFCEXL, AFCEX_L) < 0)
189 goto err;
190 if (mb86a16_write(state, MB86A16_AFCEXH, AFCEX_H) < 0)
191 goto err;
192
193 return 0;
194err:
195 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
196
197 return -1;
198}
199
200static int afcofs_data_set(struct mb86a16_state *state,
201 unsigned char AFCEX_L,
202 unsigned char AFCEX_H)
203{
204 if (mb86a16_write(state, 0x58, AFCEX_L) < 0)
205 goto err;
206 if (mb86a16_write(state, 0x59, AFCEX_H) < 0)
207 goto err;
208
209 return 0;
210err:
211 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
212 return -EREMOTEIO;
213}
214
215static int stlp_set(struct mb86a16_state *state,
216 unsigned char STRAS,
217 unsigned char STRBS)
218{
219 if (mb86a16_write(state, MB86A16_STRFILTCOEF1, (STRBS << 3) | (STRAS)) < 0)
220 goto err;
221
222 return 0;
223err:
224 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
225 return -EREMOTEIO;
226}
227
228static int Vi_set(struct mb86a16_state *state, unsigned char ETH, unsigned char VIA)
229{
230 if (mb86a16_write(state, MB86A16_VISET2, 0x04) < 0)
231 goto err;
232 if (mb86a16_write(state, MB86A16_VISET3, 0xf5) < 0)
233 goto err;
234
235 return 0;
236err:
237 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
238 return -EREMOTEIO;
239}
240
241static int initial_set(struct mb86a16_state *state)
242{
243 if (stlp_set(state, 5, 7))
244 goto err;
a890cce5
MA		 245
246 udelay(100);
41e840b1
MA		 247 if (afcex_data_set(state, 0, 0))
248 goto err;
a890cce5
MA		 249
250 udelay(100);
41e840b1
MA		 251 if (afcofs_data_set(state, 0, 0))
252 goto err;
253
a890cce5 254 udelay(100);
41e840b1
MA		 255 if (mb86a16_write(state, MB86A16_CRLFILTCOEF1, 0x16) < 0)
256 goto err;
257 if (mb86a16_write(state, 0x2f, 0x21) < 0)
258 goto err;
259 if (mb86a16_write(state, MB86A16_VIMAG, 0x38) < 0)
260 goto err;
261 if (mb86a16_write(state, MB86A16_FAGCS1, 0x00) < 0)
262 goto err;
263 if (mb86a16_write(state, MB86A16_FAGCS2, 0x1c) < 0)
264 goto err;
265 if (mb86a16_write(state, MB86A16_FAGCS3, 0x20) < 0)
266 goto err;
267 if (mb86a16_write(state, MB86A16_FAGCS4, 0x1e) < 0)
268 goto err;
269 if (mb86a16_write(state, MB86A16_FAGCS5, 0x23) < 0)
270 goto err;
271 if (mb86a16_write(state, 0x54, 0xff) < 0)
272 goto err;
273 if (mb86a16_write(state, MB86A16_TSOUT, 0x00) < 0)
274 goto err;
275
276 return 0;
277
278err:
279 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
280 return -EREMOTEIO;
281}
282
283static int S01T_set(struct mb86a16_state *state,
284 unsigned char s1t,
285 unsigned s0t)
286{
287 if (mb86a16_write(state, 0x33, (s1t << 3) | s0t) < 0)
288 goto err;
289
290 return 0;
291err:
292 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
293 return -EREMOTEIO;
294}
295
296
297static int EN_set(struct mb86a16_state *state,
298 int cren,
299 int afcen)
300{
301 unsigned char val;
302
303 val = 0x7a | (cren << 7) | (afcen << 2);
304 if (mb86a16_write(state, 0x49, val) < 0)
305 goto err;
306
307 return 0;
308err:
309 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
310 return -EREMOTEIO;
311}
312
313static int AFCEXEN_set(struct mb86a16_state *state,
314 int afcexen,
315 int smrt)
316{
317 unsigned char AFCA ;
318
319 if (smrt > 18875)
320 AFCA = 4;
321 else if (smrt > 9375)
322 AFCA = 3;
323 else if (smrt > 2250)
324 AFCA = 2;
325 else
326 AFCA = 1;
327
328 if (mb86a16_write(state, 0x2a, 0x02 | (afcexen << 5) | (AFCA << 2)) < 0)
329 goto err;
330
331 return 0;
332
333err:
334 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
335 return -EREMOTEIO;
336}
337
338static int DAGC_data_set(struct mb86a16_state *state,
339 unsigned char DAGCA,
340 unsigned char DAGCW)
341{
342 if (mb86a16_write(state, 0x2d, (DAGCA << 3) | DAGCW) < 0)
343 goto err;
344
345 return 0;
346
347err:
348 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
349 return -EREMOTEIO;
350}
351
352static void smrt_info_get(struct mb86a16_state *state, int rate)
353{
354 if (rate >= 37501) {
355 state->deci = 0; state->csel = 0; state->rsel = 0;
356 } else if (rate >= 30001) {
357 state->deci = 0; state->csel = 0; state->rsel = 1;
358 } else if (rate >= 26251) {
359 state->deci = 0; state->csel = 1; state->rsel = 0;
360 } else if (rate >= 22501) {
361 state->deci = 0; state->csel = 1; state->rsel = 1;
362 } else if (rate >= 18751) {
363 state->deci = 1; state->csel = 0; state->rsel = 0;
364 } else if (rate >= 15001) {
365 state->deci = 1; state->csel = 0; state->rsel = 1;
366 } else if (rate >= 13126) {
367 state->deci = 1; state->csel = 1; state->rsel = 0;
368 } else if (rate >= 11251) {
369 state->deci = 1; state->csel = 1; state->rsel = 1;
370 } else if (rate >= 9376) {
371 state->deci = 2; state->csel = 0; state->rsel = 0;
372 } else if (rate >= 7501) {
373 state->deci = 2; state->csel = 0; state->rsel = 1;
374 } else if (rate >= 6563) {
375 state->deci = 2; state->csel = 1; state->rsel = 0;
376 } else if (rate >= 5626) {
377 state->deci = 2; state->csel = 1; state->rsel = 1;
378 } else if (rate >= 4688) {
379 state->deci = 3; state->csel = 0; state->rsel = 0;
380 } else if (rate >= 3751) {
381 state->deci = 3; state->csel = 0; state->rsel = 1;
382 } else if (rate >= 3282) {
383 state->deci = 3; state->csel = 1; state->rsel = 0;
384 } else if (rate >= 2814) {
385 state->deci = 3; state->csel = 1; state->rsel = 1;
386 } else if (rate >= 2344) {
387 state->deci = 4; state->csel = 0; state->rsel = 0;
388 } else if (rate >= 1876) {
389 state->deci = 4; state->csel = 0; state->rsel = 1;
390 } else if (rate >= 1641) {
391 state->deci = 4; state->csel = 1; state->rsel = 0;
392 } else if (rate >= 1407) {
393 state->deci = 4; state->csel = 1; state->rsel = 1;
394 } else if (rate >= 1172) {
395 state->deci = 5; state->csel = 0; state->rsel = 0;
396 } else if (rate >= 939) {
397 state->deci = 5; state->csel = 0; state->rsel = 1;
398 } else if (rate >= 821) {
399 state->deci = 5; state->csel = 1; state->rsel = 0;
400 } else {
401 state->deci = 5; state->csel = 1; state->rsel = 1;
402 }
403
404 if (state->csel == 0)
405 state->master_clk = 92000;
406 else
407 state->master_clk = 61333;
408
409}
410
411static int signal_det(struct mb86a16_state *state,
412 int smrt,
413 unsigned char *SIG)
414{
415
416 int ret ;
417 int smrtd ;
418 int wait_sym ;
e15c7ccd
MA		 419
420 u32 wait_t;
41e840b1
MA		 421 unsigned char S[3] ;
422 int i ;
423
424 if (*SIG > 45) {
425 if (CNTM_set(state, 2, 1, 2) < 0) {
426 dprintk(verbose, MB86A16_ERROR, 1, "CNTM set Error");
427 return -1;
428 }
429 wait_sym = 40000;
430 } else {
431 if (CNTM_set(state, 3, 1, 2) < 0) {
432 dprintk(verbose, MB86A16_ERROR, 1, "CNTM set Error");
433 return -1;
434 }
435 wait_sym = 80000;
436 }
437 for (i = 0; i < 3; i++) {
f5ae4f6f 438 if (i == 0)
41e840b1
MA		 439 smrtd = smrt * 98 / 100;
440 else if (i == 1)
441 smrtd = smrt;
442 else
443 smrtd = smrt * 102 / 100;
444 smrt_info_get(state, smrtd);
445 smrt_set(state, smrtd);
446 srst(state);
447 wait_t = (wait_sym + 99 * smrtd / 100) / smrtd;
448 if (wait_t == 0)
449 wait_t = 1;
450 msleep_interruptible(10);
451 if (mb86a16_read(state, 0x37, &(S[i])) != 2) {
452 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
453 return -EREMOTEIO;
454 }
455 }
456 if ((S[1] > S[0] * 112 / 100) &&
457 (S[1] > S[2] * 112 / 100)) {
458
459 ret = 1;
460 } else {
461 ret = 0;
462 }
463 *SIG = S[1];
464
465 if (CNTM_set(state, 0, 1, 2) < 0) {
466 dprintk(verbose, MB86A16_ERROR, 1, "CNTM set Error");
467 return -1;
468 }
469
470 return ret;
471}
472
473static int rf_val_set(struct mb86a16_state *state,
474 int f,
475 int smrt,
476 unsigned char R)
477{
478 unsigned char C, F, B;
479 int M;
480 unsigned char rf_val[5];
481 int ack = -1;
482
f5ae4f6f 483 if (smrt > 37750)
41e840b1
MA		 484 C = 1;
485 else if (smrt > 18875)
486 C = 2;
f5ae4f6f 487 else if (smrt > 5500)
41e840b1
MA		 488 C = 3;
489 else
490 C = 4;
491
492 if (smrt > 30500)
493 F = 3;
494 else if (smrt > 9375)
495 F = 1;
496 else if (smrt > 4625)
497 F = 0;
498 else
499 F = 2;
500
501 if (f < 1060)
502 B = 0;
503 else if (f < 1175)
504 B = 1;
505 else if (f < 1305)
506 B = 2;
507 else if (f < 1435)
508 B = 3;
509 else if (f < 1570)
510 B = 4;
511 else if (f < 1715)
512 B = 5;
513 else if (f < 1845)
514 B = 6;
515 else if (f < 1980)
516 B = 7;
517 else if (f < 2080)
518 B = 8;
519 else
520 B = 9;
521
522 M = f * (1 << R) / 2;
523
524 rf_val[0] = 0x01 | (C << 3) | (F << 1);
525 rf_val[1] = (R << 5) | ((M & 0x1f000) >> 12);
526 rf_val[2] = (M & 0x00ff0) >> 4;
527 rf_val[3] = ((M & 0x0000f) << 4) | B;
528
f5ae4f6f 529 /* Frequency Set */
41e840b1
MA		 530 if (mb86a16_write(state, 0x21, rf_val[0]) < 0)
531 ack = 0;
532 if (mb86a16_write(state, 0x22, rf_val[1]) < 0)
533 ack = 0;
534 if (mb86a16_write(state, 0x23, rf_val[2]) < 0)
535 ack = 0;
536 if (mb86a16_write(state, 0x24, rf_val[3]) < 0)
537 ack = 0;
538 if (mb86a16_write(state, 0x25, 0x01) < 0)
539 ack = 0;
540 if (ack == 0) {
541 dprintk(verbose, MB86A16_ERROR, 1, "RF Setup - I2C transfer error");
542 return -EREMOTEIO;
543 }
544
545 return 0;
546}
547
548static int afcerr_chk(struct mb86a16_state *state)
549{
550 unsigned char AFCM_L, AFCM_H ;
551 int AFCM ;
552 int afcm, afcerr ;
553
554 if (mb86a16_read(state, 0x0e, &AFCM_L) != 2)
555 goto err;
556 if (mb86a16_read(state, 0x0f, &AFCM_H) != 2)
557 goto err;
558
559 AFCM = (AFCM_H << 8) + AFCM_L;
560
561 if (AFCM > 2048)
562 afcm = AFCM - 4096;
563 else
564 afcm = AFCM;
565 afcerr = afcm * state->master_clk / 8192;
566
567 return afcerr;
568
569err:
570 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
571 return -EREMOTEIO;
572}
573
574static int dagcm_val_get(struct mb86a16_state *state)
575{
576 int DAGCM;
577 unsigned char DAGCM_H, DAGCM_L;
578
579 if (mb86a16_read(state, 0x45, &DAGCM_L) != 2)
580 goto err;
581 if (mb86a16_read(state, 0x46, &DAGCM_H) != 2)
582 goto err;
583
584 DAGCM = (DAGCM_H << 8) + DAGCM_L;
585
586 return DAGCM;
587
588err:
589 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
590 return -EREMOTEIO;
591}
592
593static int mb86a16_read_status(struct dvb_frontend *fe, fe_status_t *status)
594{
77557abe 595 u8 stat, stat2;
41e840b1
MA		 596 struct mb86a16_state *state = fe->demodulator_priv;
597
1fa1f107 598 *status = 0;
77557abe
MA		 599
600 if (mb86a16_read(state, MB86A16_SIG1, &stat) != 2)
601 goto err;
602 if (mb86a16_read(state, MB86A16_SIG2, &stat2) != 2)
603 goto err;
604 if ((stat > 25) && (stat2 > 25))
605 *status |= FE_HAS_SIGNAL;
606 if ((stat > 45) && (stat2 > 45))
607 *status |= FE_HAS_CARRIER;
608
609 if (mb86a16_read(state, MB86A16_STATUS, &stat) != 2)
610 goto err;
611
612 if (stat & 0x01)
41e840b1 613 *status |= FE_HAS_SYNC;
77557abe
MA		 614 if (stat & 0x01)
615 *status |= FE_HAS_VITERBI;
616
617 if (mb86a16_read(state, MB86A16_FRAMESYNC, &stat) != 2)
618 goto err;
619
620 if ((stat & 0x0f) && (*status & FE_HAS_VITERBI))
41e840b1
MA		 621 *status |= FE_HAS_LOCK;
622
623 return 0;
77557abe
MA		 624
625err:
626 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
627 return -EREMOTEIO;
41e840b1
MA		 628}
629
630static int sync_chk(struct mb86a16_state *state,
631 unsigned char *VIRM)
632{
633 unsigned char val;
634 int sync;
635
636 if (mb86a16_read(state, 0x0d, &val) != 2)
637 goto err;
638
639 dprintk(verbose, MB86A16_INFO, 1, "Status = %02x,", val);
640 sync = val & 0x01;
641 *VIRM = (val & 0x1c) >> 2;
642
643 return sync;
644err:
645 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
646 return -EREMOTEIO;
647
648}
649
650static int freqerr_chk(struct mb86a16_state *state,
651 int fTP,
652 int smrt,
653 int unit)
654{
655 unsigned char CRM, AFCML, AFCMH;
656 unsigned char temp1, temp2, temp3;
657 int crm, afcm, AFCM;
f5ae4f6f
MA		 658 int crrerr, afcerr; /* kHz */
659 int frqerr; /* MHz */
41e840b1
MA		 660 int afcen, afcexen = 0;
661 int R, M, fOSC, fOSC_OFS;
662
663 if (mb86a16_read(state, 0x43, &CRM) != 2)
664 goto err;
665
666 if (CRM > 127)
667 crm = CRM - 256;
668 else
669 crm = CRM;
670
671 crrerr = smrt * crm / 256;
672 if (mb86a16_read(state, 0x49, &temp1) != 2)
673 goto err;
674
675 afcen = (temp1 & 0x04) >> 2;
676 if (afcen == 0) {
677 if (mb86a16_read(state, 0x2a, &temp1) != 2)
678 goto err;
679 afcexen = (temp1 & 0x20) >> 5;
680 }
681
682 if (afcen == 1) {
683 if (mb86a16_read(state, 0x0e, &AFCML) != 2)
684 goto err;
685 if (mb86a16_read(state, 0x0f, &AFCMH) != 2)
686 goto err;
687 } else if (afcexen == 1) {
688 if (mb86a16_read(state, 0x2b, &AFCML) != 2)
689 goto err;
690 if (mb86a16_read(state, 0x2c, &AFCMH) != 2)
691 goto err;
692 }
693 if ((afcen == 1) || (afcexen == 1)) {
694 smrt_info_get(state, smrt);
695 AFCM = ((AFCMH & 0x01) << 8) + AFCML;
696 if (AFCM > 255)
697 afcm = AFCM - 512;
698 else
699 afcm = AFCM;
700
701 afcerr = afcm * state->master_clk / 8192;
702 } else
703 afcerr = 0;
704
705 if (mb86a16_read(state, 0x22, &temp1) != 2)
706 goto err;
707 if (mb86a16_read(state, 0x23, &temp2) != 2)
708 goto err;
709 if (mb86a16_read(state, 0x24, &temp3) != 2)
710 goto err;
711
712 R = (temp1 & 0xe0) >> 5;
713 M = ((temp1 & 0x1f) << 12) + (temp2 << 4) + (temp3 >> 4);
714 if (R == 0)
715 fOSC = 2 * M;
716 else
717 fOSC = M;
718
719 fOSC_OFS = fOSC - fTP;
720
f5ae4f6f 721 if (unit == 0) { /* MHz */
41e840b1
MA		 722 if (crrerr + afcerr + fOSC_OFS * 1000 >= 0)
723 frqerr = (crrerr + afcerr + fOSC_OFS * 1000 + 500) / 1000;
724 else
725 frqerr = (crrerr + afcerr + fOSC_OFS * 1000 - 500) / 1000;
f5ae4f6f 726 } else { /* kHz */
41e840b1
MA		 727 frqerr = crrerr + afcerr + fOSC_OFS * 1000;
728 }
729
730 return frqerr;
731err:
732 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
733 return -EREMOTEIO;
734}
735
736static unsigned char vco_dev_get(struct mb86a16_state *state, int smrt)
737{
738 unsigned char R;
739
740 if (smrt > 9375)
741 R = 0;
742 else
743 R = 1;
744
745 return R;
746}
747
748static void swp_info_get(struct mb86a16_state *state,
749 int fOSC_start,
750 int smrt,
751 int v, int R,
752 int swp_ofs,
753 int *fOSC,
754 int *afcex_freq,
755 unsigned char *AFCEX_L,
756 unsigned char *AFCEX_H)
757{
758 int AFCEX ;
759 int crnt_swp_freq ;
760
761 crnt_swp_freq = fOSC_start * 1000 + v * swp_ofs;
762
f5ae4f6f 763 if (R == 0)
41e840b1
MA		 764 *fOSC = (crnt_swp_freq + 1000) / 2000 * 2;
765 else
766 *fOSC = (crnt_swp_freq + 500) / 1000;
767
768 if (*fOSC >= crnt_swp_freq)
f5ae4f6f 769 *afcex_freq = *fOSC * 1000 - crnt_swp_freq;
41e840b1
MA		 770 else
771 *afcex_freq = crnt_swp_freq - *fOSC * 1000;
772
773 AFCEX = *afcex_freq * 8192 / state->master_clk;
774 *AFCEX_L = AFCEX & 0x00ff;
775 *AFCEX_H = (AFCEX & 0x0f00) >> 8;
776}
777
778
779static int swp_freq_calcuation(struct mb86a16_state *state, int i, int v, int *V, int vmax, int vmin,
780 int SIGMIN, int fOSC, int afcex_freq, int swp_ofs, unsigned char *SIG1)
781{
782 int swp_freq ;
783
784 if ((i % 2 == 1) && (v <= vmax)) {
f5ae4f6f 785 /* positive v (case 1) */
41e840b1
MA		 786 if ((v - 1 == vmin) &&
787 (*(V + 30 + v) >= 0) &&
788 (*(V + 30 + v - 1) >= 0) &&
789 (*(V + 30 + v - 1) > *(V + 30 + v)) &&
790 (*(V + 30 + v - 1) > SIGMIN)) {
791
792 swp_freq = fOSC * 1000 + afcex_freq - swp_ofs;
793 *SIG1 = *(V + 30 + v - 1);
794 } else if ((v == vmax) &&
795 (*(V + 30 + v) >= 0) &&
796 (*(V + 30 + v - 1) >= 0) &&
797 (*(V + 30 + v) > *(V + 30 + v - 1)) &&
798 (*(V + 30 + v) > SIGMIN)) {
f5ae4f6f 799 /* (case 2) */
41e840b1
MA		 800 swp_freq = fOSC * 1000 + afcex_freq;
801 *SIG1 = *(V + 30 + v);
802 } else if ((*(V + 30 + v) > 0) &&
803 (*(V + 30 + v - 1) > 0) &&
804 (*(V + 30 + v - 2) > 0) &&
805 (*(V + 30 + v - 3) > 0) &&
806 (*(V + 30 + v - 1) > *(V + 30 + v)) &&
807 (*(V + 30 + v - 2) > *(V + 30 + v - 3)) &&
808 ((*(V + 30 + v - 1) > SIGMIN) ||
809 (*(V + 30 + v - 2) > SIGMIN))) {
f5ae4f6f 810 /* (case 3) */
41e840b1
MA		 811 if (*(V + 30 + v - 1) >= *(V + 30 + v - 2)) {
812 swp_freq = fOSC * 1000 + afcex_freq - swp_ofs;
813 *SIG1 = *(V + 30 + v - 1);
814 } else {
815 swp_freq = fOSC * 1000 + afcex_freq - swp_ofs * 2;
816 *SIG1 = *(V + 30 + v - 2);
817 }
818 } else if ((v == vmax) &&
819 (*(V + 30 + v) >= 0) &&
820 (*(V + 30 + v - 1) >= 0) &&
821 (*(V + 30 + v - 2) >= 0) &&
822 (*(V + 30 + v) > *(V + 30 + v - 2)) &&
823 (*(V + 30 + v - 1) > *(V + 30 + v - 2)) &&
824 ((*(V + 30 + v) > SIGMIN) ||
825 (*(V + 30 + v - 1) > SIGMIN))) {
f5ae4f6f 826 /* (case 4) */
41e840b1
MA		 827 if (*(V + 30 + v) >= *(V + 30 + v - 1)) {
828 swp_freq = fOSC * 1000 + afcex_freq;
829 *SIG1 = *(V + 30 + v);
830 } else {
831 swp_freq = fOSC * 1000 + afcex_freq - swp_ofs;
832 *SIG1 = *(V + 30 + v - 1);
833 }
834 } else {
835 swp_freq = -1 ;
836 }
837 } else if ((i % 2 == 0) && (v >= vmin)) {
f5ae4f6f 838 /* Negative v (case 1) */
41e840b1
MA		 839 if ((*(V + 30 + v) > 0) &&
840 (*(V + 30 + v + 1) > 0) &&
841 (*(V + 30 + v + 2) > 0) &&
842 (*(V + 30 + v + 1) > *(V + 30 + v)) &&
843 (*(V + 30 + v + 1) > *(V + 30 + v + 2)) &&
844 (*(V + 30 + v + 1) > SIGMIN)) {
845
846 swp_freq = fOSC * 1000 + afcex_freq + swp_ofs;
847 *SIG1 = *(V + 30 + v + 1);
848 } else if ((v + 1 == vmax) &&
849 (*(V + 30 + v) >= 0) &&
850 (*(V + 30 + v + 1) >= 0) &&
851 (*(V + 30 + v + 1) > *(V + 30 + v)) &&
852 (*(V + 30 + v + 1) > SIGMIN)) {
f5ae4f6f 853 /* (case 2) */
41e840b1
MA		 854 swp_freq = fOSC * 1000 + afcex_freq + swp_ofs;
855 *SIG1 = *(V + 30 + v);
856 } else if ((v == vmin) &&
857 (*(V + 30 + v) > 0) &&
858 (*(V + 30 + v + 1) > 0) &&
859 (*(V + 30 + v + 2) > 0) &&
860 (*(V + 30 + v) > *(V + 30 + v + 1)) &&
861 (*(V + 30 + v) > *(V + 30 + v + 2)) &&
862 (*(V + 30 + v) > SIGMIN)) {
f5ae4f6f 863 /* (case 3) */
41e840b1
MA		 864 swp_freq = fOSC * 1000 + afcex_freq;
865 *SIG1 = *(V + 30 + v);
866 } else if ((*(V + 30 + v) >= 0) &&
867 (*(V + 30 + v + 1) >= 0) &&
868 (*(V + 30 + v + 2) >= 0) &&
f5ae4f6f 869 (*(V + 30 + v + 3) >= 0) &&
41e840b1
MA		 870 (*(V + 30 + v + 1) > *(V + 30 + v)) &&
871 (*(V + 30 + v + 2) > *(V + 30 + v + 3)) &&
872 ((*(V + 30 + v + 1) > SIGMIN) ||
873 (*(V + 30 + v + 2) > SIGMIN))) {
f5ae4f6f 874 /* (case 4) */
41e840b1
MA		 875 if (*(V + 30 + v + 1) >= *(V + 30 + v + 2)) {
876 swp_freq = fOSC * 1000 + afcex_freq + swp_ofs;
877 *SIG1 = *(V + 30 + v + 1);
878 } else {
879 swp_freq = fOSC * 1000 + afcex_freq + swp_ofs * 2;
880 *SIG1 = *(V + 30 + v + 2);
881 }
882 } else if ((*(V + 30 + v) >= 0) &&
883 (*(V + 30 + v + 1) >= 0) &&
884 (*(V + 30 + v + 2) >= 0) &&
885 (*(V + 30 + v + 3) >= 0) &&
886 (*(V + 30 + v) > *(V + 30 + v + 2)) &&
887 (*(V + 30 + v + 1) > *(V + 30 + v + 2)) &&
888 (*(V + 30 + v) > *(V + 30 + v + 3)) &&
889 (*(V + 30 + v + 1) > *(V + 30 + v + 3)) &&
890 ((*(V + 30 + v) > SIGMIN) ||
891 (*(V + 30 + v + 1) > SIGMIN))) {
f5ae4f6f 892 /* (case 5) */
41e840b1
MA		 893 if (*(V + 30 + v) >= *(V + 30 + v + 1)) {
894 swp_freq = fOSC * 1000 + afcex_freq;
895 *SIG1 = *(V + 30 + v);
896 } else {
897 swp_freq = fOSC * 1000 + afcex_freq + swp_ofs;
898 *SIG1 = *(V + 30 + v + 1);
899 }
900 } else if ((v + 2 == vmin) &&
901 (*(V + 30 + v) >= 0) &&
902 (*(V + 30 + v + 1) >= 0) &&
903 (*(V + 30 + v + 2) >= 0) &&
904 (*(V + 30 + v + 1) > *(V + 30 + v)) &&
905 (*(V + 30 + v + 2) > *(V + 30 + v)) &&
906 ((*(V + 30 + v + 1) > SIGMIN) ||
907 (*(V + 30 + v + 2) > SIGMIN))) {
f5ae4f6f 908 /* (case 6) */
41e840b1
MA		 909 if (*(V + 30 + v + 1) >= *(V + 30 + v + 2)) {
910 swp_freq = fOSC * 1000 + afcex_freq + swp_ofs;
911 *SIG1 = *(V + 30 + v + 1);
912 } else {
913 swp_freq = fOSC * 1000 + afcex_freq + swp_ofs * 2;
914 *SIG1 = *(V + 30 + v + 2);
915 }
916 } else if ((vmax == 0) && (vmin == 0) && (*(V + 30 + v) > SIGMIN)) {
917 swp_freq = fOSC * 1000;
918 *SIG1 = *(V + 30 + v);
f5ae4f6f
MA		 919 } else
920 swp_freq = -1;
921 } else
922 swp_freq = -1;
41e840b1
MA		 923
924 return swp_freq;
925}
926
927static void swp_info_get2(struct mb86a16_state *state,
928 int smrt,
929 int R,
930 int swp_freq,
931 int *afcex_freq,
932 int *fOSC,
933 unsigned char *AFCEX_L,
934 unsigned char *AFCEX_H)
935{
936 int AFCEX ;
937
938 if (R == 0)
939 *fOSC = (swp_freq + 1000) / 2000 * 2;
940 else
941 *fOSC = (swp_freq + 500) / 1000;
942
943 if (*fOSC >= swp_freq)
944 *afcex_freq = *fOSC * 1000 - swp_freq;
945 else
946 *afcex_freq = swp_freq - *fOSC * 1000;
947
948 AFCEX = *afcex_freq * 8192 / state->master_clk;
949 *AFCEX_L = AFCEX & 0x00ff;
950 *AFCEX_H = (AFCEX & 0x0f00) >> 8;
951}
952
953static void afcex_info_get(struct mb86a16_state *state,
954 int afcex_freq,
955 unsigned char *AFCEX_L,
956 unsigned char *AFCEX_H)
957{
958 int AFCEX ;
959
960 AFCEX = afcex_freq * 8192 / state->master_clk;
961 *AFCEX_L = AFCEX & 0x00ff;
962 *AFCEX_H = (AFCEX & 0x0f00) >> 8;
963}
964
965static int SEQ_set(struct mb86a16_state *state, unsigned char loop)
966{
f5ae4f6f 967 /* SLOCK0 = 0 */
41e840b1
MA		 968 if (mb86a16_write(state, 0x32, 0x02 | (loop << 2)) < 0) {
969 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
970 return -EREMOTEIO;
971 }
972
973 return 0;
974}
975
976static int iq_vt_set(struct mb86a16_state *state, unsigned char IQINV)
977{
f5ae4f6f 978 /* Viterbi Rate, IQ Settings */
41e840b1
MA		 979 if (mb86a16_write(state, 0x06, 0xdf | (IQINV << 5)) < 0) {
980 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
981 return -EREMOTEIO;
982 }
983
984 return 0;
985}
986
987static int FEC_srst(struct mb86a16_state *state)
988{
989 if (mb86a16_write(state, MB86A16_RESET, 0x02) < 0) {
990 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
991 return -EREMOTEIO;
992 }
993
994 return 0;
995}
996
997static int S2T_set(struct mb86a16_state *state, unsigned char S2T)
998{
999 if (mb86a16_write(state, 0x34, 0x70 | S2T) < 0) {
1000 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
1001 return -EREMOTEIO;
1002 }
1003
1004 return 0;
1005}
1006
1007static int S45T_set(struct mb86a16_state *state, unsigned char S4T, unsigned char S5T)
1008{
1009 if (mb86a16_write(state, 0x35, 0x00 | (S5T << 4) | S4T) < 0) {
1010 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
1011 return -EREMOTEIO;
1012 }
1013
1014 return 0;
1015}
1016
1017
1018static int mb86a16_set_fe(struct mb86a16_state *state)
1019{
1020 u8 agcval, cnmval;
1021
1022 int i, j;
1023 int fOSC = 0;
1024 int fOSC_start = 0;
1025 int wait_t;
1026 int fcp;
1027 int swp_ofs;
1028 int V[60];
1029 u8 SIG1MIN;
1030
1031 unsigned char CREN, AFCEN, AFCEXEN;
1032 unsigned char SIG1;
1033 unsigned char TIMINT1, TIMINT2, TIMEXT;
1034 unsigned char S0T, S1T;
1035 unsigned char S2T;
f5ae4f6f 1036/* unsigned char S2T, S3T; */
41e840b1
MA		 1037 unsigned char S4T, S5T;
1038 unsigned char AFCEX_L, AFCEX_H;
1039 unsigned char R;
1040 unsigned char VIRM;
1041 unsigned char ETH, VIA;
1042 unsigned char junk;
1043
1044 int loop;
1045 int ftemp;
1046 int v, vmax, vmin;
1047 int vmax_his, vmin_his;
1048 int swp_freq, prev_swp_freq[20];
1049 int prev_freq_num;
1050 int signal_dupl;
1051 int afcex_freq;
1052 int signal;
1053 int afcerr;
1054 int temp_freq, delta_freq;
1055 int dagcm[4];
1056 int smrt_d;
f5ae4f6f 1057/* int freq_err; */
41e840b1
MA		 1058 int n;
1059 int ret = -1;
1060 int sync;
1061
1062 dprintk(verbose, MB86A16_INFO, 1, "freq=%d Mhz, symbrt=%d Ksps", state->frequency, state->srate);
1063
b05c90de 1064 fcp = 3000;
41e840b1
MA		 1065 swp_ofs = state->srate / 4;
1066
1067 for (i = 0; i < 60; i++)
1068 V[i] = -1;
1069
1070 for (i = 0; i < 20; i++)
1071 prev_swp_freq[i] = 0;
1072
1073 SIG1MIN = 25;
1074
1075 for (n = 0; ((n < 3) && (ret == -1)); n++) {
1076 SEQ_set(state, 0);
1077 iq_vt_set(state, 0);
1078
1079 CREN = 0;
1080 AFCEN = 0;
1081 AFCEXEN = 1;
1082 TIMINT1 = 0;
1083 TIMINT2 = 1;
1084 TIMEXT = 2;
1085 S1T = 0;
1086 S0T = 0;
1087
1088 if (initial_set(state) < 0) {
1089 dprintk(verbose, MB86A16_ERROR, 1, "initial set failed");
1090 return -1;
1091 }
1092 if (DAGC_data_set(state, 3, 2) < 0) {
1093 dprintk(verbose, MB86A16_ERROR, 1, "DAGC data set error");
1094 return -1;
1095 }
1096 if (EN_set(state, CREN, AFCEN) < 0) {
1097 dprintk(verbose, MB86A16_ERROR, 1, "EN set error");
f5ae4f6f 1098 return -1; /* (0, 0) */
41e840b1
MA		 1099 }
1100 if (AFCEXEN_set(state, AFCEXEN, state->srate) < 0) {
1101 dprintk(verbose, MB86A16_ERROR, 1, "AFCEXEN set error");
f5ae4f6f 1102 return -1; /* (1, smrt) = (1, symbolrate) */
41e840b1
MA		 1103 }
1104 if (CNTM_set(state, TIMINT1, TIMINT2, TIMEXT) < 0) {
1105 dprintk(verbose, MB86A16_ERROR, 1, "CNTM set error");
f5ae4f6f 1106 return -1; /* (0, 1, 2) */
41e840b1
MA		 1107 }
1108 if (S01T_set(state, S1T, S0T) < 0) {
1109 dprintk(verbose, MB86A16_ERROR, 1, "S01T set error");
f5ae4f6f 1110 return -1; /* (0, 0) */
41e840b1
MA		 1111 }
1112 smrt_info_get(state, state->srate);
1113 if (smrt_set(state, state->srate) < 0) {
1114 dprintk(verbose, MB86A16_ERROR, 1, "smrt info get error");
1115 return -1;
1116 }
1117
1118 R = vco_dev_get(state, state->srate);
1119 if (R == 1)
1120 fOSC_start = state->frequency;
1121
1122 else if (R == 0) {
1123 if (state->frequency % 2 == 0) {
1124 fOSC_start = state->frequency;
1125 } else {
1126 fOSC_start = state->frequency + 1;
1127 if (fOSC_start > 2150)
1128 fOSC_start = state->frequency - 1;
1129 }
1130 }
1131 loop = 1;
1132 ftemp = fOSC_start * 1000;
1133 vmax = 0 ;
1134 while (loop == 1) {
1135 ftemp = ftemp + swp_ofs;
1136 vmax++;
1137
f5ae4f6f 1138 /* Upper bound */
41e840b1
MA		 1139 if (ftemp > 2150000) {
1140 loop = 0;
1141 vmax--;
f5ae4f6f
MA		 1142 } else {
1143 if ((ftemp == 2150000) ||
1144 (ftemp - state->frequency * 1000 >= fcp + state->srate / 4))
1145 loop = 0;
41e840b1 1146 }
41e840b1
MA		 1147 }
1148
1149 loop = 1;
1150 ftemp = fOSC_start * 1000;
1151 vmin = 0 ;
1152 while (loop == 1) {
1153 ftemp = ftemp - swp_ofs;
1154 vmin--;
1155
f5ae4f6f 1156 /* Lower bound */
41e840b1
MA		 1157 if (ftemp < 950000) {
1158 loop = 0;
1159 vmin++;
f5ae4f6f
MA		 1160 } else {
1161 if ((ftemp == 950000) ||
1162 (state->frequency * 1000 - ftemp >= fcp + state->srate / 4))
1163 loop = 0;
41e840b1 1164 }
41e840b1
MA		 1165 }
1166
1167 wait_t = (8000 + state->srate / 2) / state->srate;
1168 if (wait_t == 0)
1169 wait_t = 1;
1170
1171 i = 0;
1172 j = 0;
1173 prev_freq_num = 0;
1174 loop = 1;
1175 signal = 0;
1176 vmax_his = 0;
1177 vmin_his = 0;
1178 v = 0;
1179
1180 while (loop == 1) {
1181 swp_info_get(state, fOSC_start, state->srate,
1182 v, R, swp_ofs, &fOSC,
1183 &afcex_freq, &AFCEX_L, &AFCEX_H);
1184
a890cce5 1185 udelay(100);
41e840b1
MA		 1186 if (rf_val_set(state, fOSC, state->srate, R) < 0) {
1187 dprintk(verbose, MB86A16_ERROR, 1, "rf val set error");
1188 return -1;
1189 }
a890cce5 1190 udelay(100);
41e840b1
MA		 1191 if (afcex_data_set(state, AFCEX_L, AFCEX_H) < 0) {
1192 dprintk(verbose, MB86A16_ERROR, 1, "afcex data set error");
1193 return -1;
1194 }
1195 if (srst(state) < 0) {
1196 dprintk(verbose, MB86A16_ERROR, 1, "srst error");
1197 return -1;
1198 }
1199 msleep_interruptible(wait_t);
1200
1201 if (mb86a16_read(state, 0x37, &SIG1) != 2) {
1202 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
1203 return -1;
1204 }
1205 V[30 + v] = SIG1 ;
1206 swp_freq = swp_freq_calcuation(state, i, v, V, vmax, vmin,
1207 SIG1MIN, fOSC, afcex_freq,
f5ae4f6f 1208 swp_ofs, &SIG1); /* changed */
41e840b1
MA		 1209
1210 signal_dupl = 0;
1211 for (j = 0; j < prev_freq_num; j++) {
1212 if ((ABS(prev_swp_freq[j] - swp_freq)) < (swp_ofs * 3 / 2)) {
1213 signal_dupl = 1;
1214 dprintk(verbose, MB86A16_INFO, 1, "Probably Duplicate Signal, j = %d", j);
1215 }
1216 }
1217 if ((signal_dupl == 0) && (swp_freq > 0) && (ABS(swp_freq - state->frequency * 1000) < fcp + state->srate / 6)) {
1218 dprintk(verbose, MB86A16_DEBUG, 1, "------ Signal detect ------ [swp_freq=[%07d, srate=%05d]]", swp_freq, state->srate);
1219 prev_swp_freq[prev_freq_num] = swp_freq;
1220 prev_freq_num++;
1221 swp_info_get2(state, state->srate, R, swp_freq,
1222 &afcex_freq, &fOSC,
1223 &AFCEX_L, &AFCEX_H);
1224
1225 if (rf_val_set(state, fOSC, state->srate, R) < 0) {
1226 dprintk(verbose, MB86A16_ERROR, 1, "rf val set error");
1227 return -1;
1228 }
1229 if (afcex_data_set(state, AFCEX_L, AFCEX_H) < 0) {
1230 dprintk(verbose, MB86A16_ERROR, 1, "afcex data set error");
1231 return -1;
1232 }
1233 signal = signal_det(state, state->srate, &SIG1);
1234 if (signal == 1) {
1235 dprintk(verbose, MB86A16_ERROR, 1, "***** Signal Found *****");
1236 loop = 0;
1237 } else {
1238 dprintk(verbose, MB86A16_ERROR, 1, "!!!!! No signal !!!!!, try again...");
1239 smrt_info_get(state, state->srate);
1240 if (smrt_set(state, state->srate) < 0) {
1241 dprintk(verbose, MB86A16_ERROR, 1, "smrt set error");
1242 return -1;
1243 }
1244 }
1245 }
1246 if (v > vmax)
1247 vmax_his = 1 ;
1248 if (v < vmin)
1249 vmin_his = 1 ;
1250 i++;
1251
1252 if ((i % 2 == 1) && (vmax_his == 1))
1253 i++;
1254 if ((i % 2 == 0) && (vmin_his == 1))
1255 i++;
1256
1257 if (i % 2 == 1)
1258 v = (i + 1) / 2;
1259 else
1260 v = -i / 2;
1261
1262 if ((vmax_his == 1) && (vmin_his == 1))
1263 loop = 0 ;
1264 }
1265
1266 if (signal == 1) {
1267 dprintk(verbose, MB86A16_INFO, 1, " Start Freq Error Check");
1268 S1T = 7 ;
1269 S0T = 1 ;
1270 CREN = 0 ;
1271 AFCEN = 1 ;
1272 AFCEXEN = 0 ;
1273
1274 if (S01T_set(state, S1T, S0T) < 0) {
1275 dprintk(verbose, MB86A16_ERROR, 1, "S01T set error");
1276 return -1;
1277 }
1278 smrt_info_get(state, state->srate);
1279 if (smrt_set(state, state->srate) < 0) {
1280 dprintk(verbose, MB86A16_ERROR, 1, "smrt set error");
1281 return -1;
1282 }
1283 if (EN_set(state, CREN, AFCEN) < 0) {
1284 dprintk(verbose, MB86A16_ERROR, 1, "EN set error");
1285 return -1;
1286 }
1287 if (AFCEXEN_set(state, AFCEXEN, state->srate) < 0) {
1288 dprintk(verbose, MB86A16_ERROR, 1, "AFCEXEN set error");
1289 return -1;
1290 }
1291 afcex_info_get(state, afcex_freq, &AFCEX_L, &AFCEX_H);
1292 if (afcofs_data_set(state, AFCEX_L, AFCEX_H) < 0) {
1293 dprintk(verbose, MB86A16_ERROR, 1, "AFCOFS data set error");
1294 return -1;
1295 }
1296 if (srst(state) < 0) {
1297 dprintk(verbose, MB86A16_ERROR, 1, "srst error");
1298 return -1;
1299 }
f5ae4f6f 1300 /* delay 4~200 */
41e840b1
MA		 1301 wait_t = 200000 / state->master_clk + 200000 / state->srate;
1302 msleep(wait_t);
1303 afcerr = afcerr_chk(state);
1304 if (afcerr == -1)
1305 return -1;
1306
1307 swp_freq = fOSC * 1000 + afcerr ;
1308 AFCEXEN = 1 ;
1309 if (state->srate >= 1500)
1310 smrt_d = state->srate / 3;
1311 else
1312 smrt_d = state->srate / 2;
1313 smrt_info_get(state, smrt_d);
1314 if (smrt_set(state, smrt_d) < 0) {
1315 dprintk(verbose, MB86A16_ERROR, 1, "smrt set error");
1316 return -1;
1317 }
1318 if (AFCEXEN_set(state, AFCEXEN, smrt_d) < 0) {
1319 dprintk(verbose, MB86A16_ERROR, 1, "AFCEXEN set error");
1320 return -1;
1321 }
1322 R = vco_dev_get(state, smrt_d);
1323 if (DAGC_data_set(state, 2, 0) < 0) {
1324 dprintk(verbose, MB86A16_ERROR, 1, "DAGC data set error");
1325 return -1;
1326 }
1327 for (i = 0; i < 3; i++) {
1328 temp_freq = swp_freq + (i - 1) * state->srate / 8;
1329 swp_info_get2(state, smrt_d, R, temp_freq, &afcex_freq, &fOSC, &AFCEX_L, &AFCEX_H);
1330 if (rf_val_set(state, fOSC, smrt_d, R) < 0) {
1331 dprintk(verbose, MB86A16_ERROR, 1, "rf val set error");
1332 return -1;
1333 }
1334 if (afcex_data_set(state, AFCEX_L, AFCEX_H) < 0) {
1335 dprintk(verbose, MB86A16_ERROR, 1, "afcex data set error");
1336 return -1;
1337 }
1338 wait_t = 200000 / state->master_clk + 40000 / smrt_d;
1339 msleep(wait_t);
1340 dagcm[i] = dagcm_val_get(state);
1341 }
1342 if ((dagcm[0] > dagcm[1]) &&
1343 (dagcm[0] > dagcm[2]) &&
1344 (dagcm[0] - dagcm[1] > 2 * (dagcm[2] - dagcm[1]))) {
1345
1346 temp_freq = swp_freq - 2 * state->srate / 8;
1347 swp_info_get2(state, smrt_d, R, temp_freq, &afcex_freq, &fOSC, &AFCEX_L, &AFCEX_H);
1348 if (rf_val_set(state, fOSC, smrt_d, R) < 0) {
1349 dprintk(verbose, MB86A16_ERROR, 1, "rf val set error");
1350 return -1;
1351 }
1352 if (afcex_data_set(state, AFCEX_L, AFCEX_H) < 0) {
1353 dprintk(verbose, MB86A16_ERROR, 1, "afcex data set");
1354 return -1;
1355 }
1356 wait_t = 200000 / state->master_clk + 40000 / smrt_d;
1357 msleep(wait_t);
1358 dagcm[3] = dagcm_val_get(state);
1359 if (dagcm[3] > dagcm[1])
1360 delta_freq = (dagcm[2] - dagcm[0] + dagcm[1] - dagcm[3]) * state->srate / 300;
1361 else
1362 delta_freq = 0;
1363 } else if ((dagcm[2] > dagcm[1]) &&
1364 (dagcm[2] > dagcm[0]) &&
1365 (dagcm[2] - dagcm[1] > 2 * (dagcm[0] - dagcm[1]))) {
1366
1367 temp_freq = swp_freq + 2 * state->srate / 8;
1368 swp_info_get2(state, smrt_d, R, temp_freq, &afcex_freq, &fOSC, &AFCEX_L, &AFCEX_H);
1369 if (rf_val_set(state, fOSC, smrt_d, R) < 0) {
1370 dprintk(verbose, MB86A16_ERROR, 1, "rf val set");
1371 return -1;
1372 }
1373 if (afcex_data_set(state, AFCEX_L, AFCEX_H) < 0) {
1374 dprintk(verbose, MB86A16_ERROR, 1, "afcex data set");
1375 return -1;
1376 }
1377 wait_t = 200000 / state->master_clk + 40000 / smrt_d;
1378 msleep(wait_t);
1379 dagcm[3] = dagcm_val_get(state);
1380 if (dagcm[3] > dagcm[1])
1381 delta_freq = (dagcm[2] - dagcm[0] + dagcm[3] - dagcm[1]) * state->srate / 300;
1382 else
1383 delta_freq = 0 ;
1384
1385 } else {
1386 delta_freq = 0 ;
1387 }
1388 dprintk(verbose, MB86A16_INFO, 1, "SWEEP Frequency = %d", swp_freq);
1389 swp_freq += delta_freq;
1390 dprintk(verbose, MB86A16_INFO, 1, "Adjusting .., DELTA Freq = %d, SWEEP Freq=%d", delta_freq, swp_freq);
1391 if (ABS(state->frequency * 1000 - swp_freq) > 3800) {
1392 dprintk(verbose, MB86A16_INFO, 1, "NO -- SIGNAL !");
1393 } else {
1394
1395 S1T = 0;
1396 S0T = 3;
1397 CREN = 1;
1398 AFCEN = 0;
1399 AFCEXEN = 1;
1400
1401 if (S01T_set(state, S1T, S0T) < 0) {
1402 dprintk(verbose, MB86A16_ERROR, 1, "S01T set error");
1403 return -1;
1404 }
1405 if (DAGC_data_set(state, 0, 0) < 0) {
1406 dprintk(verbose, MB86A16_ERROR, 1, "DAGC data set error");
1407 return -1;
1408 }
1409 R = vco_dev_get(state, state->srate);
1410 smrt_info_get(state, state->srate);
1411 if (smrt_set(state, state->srate) < 0) {
1412 dprintk(verbose, MB86A16_ERROR, 1, "smrt set error");
1413 return -1;
1414 }
1415 if (EN_set(state, CREN, AFCEN) < 0) {
1416 dprintk(verbose, MB86A16_ERROR, 1, "EN set error");
1417 return -1;
1418 }
1419 if (AFCEXEN_set(state, AFCEXEN, state->srate) < 0) {
1420 dprintk(verbose, MB86A16_ERROR, 1, "AFCEXEN set error");
1421 return -1;
1422 }
1423 swp_info_get2(state, state->srate, R, swp_freq, &afcex_freq, &fOSC, &AFCEX_L, &AFCEX_H);
1424 if (rf_val_set(state, fOSC, state->srate, R) < 0) {
1425 dprintk(verbose, MB86A16_ERROR, 1, "rf val set error");
1426 return -1;
1427 }
1428 if (afcex_data_set(state, AFCEX_L, AFCEX_H) < 0) {
1429 dprintk(verbose, MB86A16_ERROR, 1, "afcex data set error");
1430 return -1;
1431 }
1432 if (srst(state) < 0) {
1433 dprintk(verbose, MB86A16_ERROR, 1, "srst error");
1434 return -1;
1435 }
1436 wait_t = 7 + (10000 + state->srate / 2) / state->srate;
1437 if (wait_t == 0)
1438 wait_t = 1;
1439 msleep_interruptible(wait_t);
1440 if (mb86a16_read(state, 0x37, &SIG1) != 2) {
1441 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
1442 return -EREMOTEIO;
1443 }
1444
1445 if (SIG1 > 110) {
1446 S2T = 4; S4T = 1; S5T = 6; ETH = 4; VIA = 6;
1447 wait_t = 7 + (917504 + state->srate / 2) / state->srate;
1448 } else if (SIG1 > 105) {
1449 S2T = 4; S4T = 2; S5T = 8; ETH = 7; VIA = 2;
1450 wait_t = 7 + (1048576 + state->srate / 2) / state->srate;
1451 } else if (SIG1 > 85) {
1452 S2T = 5; S4T = 2; S5T = 8; ETH = 7; VIA = 2;
1453 wait_t = 7 + (1310720 + state->srate / 2) / state->srate;
1454 } else if (SIG1 > 65) {
1455 S2T = 6; S4T = 2; S5T = 8; ETH = 7; VIA = 2;
1456 wait_t = 7 + (1572864 + state->srate / 2) / state->srate;
1457 } else {
1458 S2T = 7; S4T = 2; S5T = 8; ETH = 7; VIA = 2;
1459 wait_t = 7 + (2097152 + state->srate / 2) / state->srate;
1460 }
f5ae4f6f 1461 wait_t *= 2; /* FOS */
41e840b1
MA		 1462 S2T_set(state, S2T);
1463 S45T_set(state, S4T, S5T);
1464 Vi_set(state, ETH, VIA);
1465 srst(state);
1466 msleep_interruptible(wait_t);
1467 sync = sync_chk(state, &VIRM);
1468 dprintk(verbose, MB86A16_INFO, 1, "-------- Viterbi=[%d] SYNC=[%d] ---------", VIRM, sync);
41e840b1 1469 if (VIRM) {
f5ae4f6f
MA		 1470 if (VIRM == 4) {
1471 /* 5/6 */
41e840b1 1472 if (SIG1 > 110)
f5ae4f6f 1473 wait_t = (786432 + state->srate / 2) / state->srate;
41e840b1
MA		 1474 else
1475 wait_t = (1572864 + state->srate / 2) / state->srate;
1476 if (state->srate < 5000)
f5ae4f6f 1477 /* FIXME ! , should be a long wait ! */
41e840b1
MA		 1478 msleep_interruptible(wait_t);
1479 else
1480 msleep_interruptible(wait_t);
1481
1482 if (sync_chk(state, &junk) == 0) {
1483 iq_vt_set(state, 1);
1484 FEC_srst(state);
1485 }
41e840b1 1486 }
f5ae4f6f 1487 /* 1/2, 2/3, 3/4, 7/8 */
77557abe 1488 if (SIG1 > 110)
f5ae4f6f 1489 wait_t = (786432 + state->srate / 2) / state->srate;
77557abe
MA		 1490 else
1491 wait_t = (1572864 + state->srate / 2) / state->srate;
1492 msleep_interruptible(wait_t);
1493 SEQ_set(state, 1);
41e840b1 1494 } else {
776c3ebe 1495 dprintk(verbose, MB86A16_INFO, 1, "NO -- SYNC");
41e840b1 1496 SEQ_set(state, 1);
5dd83a35 1497 ret = -1;
41e840b1
MA		 1498 }
1499 }
1500 } else {
f5ae4f6f 1501 dprintk(verbose, MB86A16_INFO, 1, "NO -- SIGNAL");
5dd83a35 1502 ret = -1;
41e840b1
MA		 1503 }
1504
1505 sync = sync_chk(state, &junk);
1506 if (sync) {
1507 dprintk(verbose, MB86A16_INFO, 1, "******* SYNC *******");
1508 freqerr_chk(state, state->frequency, state->srate, 1);
5dd83a35 1509 ret = 0;
071e3060 1510 break;
41e840b1
MA		 1511 }
1512 }
1513
1514 mb86a16_read(state, 0x15, &agcval);
1515 mb86a16_read(state, 0x26, &cnmval);
1516 dprintk(verbose, MB86A16_INFO, 1, "AGC = %02x CNM = %02x", agcval, cnmval);
1517
1518 return ret;
1519}
1520
1521static int mb86a16_send_diseqc_msg(struct dvb_frontend *fe,
1522 struct dvb_diseqc_master_cmd *cmd)
1523{
1524 struct mb86a16_state *state = fe->demodulator_priv;
1525 int i;
1526 u8 regs;
1527
1528 if (mb86a16_write(state, MB86A16_DCC1, MB86A16_DCC1_DISTA) < 0)
1529 goto err;
1530 if (mb86a16_write(state, MB86A16_DCCOUT, 0x00) < 0)
1531 goto err;
1532 if (mb86a16_write(state, MB86A16_TONEOUT2, 0x04) < 0)
1533 goto err;
1534
1535 regs = 0x18;
1536
1537 if (cmd->msg_len > 5 || cmd->msg_len < 4)
1538 return -EINVAL;
1539
1540 for (i = 0; i < cmd->msg_len; i++) {
1541 if (mb86a16_write(state, regs, cmd->msg[i]) < 0)
1542 goto err;
1543
1544 regs++;
1545 }
1546 i += 0x90;
1547
1548 msleep_interruptible(10);
1549
1550 if (mb86a16_write(state, MB86A16_DCC1, i) < 0)
1551 goto err;
1552 if (mb86a16_write(state, MB86A16_DCCOUT, MB86A16_DCCOUT_DISEN) < 0)
1553 goto err;
1554
1555 return 0;
1556
1557err:
1558 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
1559 return -EREMOTEIO;
1560}
1561
1562static int mb86a16_send_diseqc_burst(struct dvb_frontend *fe, fe_sec_mini_cmd_t burst)
1563{
1564 struct mb86a16_state *state = fe->demodulator_priv;
1565
1566 switch (burst) {
1567 case SEC_MINI_A:
1568 if (mb86a16_write(state, MB86A16_DCC1, MB86A16_DCC1_DISTA |
1569 MB86A16_DCC1_TBEN |
1570 MB86A16_DCC1_TBO) < 0)
1571 goto err;
1572 if (mb86a16_write(state, MB86A16_DCCOUT, MB86A16_DCCOUT_DISEN) < 0)
1573 goto err;
1574 break;
1575 case SEC_MINI_B:
1576 if (mb86a16_write(state, MB86A16_DCC1, MB86A16_DCC1_DISTA |
1577 MB86A16_DCC1_TBEN) < 0)
1578 goto err;
1579 if (mb86a16_write(state, MB86A16_DCCOUT, MB86A16_DCCOUT_DISEN) < 0)
1580 goto err;
1581 break;
1582 }
1583
1584 return 0;
1585err:
1586 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
1587 return -EREMOTEIO;
1588}
1589
1590static int mb86a16_set_tone(struct dvb_frontend *fe, fe_sec_tone_mode_t tone)
1591{
1592 struct mb86a16_state *state = fe->demodulator_priv;
1593
1594 switch (tone) {
1595 case SEC_TONE_ON:
1596 if (mb86a16_write(state, MB86A16_TONEOUT2, 0x00) < 0)
1597 goto err;
1598 if (mb86a16_write(state, MB86A16_DCC1, MB86A16_DCC1_DISTA |
1599 MB86A16_DCC1_CTOE) < 0)
1600
1601 goto err;
1602 if (mb86a16_write(state, MB86A16_DCCOUT, MB86A16_DCCOUT_DISEN) < 0)
1603 goto err;
1604 break;
1605 case SEC_TONE_OFF:
1606 if (mb86a16_write(state, MB86A16_TONEOUT2, 0x04) < 0)
1607 goto err;
1608 if (mb86a16_write(state, MB86A16_DCC1, MB86A16_DCC1_DISTA) < 0)
1609 goto err;
1610 if (mb86a16_write(state, MB86A16_DCCOUT, 0x00) < 0)
1611 goto err;
1612 break;
1613 default:
1614 return -EINVAL;
1615 }
1616 return 0;
1617
1618err:
1619 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
1620 return -EREMOTEIO;
1621}
1622
5dd83a35
MA		 1623static enum dvbfe_search mb86a16_search(struct dvb_frontend *fe,
1624 struct dvb_frontend_parameters *p)
41e840b1 1625{
41e840b1
MA		 1626 struct mb86a16_state *state = fe->demodulator_priv;
1627
5dd83a35
MA		 1628 state->frequency = p->frequency / 1000;
1629 state->srate = p->u.qpsk.symbol_rate / 1000;
41e840b1 1630
5dd83a35
MA		 1631 if (!mb86a16_set_fe(state)) {
1632 dprintk(verbose, MB86A16_ERROR, 1, "Succesfully acquired LOCK");
1633 return DVBFE_ALGO_SEARCH_SUCCESS;
1634 }
41e840b1 1635
5dd83a35
MA		 1636 dprintk(verbose, MB86A16_ERROR, 1, "Lock acquisition failed!");
1637 return DVBFE_ALGO_SEARCH_FAILED;
41e840b1
MA		 1638}
1639
1640static void mb86a16_release(struct dvb_frontend *fe)
1641{
1642 struct mb86a16_state *state = fe->demodulator_priv;
1643 kfree(state);
1644}
1645
1646static int mb86a16_init(struct dvb_frontend *fe)
1647{
1648 return 0;
1649}
1650
1651static int mb86a16_sleep(struct dvb_frontend *fe)
1652{
1653 return 0;
1654}
1655
1656static int mb86a16_read_ber(struct dvb_frontend *fe, u32 *ber)
1657{
77557abe
MA		 1658 u8 ber_mon, ber_tab, ber_lsb, ber_mid, ber_msb, ber_tim, ber_rst;
1659 u32 timer;
1660
1661 struct mb86a16_state *state = fe->demodulator_priv;
1662
1663 *ber = 0;
1664 if (mb86a16_read(state, MB86A16_BERMON, &ber_mon) != 2)
1665 goto err;
1666 if (mb86a16_read(state, MB86A16_BERTAB, &ber_tab) != 2)
1667 goto err;
1668 if (mb86a16_read(state, MB86A16_BERLSB, &ber_lsb) != 2)
1669 goto err;
1670 if (mb86a16_read(state, MB86A16_BERMID, &ber_mid) != 2)
1671 goto err;
1672 if (mb86a16_read(state, MB86A16_BERMSB, &ber_msb) != 2)
1673 goto err;
1674 /* BER monitor invalid when BER_EN = 0 */
1675 if (ber_mon & 0x04) {
1676 /* coarse, fast calculation */
1677 *ber = ber_tab & 0x1f;
1678 dprintk(verbose, MB86A16_DEBUG, 1, "BER coarse=[0x%02x]", *ber);
1679 if (ber_mon & 0x01) {
1680 /*
1681 * BER_SEL = 1, The monitored BER is the estimated
1682 * value with a Reed-Solomon decoder error amount at
1683 * the deinterleaver output.
1684 * monitored BER is expressed as a 20 bit output in total
1685 */
1686 ber_rst = ber_mon >> 3;
1687 *ber = (((ber_msb << 8) | ber_mid) << 8) | ber_lsb;
1688 if (ber_rst == 0)
1689 timer = 12500000;
1690 if (ber_rst == 1)
1691 timer = 25000000;
1692 if (ber_rst == 2)
1693 timer = 50000000;
1694 if (ber_rst == 3)
1695 timer = 100000000;
1696
1697 *ber /= timer;
1698 dprintk(verbose, MB86A16_DEBUG, 1, "BER fine=[0x%02x]", *ber);
1699 } else {
1700 /*
1701 * BER_SEL = 0, The monitored BER is the estimated
1702 * value with a Viterbi decoder error amount at the
1703 * QPSK demodulator output.
1704 * monitored BER is expressed as a 24 bit output in total
1705 */
1706 ber_tim = ber_mon >> 1;
1707 *ber = (((ber_msb << 8) | ber_mid) << 8) | ber_lsb;
1708 if (ber_tim == 0)
1709 timer = 16;
1710 if (ber_tim == 1)
1711 timer = 24;
1712
1713 *ber /= 2 ^ timer;
1714 dprintk(verbose, MB86A16_DEBUG, 1, "BER fine=[0x%02x]", *ber);
1715 }
1716 }
41e840b1 1717 return 0;
77557abe
MA		 1718err:
1719 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
1720 return -EREMOTEIO;
41e840b1
MA		 1721}
1722
1723static int mb86a16_read_signal_strength(struct dvb_frontend *fe, u16 *strength)
1724{
77557abe
MA		 1725 u8 agcm = 0;
1726 struct mb86a16_state *state = fe->demodulator_priv;
1727
41e840b1 1728 *strength = 0;
77557abe
MA		 1729 if (mb86a16_read(state, MB86A16_AGCM, &agcm) != 2) {
1730 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
1731 return -EREMOTEIO;
1732 }
1733
1734 *strength = ((0xff - agcm) * 100) / 256;
1735 dprintk(verbose, MB86A16_DEBUG, 1, "Signal strength=[%d %%]", (u8) *strength);
1736 *strength = (0xffff - 0xff) + agcm;
41e840b1
MA		 1737
1738 return 0;
1739}
1740
1741struct cnr {
1742 u8 cn_reg;
1743 u8 cn_val;
1744};
1745
1746static const struct cnr cnr_tab[] = {
1747 { 35, 2 },
1748 { 40, 3 },
1749 { 50, 4 },
1750 { 60, 5 },
1751 { 70, 6 },
1752 { 80, 7 },
1753 { 92, 8 },
1754 { 103, 9 },
1755 { 115, 10 },
1756 { 138, 12 },
1757 { 162, 15 },
1758 { 180, 18 },
1759 { 185, 19 },
1760 { 189, 20 },
1761 { 195, 22 },
1762 { 199, 24 },
1763 { 201, 25 },
1764 { 202, 26 },
1765 { 203, 27 },
1766 { 205, 28 },
1767 { 208, 30 }
1768};
1769
1770static int mb86a16_read_snr(struct dvb_frontend *fe, u16 *snr)
1771{
1772 struct mb86a16_state *state = fe->demodulator_priv;
1773 int i = 0;
1774 int low_tide = 2, high_tide = 30, q_level;
1775 u8 cn;
1776
1fa1f107 1777 *snr = 0;
41e840b1
MA		 1778 if (mb86a16_read(state, 0x26, &cn) != 2) {
1779 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
1780 return -EREMOTEIO;
1781 }
1782
1783 for (i = 0; i < ARRAY_SIZE(cnr_tab); i++) {
1784 if (cn < cnr_tab[i].cn_reg) {
1785 *snr = cnr_tab[i].cn_val;
1786 break;
1787 }
1788 }
1789 q_level = (*snr * 100) / (high_tide - low_tide);
1790 dprintk(verbose, MB86A16_ERROR, 1, "SNR (Quality) = [%d dB], Level=%d %%", *snr, q_level);
77557abe 1791 *snr = (0xffff - 0xff) + *snr;
41e840b1
MA		 1792
1793 return 0;
1794}
1795
1796static int mb86a16_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
1797{
77557abe
MA		 1798 u8 dist;
1799 struct mb86a16_state *state = fe->demodulator_priv;
1800
1801 if (mb86a16_read(state, MB86A16_DISTMON, &dist) != 2) {
1802 dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
1803 return -EREMOTEIO;
1804 }
1805 *ucblocks = dist;
1806
41e840b1
MA		 1807 return 0;
1808}
1809
5dd83a35
MA		 1810static enum dvbfe_algo mb86a16_frontend_algo(struct dvb_frontend *fe)
1811{
1812 return DVBFE_ALGO_CUSTOM;
1813}
1814
41e840b1
MA		 1815static struct dvb_frontend_ops mb86a16_ops = {
1816 .info = {
1817 .name = "Fujitsu MB86A16 DVB-S",
1818 .type = FE_QPSK,
1819 .frequency_min = 950000,
1820 .frequency_max = 2150000,
77557abe 1821 .frequency_stepsize = 3000,
41e840b1
MA		 1822 .frequency_tolerance = 0,
1823 .symbol_rate_min = 1000000,
1824 .symbol_rate_max = 45000000,
1825 .symbol_rate_tolerance = 500,
1826 .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 |
1827 FE_CAN_FEC_3_4 | FE_CAN_FEC_5_6 |
1828 FE_CAN_FEC_7_8 | FE_CAN_QPSK |
1829 FE_CAN_FEC_AUTO
1830 },
1831 .release = mb86a16_release,
5dd83a35 1832
41e840b1 1833 .get_frontend_algo = mb86a16_frontend_algo,
5dd83a35
MA		 1834 .search = mb86a16_search,
1835 .read_status = mb86a16_read_status,
41e840b1
MA		 1836 .init = mb86a16_init,
1837 .sleep = mb86a16_sleep,
1838 .read_status = mb86a16_read_status,
1839
1840 .read_ber = mb86a16_read_ber,
1841 .read_signal_strength = mb86a16_read_signal_strength,
1842 .read_snr = mb86a16_read_snr,
1843 .read_ucblocks = mb86a16_read_ucblocks,
1844
1845 .diseqc_send_master_cmd = mb86a16_send_diseqc_msg,
1846 .diseqc_send_burst = mb86a16_send_diseqc_burst,
1847 .set_tone = mb86a16_set_tone,
1848};
1849
1850struct dvb_frontend *mb86a16_attach(const struct mb86a16_config *config,
1851 struct i2c_adapter *i2c_adap)
1852{
1853 u8 dev_id = 0;
1854 struct mb86a16_state *state = NULL;
1855
f5ae4f6f 1856 state = kmalloc(sizeof(struct mb86a16_state), GFP_KERNEL);
41e840b1
MA		 1857 if (state == NULL)
1858 goto error;
1859
1860 state->config = config;
1861 state->i2c_adap = i2c_adap;
1862
1863 mb86a16_read(state, 0x7f, &dev_id);
1864 if (dev_id != 0xfe)
1865 goto error;
1866
f5ae4f6f 1867 memcpy(&state->frontend.ops, &mb86a16_ops, sizeof(struct dvb_frontend_ops));
41e840b1
MA		 1868 state->frontend.demodulator_priv = state;
1869 state->frontend.ops.set_voltage = state->config->set_voltage;
1870
1871 return &state->frontend;
1872error:
1873 kfree(state);
1874 return NULL;
1875}
1876EXPORT_SYMBOL(mb86a16_attach);
1877MODULE_LICENSE("GPL");
1878MODULE_AUTHOR("Manu Abraham");
Linux 6.x block layer and io_uring tree(s)