[linux-2.6-block.git] / drivers / media / dvb / frontends / drxk_hard.h

#include "drxk_map.h"

#define DRXK_VERSION_MAJOR 0
#define DRXK_VERSION_MINOR 9
#define DRXK_VERSION_PATCH 4300

#define HI_I2C_DELAY        42
#define HI_I2C_BRIDGE_DELAY 350
#define DRXK_MAX_RETRIES    100

#define DRIVER_4400 1

#define DRXX_JTAGID   0x039210D9
#define DRXX_J_JTAGID 0x239310D9
#define DRXX_K_JTAGID 0x039210D9

#define DRX_UNKNOWN     254
#define DRX_AUTO        255

#define DRX_SCU_READY   0
#define DRXK_MAX_WAITTIME (200)
#define SCU_RESULT_OK      0
#define SCU_RESULT_UNKSTD -2
#define SCU_RESULT_UNKCMD -1

#ifndef DRXK_OFDM_TR_SHUTDOWN_TIMEOUT
#define DRXK_OFDM_TR_SHUTDOWN_TIMEOUT (200)
#endif

#define DRXK_8VSB_MPEG_BIT_RATE     19392658UL  /*bps*/
#define DRXK_DVBT_MPEG_BIT_RATE     32000000UL  /*bps*/
#define DRXK_QAM16_MPEG_BIT_RATE    27000000UL  /*bps*/
#define DRXK_QAM32_MPEG_BIT_RATE    33000000UL  /*bps*/
#define DRXK_QAM64_MPEG_BIT_RATE    40000000UL  /*bps*/
#define DRXK_QAM128_MPEG_BIT_RATE   46000000UL  /*bps*/
#define DRXK_QAM256_MPEG_BIT_RATE   52000000UL  /*bps*/
#define DRXK_MAX_MPEG_BIT_RATE      52000000UL  /*bps*/

#define   IQM_CF_OUT_ENA_OFDM__M                                            0x4
#define     IQM_FS_ADJ_SEL_B_QAM                                            0x1
#define     IQM_FS_ADJ_SEL_B_OFF                                            0x0
#define     IQM_FS_ADJ_SEL_B_VSB                                            0x2
#define     IQM_RC_ADJ_SEL_B_OFF                                            0x0
#define     IQM_RC_ADJ_SEL_B_QAM                                            0x1
#define     IQM_RC_ADJ_SEL_B_VSB                                            0x2

enum OperationMode {
	OM_NONE,
	OM_QAM_ITU_A,
	OM_QAM_ITU_B,
	OM_QAM_ITU_C,
	OM_DVBT
};

enum DRXPowerMode {
	DRX_POWER_UP = 0,
	DRX_POWER_MODE_1,
	DRX_POWER_MODE_2,
	DRX_POWER_MODE_3,
	DRX_POWER_MODE_4,
	DRX_POWER_MODE_5,
	DRX_POWER_MODE_6,
	DRX_POWER_MODE_7,
	DRX_POWER_MODE_8,

	DRX_POWER_MODE_9,
	DRX_POWER_MODE_10,
	DRX_POWER_MODE_11,
	DRX_POWER_MODE_12,
	DRX_POWER_MODE_13,
	DRX_POWER_MODE_14,
	DRX_POWER_MODE_15,
	DRX_POWER_MODE_16,
	DRX_POWER_DOWN = 255
};


/** /brief Intermediate power mode for DRXK, power down OFDM clock domain */
#ifndef DRXK_POWER_DOWN_OFDM
#define DRXK_POWER_DOWN_OFDM        DRX_POWER_MODE_1
#endif

/** /brief Intermediate power mode for DRXK, power down core (sysclk) */
#ifndef DRXK_POWER_DOWN_CORE
#define DRXK_POWER_DOWN_CORE        DRX_POWER_MODE_9
#endif

/** /brief Intermediate power mode for DRXK, power down pll (only osc runs) */
#ifndef DRXK_POWER_DOWN_PLL
#define DRXK_POWER_DOWN_PLL         DRX_POWER_MODE_10
#endif


enum AGC_CTRL_MODE { DRXK_AGC_CTRL_AUTO = 0, DRXK_AGC_CTRL_USER, DRXK_AGC_CTRL_OFF };
enum EDrxkState { DRXK_UNINITIALIZED = 0, DRXK_STOPPED, DRXK_DTV_STARTED, DRXK_ATV_STARTED, DRXK_POWERED_DOWN };
enum EDrxkCoefArrayIndex {
	DRXK_COEF_IDX_MN = 0,
	DRXK_COEF_IDX_FM    ,
	DRXK_COEF_IDX_L     ,
	DRXK_COEF_IDX_LP    ,
	DRXK_COEF_IDX_BG    ,
	DRXK_COEF_IDX_DK    ,
	DRXK_COEF_IDX_I     ,
	DRXK_COEF_IDX_MAX
};
enum EDrxkSifAttenuation {
	DRXK_SIF_ATTENUATION_0DB,
	DRXK_SIF_ATTENUATION_3DB,
	DRXK_SIF_ATTENUATION_6DB,
	DRXK_SIF_ATTENUATION_9DB
};
enum EDrxkConstellation {
	DRX_CONSTELLATION_BPSK = 0,
	DRX_CONSTELLATION_QPSK,
	DRX_CONSTELLATION_PSK8,
	DRX_CONSTELLATION_QAM16,
	DRX_CONSTELLATION_QAM32,
	DRX_CONSTELLATION_QAM64,
	DRX_CONSTELLATION_QAM128,
	DRX_CONSTELLATION_QAM256,
	DRX_CONSTELLATION_QAM512,
	DRX_CONSTELLATION_QAM1024,
	DRX_CONSTELLATION_UNKNOWN = DRX_UNKNOWN,
	DRX_CONSTELLATION_AUTO    = DRX_AUTO
};
enum EDrxkInterleaveMode {
	DRXK_QAM_I12_J17    = 16,
	DRXK_QAM_I_UNKNOWN  = DRX_UNKNOWN
};
enum {
	DRXK_SPIN_A1 = 0,
	DRXK_SPIN_A2,
	DRXK_SPIN_A3,
	DRXK_SPIN_UNKNOWN
};

enum DRXKCfgDvbtSqiSpeed {
	DRXK_DVBT_SQI_SPEED_FAST = 0,
	DRXK_DVBT_SQI_SPEED_MEDIUM,
	DRXK_DVBT_SQI_SPEED_SLOW,
	DRXK_DVBT_SQI_SPEED_UNKNOWN = DRX_UNKNOWN
} ;

enum DRXFftmode_t {
	DRX_FFTMODE_2K = 0,
	DRX_FFTMODE_4K,
	DRX_FFTMODE_8K,
	DRX_FFTMODE_UNKNOWN = DRX_UNKNOWN,
	DRX_FFTMODE_AUTO    = DRX_AUTO
};

enum DRXMPEGStrWidth_t {
	DRX_MPEG_STR_WIDTH_1,
	DRX_MPEG_STR_WIDTH_8
};

enum DRXQamLockRange_t {
	DRX_QAM_LOCKRANGE_NORMAL,
	DRX_QAM_LOCKRANGE_EXTENDED
};

struct DRXKCfgDvbtEchoThres_t {
	u16             threshold;
	enum DRXFftmode_t      fftMode;
} ;

struct SCfgAgc {
	enum AGC_CTRL_MODE     ctrlMode;        /* off, user, auto */
	u16            outputLevel;     /* range dependent on AGC */
	u16            minOutputLevel;  /* range dependent on AGC */
	u16            maxOutputLevel;  /* range dependent on AGC */
	u16            speed;           /* range dependent on AGC */
	u16            top;             /* rf-agc take over point */
	u16            cutOffCurrent;   /* rf-agc is accelerated if output current
					   is below cut-off current */
	u16            IngainTgtMax;
	u16            FastClipCtrlDelay;
};

struct SCfgPreSaw {
	u16        reference; /* pre SAW reference value, range 0 .. 31 */
	bool          usePreSaw; /* TRUE algorithms must use pre SAW sense */
};

struct DRXKOfdmScCmd_t {
	u16 cmd;        /**< Command number */
	u16 subcmd;     /**< Sub-command parameter*/
	u16 param0;     /**< General purpous param */
	u16 param1;     /**< General purpous param */
	u16 param2;     /**< General purpous param */
	u16 param3;     /**< General purpous param */
	u16 param4;     /**< General purpous param */
};

struct drxk_state {
	struct dvb_frontend c_frontend;
	struct dvb_frontend t_frontend;
	struct dvb_frontend_parameters param;
	struct device *dev;

	struct i2c_adapter *i2c;
	u8     demod_address;
	void  *priv;

	struct mutex mutex;
	struct mutex ctlock;

	u32    m_Instance;           /**< Channel 1,2,3 or 4 */

	int    m_ChunkSize;
	u8 Chunk[256];

	bool   m_hasLNA;
	bool   m_hasDVBT;
	bool   m_hasDVBC;
	bool   m_hasAudio;
	bool   m_hasATV;
	bool   m_hasOOB;
	bool   m_hasSAWSW;         /**< TRUE if mat_tx is available */
	bool   m_hasGPIO1;         /**< TRUE if mat_rx is available */
	bool   m_hasGPIO2;         /**< TRUE if GPIO is available */
	bool   m_hasIRQN;          /**< TRUE if IRQN is available */
	u16    m_oscClockFreq;
	u16    m_HICfgTimingDiv;
	u16    m_HICfgBridgeDelay;
	u16    m_HICfgWakeUpKey;
	u16    m_HICfgTimeout;
	u16    m_HICfgCtrl;
	s32    m_sysClockFreq;      /**< system clock frequency in kHz */

	enum EDrxkState    m_DrxkState;      /**< State of Drxk (init,stopped,started) */
	enum OperationMode m_OperationMode;  /**< digital standards */
	struct SCfgAgc     m_vsbRfAgcCfg;    /**< settings for VSB RF-AGC */
	struct SCfgAgc     m_vsbIfAgcCfg;    /**< settings for VSB IF-AGC */
	u16                m_vsbPgaCfg;      /**< settings for VSB PGA */
	struct SCfgPreSaw  m_vsbPreSawCfg;   /**< settings for pre SAW sense */
	s32    m_Quality83percent;  /**< MER level (*0.1 dB) for 83% quality indication */
	s32    m_Quality93percent;  /**< MER level (*0.1 dB) for 93% quality indication */
	bool   m_smartAntInverted;
	bool   m_bDebugEnableBridge;
	bool   m_bPDownOpenBridge;  /**< only open DRXK bridge before power-down once it has been accessed */
	bool   m_bPowerDown;        /**< Power down when not used */

	u32    m_IqmFsRateOfs;      /**< frequency shift as written to DRXK register (28bit fixpoint) */

	bool   m_enableMPEGOutput;  /**< If TRUE, enable MPEG output */
	bool   m_insertRSByte;      /**< If TRUE, insert RS byte */
	bool   m_enableParallel;    /**< If TRUE, parallel out otherwise serial */
	bool   m_invertDATA;        /**< If TRUE, invert DATA signals */
	bool   m_invertERR;         /**< If TRUE, invert ERR signal */
	bool   m_invertSTR;         /**< If TRUE, invert STR signals */
	bool   m_invertVAL;         /**< If TRUE, invert VAL signals */
	bool   m_invertCLK;         /**< If TRUE, invert CLK signals */
	bool   m_DVBCStaticCLK;
	bool   m_DVBTStaticCLK;     /**< If TRUE, static MPEG clockrate will
					 be used, otherwise clockrate will
					 adapt to the bitrate of the TS */
	u32    m_DVBTBitrate;
	u32    m_DVBCBitrate;

	u8     m_TSDataStrength;
	u8     m_TSClockkStrength;

	enum DRXMPEGStrWidth_t  m_widthSTR;    /**< MPEG start width */
	u32    m_mpegTsStaticBitrate;          /**< Maximum bitrate in b/s in case
						    static clockrate is selected */

	/* LARGE_INTEGER   m_StartTime; */     /**< Contains the time of the last demod start */
	s32    m_MpegLockTimeOut;      /**< WaitForLockStatus Timeout (counts from start time) */
	s32    m_DemodLockTimeOut;     /**< WaitForLockStatus Timeout (counts from start time) */

	bool   m_disableTEIhandling;

	bool   m_RfAgcPol;
	bool   m_IfAgcPol;

	struct SCfgAgc    m_atvRfAgcCfg;  /**< settings for ATV RF-AGC */
	struct SCfgAgc    m_atvIfAgcCfg;  /**< settings for ATV IF-AGC */
	struct SCfgPreSaw m_atvPreSawCfg; /**< settings for ATV pre SAW sense */
	bool              m_phaseCorrectionBypass;
	s16               m_atvTopVidPeak;
	u16               m_atvTopNoiseTh;
	enum EDrxkSifAttenuation m_sifAttenuation;
	bool              m_enableCVBSOutput;
	bool              m_enableSIFOutput;
	bool              m_bMirrorFreqSpect;
	enum EDrxkConstellation  m_Constellation; /**< Constellation type of the channel */
	u32               m_CurrSymbolRate;       /**< Current QAM symbol rate */
	struct SCfgAgc    m_qamRfAgcCfg;          /**< settings for QAM RF-AGC */
	struct SCfgAgc    m_qamIfAgcCfg;          /**< settings for QAM IF-AGC */
	u16               m_qamPgaCfg;            /**< settings for QAM PGA */
	struct SCfgPreSaw m_qamPreSawCfg;         /**< settings for QAM pre SAW sense */
	enum EDrxkInterleaveMode m_qamInterleaveMode; /**< QAM Interleave mode */
	u16               m_fecRsPlen;
	u16               m_fecRsPrescale;

	enum DRXKCfgDvbtSqiSpeed m_sqiSpeed;

	u16               m_GPIO;
	u16               m_GPIOCfg;

	struct SCfgAgc    m_dvbtRfAgcCfg;     /**< settings for QAM RF-AGC */
	struct SCfgAgc    m_dvbtIfAgcCfg;     /**< settings for QAM IF-AGC */
	struct SCfgPreSaw m_dvbtPreSawCfg;    /**< settings for QAM pre SAW sense */

	u16               m_agcFastClipCtrlDelay;
	bool              m_adcCompPassed;
	u16               m_adcCompCoef[64];
	u16               m_adcState;

	u8               *m_microcode;
	int               m_microcode_length;
	bool              m_DRXK_A1_PATCH_CODE;
	bool              m_DRXK_A1_ROM_CODE;
	bool              m_DRXK_A2_ROM_CODE;
	bool              m_DRXK_A3_ROM_CODE;
	bool              m_DRXK_A2_PATCH_CODE;
	bool              m_DRXK_A3_PATCH_CODE;

	bool              m_rfmirror;
	u8                m_deviceSpin;
	u32               m_iqmRcRate;

	u16               m_AntennaDVBC;
	u16               m_AntennaDVBT;
	u16               m_AntennaSwitchDVBTDVBC;

	enum DRXPowerMode m_currentPowerMode;

	/* Configurable parameters at the driver */

	u32 single_master : 1;		/* Use single master i2c mode */
	u32 no_i2c_bridge : 1;		/* Tuner is not on port 1, don't use I2C bridge */
	const char *microcode_name;

};

#define NEVER_LOCK 0
#define NOT_LOCKED 1
#define DEMOD_LOCK 2
#define FEC_LOCK   3
#define MPEG_LOCK  4
Commit	Line	Data
43dd07f7 RM	1	#include "drxk_map.h"
	2
	3	#define DRXK_VERSION_MAJOR 0
	4	#define DRXK_VERSION_MINOR 9
	5	#define DRXK_VERSION_PATCH 4300
	6
	7	#define HI_I2C_DELAY 42
	8	#define HI_I2C_BRIDGE_DELAY 350
	9	#define DRXK_MAX_RETRIES 100
	10
	11	#define DRIVER_4400 1
	12
	13	#define DRXX_JTAGID 0x039210D9
	14	#define DRXX_J_JTAGID 0x239310D9
	15	#define DRXX_K_JTAGID 0x039210D9
	16
	17	#define DRX_UNKNOWN 254
	18	#define DRX_AUTO 255
	19
	20	#define DRX_SCU_READY 0
	21	#define DRXK_MAX_WAITTIME (200)
	22	#define SCU_RESULT_OK 0
	23	#define SCU_RESULT_UNKSTD -2
	24	#define SCU_RESULT_UNKCMD -1
	25
	26	#ifndef DRXK_OFDM_TR_SHUTDOWN_TIMEOUT
	27	#define DRXK_OFDM_TR_SHUTDOWN_TIMEOUT (200)
	28	#endif
	29
	30	#define DRXK_8VSB_MPEG_BIT_RATE 19392658UL /bps/
	31	#define DRXK_DVBT_MPEG_BIT_RATE 32000000UL /bps/
	32	#define DRXK_QAM16_MPEG_BIT_RATE 27000000UL /bps/
	33	#define DRXK_QAM32_MPEG_BIT_RATE 33000000UL /bps/
	34	#define DRXK_QAM64_MPEG_BIT_RATE 40000000UL /bps/
	35	#define DRXK_QAM128_MPEG_BIT_RATE 46000000UL /bps/
	36	#define DRXK_QAM256_MPEG_BIT_RATE 52000000UL /bps/
	37	#define DRXK_MAX_MPEG_BIT_RATE 52000000UL /bps/
	38
	39	#define IQM_CF_OUT_ENA_OFDM__M 0x4
	40	#define IQM_FS_ADJ_SEL_B_QAM 0x1
	41	#define IQM_FS_ADJ_SEL_B_OFF 0x0
	42	#define IQM_FS_ADJ_SEL_B_VSB 0x2
	43	#define IQM_RC_ADJ_SEL_B_OFF 0x0
	44	#define IQM_RC_ADJ_SEL_B_QAM 0x1
	45	#define IQM_RC_ADJ_SEL_B_VSB 0x2
	46
	47	enum OperationMode {
	48	OM_NONE,
	49	OM_QAM_ITU_A,
	50	OM_QAM_ITU_B,
	51	OM_QAM_ITU_C,
	52	OM_DVBT
	53	};
	54
ebc7de22	55	enum DRXPowerMode {
43dd07f7 RM	56	DRX_POWER_UP = 0,
	57	DRX_POWER_MODE_1,
	58	DRX_POWER_MODE_2,
	59	DRX_POWER_MODE_3,
	60	DRX_POWER_MODE_4,
	61	DRX_POWER_MODE_5,
	62	DRX_POWER_MODE_6,
	63	DRX_POWER_MODE_7,
	64	DRX_POWER_MODE_8,
	65
	66	DRX_POWER_MODE_9,
	67	DRX_POWER_MODE_10,
	68	DRX_POWER_MODE_11,
	69	DRX_POWER_MODE_12,
	70	DRX_POWER_MODE_13,
	71	DRX_POWER_MODE_14,
	72	DRX_POWER_MODE_15,
	73	DRX_POWER_MODE_16,
	74	DRX_POWER_DOWN = 255
ebc7de22	75	};
43dd07f7 RM	76
	77
	78	/** /brief Intermediate power mode for DRXK, power down OFDM clock domain */
	79	#ifndef DRXK_POWER_DOWN_OFDM
	80	#define DRXK_POWER_DOWN_OFDM DRX_POWER_MODE_1
	81	#endif
	82
	83	/** /brief Intermediate power mode for DRXK, power down core (sysclk) */
	84	#ifndef DRXK_POWER_DOWN_CORE
	85	#define DRXK_POWER_DOWN_CORE DRX_POWER_MODE_9
	86	#endif
	87
	88	/** /brief Intermediate power mode for DRXK, power down pll (only osc runs) */
	89	#ifndef DRXK_POWER_DOWN_PLL
	90	#define DRXK_POWER_DOWN_PLL DRX_POWER_MODE_10
	91	#endif
	92
	93
	94	enum AGC_CTRL_MODE { DRXK_AGC_CTRL_AUTO = 0, DRXK_AGC_CTRL_USER, DRXK_AGC_CTRL_OFF };
	95	enum EDrxkState { DRXK_UNINITIALIZED = 0, DRXK_STOPPED, DRXK_DTV_STARTED, DRXK_ATV_STARTED, DRXK_POWERED_DOWN };
	96	enum EDrxkCoefArrayIndex {
	97	DRXK_COEF_IDX_MN = 0,
	98	DRXK_COEF_IDX_FM ,
	99	DRXK_COEF_IDX_L ,
	100	DRXK_COEF_IDX_LP ,
	101	DRXK_COEF_IDX_BG ,
	102	DRXK_COEF_IDX_DK ,
	103	DRXK_COEF_IDX_I ,
	104	DRXK_COEF_IDX_MAX
	105	};
	106	enum EDrxkSifAttenuation {
	107	DRXK_SIF_ATTENUATION_0DB,
	108	DRXK_SIF_ATTENUATION_3DB,
	109	DRXK_SIF_ATTENUATION_6DB,
	110	DRXK_SIF_ATTENUATION_9DB
	111	};
	112	enum EDrxkConstellation {
	113	DRX_CONSTELLATION_BPSK = 0,
	114	DRX_CONSTELLATION_QPSK,
	115	DRX_CONSTELLATION_PSK8,
	116	DRX_CONSTELLATION_QAM16,
	117	DRX_CONSTELLATION_QAM32,
	118	DRX_CONSTELLATION_QAM64,
	119	DRX_CONSTELLATION_QAM128,
	120	DRX_CONSTELLATION_QAM256,
	121	DRX_CONSTELLATION_QAM512,
	122	DRX_CONSTELLATION_QAM1024,
	123	DRX_CONSTELLATION_UNKNOWN = DRX_UNKNOWN,
	124	DRX_CONSTELLATION_AUTO = DRX_AUTO
	125	};
	126	enum EDrxkInterleaveMode {
	127	DRXK_QAM_I12_J17 = 16,
	128	DRXK_QAM_I_UNKNOWN = DRX_UNKNOWN
	129	};
	130	enum {
	131	DRXK_SPIN_A1 = 0,
	132	DRXK_SPIN_A2,
	133	DRXK_SPIN_A3,
	134	DRXK_SPIN_UNKNOWN
	135	};
	136
	137	enum DRXKCfgDvbtSqiSpeed {
	138	DRXK_DVBT_SQI_SPEED_FAST = 0,
	139	DRXK_DVBT_SQI_SPEED_MEDIUM,
140	DRXK_DVBT_SQI_SPEED_SLOW,
141	DRXK_DVBT_SQI_SPEED_UNKNOWN = DRX_UNKNOWN
142	} ;
143
144	enum DRXFftmode_t {
145	DRX_FFTMODE_2K = 0,
146	DRX_FFTMODE_4K,
147	DRX_FFTMODE_8K,
148	DRX_FFTMODE_UNKNOWN = DRX_UNKNOWN,
149	DRX_FFTMODE_AUTO = DRX_AUTO
150	};
151
152	enum DRXMPEGStrWidth_t {
153	DRX_MPEG_STR_WIDTH_1,
154	DRX_MPEG_STR_WIDTH_8
155	};
156
157	enum DRXQamLockRange_t {
158	DRX_QAM_LOCKRANGE_NORMAL,
159	DRX_QAM_LOCKRANGE_EXTENDED
160	};
161
162	struct DRXKCfgDvbtEchoThres_t {
163	u16 threshold;
164	enum DRXFftmode_t fftMode;
165	} ;
166
ebc7de22	167	struct SCfgAgc {
43dd07f7 RM	168	enum AGC_CTRL_MODE ctrlMode; /* off, user, auto */
	169	u16 outputLevel; /* range dependent on AGC */
	170	u16 minOutputLevel; /* range dependent on AGC */
	171	u16 maxOutputLevel; /* range dependent on AGC */
	172	u16 speed; /* range dependent on AGC */
	173	u16 top; /* rf-agc take over point */
	174	u16 cutOffCurrent; /* rf-agc is accelerated if output current
ebc7de22	175	is below cut-off current */
43dd07f7 RM	176	u16 IngainTgtMax;
	177	u16 FastClipCtrlDelay;
	178	};
	179
ebc7de22	180	struct SCfgPreSaw {
43dd07f7 RM	181	u16 reference; /* pre SAW reference value, range 0 .. 31 */
	182	bool usePreSaw; /* TRUE algorithms must use pre SAW sense */
	183	};
	184
ebc7de22	185	struct DRXKOfdmScCmd_t {
43dd07f7 RM	186	u16 cmd; /*< Command number /
	187	u16 subcmd; /*< Sub-command parameter/
	188	u16 param0; /*< General purpous param /
	189	u16 param1; /*< General purpous param /
	190	u16 param2; /*< General purpous param /
	191	u16 param3; /*< General purpous param /
	192	u16 param4; /*< General purpous param /
	193	};
	194
	195	struct drxk_state {
	196	struct dvb_frontend c_frontend;
	197	struct dvb_frontend t_frontend;
	198	struct dvb_frontend_parameters param;
	199	struct device *dev;
	200
	201	struct i2c_adapter *i2c;
	202	u8 demod_address;
	203	void *priv;
	204
	205	struct mutex mutex;
	206	struct mutex ctlock;
	207
ebc7de22	208	u32 m_Instance; /*< Channel 1,2,3 or 4 /
43dd07f7	209
ebc7de22	210	int m_ChunkSize;
43dd07f7 RM	211	u8 Chunk[256];
43dd07f7 RM	212
ebc7de22 OE	213	bool m_hasLNA;
	214	bool m_hasDVBT;
	215	bool m_hasDVBC;
	216	bool m_hasAudio;
	217	bool m_hasATV;
	218	bool m_hasOOB;
	219	bool m_hasSAWSW; /*< TRUE if mat_tx is available /
	220	bool m_hasGPIO1; /*< TRUE if mat_rx is available /
	221	bool m_hasGPIO2; /*< TRUE if GPIO is available /
	222	bool m_hasIRQN; /*< TRUE if IRQN is available /
	223	u16 m_oscClockFreq;
	224	u16 m_HICfgTimingDiv;
	225	u16 m_HICfgBridgeDelay;
	226	u16 m_HICfgWakeUpKey;
	227	u16 m_HICfgTimeout;
	228	u16 m_HICfgCtrl;
	229	s32 m_sysClockFreq; /*< system clock frequency in kHz /
	230
	231	enum EDrxkState m_DrxkState; /*< State of Drxk (init,stopped,started) /
	232	enum OperationMode m_OperationMode; /*< digital standards /
	233	struct SCfgAgc m_vsbRfAgcCfg; /*< settings for VSB RF-AGC /
	234	struct SCfgAgc m_vsbIfAgcCfg; /*< settings for VSB IF-AGC /
	235	u16 m_vsbPgaCfg; /*< settings for VSB PGA /
	236	struct SCfgPreSaw m_vsbPreSawCfg; /*< settings for pre SAW sense /
	237	s32 m_Quality83percent; /*< MER level (0.1 dB) for 83% quality indication */
	238	s32 m_Quality93percent; /*< MER level (0.1 dB) for 93% quality indication */
	239	bool m_smartAntInverted;
	240	bool m_bDebugEnableBridge;
	241	bool m_bPDownOpenBridge; /*< only open DRXK bridge before power-down once it has been accessed /
	242	bool m_bPowerDown; /*< Power down when not used /
	243
	244	u32 m_IqmFsRateOfs; /*< frequency shift as written to DRXK register (28bit fixpoint) /
	245
	246	bool m_enableMPEGOutput; /*< If TRUE, enable MPEG output /
	247	bool m_insertRSByte; /*< If TRUE, insert RS byte /
	248	bool m_enableParallel; /*< If TRUE, parallel out otherwise serial /
	249	bool m_invertDATA; /*< If TRUE, invert DATA signals /
	250	bool m_invertERR; /*< If TRUE, invert ERR signal /
	251	bool m_invertSTR; /*< If TRUE, invert STR signals /
	252	bool m_invertVAL; /*< If TRUE, invert VAL signals /
	253	bool m_invertCLK; /*< If TRUE, invert CLK signals /
	254	bool m_DVBCStaticCLK;
	255	bool m_DVBTStaticCLK; /**< If TRUE, static MPEG clockrate will
	256	be used, otherwise clockrate will
	257	adapt to the bitrate of the TS */
	258	u32 m_DVBTBitrate;
	259	u32 m_DVBCBitrate;
	260
	261	u8 m_TSDataStrength;
	262	u8 m_TSClockkStrength;
	263
	264	enum DRXMPEGStrWidth_t m_widthSTR; /*< MPEG start width /
	265	u32 m_mpegTsStaticBitrate; /**< Maximum bitrate in b/s in case
	266	static clockrate is selected */
	267
	268	/* LARGE_INTEGER m_StartTime; / /< Contains the time of the last demod start /
	269	s32 m_MpegLockTimeOut; /*< WaitForLockStatus Timeout (counts from start time) /
	270	s32 m_DemodLockTimeOut; /*< WaitForLockStatus Timeout (counts from start time) /
	271
	272	bool m_disableTEIhandling;
	273
	274	bool m_RfAgcPol;
	275	bool m_IfAgcPol;
	276
277	struct SCfgAgc m_atvRfAgcCfg; /*< settings for ATV RF-AGC /
278	struct SCfgAgc m_atvIfAgcCfg; /*< settings for ATV IF-AGC /
279	struct SCfgPreSaw m_atvPreSawCfg; /*< settings for ATV pre SAW sense /
280	bool m_phaseCorrectionBypass;
281	s16 m_atvTopVidPeak;
282	u16 m_atvTopNoiseTh;
43dd07f7	283	enum EDrxkSifAttenuation m_sifAttenuation;
ebc7de22 OE	284	bool m_enableCVBSOutput;
	285	bool m_enableSIFOutput;
	286	bool m_bMirrorFreqSpect;
	287	enum EDrxkConstellation m_Constellation; /*< Constellation type of the channel /
	288	u32 m_CurrSymbolRate; /*< Current QAM symbol rate /
	289	struct SCfgAgc m_qamRfAgcCfg; /*< settings for QAM RF-AGC /
	290	struct SCfgAgc m_qamIfAgcCfg; /*< settings for QAM IF-AGC /
	291	u16 m_qamPgaCfg; /*< settings for QAM PGA /
	292	struct SCfgPreSaw m_qamPreSawCfg; /*< settings for QAM pre SAW sense /
	293	enum EDrxkInterleaveMode m_qamInterleaveMode; /*< QAM Interleave mode /
	294	u16 m_fecRsPlen;
	295	u16 m_fecRsPrescale;
43dd07f7 RM	296
	297	enum DRXKCfgDvbtSqiSpeed m_sqiSpeed;
	298
ebc7de22 OE	299	u16 m_GPIO;
ebc7de22 OE	300	u16 m_GPIOCfg;
43dd07f7	301
ebc7de22 OE	302	struct SCfgAgc m_dvbtRfAgcCfg; /*< settings for QAM RF-AGC /
	303	struct SCfgAgc m_dvbtIfAgcCfg; /*< settings for QAM IF-AGC /
	304	struct SCfgPreSaw m_dvbtPreSawCfg; /*< settings for QAM pre SAW sense /
43dd07f7	305
ebc7de22 OE	306	u16 m_agcFastClipCtrlDelay;
	307	bool m_adcCompPassed;
	308	u16 m_adcCompCoef[64];
	309	u16 m_adcState;
43dd07f7	310
ebc7de22 OE	311	u8 *m_microcode;
	312	int m_microcode_length;
	313	bool m_DRXK_A1_PATCH_CODE;
	314	bool m_DRXK_A1_ROM_CODE;
	315	bool m_DRXK_A2_ROM_CODE;
	316	bool m_DRXK_A3_ROM_CODE;
	317	bool m_DRXK_A2_PATCH_CODE;
	318	bool m_DRXK_A3_PATCH_CODE;
43dd07f7	319
ebc7de22 OE	320	bool m_rfmirror;
	321	u8 m_deviceSpin;
	322	u32 m_iqmRcRate;
43dd07f7	323
ebc7de22 OE	324	u16 m_AntennaDVBC;
	325	u16 m_AntennaDVBT;
	326	u16 m_AntennaSwitchDVBTDVBC;
43dd07f7	327
ebc7de22	328	enum DRXPowerMode m_currentPowerMode;
e076c92e MCC	329
	330	/* Configurable parameters at the driver */
	331
	332	u32 single_master : 1; /* Use single master i2c mode */
f1fe1b75	333	u32 no_i2c_bridge : 1; /* Tuner is not on port 1, don't use I2C bridge */
e4f4f875	334	const char *microcode_name;
e076c92e	335
43dd07f7 RM	336	};
	337
	338	#define NEVER_LOCK 0
	339	#define NOT_LOCKED 1
	340	#define DEMOD_LOCK 2
	341	#define FEC_LOCK 3
	342	#define MPEG_LOCK 4
	343