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drx: add initial drx-d driver
[linux-block.git] / drivers / media / dvb / frontends / drxd_firm.c
CommitLineData
126f1e61
RM		 1/*
2 * drxd_firm.c : DRXD firmware tables
3 *
4 * Copyright (C) 2006-2007 Micronas
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * version 2 only, as published by the Free Software Foundation.
9 *
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
20 * 02110-1301, USA
21 * Or, point your browser to http://www.gnu.org/copyleft/gpl.html
22 */
23
24/* TODO: generate this file with a script from a settings file */
25
26/* Contains A2 firmware version: 1.4.2
27 * Contains B1 firmware version: 3.3.33
28 * Contains settings from driver 1.4.23
29*/
30
31#include "drxd_firm.h"
32
33#define ADDRESS(x) ((x) & 0xFF), (((x)>>8) & 0xFF), (((x)>>16) & 0xFF), (((x)>>24) & 0xFF)
34#define LENGTH(x) ((x) & 0xFF), (((x)>>8) & 0xFF)
35
36/* Is written via block write, must be little endian */
37#define DATA16(x) ((x) & 0xFF), (((x)>>8) & 0xFF)
38
39#define WRBLOCK(a,l) ADDRESS(a),LENGTH(l)
40#define WR16(a,d) ADDRESS(a),LENGTH(1),DATA16(d)
41
42#define END_OF_TABLE 0xFF,0xFF,0xFF,0xFF
43
44/* HI firmware patches */
45
46#define HI_TR_FUNC_ADDR HI_IF_RAM_USR_BEGIN__A
47#define HI_TR_FUNC_SIZE 9 /* size of this function in instruction words */
48
49u8_t DRXD_InitAtomicRead[] =
50{
51 WRBLOCK(HI_TR_FUNC_ADDR,HI_TR_FUNC_SIZE),
52 0x26, 0x00, /* 0 -> ring.rdy; */
53 0x60, 0x04, /* r0rami.dt -> ring.xba; */
54 0x61, 0x04, /* r0rami.dt -> ring.xad; */
55 0xE3, 0x07, /* HI_RA_RAM_USR_BEGIN -> ring.iad; */
56 0x40, 0x00, /* (long immediate) */
57 0x64, 0x04, /* r0rami.dt -> ring.len; */
58 0x65, 0x04, /* r0rami.dt -> ring.ctl; */
59 0x26, 0x00, /* 0 -> ring.rdy; */
60 0x38, 0x00, /* 0 -> jumps.ad; */
61 END_OF_TABLE
62};
63
64/* Pins D0 and D1 of the parallel MPEG output can be used
65 to set the I2C address of a device. */
66
67#define HI_RST_FUNC_ADDR ( HI_IF_RAM_USR_BEGIN__A + HI_TR_FUNC_SIZE)
68#define HI_RST_FUNC_SIZE 54 /* size of this function in instruction words */
69
70/* D0 Version */
71u8_t DRXD_HiI2cPatch_1[] =
72{
73 WRBLOCK(HI_RST_FUNC_ADDR,HI_RST_FUNC_SIZE),
74 0xC8, 0x07, 0x01, 0x00, /* MASK -> reg0.dt; */
75 0xE0, 0x07, 0x15, 0x02, /* (EC__BLK << 6) + EC_OC_REG__BNK -> ring.xba; */
76 0xE1, 0x07, 0x12, 0x00, /* EC_OC_REG_OC_MPG_SIO__A -> ring.xad; */
77 0xA2, 0x00, /* M_BNK_ID_DAT -> ring.iba; */
78 0x23, 0x00, /* &data -> ring.iad; */
79 0x24, 0x00, /* 0 -> ring.len; */
80 0xA5, 0x02, /* M_RC_CTR_SWAP | M_RC_CTR_READ -> ring.ctl; */
81 0x26, 0x00, /* 0 -> ring.rdy; */
82 0x42, 0x00, /* &data+1 -> w0ram.ad; */
83 0xC0, 0x07, 0xFF, 0x0F, /* -1 -> w0ram.dt; */
84 0x63, 0x00, /* &data+1 -> ring.iad; */
85 0x65, 0x02, /* M_RC_CTR_SWAP | M_RC_CTR_WRITE -> ring.ctl; */
86 0x26, 0x00, /* 0 -> ring.rdy; */
87 0xE1, 0x07, 0x38, 0x00, /* EC_OC_REG_OCR_MPG_USR_DAT__A -> ring.xad; */
88 0xA5, 0x02, /* M_RC_CTR_SWAP | M_RC_CTR_READ -> ring.ctl; */
89 0x26, 0x00, /* 0 -> ring.rdy; */
90 0xE1, 0x07, 0x12, 0x00, /* EC_OC_REG_OC_MPG_SIO__A -> ring.xad; */
91 0x23, 0x00, /* &data -> ring.iad; */
92 0x65, 0x02, /* M_RC_CTR_SWAP | M_RC_CTR_WRITE -> ring.ctl; */
93 0x26, 0x00, /* 0 -> ring.rdy; */
94 0x42, 0x00, /* &data+1 -> w0ram.ad; */
95 0x0F, 0x04, /* r0ram.dt -> and.op; */
96 0x1C, 0x06, /* reg0.dt -> and.tr; */
97 0xCF, 0x04, /* and.rs -> add.op; */
98 0xD0, 0x07, 0x70, 0x00, /* DEF_DEV_ID -> add.tr; */
99 0xD0, 0x04, /* add.rs -> add.tr; */
100 0xC8, 0x04, /* add.rs -> reg0.dt; */
101 0x60, 0x00, /* reg0.dt -> w0ram.dt; */
102 0xC2, 0x07, 0x10, 0x00, /* SLV0_BASE -> w0rami.ad; */
103 0x01, 0x00, /* 0 -> w0rami.dt; */
104 0x01, 0x06, /* reg0.dt -> w0rami.dt; */
105 0xC2, 0x07, 0x20, 0x00, /* SLV1_BASE -> w0rami.ad; */
106 0x01, 0x00, /* 0 -> w0rami.dt; */
107 0x01, 0x06, /* reg0.dt -> w0rami.dt; */
108 0xC2, 0x07, 0x30, 0x00, /* CMD_BASE -> w0rami.ad; */
109 0x01, 0x00, /* 0 -> w0rami.dt; */
110 0x01, 0x00, /* 0 -> w0rami.dt; */
111 0x01, 0x00, /* 0 -> w0rami.dt; */
112 0x68, 0x00, /* M_IC_SEL_PT1 -> i2c.sel; */
113 0x29, 0x00, /* M_IC_CMD_RESET -> i2c.cmd; */
114 0x28, 0x00, /* M_IC_SEL_PT0 -> i2c.sel; */
115 0x29, 0x00, /* M_IC_CMD_RESET -> i2c.cmd; */
116 0xF8, 0x07, 0x2F, 0x00, /* 0x2F -> jumps.ad; */
117
118 WR16((B_HI_IF_RAM_TRP_BPT0__AX+((2*0)+1)),(u16_t)(HI_RST_FUNC_ADDR & 0x3FF)),
119 WR16((B_HI_IF_RAM_TRP_BPT0__AX+((2*1)+1)),(u16_t)(HI_RST_FUNC_ADDR & 0x3FF)),
120 WR16((B_HI_IF_RAM_TRP_BPT0__AX+((2*2)+1)),(u16_t)(HI_RST_FUNC_ADDR & 0x3FF)),
121 WR16((B_HI_IF_RAM_TRP_BPT0__AX+((2*3)+1)),(u16_t)(HI_RST_FUNC_ADDR & 0x3FF)),
122
123 /* Force quick and dirty reset */
124 WR16(B_HI_CT_REG_COMM_STATE__A,0),
125 END_OF_TABLE
126};
127
128/* D0,D1 Version */
129u8_t DRXD_HiI2cPatch_3[] =
130{
131 WRBLOCK(HI_RST_FUNC_ADDR,HI_RST_FUNC_SIZE),
132 0xC8, 0x07, 0x03, 0x00, /* MASK -> reg0.dt; */
133 0xE0, 0x07, 0x15, 0x02, /* (EC__BLK << 6) + EC_OC_REG__BNK -> ring.xba; */
134 0xE1, 0x07, 0x12, 0x00, /* EC_OC_REG_OC_MPG_SIO__A -> ring.xad; */
135 0xA2, 0x00, /* M_BNK_ID_DAT -> ring.iba; */
136 0x23, 0x00, /* &data -> ring.iad; */
137 0x24, 0x00, /* 0 -> ring.len; */
138 0xA5, 0x02, /* M_RC_CTR_SWAP | M_RC_CTR_READ -> ring.ctl; */
139 0x26, 0x00, /* 0 -> ring.rdy; */
140 0x42, 0x00, /* &data+1 -> w0ram.ad; */
141 0xC0, 0x07, 0xFF, 0x0F, /* -1 -> w0ram.dt; */
142 0x63, 0x00, /* &data+1 -> ring.iad; */
143 0x65, 0x02, /* M_RC_CTR_SWAP | M_RC_CTR_WRITE -> ring.ctl; */
144 0x26, 0x00, /* 0 -> ring.rdy; */
145 0xE1, 0x07, 0x38, 0x00, /* EC_OC_REG_OCR_MPG_USR_DAT__A -> ring.xad; */
146 0xA5, 0x02, /* M_RC_CTR_SWAP | M_RC_CTR_READ -> ring.ctl; */
147 0x26, 0x00, /* 0 -> ring.rdy; */
148 0xE1, 0x07, 0x12, 0x00, /* EC_OC_REG_OC_MPG_SIO__A -> ring.xad; */
149 0x23, 0x00, /* &data -> ring.iad; */
150 0x65, 0x02, /* M_RC_CTR_SWAP | M_RC_CTR_WRITE -> ring.ctl; */
151 0x26, 0x00, /* 0 -> ring.rdy; */
152 0x42, 0x00, /* &data+1 -> w0ram.ad; */
153 0x0F, 0x04, /* r0ram.dt -> and.op; */
154 0x1C, 0x06, /* reg0.dt -> and.tr; */
155 0xCF, 0x04, /* and.rs -> add.op; */
156 0xD0, 0x07, 0x70, 0x00, /* DEF_DEV_ID -> add.tr; */
157 0xD0, 0x04, /* add.rs -> add.tr; */
158 0xC8, 0x04, /* add.rs -> reg0.dt; */
159 0x60, 0x00, /* reg0.dt -> w0ram.dt; */
160 0xC2, 0x07, 0x10, 0x00, /* SLV0_BASE -> w0rami.ad; */
161 0x01, 0x00, /* 0 -> w0rami.dt; */
162 0x01, 0x06, /* reg0.dt -> w0rami.dt; */
163 0xC2, 0x07, 0x20, 0x00, /* SLV1_BASE -> w0rami.ad; */
164 0x01, 0x00, /* 0 -> w0rami.dt; */
165 0x01, 0x06, /* reg0.dt -> w0rami.dt; */
166 0xC2, 0x07, 0x30, 0x00, /* CMD_BASE -> w0rami.ad; */
167 0x01, 0x00, /* 0 -> w0rami.dt; */
168 0x01, 0x00, /* 0 -> w0rami.dt; */
169 0x01, 0x00, /* 0 -> w0rami.dt; */
170 0x68, 0x00, /* M_IC_SEL_PT1 -> i2c.sel; */
171 0x29, 0x00, /* M_IC_CMD_RESET -> i2c.cmd; */
172 0x28, 0x00, /* M_IC_SEL_PT0 -> i2c.sel; */
173 0x29, 0x00, /* M_IC_CMD_RESET -> i2c.cmd; */
174 0xF8, 0x07, 0x2F, 0x00, /* 0x2F -> jumps.ad; */
175
176 WR16((B_HI_IF_RAM_TRP_BPT0__AX+((2*0)+1)),(u16_t)(HI_RST_FUNC_ADDR & 0x3FF)),
177 WR16((B_HI_IF_RAM_TRP_BPT0__AX+((2*1)+1)),(u16_t)(HI_RST_FUNC_ADDR & 0x3FF)),
178 WR16((B_HI_IF_RAM_TRP_BPT0__AX+((2*2)+1)),(u16_t)(HI_RST_FUNC_ADDR & 0x3FF)),
179 WR16((B_HI_IF_RAM_TRP_BPT0__AX+((2*3)+1)),(u16_t)(HI_RST_FUNC_ADDR & 0x3FF)),
180
181 /* Force quick and dirty reset */
182 WR16(B_HI_CT_REG_COMM_STATE__A,0),
183 END_OF_TABLE
184};
185
186u8_t DRXD_ResetCEFR[] =
187{
188 WRBLOCK(CE_REG_FR_TREAL00__A, 57),
189 0x52,0x00, /* CE_REG_FR_TREAL00__A */
190 0x00,0x00, /* CE_REG_FR_TIMAG00__A */
191 0x52,0x00, /* CE_REG_FR_TREAL01__A */
192 0x00,0x00, /* CE_REG_FR_TIMAG01__A */
193 0x52,0x00, /* CE_REG_FR_TREAL02__A */
194 0x00,0x00, /* CE_REG_FR_TIMAG02__A */
195 0x52,0x00, /* CE_REG_FR_TREAL03__A */
196 0x00,0x00, /* CE_REG_FR_TIMAG03__A */
197 0x52,0x00, /* CE_REG_FR_TREAL04__A */
198 0x00,0x00, /* CE_REG_FR_TIMAG04__A */
199 0x52,0x00, /* CE_REG_FR_TREAL05__A */
200 0x00,0x00, /* CE_REG_FR_TIMAG05__A */
201 0x52,0x00, /* CE_REG_FR_TREAL06__A */
202 0x00,0x00, /* CE_REG_FR_TIMAG06__A */
203 0x52,0x00, /* CE_REG_FR_TREAL07__A */
204 0x00,0x00, /* CE_REG_FR_TIMAG07__A */
205 0x52,0x00, /* CE_REG_FR_TREAL08__A */
206 0x00,0x00, /* CE_REG_FR_TIMAG08__A */
207 0x52,0x00, /* CE_REG_FR_TREAL09__A */
208 0x00,0x00, /* CE_REG_FR_TIMAG09__A */
209 0x52,0x00, /* CE_REG_FR_TREAL10__A */
210 0x00,0x00, /* CE_REG_FR_TIMAG10__A */
211 0x52,0x00, /* CE_REG_FR_TREAL11__A */
212 0x00,0x00, /* CE_REG_FR_TIMAG11__A */
213
214 0x52,0x00, /* CE_REG_FR_MID_TAP__A */
215
216 0x0B,0x00, /* CE_REG_FR_SQS_G00__A */
217 0x0B,0x00, /* CE_REG_FR_SQS_G01__A */
218 0x0B,0x00, /* CE_REG_FR_SQS_G02__A */
219 0x0B,0x00, /* CE_REG_FR_SQS_G03__A */
220 0x0B,0x00, /* CE_REG_FR_SQS_G04__A */
221 0x0B,0x00, /* CE_REG_FR_SQS_G05__A */
222 0x0B,0x00, /* CE_REG_FR_SQS_G06__A */
223 0x0B,0x00, /* CE_REG_FR_SQS_G07__A */
224 0x0B,0x00, /* CE_REG_FR_SQS_G08__A */
225 0x0B,0x00, /* CE_REG_FR_SQS_G09__A */
226 0x0B,0x00, /* CE_REG_FR_SQS_G10__A */
227 0x0B,0x00, /* CE_REG_FR_SQS_G11__A */
228 0x0B,0x00, /* CE_REG_FR_SQS_G12__A */
229
230 0xFF,0x01, /* CE_REG_FR_RIO_G00__A */
231 0x90,0x01, /* CE_REG_FR_RIO_G01__A */
232 0x0B,0x01, /* CE_REG_FR_RIO_G02__A */
233 0xC8,0x00, /* CE_REG_FR_RIO_G03__A */
234 0xA0,0x00, /* CE_REG_FR_RIO_G04__A */
235 0x85,0x00, /* CE_REG_FR_RIO_G05__A */
236 0x72,0x00, /* CE_REG_FR_RIO_G06__A */
237 0x64,0x00, /* CE_REG_FR_RIO_G07__A */
238 0x59,0x00, /* CE_REG_FR_RIO_G08__A */
239 0x50,0x00, /* CE_REG_FR_RIO_G09__A */
240 0x49,0x00, /* CE_REG_FR_RIO_G10__A */
241
242 0x10,0x00, /* CE_REG_FR_MODE__A */
243 0x78,0x00, /* CE_REG_FR_SQS_TRH__A */
244 0x00,0x00, /* CE_REG_FR_RIO_GAIN__A */
245 0x00,0x02, /* CE_REG_FR_BYPASS__A */
246 0x0D,0x00, /* CE_REG_FR_PM_SET__A */
247 0x07,0x00, /* CE_REG_FR_ERR_SH__A */
248 0x04,0x00, /* CE_REG_FR_MAN_SH__A */
249 0x06,0x00, /* CE_REG_FR_TAP_SH__A */
250
251 END_OF_TABLE
252};
253
254
255u8_t DRXD_InitFEA2_1[] =
256{
257 WRBLOCK(FE_AD_REG_PD__A , 3),
258 0x00,0x00, /* FE_AD_REG_PD__A */
259 0x01,0x00, /* FE_AD_REG_INVEXT__A */
260 0x00,0x00, /* FE_AD_REG_CLKNEG__A */
261
262 WRBLOCK(FE_AG_REG_DCE_AUR_CNT__A , 2),
263 0x10,0x00, /* FE_AG_REG_DCE_AUR_CNT__A */
264 0x10,0x00, /* FE_AG_REG_DCE_RUR_CNT__A */
265
266 WRBLOCK(FE_AG_REG_ACE_AUR_CNT__A , 2),
267 0x0E,0x00, /* FE_AG_REG_ACE_AUR_CNT__A */
268 0x00,0x00, /* FE_AG_REG_ACE_RUR_CNT__A */
269
270 WRBLOCK(FE_AG_REG_EGC_FLA_RGN__A , 5),
271 0x04,0x00, /* FE_AG_REG_EGC_FLA_RGN__A */
272 0x1F,0x00, /* FE_AG_REG_EGC_SLO_RGN__A */
273 0x00,0x00, /* FE_AG_REG_EGC_JMP_PSN__A */
274 0x00,0x00, /* FE_AG_REG_EGC_FLA_INC__A */
275 0x00,0x00, /* FE_AG_REG_EGC_FLA_DEC__A */
276
277 WRBLOCK(FE_AG_REG_GC1_AGC_MAX__A , 2),
278 0xFF,0x01, /* FE_AG_REG_GC1_AGC_MAX__A */
279 0x00,0xFE, /* FE_AG_REG_GC1_AGC_MIN__A */
280
281 WRBLOCK(FE_AG_REG_IND_WIN__A , 29),
282 0x00,0x00, /* FE_AG_REG_IND_WIN__A */
283 0x05,0x00, /* FE_AG_REG_IND_THD_LOL__A */
284 0x0F,0x00, /* FE_AG_REG_IND_THD_HIL__A */
285 0x00,0x00, /* FE_AG_REG_IND_DEL__A don't care */
286 0x1E,0x00, /* FE_AG_REG_IND_PD1_WRI__A */
287 0x0C,0x00, /* FE_AG_REG_PDA_AUR_CNT__A */
288 0x00,0x00, /* FE_AG_REG_PDA_RUR_CNT__A */
289 0x00,0x00, /* FE_AG_REG_PDA_AVE_DAT__A don't care */
290 0x00,0x00, /* FE_AG_REG_PDC_RUR_CNT__A */
291 0x01,0x00, /* FE_AG_REG_PDC_SET_LVL__A */
292 0x02,0x00, /* FE_AG_REG_PDC_FLA_RGN__A */
293 0x00,0x00, /* FE_AG_REG_PDC_JMP_PSN__A don't care */
294 0xFF,0xFF, /* FE_AG_REG_PDC_FLA_STP__A */
295 0xFF,0xFF, /* FE_AG_REG_PDC_SLO_STP__A */
296 0x00,0x1F, /* FE_AG_REG_PDC_PD2_WRI__A don't care */
297 0x00,0x00, /* FE_AG_REG_PDC_MAP_DAT__A don't care */
298 0x02,0x00, /* FE_AG_REG_PDC_MAX__A */
299 0x0C,0x00, /* FE_AG_REG_TGA_AUR_CNT__A */
300 0x00,0x00, /* FE_AG_REG_TGA_RUR_CNT__A */
301 0x00,0x00, /* FE_AG_REG_TGA_AVE_DAT__A don't care */
302 0x00,0x00, /* FE_AG_REG_TGC_RUR_CNT__A */
303 0x22,0x00, /* FE_AG_REG_TGC_SET_LVL__A */
304 0x15,0x00, /* FE_AG_REG_TGC_FLA_RGN__A */
305 0x00,0x00, /* FE_AG_REG_TGC_JMP_PSN__A don't care */
306 0x01,0x00, /* FE_AG_REG_TGC_FLA_STP__A */
307 0x0A,0x00, /* FE_AG_REG_TGC_SLO_STP__A */
308 0x00,0x00, /* FE_AG_REG_TGC_MAP_DAT__A don't care */
309 0x10,0x00, /* FE_AG_REG_FGA_AUR_CNT__A */
310 0x10,0x00, /* FE_AG_REG_FGA_RUR_CNT__A */
311
312 WRBLOCK(FE_AG_REG_BGC_FGC_WRI__A , 2),
313 0x00,0x00, /* FE_AG_REG_BGC_FGC_WRI__A */
314 0x00,0x00, /* FE_AG_REG_BGC_CGC_WRI__A */
315
316 WRBLOCK(FE_FD_REG_SCL__A , 3),
317 0x05,0x00, /* FE_FD_REG_SCL__A */
318 0x03,0x00, /* FE_FD_REG_MAX_LEV__A */
319 0x05,0x00, /* FE_FD_REG_NR__A */
320
321 WRBLOCK(FE_CF_REG_SCL__A , 5),
322 0x16,0x00, /* FE_CF_REG_SCL__A */
323 0x04,0x00, /* FE_CF_REG_MAX_LEV__A */
324 0x06,0x00, /* FE_CF_REG_NR__A */
325 0x00,0x00, /* FE_CF_REG_IMP_VAL__A */
326 0x01,0x00, /* FE_CF_REG_MEAS_VAL__A */
327
328 WRBLOCK(FE_CU_REG_FRM_CNT_RST__A , 2),
329 0x00,0x08, /* FE_CU_REG_FRM_CNT_RST__A */
330 0x00,0x00, /* FE_CU_REG_FRM_CNT_STR__A */
331
332 END_OF_TABLE
333};
334
335 /* with PGA */
336/* WR16COND( DRXD_WITH_PGA, FE_AG_REG_AG_PGA_MODE__A , 0x0004), */
337 /* without PGA */
338/* WR16COND( DRXD_WITHOUT_PGA, FE_AG_REG_AG_PGA_MODE__A , 0x0001), */
339/* WR16(FE_AG_REG_AG_AGC_SIO__A, (extAttr -> FeAgRegAgAgcSio), 0x0000 );*/
340/* WR16(FE_AG_REG_AG_PWD__A ,(extAttr -> FeAgRegAgPwd), 0x0000 );*/
341
342u8_t DRXD_InitFEA2_2[] =
343{
344 WR16(FE_AG_REG_CDR_RUR_CNT__A, 0x0010),
345 WR16(FE_AG_REG_FGM_WRI__A , 48),
346 /* Activate measurement, activate scale */
347 WR16(FE_FD_REG_MEAS_VAL__A , 0x0001),
348
349 WR16(FE_CU_REG_COMM_EXEC__A, 0x0001),
350 WR16(FE_CF_REG_COMM_EXEC__A, 0x0001),
351 WR16(FE_IF_REG_COMM_EXEC__A, 0x0001),
352 WR16(FE_FD_REG_COMM_EXEC__A, 0x0001),
353 WR16(FE_FS_REG_COMM_EXEC__A, 0x0001),
354 WR16(FE_AD_REG_COMM_EXEC__A , 0x0001),
355 WR16(FE_AG_REG_COMM_EXEC__A , 0x0001),
356 WR16(FE_AG_REG_AG_MODE_LOP__A , 0x895E),
357
358 END_OF_TABLE
359};
360
361u8_t DRXD_InitFEB1_1[] =
362{
363 WR16(B_FE_AD_REG_PD__A ,0x0000 ),
364 WR16(B_FE_AD_REG_CLKNEG__A ,0x0000 ),
365 WR16(B_FE_AG_REG_BGC_FGC_WRI__A ,0x0000 ),
366 WR16(B_FE_AG_REG_BGC_CGC_WRI__A ,0x0000 ),
367 WR16(B_FE_AG_REG_AG_MODE_LOP__A ,0x000a ),
368 WR16(B_FE_AG_REG_IND_PD1_WRI__A ,35 ),
369 WR16(B_FE_AG_REG_IND_WIN__A ,0 ),
370 WR16(B_FE_AG_REG_IND_THD_LOL__A ,8 ),
371 WR16(B_FE_AG_REG_IND_THD_HIL__A ,8 ),
372 WR16(B_FE_CF_REG_IMP_VAL__A ,1 ),
373 WR16(B_FE_AG_REG_EGC_FLA_RGN__A ,7 ),
374 END_OF_TABLE
375};
376 /* with PGA */
377/* WR16(B_FE_AG_REG_AG_PGA_MODE__A , 0x0000, 0x0000); */
378 /* without PGA */
379/* WR16(B_FE_AG_REG_AG_PGA_MODE__A ,
380 B_FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFY_REN, 0x0000);*/
381/* WR16(B_FE_AG_REG_AG_AGC_SIO__A,(extAttr -> FeAgRegAgAgcSio), 0x0000 );*//*added HS 23-05-2005*/
382/* WR16(B_FE_AG_REG_AG_PWD__A ,(extAttr -> FeAgRegAgPwd), 0x0000 );*/
383
384u8_t DRXD_InitFEB1_2[] =
385{
386 WR16(B_FE_COMM_EXEC__A ,0x0001 ),
387
388 /* RF-AGC setup */
389 WR16(B_FE_AG_REG_PDA_AUR_CNT__A , 0x0C ),
390 WR16(B_FE_AG_REG_PDC_SET_LVL__A , 0x01 ),
391 WR16(B_FE_AG_REG_PDC_FLA_RGN__A , 0x02 ),
392 WR16(B_FE_AG_REG_PDC_FLA_STP__A , 0xFFFF ),
393 WR16(B_FE_AG_REG_PDC_SLO_STP__A , 0xFFFF ),
394 WR16(B_FE_AG_REG_PDC_MAX__A , 0x02 ),
395 WR16(B_FE_AG_REG_TGA_AUR_CNT__A , 0x0C ),
396 WR16(B_FE_AG_REG_TGC_SET_LVL__A , 0x22 ),
397 WR16(B_FE_AG_REG_TGC_FLA_RGN__A , 0x15 ),
398 WR16(B_FE_AG_REG_TGC_FLA_STP__A , 0x01 ),
399 WR16(B_FE_AG_REG_TGC_SLO_STP__A , 0x0A ),
400
401 WR16(B_FE_CU_REG_DIV_NFC_CLP__A , 0 ),
402 WR16(B_FE_CU_REG_CTR_NFC_OCR__A , 25000 ),
403 WR16(B_FE_CU_REG_CTR_NFC_ICR__A , 1 ),
404 END_OF_TABLE
405};
406
407u8_t DRXD_InitCPA2[] =
408{
409 WRBLOCK(CP_REG_BR_SPL_OFFSET__A , 2),
410 0x07,0x00, /* CP_REG_BR_SPL_OFFSET__A */
411 0x0A,0x00, /* CP_REG_BR_STR_DEL__A */
412
413 WRBLOCK(CP_REG_RT_ANG_INC0__A , 4),
414 0x00,0x00, /* CP_REG_RT_ANG_INC0__A */
415 0x00,0x00, /* CP_REG_RT_ANG_INC1__A */
416 0x03,0x00, /* CP_REG_RT_DETECT_ENA__A */
417 0x03,0x00, /* CP_REG_RT_DETECT_TRH__A */
418
419 WRBLOCK(CP_REG_AC_NEXP_OFFS__A , 5),
420 0x32,0x00, /* CP_REG_AC_NEXP_OFFS__A */
421 0x62,0x00, /* CP_REG_AC_AVER_POW__A */
422 0x82,0x00, /* CP_REG_AC_MAX_POW__A */
423 0x26,0x00, /* CP_REG_AC_WEIGHT_MAN__A */
424 0x0F,0x00, /* CP_REG_AC_WEIGHT_EXP__A */
425
426 WRBLOCK(CP_REG_AC_AMP_MODE__A ,2),
427 0x02,0x00, /* CP_REG_AC_AMP_MODE__A */
428 0x01,0x00, /* CP_REG_AC_AMP_FIX__A */
429
430 WR16(CP_REG_INTERVAL__A , 0x0005 ),
431 WR16(CP_REG_RT_EXP_MARG__A , 0x0004 ),
432 WR16(CP_REG_AC_ANG_MODE__A , 0x0003 ),
433
434 WR16(CP_REG_COMM_EXEC__A , 0x0001 ),
435 END_OF_TABLE
436};
437
438u8_t DRXD_InitCPB1[] =
439{
440 WR16(B_CP_REG_BR_SPL_OFFSET__A ,0x0008 ),
441 WR16(B_CP_COMM_EXEC__A ,0x0001 ),
442 END_OF_TABLE
443};
444
445
446u8_t DRXD_InitCEA2[] =
447{
448 WRBLOCK(CE_REG_AVG_POW__A , 4),
449 0x62,0x00, /* CE_REG_AVG_POW__A */
450 0x78,0x00, /* CE_REG_MAX_POW__A */
451 0x62,0x00, /* CE_REG_ATT__A */
452 0x17,0x00, /* CE_REG_NRED__A */
453
454 WRBLOCK(CE_REG_NE_ERR_SELECT__A , 2),
455 0x07,0x00, /* CE_REG_NE_ERR_SELECT__A */
456 0xEB,0xFF, /* CE_REG_NE_TD_CAL__A */
457
458 WRBLOCK(CE_REG_NE_MIXAVG__A , 2),
459 0x06,0x00, /* CE_REG_NE_MIXAVG__A */
460 0x00,0x00, /* CE_REG_NE_NUPD_OFS__A */
461
462 WRBLOCK(CE_REG_PE_NEXP_OFFS__A , 2),
463 0x00,0x00, /* CE_REG_PE_NEXP_OFFS__A */
464 0x00,0x00, /* CE_REG_PE_TIMESHIFT__A */
465
466 WRBLOCK(CE_REG_TP_A0_TAP_NEW__A , 3),
467 0x00,0x01, /* CE_REG_TP_A0_TAP_NEW__A */
468 0x01,0x00, /* CE_REG_TP_A0_TAP_NEW_VALID__A */
469 0x0E,0x00, /* CE_REG_TP_A0_MU_LMS_STEP__A */
470
471 WRBLOCK(CE_REG_TP_A1_TAP_NEW__A , 3),
472 0x00,0x00, /* CE_REG_TP_A1_TAP_NEW__A */
473 0x01,0x00, /* CE_REG_TP_A1_TAP_NEW_VALID__A */
474 0x0A,0x00, /* CE_REG_TP_A1_MU_LMS_STEP__A */
475
476 WRBLOCK(CE_REG_FI_SHT_INCR__A , 2),
477 0x12,0x00, /* CE_REG_FI_SHT_INCR__A */
478 0x0C,0x00, /* CE_REG_FI_EXP_NORM__A */
479
480 WRBLOCK(CE_REG_IR_INPUTSEL__A , 3),
481 0x00,0x00, /* CE_REG_IR_INPUTSEL__A */
482 0x00,0x00, /* CE_REG_IR_STARTPOS__A */
483 0xFF,0x00, /* CE_REG_IR_NEXP_THRES__A */
484
485
486 WR16(CE_REG_TI_NEXP_OFFS__A ,0x0000),
487
488 END_OF_TABLE
489};
490
491u8_t DRXD_InitCEB1[] =
492{
493 WR16(B_CE_REG_TI_PHN_ENABLE__A ,0x0001),
494 WR16(B_CE_REG_FR_PM_SET__A ,0x000D),
495
496 END_OF_TABLE
497};
498
499u8_t DRXD_InitEQA2[] =
500{
501 WRBLOCK(EQ_REG_OT_QNT_THRES0__A , 4),
502 0x1E,0x00, /* EQ_REG_OT_QNT_THRES0__A */
503 0x1F,0x00, /* EQ_REG_OT_QNT_THRES1__A */
504 0x06,0x00, /* EQ_REG_OT_CSI_STEP__A */
505 0x02,0x00, /* EQ_REG_OT_CSI_OFFSET__A */
506
507 WR16(EQ_REG_TD_REQ_SMB_CNT__A ,0x0200 ),
508 WR16(EQ_REG_IS_CLIP_EXP__A ,0x001F ),
509 WR16(EQ_REG_SN_OFFSET__A ,(u16_t)(-7) ),
510 WR16(EQ_REG_RC_SEL_CAR__A ,0x0002 ),
511 WR16(EQ_REG_COMM_EXEC__A ,0x0001 ),
512 END_OF_TABLE
513};
514
515u8_t DRXD_InitEQB1[] =
516{
517 WR16(B_EQ_REG_COMM_EXEC__A ,0x0001 ),
518 END_OF_TABLE
519};
520
521u8_t DRXD_ResetECRAM[] =
522{
523 /* Reset packet sync bytes in EC_VD ram */
524 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 0*17) , 0x0000 ),
525 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 1*17) , 0x0000 ),
526 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 2*17) , 0x0000 ),
527 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 3*17) , 0x0000 ),
528 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 4*17) , 0x0000 ),
529 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 5*17) , 0x0000 ),
530 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 6*17) , 0x0000 ),
531 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 7*17) , 0x0000 ),
532 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 8*17) , 0x0000 ),
533 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 9*17) , 0x0000 ),
534 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (10*17) , 0x0000 ),
535
536 /* Reset packet sync bytes in EC_RS ram */
537 WR16(EC_RS_EC_RAM__A , 0x0000 ),
538 WR16(EC_RS_EC_RAM__A + 204 , 0x0000 ),
539 END_OF_TABLE
540};
541
542u8_t DRXD_InitECA2[] =
543{
544 WRBLOCK( EC_SB_REG_CSI_HI__A , 6),
545 0x1F,0x00, /* EC_SB_REG_CSI_HI__A */
546 0x1E,0x00, /* EC_SB_REG_CSI_LO__A */
547 0x01,0x00, /* EC_SB_REG_SMB_TGL__A */
548 0x7F,0x00, /* EC_SB_REG_SNR_HI__A */
549 0x7F,0x00, /* EC_SB_REG_SNR_MID__A */
550 0x7F,0x00, /* EC_SB_REG_SNR_LO__A */
551
552 WRBLOCK( EC_RS_REG_REQ_PCK_CNT__A , 2),
553 0x00,0x10, /* EC_RS_REG_REQ_PCK_CNT__A */
554 DATA16(EC_RS_REG_VAL_PCK), /* EC_RS_REG_VAL__A */
555
556 WRBLOCK( EC_OC_REG_TMD_TOP_MODE__A , 5),
557 0x03,0x00, /* EC_OC_REG_TMD_TOP_MODE__A */
558 0xF4,0x01, /* EC_OC_REG_TMD_TOP_CNT__A */
559 0xC0,0x03, /* EC_OC_REG_TMD_HIL_MAR__A */
560 0x40,0x00, /* EC_OC_REG_TMD_LOL_MAR__A */
561 0x03,0x00, /* EC_OC_REG_TMD_CUR_CNT__A */
562
563 WRBLOCK( EC_OC_REG_AVR_ASH_CNT__A , 2),
564 0x06,0x00, /* EC_OC_REG_AVR_ASH_CNT__A */
565 0x02,0x00, /* EC_OC_REG_AVR_BSH_CNT__A */
566
567 WRBLOCK( EC_OC_REG_RCN_MODE__A , 7),
568 0x07,0x00, /* EC_OC_REG_RCN_MODE__A */
569 0x00,0x00, /* EC_OC_REG_RCN_CRA_LOP__A */
570 0xc0,0x00, /* EC_OC_REG_RCN_CRA_HIP__A */
571 0x00,0x10, /* EC_OC_REG_RCN_CST_LOP__A */
572 0x00,0x00, /* EC_OC_REG_RCN_CST_HIP__A */
573 0xFF,0x01, /* EC_OC_REG_RCN_SET_LVL__A */
574 0x0D,0x00, /* EC_OC_REG_RCN_GAI_LVL__A */
575
576 WRBLOCK( EC_OC_REG_RCN_CLP_LOP__A , 2),
577 0x00,0x00, /* EC_OC_REG_RCN_CLP_LOP__A */
578 0xC0,0x00, /* EC_OC_REG_RCN_CLP_HIP__A */
579
580 WR16(EC_SB_REG_CSI_OFS__A , 0x0001 ),
581 WR16(EC_VD_REG_FORCE__A , 0x0002 ),
582 WR16(EC_VD_REG_REQ_SMB_CNT__A , 0x0001 ),
583 WR16(EC_VD_REG_RLK_ENA__A , 0x0001 ),
584 WR16(EC_OD_REG_SYNC__A , 0x0664 ),
585 WR16(EC_OC_REG_OC_MON_SIO__A , 0x0000 ),
586 WR16(EC_OC_REG_SNC_ISC_LVL__A , 0x0D0C ),
587 /* Output zero on monitorbus pads, power saving */
588 WR16(EC_OC_REG_OCR_MON_UOS__A ,
589 ( EC_OC_REG_OCR_MON_UOS_DAT_0_ENABLE |
590 EC_OC_REG_OCR_MON_UOS_DAT_1_ENABLE |
591 EC_OC_REG_OCR_MON_UOS_DAT_2_ENABLE |
592 EC_OC_REG_OCR_MON_UOS_DAT_3_ENABLE |
593 EC_OC_REG_OCR_MON_UOS_DAT_4_ENABLE |
594 EC_OC_REG_OCR_MON_UOS_DAT_5_ENABLE |
595 EC_OC_REG_OCR_MON_UOS_DAT_6_ENABLE |
596 EC_OC_REG_OCR_MON_UOS_DAT_7_ENABLE |
597 EC_OC_REG_OCR_MON_UOS_DAT_8_ENABLE |
598 EC_OC_REG_OCR_MON_UOS_DAT_9_ENABLE |
599 EC_OC_REG_OCR_MON_UOS_VAL_ENABLE |
600 EC_OC_REG_OCR_MON_UOS_CLK_ENABLE ) ),
601 WR16(EC_OC_REG_OCR_MON_WRI__A,
602 EC_OC_REG_OCR_MON_WRI_INIT ),
603
604/* CHK_ERROR(ResetECRAM(demod)); */
605 /* Reset packet sync bytes in EC_VD ram */
606 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 0*17) , 0x0000 ),
607 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 1*17) , 0x0000 ),
608 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 2*17) , 0x0000 ),
609 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 3*17) , 0x0000 ),
610 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 4*17) , 0x0000 ),
611 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 5*17) , 0x0000 ),
612 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 6*17) , 0x0000 ),
613 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 7*17) , 0x0000 ),
614 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 8*17) , 0x0000 ),
615 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 9*17) , 0x0000 ),
616 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (10*17) , 0x0000 ),
617
618 /* Reset packet sync bytes in EC_RS ram */
619 WR16(EC_RS_EC_RAM__A , 0x0000 ),
620 WR16(EC_RS_EC_RAM__A + 204 , 0x0000 ),
621
622 WR16(EC_SB_REG_COMM_EXEC__A , 0x0001 ),
623 WR16(EC_VD_REG_COMM_EXEC__A , 0x0001 ),
624 WR16(EC_OD_REG_COMM_EXEC__A , 0x0001 ),
625 WR16(EC_RS_REG_COMM_EXEC__A , 0x0001 ),
626 END_OF_TABLE
627};
628
629u8_t DRXD_InitECB1[] =
630{
631 WR16(B_EC_SB_REG_CSI_OFS0__A ,0x0001 ),
632 WR16(B_EC_SB_REG_CSI_OFS1__A ,0x0001 ),
633 WR16(B_EC_SB_REG_CSI_OFS2__A ,0x0001 ),
634 WR16(B_EC_SB_REG_CSI_LO__A ,0x000c ),
635 WR16(B_EC_SB_REG_CSI_HI__A ,0x0018 ),
636 WR16(B_EC_SB_REG_SNR_HI__A ,0x007f ),
637 WR16(B_EC_SB_REG_SNR_MID__A ,0x007f ),
638 WR16(B_EC_SB_REG_SNR_LO__A ,0x007f ),
639
640 WR16(B_EC_OC_REG_DTO_CLKMODE__A ,0x0002 ),
641 WR16(B_EC_OC_REG_DTO_PER__A ,0x0006 ),
642 WR16(B_EC_OC_REG_DTO_BUR__A ,0x0001 ),
643 WR16(B_EC_OC_REG_RCR_CLKMODE__A ,0x0000 ),
644 WR16(B_EC_OC_REG_RCN_GAI_LVL__A ,0x000D ),
645 WR16(B_EC_OC_REG_OC_MPG_SIO__A ,0x0000 ),
646
647 /* Needed because shadow registers do not have correct default value */
648 WR16(B_EC_OC_REG_RCN_CST_LOP__A ,0x1000 ),
649 WR16(B_EC_OC_REG_RCN_CST_HIP__A ,0x0000 ),
650 WR16(B_EC_OC_REG_RCN_CRA_LOP__A ,0x0000 ),
651 WR16(B_EC_OC_REG_RCN_CRA_HIP__A ,0x00C0 ),
652 WR16(B_EC_OC_REG_RCN_CLP_LOP__A ,0x0000 ),
653 WR16(B_EC_OC_REG_RCN_CLP_HIP__A ,0x00C0 ),
654 WR16(B_EC_OC_REG_DTO_INC_LOP__A ,0x0000 ),
655 WR16(B_EC_OC_REG_DTO_INC_HIP__A ,0x00C0 ),
656
657 WR16(B_EC_OD_REG_SYNC__A ,0x0664 ),
658 WR16(B_EC_RS_REG_REQ_PCK_CNT__A ,0x1000 ),
659
660/* CHK_ERROR(ResetECRAM(demod)); */
661 /* Reset packet sync bytes in EC_VD ram */
662 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 0*17) , 0x0000 ),
663 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 1*17) , 0x0000 ),
664 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 2*17) , 0x0000 ),
665 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 3*17) , 0x0000 ),
666 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 4*17) , 0x0000 ),
667 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 5*17) , 0x0000 ),
668 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 6*17) , 0x0000 ),
669 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 7*17) , 0x0000 ),
670 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 8*17) , 0x0000 ),
671 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 9*17) , 0x0000 ),
672 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (10*17) , 0x0000 ),
673
674 /* Reset packet sync bytes in EC_RS ram */
675 WR16(EC_RS_EC_RAM__A , 0x0000 ),
676 WR16(EC_RS_EC_RAM__A + 204 , 0x0000 ),
677
678 WR16(B_EC_SB_REG_COMM_EXEC__A , 0x0001 ),
679 WR16(B_EC_VD_REG_COMM_EXEC__A , 0x0001 ),
680 WR16(B_EC_OD_REG_COMM_EXEC__A , 0x0001 ),
681 WR16(B_EC_RS_REG_COMM_EXEC__A , 0x0001 ),
682 END_OF_TABLE
683};
684
685u8_t DRXD_ResetECA2[] =
686{
687
688 WR16(EC_OC_REG_COMM_EXEC__A , 0x0000 ),
689 WR16(EC_OD_REG_COMM_EXEC__A , 0x0000 ),
690
691 WRBLOCK( EC_OC_REG_TMD_TOP_MODE__A , 5),
692 0x03,0x00, /* EC_OC_REG_TMD_TOP_MODE__A */
693 0xF4,0x01, /* EC_OC_REG_TMD_TOP_CNT__A */
694 0xC0,0x03, /* EC_OC_REG_TMD_HIL_MAR__A */
695 0x40,0x00, /* EC_OC_REG_TMD_LOL_MAR__A */
696 0x03,0x00, /* EC_OC_REG_TMD_CUR_CNT__A */
697
698 WRBLOCK( EC_OC_REG_AVR_ASH_CNT__A , 2),
699 0x06,0x00, /* EC_OC_REG_AVR_ASH_CNT__A */
700 0x02,0x00, /* EC_OC_REG_AVR_BSH_CNT__A */
701
702 WRBLOCK( EC_OC_REG_RCN_MODE__A , 7),
703 0x07,0x00, /* EC_OC_REG_RCN_MODE__A */
704 0x00,0x00, /* EC_OC_REG_RCN_CRA_LOP__A */
705 0xc0,0x00, /* EC_OC_REG_RCN_CRA_HIP__A */
706 0x00,0x10, /* EC_OC_REG_RCN_CST_LOP__A */
707 0x00,0x00, /* EC_OC_REG_RCN_CST_HIP__A */
708 0xFF,0x01, /* EC_OC_REG_RCN_SET_LVL__A */
709 0x0D,0x00, /* EC_OC_REG_RCN_GAI_LVL__A */
710
711 WRBLOCK( EC_OC_REG_RCN_CLP_LOP__A , 2),
712 0x00,0x00, /* EC_OC_REG_RCN_CLP_LOP__A */
713 0xC0,0x00, /* EC_OC_REG_RCN_CLP_HIP__A */
714
715 WR16(EC_OD_REG_SYNC__A , 0x0664 ),
716 WR16(EC_OC_REG_OC_MON_SIO__A , 0x0000 ),
717 WR16(EC_OC_REG_SNC_ISC_LVL__A , 0x0D0C ),
718 /* Output zero on monitorbus pads, power saving */
719 WR16(EC_OC_REG_OCR_MON_UOS__A ,
720 ( EC_OC_REG_OCR_MON_UOS_DAT_0_ENABLE |
721 EC_OC_REG_OCR_MON_UOS_DAT_1_ENABLE |
722 EC_OC_REG_OCR_MON_UOS_DAT_2_ENABLE |
723 EC_OC_REG_OCR_MON_UOS_DAT_3_ENABLE |
724 EC_OC_REG_OCR_MON_UOS_DAT_4_ENABLE |
725 EC_OC_REG_OCR_MON_UOS_DAT_5_ENABLE |
726 EC_OC_REG_OCR_MON_UOS_DAT_6_ENABLE |
727 EC_OC_REG_OCR_MON_UOS_DAT_7_ENABLE |
728 EC_OC_REG_OCR_MON_UOS_DAT_8_ENABLE |
729 EC_OC_REG_OCR_MON_UOS_DAT_9_ENABLE |
730 EC_OC_REG_OCR_MON_UOS_VAL_ENABLE |
731 EC_OC_REG_OCR_MON_UOS_CLK_ENABLE ) ),
732 WR16(EC_OC_REG_OCR_MON_WRI__A,
733 EC_OC_REG_OCR_MON_WRI_INIT ),
734
735/* CHK_ERROR(ResetECRAM(demod)); */
736 /* Reset packet sync bytes in EC_VD ram */
737 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 0*17) , 0x0000 ),
738 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 1*17) , 0x0000 ),
739 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 2*17) , 0x0000 ),
740 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 3*17) , 0x0000 ),
741 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 4*17) , 0x0000 ),
742 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 5*17) , 0x0000 ),
743 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 6*17) , 0x0000 ),
744 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 7*17) , 0x0000 ),
745 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 8*17) , 0x0000 ),
746 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 9*17) , 0x0000 ),
747 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (10*17) , 0x0000 ),
748
749 /* Reset packet sync bytes in EC_RS ram */
750 WR16(EC_RS_EC_RAM__A , 0x0000 ),
751 WR16(EC_RS_EC_RAM__A + 204 , 0x0000 ),
752
753 WR16(EC_OD_REG_COMM_EXEC__A , 0x0001 ),
754 END_OF_TABLE
755};
756
757u8_t DRXD_InitSC[] =
758{
759 WR16(SC_COMM_EXEC__A, 0 ),
760 WR16(SC_COMM_STATE__A, 0 ),
761
762#ifdef COMPILE_FOR_QT
763 WR16(SC_RA_RAM_BE_OPT_DELAY__A, 0x100 ),
764#endif
765
766 /* SC is not started, this is done in SetChannels() */
767 END_OF_TABLE
768};
769
770/* Diversity settings */
771
772u8_t DRXD_InitDiversityFront[] =
773{
774 /* Start demod ********* RF in , diversity out *****************************/
775 WR16( B_SC_RA_RAM_CONFIG__A, B_SC_RA_RAM_CONFIG_FR_ENABLE__M |
776 B_SC_RA_RAM_CONFIG_FREQSCAN__M ),
777
778 WR16( B_SC_RA_RAM_LC_ABS_2K__A, 0x7),
779 WR16( B_SC_RA_RAM_LC_ABS_8K__A, 0x7),
780 WR16( B_SC_RA_RAM_IR_COARSE_8K_LENGTH__A, IRLEN_COARSE_8K ),
781 WR16( B_SC_RA_RAM_IR_COARSE_8K_FREQINC__A, 1<<(11-IRLEN_COARSE_8K) ),
782 WR16( B_SC_RA_RAM_IR_COARSE_8K_KAISINC__A, 1<<(17-IRLEN_COARSE_8K) ),
783 WR16( B_SC_RA_RAM_IR_FINE_8K_LENGTH__A, IRLEN_FINE_8K ),
784 WR16( B_SC_RA_RAM_IR_FINE_8K_FREQINC__A, 1<<(11-IRLEN_FINE_8K) ),
785 WR16( B_SC_RA_RAM_IR_FINE_8K_KAISINC__A, 1<<(17-IRLEN_FINE_8K) ),
786
787 WR16( B_SC_RA_RAM_IR_COARSE_2K_LENGTH__A, IRLEN_COARSE_2K ),
788 WR16( B_SC_RA_RAM_IR_COARSE_2K_FREQINC__A, 1<<(11-IRLEN_COARSE_2K) ),
789 WR16( B_SC_RA_RAM_IR_COARSE_2K_KAISINC__A, 1<<(17-IRLEN_COARSE_2K) ),
790 WR16( B_SC_RA_RAM_IR_FINE_2K_LENGTH__A, IRLEN_FINE_2K ),
791 WR16( B_SC_RA_RAM_IR_FINE_2K_FREQINC__A, 1<<(11-IRLEN_FINE_2K) ),
792 WR16( B_SC_RA_RAM_IR_FINE_2K_KAISINC__A, 1<<(17-IRLEN_FINE_2K) ),
793
794 WR16( B_LC_RA_RAM_FILTER_CRMM_A__A, 7),
795 WR16( B_LC_RA_RAM_FILTER_CRMM_B__A, 4),
796 WR16( B_LC_RA_RAM_FILTER_SRMM_A__A, 7),
797 WR16( B_LC_RA_RAM_FILTER_SRMM_B__A, 4),
798 WR16( B_LC_RA_RAM_FILTER_SYM_SET__A, 500),
799
800 WR16( B_CC_REG_DIVERSITY__A, 0x0001 ),
801 WR16( B_EC_OC_REG_OC_MODE_HIP__A, 0x0010 ),
802 WR16( B_EQ_REG_RC_SEL_CAR__A, B_EQ_REG_RC_SEL_CAR_PASS_B_CE |
803 B_EQ_REG_RC_SEL_CAR_LOCAL_B_CE |
804 B_EQ_REG_RC_SEL_CAR_MEAS_B_CE ),
805
806
807 /* 0x2a ),*/ /* CE to PASS mux */
808
809 END_OF_TABLE
810};
811
812u8_t DRXD_InitDiversityEnd[] =
813{
814 /* End demod *********** combining RF in and diversity in, MPEG TS out *****/
815 /* disable near/far; switch on timing slave mode */
816 WR16( B_SC_RA_RAM_CONFIG__A, B_SC_RA_RAM_CONFIG_FR_ENABLE__M |
817 B_SC_RA_RAM_CONFIG_FREQSCAN__M |
818 B_SC_RA_RAM_CONFIG_DIV_ECHO_ENABLE__M |
819 B_SC_RA_RAM_CONFIG_SLAVE__M |
820 B_SC_RA_RAM_CONFIG_DIV_BLANK_ENABLE__M
821/* MV from CtrlDiversity */
822 ),
823#ifdef DRXDDIV_SRMM_SLAVING
824 WR16( SC_RA_RAM_LC_ABS_2K__A, 0x3c7),
825 WR16( SC_RA_RAM_LC_ABS_8K__A, 0x3c7),
826#else
827 WR16( SC_RA_RAM_LC_ABS_2K__A, 0x7),
828 WR16( SC_RA_RAM_LC_ABS_8K__A, 0x7),
829#endif
830
831 WR16( B_SC_RA_RAM_IR_COARSE_8K_LENGTH__A, IRLEN_COARSE_8K ),
832 WR16( B_SC_RA_RAM_IR_COARSE_8K_FREQINC__A, 1<<(11-IRLEN_COARSE_8K) ),
833 WR16( B_SC_RA_RAM_IR_COARSE_8K_KAISINC__A, 1<<(17-IRLEN_COARSE_8K) ),
834 WR16( B_SC_RA_RAM_IR_FINE_8K_LENGTH__A, IRLEN_FINE_8K ),
835 WR16( B_SC_RA_RAM_IR_FINE_8K_FREQINC__A, 1<<(11-IRLEN_FINE_8K) ),
836 WR16( B_SC_RA_RAM_IR_FINE_8K_KAISINC__A, 1<<(17-IRLEN_FINE_8K) ),
837
838 WR16( B_SC_RA_RAM_IR_COARSE_2K_LENGTH__A, IRLEN_COARSE_2K ),
839 WR16( B_SC_RA_RAM_IR_COARSE_2K_FREQINC__A, 1<<(11-IRLEN_COARSE_2K) ),
840 WR16( B_SC_RA_RAM_IR_COARSE_2K_KAISINC__A, 1<<(17-IRLEN_COARSE_2K) ),
841 WR16( B_SC_RA_RAM_IR_FINE_2K_LENGTH__A, IRLEN_FINE_2K ),
842 WR16( B_SC_RA_RAM_IR_FINE_2K_FREQINC__A, 1<<(11-IRLEN_FINE_2K) ),
843 WR16( B_SC_RA_RAM_IR_FINE_2K_KAISINC__A, 1<<(17-IRLEN_FINE_2K) ),
844
845 WR16( B_LC_RA_RAM_FILTER_CRMM_A__A, 7),
846 WR16( B_LC_RA_RAM_FILTER_CRMM_B__A, 4),
847 WR16( B_LC_RA_RAM_FILTER_SRMM_A__A, 7),
848 WR16( B_LC_RA_RAM_FILTER_SRMM_B__A, 4),
849 WR16( B_LC_RA_RAM_FILTER_SYM_SET__A, 500),
850
851 WR16( B_CC_REG_DIVERSITY__A, 0x0001 ),
852 END_OF_TABLE
853};
854
855u8_t DRXD_DisableDiversity[] =
856{
857 WR16( B_SC_RA_RAM_LC_ABS_2K__A, B_SC_RA_RAM_LC_ABS_2K__PRE),
858 WR16( B_SC_RA_RAM_LC_ABS_8K__A, B_SC_RA_RAM_LC_ABS_8K__PRE),
859 WR16( B_SC_RA_RAM_IR_COARSE_8K_LENGTH__A, B_SC_RA_RAM_IR_COARSE_8K_LENGTH__PRE ),
860 WR16( B_SC_RA_RAM_IR_COARSE_8K_FREQINC__A, B_SC_RA_RAM_IR_COARSE_8K_FREQINC__PRE ),
861 WR16( B_SC_RA_RAM_IR_COARSE_8K_KAISINC__A, B_SC_RA_RAM_IR_COARSE_8K_KAISINC__PRE ),
862 WR16( B_SC_RA_RAM_IR_FINE_8K_LENGTH__A, B_SC_RA_RAM_IR_FINE_8K_LENGTH__PRE ),
863 WR16( B_SC_RA_RAM_IR_FINE_8K_FREQINC__A, B_SC_RA_RAM_IR_FINE_8K_FREQINC__PRE ),
864 WR16( B_SC_RA_RAM_IR_FINE_8K_KAISINC__A, B_SC_RA_RAM_IR_FINE_8K_KAISINC__PRE ),
865
866 WR16( B_SC_RA_RAM_IR_COARSE_2K_LENGTH__A, B_SC_RA_RAM_IR_COARSE_2K_LENGTH__PRE ),
867 WR16( B_SC_RA_RAM_IR_COARSE_2K_FREQINC__A, B_SC_RA_RAM_IR_COARSE_2K_FREQINC__PRE ),
868 WR16( B_SC_RA_RAM_IR_COARSE_2K_KAISINC__A, B_SC_RA_RAM_IR_COARSE_2K_KAISINC__PRE ),
869 WR16( B_SC_RA_RAM_IR_FINE_2K_LENGTH__A, B_SC_RA_RAM_IR_FINE_2K_LENGTH__PRE ),
870 WR16( B_SC_RA_RAM_IR_FINE_2K_FREQINC__A, B_SC_RA_RAM_IR_FINE_2K_FREQINC__PRE ),
871 WR16( B_SC_RA_RAM_IR_FINE_2K_KAISINC__A, B_SC_RA_RAM_IR_FINE_2K_KAISINC__PRE ),
872
873 WR16( B_LC_RA_RAM_FILTER_CRMM_A__A, B_LC_RA_RAM_FILTER_CRMM_A__PRE),
874 WR16( B_LC_RA_RAM_FILTER_CRMM_B__A, B_LC_RA_RAM_FILTER_CRMM_B__PRE),
875 WR16( B_LC_RA_RAM_FILTER_SRMM_A__A, B_LC_RA_RAM_FILTER_SRMM_A__PRE),
876 WR16( B_LC_RA_RAM_FILTER_SRMM_B__A, B_LC_RA_RAM_FILTER_SRMM_B__PRE),
877 WR16( B_LC_RA_RAM_FILTER_SYM_SET__A, B_LC_RA_RAM_FILTER_SYM_SET__PRE),
878
879
880 WR16( B_CC_REG_DIVERSITY__A, 0x0000 ),
881 WR16( B_EQ_REG_RC_SEL_CAR__A, B_EQ_REG_RC_SEL_CAR_INIT ), /* combining disabled*/
882
883 END_OF_TABLE
884};
885
886u8_t DRXD_StartDiversityFront[] =
887{
888 /* Start demod, RF in and diversity out, no combining */
889 WR16( B_FE_CF_REG_IMP_VAL__A, 0x0 ),
890 WR16( B_FE_AD_REG_FDB_IN__A, 0x0 ),
891 WR16( B_FE_AD_REG_INVEXT__A, 0x0 ),
892 WR16( B_EQ_REG_COMM_MB__A, 0x12 ), /* EQ to MB out */
893 WR16( B_EQ_REG_RC_SEL_CAR__A, B_EQ_REG_RC_SEL_CAR_PASS_B_CE | /* CE to PASS mux */
894 B_EQ_REG_RC_SEL_CAR_LOCAL_B_CE |
895 B_EQ_REG_RC_SEL_CAR_MEAS_B_CE ),
896
897 WR16( SC_RA_RAM_ECHO_SHIFT_LIM__A, 2 ),
898
899 END_OF_TABLE
900};
901
902u8_t DRXD_StartDiversityEnd[] =
903{
904 /* End demod, combining RF in and diversity in, MPEG TS out */
905 WR16( B_FE_CF_REG_IMP_VAL__A, 0x0 ), /* disable impulse noise cruncher */
906 WR16( B_FE_AD_REG_INVEXT__A, 0x0 ), /* clock inversion (for sohard board) */
907 WR16( B_CP_REG_BR_STR_DEL__A, 10 ), /* apperently no mb delay matching is best */
908
909 WR16( B_EQ_REG_RC_SEL_CAR__A, B_EQ_REG_RC_SEL_CAR_DIV_ON | /* org = 0x81 combining enabled */
910 B_EQ_REG_RC_SEL_CAR_MEAS_A_CC |
911 B_EQ_REG_RC_SEL_CAR_PASS_A_CC |
912 B_EQ_REG_RC_SEL_CAR_LOCAL_A_CC ),
913
914 END_OF_TABLE
915};
916
917u8_t DRXD_DiversityDelay8MHZ[] =
918{
919 WR16( B_SC_RA_RAM_DIVERSITY_DELAY_2K_32__A, 1150 - 50 ),
920 WR16( B_SC_RA_RAM_DIVERSITY_DELAY_2K_16__A, 1100 - 50 ),
921 WR16( B_SC_RA_RAM_DIVERSITY_DELAY_2K_8__A , 1000 - 50 ),
922 WR16( B_SC_RA_RAM_DIVERSITY_DELAY_2K_4__A , 800 - 50 ),
923 WR16( B_SC_RA_RAM_DIVERSITY_DELAY_8K_32__A, 5420 - 50 ),
924 WR16( B_SC_RA_RAM_DIVERSITY_DELAY_8K_16__A, 5200 - 50 ),
925 WR16( B_SC_RA_RAM_DIVERSITY_DELAY_8K_8__A , 4800 - 50 ),
926 WR16( B_SC_RA_RAM_DIVERSITY_DELAY_8K_4__A , 4000 - 50 ),
927 END_OF_TABLE
928};
929
930u8_t DRXD_DiversityDelay6MHZ[] = /* also used ok for 7 MHz */
931{
932 WR16( B_SC_RA_RAM_DIVERSITY_DELAY_2K_32__A, 1100 - 50 ),
933 WR16( B_SC_RA_RAM_DIVERSITY_DELAY_2K_16__A, 1000 - 50 ),
934 WR16( B_SC_RA_RAM_DIVERSITY_DELAY_2K_8__A , 900 - 50 ),
935 WR16( B_SC_RA_RAM_DIVERSITY_DELAY_2K_4__A , 600 - 50 ),
936 WR16( B_SC_RA_RAM_DIVERSITY_DELAY_8K_32__A, 5300 - 50 ),
937 WR16( B_SC_RA_RAM_DIVERSITY_DELAY_8K_16__A, 5000 - 50 ),
938 WR16( B_SC_RA_RAM_DIVERSITY_DELAY_8K_8__A , 4500 - 50 ),
939 WR16( B_SC_RA_RAM_DIVERSITY_DELAY_8K_4__A , 3500 - 50 ),
940 END_OF_TABLE
941};
942
943#include "drxd_micro.h"
Linux 6.x block layer and io_uring tree(s)