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Merge branch 'rmobile/urgent' into rmobile-fixes-for-linus
[linux-2.6-block.git] / drivers / media / dvb / frontends / cxd2820r_core.c
CommitLineData
27cfc85e
AP		 1/*
2 * Sony CXD2820R demodulator driver
3 *
4 * Copyright (C) 2010 Antti Palosaari <crope@iki.fi>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
19 */
20
21
22#include "cxd2820r_priv.h"
23
24int cxd2820r_debug;
25module_param_named(debug, cxd2820r_debug, int, 0644);
26MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off).");
27
27cfc85e
AP		 28/* write multiple registers */
29static int cxd2820r_wr_regs_i2c(struct cxd2820r_priv *priv, u8 i2c, u8 reg,
30 u8 *val, int len)
31{
32 int ret;
33 u8 buf[len+1];
34 struct i2c_msg msg[1] = {
35 {
36 .addr = i2c,
37 .flags = 0,
38 .len = sizeof(buf),
39 .buf = buf,
40 }
41 };
42
43 buf[0] = reg;
44 memcpy(&buf[1], val, len);
45
46 ret = i2c_transfer(priv->i2c, msg, 1);
47 if (ret == 1) {
48 ret = 0;
49 } else {
50 warn("i2c wr failed ret:%d reg:%02x len:%d", ret, reg, len);
51 ret = -EREMOTEIO;
52 }
53 return ret;
54}
55
56/* read multiple registers */
57static int cxd2820r_rd_regs_i2c(struct cxd2820r_priv *priv, u8 i2c, u8 reg,
58 u8 *val, int len)
59{
60 int ret;
61 u8 buf[len];
62 struct i2c_msg msg[2] = {
63 {
64 .addr = i2c,
65 .flags = 0,
66 .len = 1,
67 .buf = &reg,
68 }, {
69 .addr = i2c,
70 .flags = I2C_M_RD,
71 .len = sizeof(buf),
72 .buf = buf,
73 }
74 };
75
76 ret = i2c_transfer(priv->i2c, msg, 2);
77 if (ret == 2) {
78 memcpy(val, buf, len);
79 ret = 0;
80 } else {
81 warn("i2c rd failed ret:%d reg:%02x len:%d", ret, reg, len);
82 ret = -EREMOTEIO;
83 }
84
85 return ret;
86}
87
88/* write multiple registers */
9ac51c5e 89int cxd2820r_wr_regs(struct cxd2820r_priv *priv, u32 reginfo, u8 *val,
27cfc85e
AP		 90 int len)
91{
92 int ret;
93 u8 i2c_addr;
94 u8 reg = (reginfo >> 0) & 0xff;
95 u8 bank = (reginfo >> 8) & 0xff;
96 u8 i2c = (reginfo >> 16) & 0x01;
97
98 /* select I2C */
99 if (i2c)
100 i2c_addr = priv->cfg.i2c_address | (1 << 1); /* DVB-C */
101 else
102 i2c_addr = priv->cfg.i2c_address; /* DVB-T/T2 */
103
104 /* switch bank if needed */
105 if (bank != priv->bank[i2c]) {
106 ret = cxd2820r_wr_regs_i2c(priv, i2c_addr, 0x00, &bank, 1);
107 if (ret)
108 return ret;
109 priv->bank[i2c] = bank;
110 }
111 return cxd2820r_wr_regs_i2c(priv, i2c_addr, reg, val, len);
112}
113
114/* read multiple registers */
9ac51c5e 115int cxd2820r_rd_regs(struct cxd2820r_priv *priv, u32 reginfo, u8 *val,
27cfc85e
AP		 116 int len)
117{
118 int ret;
119 u8 i2c_addr;
120 u8 reg = (reginfo >> 0) & 0xff;
121 u8 bank = (reginfo >> 8) & 0xff;
122 u8 i2c = (reginfo >> 16) & 0x01;
123
124 /* select I2C */
125 if (i2c)
126 i2c_addr = priv->cfg.i2c_address | (1 << 1); /* DVB-C */
127 else
128 i2c_addr = priv->cfg.i2c_address; /* DVB-T/T2 */
129
130 /* switch bank if needed */
131 if (bank != priv->bank[i2c]) {
132 ret = cxd2820r_wr_regs_i2c(priv, i2c_addr, 0x00, &bank, 1);
133 if (ret)
134 return ret;
135 priv->bank[i2c] = bank;
136 }
137 return cxd2820r_rd_regs_i2c(priv, i2c_addr, reg, val, len);
138}
139
140/* write single register */
9ac51c5e 141int cxd2820r_wr_reg(struct cxd2820r_priv *priv, u32 reg, u8 val)
27cfc85e
AP		 142{
143 return cxd2820r_wr_regs(priv, reg, &val, 1);
144}
145
146/* read single register */
9ac51c5e 147int cxd2820r_rd_reg(struct cxd2820r_priv *priv, u32 reg, u8 *val)
27cfc85e
AP		 148{
149 return cxd2820r_rd_regs(priv, reg, val, 1);
150}
151
152/* write single register with mask */
9ac51c5e 153int cxd2820r_wr_reg_mask(struct cxd2820r_priv *priv, u32 reg, u8 val,
27cfc85e
AP		 154 u8 mask)
155{
156 int ret;
157 u8 tmp;
158
159 /* no need for read if whole reg is written */
160 if (mask != 0xff) {
161 ret = cxd2820r_rd_reg(priv, reg, &tmp);
162 if (ret)
163 return ret;
164
165 val &= mask;
166 tmp &= ~mask;
167 val |= tmp;
168 }
169
170 return cxd2820r_wr_reg(priv, reg, val);
171}
172
9ac51c5e 173int cxd2820r_gpio(struct dvb_frontend *fe)
27cfc85e
AP		 174{
175 struct cxd2820r_priv *priv = fe->demodulator_priv;
176 int ret, i;
177 u8 *gpio, tmp0, tmp1;
178 dbg("%s: delsys=%d", __func__, fe->dtv_property_cache.delivery_system);
179
180 switch (fe->dtv_property_cache.delivery_system) {
181 case SYS_DVBT:
182 gpio = priv->cfg.gpio_dvbt;
183 break;
184 case SYS_DVBT2:
185 gpio = priv->cfg.gpio_dvbt2;
186 break;
187 case SYS_DVBC_ANNEX_AC:
188 gpio = priv->cfg.gpio_dvbc;
189 break;
190 default:
191 ret = -EINVAL;
192 goto error;
193 }
194
195 /* update GPIOs only when needed */
196 if (!memcmp(gpio, priv->gpio, sizeof(priv->gpio)))
197 return 0;
198
199 tmp0 = 0x00;
200 tmp1 = 0x00;
201 for (i = 0; i < sizeof(priv->gpio); i++) {
202 /* enable / disable */
203 if (gpio[i] & CXD2820R_GPIO_E)
204 tmp0 |= (2 << 6) >> (2 * i);
205 else
206 tmp0 |= (1 << 6) >> (2 * i);
207
208 /* input / output */
209 if (gpio[i] & CXD2820R_GPIO_I)
210 tmp1 |= (1 << (3 + i));
211 else
212 tmp1 |= (0 << (3 + i));
213
214 /* high / low */
215 if (gpio[i] & CXD2820R_GPIO_H)
216 tmp1 |= (1 << (0 + i));
217 else
218 tmp1 |= (0 << (0 + i));
219
220 dbg("%s: GPIO i=%d %02x %02x", __func__, i, tmp0, tmp1);
221 }
222
223 dbg("%s: wr gpio=%02x %02x", __func__, tmp0, tmp1);
224
225 /* write bits [7:2] */
226 ret = cxd2820r_wr_reg_mask(priv, 0x00089, tmp0, 0xfc);
227 if (ret)
228 goto error;
229
230 /* write bits [5:0] */
231 ret = cxd2820r_wr_reg_mask(priv, 0x0008e, tmp1, 0x3f);
232 if (ret)
233 goto error;
234
235 memcpy(priv->gpio, gpio, sizeof(priv->gpio));
236
237 return ret;
238error:
239 dbg("%s: failed:%d", __func__, ret);
240 return ret;
241}
242
27cfc85e 243/* 64 bit div with round closest, like DIV_ROUND_CLOSEST but 64 bit */
9ac51c5e 244u32 cxd2820r_div_u64_round_closest(u64 dividend, u32 divisor)
27cfc85e
AP		 245{
246 return div_u64(dividend + (divisor / 2), divisor);
247}
248
f311f68a 249static int cxd2820r_set_frontend(struct dvb_frontend *fe)
27cfc85e 250{
27cfc85e
AP		 251 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
252 int ret;
27cfc85e 253
14c03862
MA		 254 dbg("%s: delsys=%d", __func__, fe->dtv_property_cache.delivery_system);
255 switch (c->delivery_system) {
256 case SYS_DVBT:
257 ret = cxd2820r_init_t(fe);
258 if (ret < 0)
259 goto err;
f311f68a 260 ret = cxd2820r_set_frontend_t(fe);
14c03862
MA		 261 if (ret < 0)
262 goto err;
263 break;
264 case SYS_DVBT2:
265 ret = cxd2820r_init_t(fe);
266 if (ret < 0)
267 goto err;
f311f68a 268 ret = cxd2820r_set_frontend_t2(fe);
14c03862
MA		 269 if (ret < 0)
270 goto err;
271 break;
f311f68a 272 case SYS_DVBC_ANNEX_A:
14c03862
MA		 273 ret = cxd2820r_init_c(fe);
274 if (ret < 0)
275 goto err;
f311f68a 276 ret = cxd2820r_set_frontend_c(fe);
14c03862
MA		 277 if (ret < 0)
278 goto err;
279 break;
280 default:
281 dbg("%s: error state=%d", __func__, fe->dtv_property_cache.delivery_system);
282 ret = -EINVAL;
283 break;
27cfc85e 284 }
14c03862 285err:
27cfc85e
AP		 286 return ret;
287}
27cfc85e
AP		 288static int cxd2820r_read_status(struct dvb_frontend *fe, fe_status_t *status)
289{
27cfc85e 290 int ret;
27cfc85e 291
14c03862
MA		 292 dbg("%s: delsys=%d", __func__, fe->dtv_property_cache.delivery_system);
293 switch (fe->dtv_property_cache.delivery_system) {
294 case SYS_DVBT:
295 ret = cxd2820r_read_status_t(fe, status);
296 break;
297 case SYS_DVBT2:
298 ret = cxd2820r_read_status_t2(fe, status);
299 break;
f311f68a 300 case SYS_DVBC_ANNEX_A:
27cfc85e 301 ret = cxd2820r_read_status_c(fe, status);
14c03862
MA		 302 break;
303 default:
304 ret = -EINVAL;
305 break;
27cfc85e 306 }
27cfc85e
AP		 307 return ret;
308}
309
7c61d80a 310static int cxd2820r_get_frontend(struct dvb_frontend *fe)
27cfc85e 311{
27cfc85e 312 int ret;
27cfc85e 313
14c03862
MA		 314 dbg("%s: delsys=%d", __func__, fe->dtv_property_cache.delivery_system);
315 switch (fe->dtv_property_cache.delivery_system) {
316 case SYS_DVBT:
f311f68a 317 ret = cxd2820r_get_frontend_t(fe);
14c03862
MA		 318 break;
319 case SYS_DVBT2:
f311f68a 320 ret = cxd2820r_get_frontend_t2(fe);
14c03862 321 break;
f311f68a
MCC		 322 case SYS_DVBC_ANNEX_A:
323 ret = cxd2820r_get_frontend_c(fe);
14c03862
MA		 324 break;
325 default:
326 ret = -EINVAL;
327 break;
27cfc85e 328 }
27cfc85e
AP		 329 return ret;
330}
331
332static int cxd2820r_read_ber(struct dvb_frontend *fe, u32 *ber)
333{
27cfc85e 334 int ret;
27cfc85e 335
14c03862
MA		 336 dbg("%s: delsys=%d", __func__, fe->dtv_property_cache.delivery_system);
337 switch (fe->dtv_property_cache.delivery_system) {
338 case SYS_DVBT:
339 ret = cxd2820r_read_ber_t(fe, ber);
340 break;
341 case SYS_DVBT2:
342 ret = cxd2820r_read_ber_t2(fe, ber);
343 break;
f311f68a 344 case SYS_DVBC_ANNEX_A:
27cfc85e 345 ret = cxd2820r_read_ber_c(fe, ber);
14c03862
MA		 346 break;
347 default:
348 ret = -EINVAL;
349 break;
27cfc85e 350 }
27cfc85e
AP		 351 return ret;
352}
353
354static int cxd2820r_read_signal_strength(struct dvb_frontend *fe, u16 *strength)
355{
27cfc85e 356 int ret;
27cfc85e 357
14c03862
MA		 358 dbg("%s: delsys=%d", __func__, fe->dtv_property_cache.delivery_system);
359 switch (fe->dtv_property_cache.delivery_system) {
360 case SYS_DVBT:
361 ret = cxd2820r_read_signal_strength_t(fe, strength);
362 break;
363 case SYS_DVBT2:
364 ret = cxd2820r_read_signal_strength_t2(fe, strength);
365 break;
f311f68a 366 case SYS_DVBC_ANNEX_A:
27cfc85e 367 ret = cxd2820r_read_signal_strength_c(fe, strength);
14c03862
MA		 368 break;
369 default:
370 ret = -EINVAL;
371 break;
27cfc85e 372 }
27cfc85e
AP		 373 return ret;
374}
375
376static int cxd2820r_read_snr(struct dvb_frontend *fe, u16 *snr)
377{
27cfc85e 378 int ret;
27cfc85e 379
14c03862
MA		 380 dbg("%s: delsys=%d", __func__, fe->dtv_property_cache.delivery_system);
381 switch (fe->dtv_property_cache.delivery_system) {
382 case SYS_DVBT:
383 ret = cxd2820r_read_snr_t(fe, snr);
384 break;
385 case SYS_DVBT2:
386 ret = cxd2820r_read_snr_t2(fe, snr);
387 break;
f311f68a 388 case SYS_DVBC_ANNEX_A:
27cfc85e 389 ret = cxd2820r_read_snr_c(fe, snr);
14c03862
MA		 390 break;
391 default:
392 ret = -EINVAL;
393 break;
27cfc85e 394 }
27cfc85e
AP		 395 return ret;
396}
397
398static int cxd2820r_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
399{
27cfc85e 400 int ret;
27cfc85e 401
14c03862
MA		 402 dbg("%s: delsys=%d", __func__, fe->dtv_property_cache.delivery_system);
403 switch (fe->dtv_property_cache.delivery_system) {
404 case SYS_DVBT:
405 ret = cxd2820r_read_ucblocks_t(fe, ucblocks);
406 break;
407 case SYS_DVBT2:
408 ret = cxd2820r_read_ucblocks_t2(fe, ucblocks);
409 break;
f311f68a 410 case SYS_DVBC_ANNEX_A:
27cfc85e 411 ret = cxd2820r_read_ucblocks_c(fe, ucblocks);
14c03862
MA		 412 break;
413 default:
414 ret = -EINVAL;
415 break;
27cfc85e 416 }
27cfc85e
AP		 417 return ret;
418}
419
420static int cxd2820r_init(struct dvb_frontend *fe)
421{
14c03862 422 return 0;
27cfc85e
AP		 423}
424
425static int cxd2820r_sleep(struct dvb_frontend *fe)
426{
27cfc85e 427 int ret;
27cfc85e 428
14c03862
MA		 429 dbg("%s: delsys=%d", __func__, fe->dtv_property_cache.delivery_system);
430 switch (fe->dtv_property_cache.delivery_system) {
431 case SYS_DVBT:
432 ret = cxd2820r_sleep_t(fe);
433 break;
434 case SYS_DVBT2:
435 ret = cxd2820r_sleep_t2(fe);
436 break;
f311f68a 437 case SYS_DVBC_ANNEX_A:
27cfc85e 438 ret = cxd2820r_sleep_c(fe);
14c03862
MA		 439 break;
440 default:
441 ret = -EINVAL;
442 break;
27cfc85e 443 }
27cfc85e
AP		 444 return ret;
445}
446
447static int cxd2820r_get_tune_settings(struct dvb_frontend *fe,
14c03862 448 struct dvb_frontend_tune_settings *s)
27cfc85e 449{
e47b78f0 450 int ret;
27cfc85e 451
14c03862
MA		 452 dbg("%s: delsys=%d", __func__, fe->dtv_property_cache.delivery_system);
453 switch (fe->dtv_property_cache.delivery_system) {
454 case SYS_DVBT:
455 ret = cxd2820r_get_tune_settings_t(fe, s);
456 break;
457 case SYS_DVBT2:
458 ret = cxd2820r_get_tune_settings_t2(fe, s);
459 break;
f311f68a 460 case SYS_DVBC_ANNEX_A:
27cfc85e 461 ret = cxd2820r_get_tune_settings_c(fe, s);
14c03862
MA		 462 break;
463 default:
464 ret = -EINVAL;
465 break;
27cfc85e 466 }
27cfc85e
AP		 467 return ret;
468}
469
41da5320 470static enum dvbfe_search cxd2820r_search(struct dvb_frontend *fe)
e47b78f0
AP		 471{
472 struct cxd2820r_priv *priv = fe->demodulator_priv;
473 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
474 int ret, i;
475 fe_status_t status = 0;
476 dbg("%s: delsys=%d", __func__, fe->dtv_property_cache.delivery_system);
477
478 /* switch between DVB-T and DVB-T2 when tune fails */
f311f68a 479 if (priv->last_tune_failed && (priv->delivery_system != SYS_DVBC_ANNEX_A)) {
e47b78f0
AP		 480 if (priv->delivery_system == SYS_DVBT)
481 c->delivery_system = SYS_DVBT2;
482 else
483 c->delivery_system = SYS_DVBT;
484 }
485
486 /* set frontend */
f311f68a 487 ret = cxd2820r_set_frontend(fe);
e47b78f0
AP		 488 if (ret)
489 goto error;
490
491
492 /* frontend lock wait loop count */
493 switch (priv->delivery_system) {
494 case SYS_DVBT:
495 i = 20;
496 break;
497 case SYS_DVBT2:
498 i = 40;
499 break;
500 case SYS_UNDEFINED:
501 default:
502 i = 0;
503 break;
504 }
505
506 /* wait frontend lock */
507 for (; i > 0; i--) {
508 dbg("%s: LOOP=%d", __func__, i);
509 msleep(50);
510 ret = cxd2820r_read_status(fe, &status);
511 if (ret)
512 goto error;
513
514 if (status & FE_HAS_SIGNAL)
515 break;
516 }
517
518 /* check if we have a valid signal */
519 if (status) {
520 priv->last_tune_failed = 0;
521 return DVBFE_ALGO_SEARCH_SUCCESS;
522 } else {
523 priv->last_tune_failed = 1;
524 return DVBFE_ALGO_SEARCH_AGAIN;
525 }
526
527error:
528 dbg("%s: failed:%d", __func__, ret);
529 return DVBFE_ALGO_SEARCH_ERROR;
530}
531
532static int cxd2820r_get_frontend_algo(struct dvb_frontend *fe)
533{
534 return DVBFE_ALGO_CUSTOM;
535}
536
27cfc85e
AP		 537static void cxd2820r_release(struct dvb_frontend *fe)
538{
539 struct cxd2820r_priv *priv = fe->demodulator_priv;
540 dbg("%s", __func__);
541
14c03862 542 kfree(priv);
27cfc85e
AP		 543 return;
544}
545
0db4bf42 546static int cxd2820r_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
27cfc85e
AP		 547{
548 struct cxd2820r_priv *priv = fe->demodulator_priv;
0db4bf42
SK		 549 dbg("%s: %d", __func__, enable);
550
551 /* Bit 0 of reg 0xdb in bank 0x00 controls I2C repeater */
552 return cxd2820r_wr_reg_mask(priv, 0xdb, enable ? 1 : 0, 0x1);
27cfc85e 553}
27cfc85e 554
14c03862 555static const struct dvb_frontend_ops cxd2820r_ops = {
f311f68a 556 .delsys = { SYS_DVBT, SYS_DVBT2, SYS_DVBC_ANNEX_A },
14c03862
MA		 557 /* default: DVB-T/T2 */
558 .info = {
559 .name = "Sony CXD2820R (DVB-T/T2)",
14c03862
MA		 560
561 .caps = FE_CAN_FEC_1_2 |
562 FE_CAN_FEC_2_3 |
563 FE_CAN_FEC_3_4 |
564 FE_CAN_FEC_5_6 |
565 FE_CAN_FEC_7_8 |
566 FE_CAN_FEC_AUTO |
567 FE_CAN_QPSK |
568 FE_CAN_QAM_16 |
569 FE_CAN_QAM_64 |
570 FE_CAN_QAM_256 |
571 FE_CAN_QAM_AUTO |
572 FE_CAN_TRANSMISSION_MODE_AUTO |
573 FE_CAN_GUARD_INTERVAL_AUTO |
574 FE_CAN_HIERARCHY_AUTO |
575 FE_CAN_MUTE_TS |
576 FE_CAN_2G_MODULATION
577 },
27cfc85e 578
14c03862
MA		 579 .release = cxd2820r_release,
580 .init = cxd2820r_init,
581 .sleep = cxd2820r_sleep,
27cfc85e 582
14c03862
MA		 583 .get_tune_settings = cxd2820r_get_tune_settings,
584 .i2c_gate_ctrl = cxd2820r_i2c_gate_ctrl,
27cfc85e 585
f311f68a 586 .get_frontend = cxd2820r_get_frontend,
27cfc85e 587
14c03862
MA		 588 .get_frontend_algo = cxd2820r_get_frontend_algo,
589 .search = cxd2820r_search,
27cfc85e 590
14c03862
MA		 591 .read_status = cxd2820r_read_status,
592 .read_snr = cxd2820r_read_snr,
593 .read_ber = cxd2820r_read_ber,
594 .read_ucblocks = cxd2820r_read_ucblocks,
595 .read_signal_strength = cxd2820r_read_signal_strength,
14c03862 596};
27cfc85e 597
14c03862
MA		 598struct dvb_frontend *cxd2820r_attach(const struct cxd2820r_config *cfg,
599 struct i2c_adapter *i2c,
600 struct dvb_frontend *fe)
601{
602 struct cxd2820r_priv *priv = NULL;
603 int ret;
604 u8 tmp;
605
606 priv = kzalloc(sizeof (struct cxd2820r_priv), GFP_KERNEL);
607 if (!priv)
608 goto error;
27cfc85e 609
14c03862
MA		 610 priv->i2c = i2c;
611 memcpy(&priv->cfg, cfg, sizeof (struct cxd2820r_config));
612
613 priv->bank[0] = priv->bank[1] = 0xff;
614 ret = cxd2820r_rd_reg(priv, 0x000fd, &tmp);
615 dbg("%s: chip id=%02x", __func__, tmp);
616 if (ret || tmp != 0xe1)
617 goto error;
618
619 memcpy(&priv->fe.ops, &cxd2820r_ops, sizeof (struct dvb_frontend_ops));
620 priv->fe.demodulator_priv = priv;
621 return &priv->fe;
27cfc85e
AP		 622error:
623 kfree(priv);
624 return NULL;
625}
626EXPORT_SYMBOL(cxd2820r_attach);
627
27cfc85e
AP		 628MODULE_AUTHOR("Antti Palosaari <crope@iki.fi>");
629MODULE_DESCRIPTION("Sony CXD2820R demodulator driver");
630MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)