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af4e067e LO |
1 | /* Common header-file of the Linux driver for the Afatech 9005 |
2 | * USB1.1 DVB-T receiver. | |
3 | * | |
4 | * Copyright (C) 2007 Luca Olivetti (luca@ventoso.org) | |
5 | * | |
6 | * Thanks to Afatech who kindly provided information. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
21 | * | |
22 | * see Documentation/dvb/README.dvb-usb for more information | |
23 | */ | |
24 | #ifndef _DVB_USB_AF9005_H_ | |
25 | #define _DVB_USB_AF9005_H_ | |
26 | ||
27 | #define DVB_USB_LOG_PREFIX "af9005" | |
28 | #include "dvb-usb.h" | |
29 | ||
30 | extern int dvb_usb_af9005_debug; | |
31 | #define deb_info(args...) dprintk(dvb_usb_af9005_debug,0x01,args) | |
32 | #define deb_xfer(args...) dprintk(dvb_usb_af9005_debug,0x02,args) | |
33 | #define deb_rc(args...) dprintk(dvb_usb_af9005_debug,0x04,args) | |
34 | #define deb_reg(args...) dprintk(dvb_usb_af9005_debug,0x08,args) | |
35 | #define deb_i2c(args...) dprintk(dvb_usb_af9005_debug,0x10,args) | |
36 | #define deb_fw(args...) dprintk(dvb_usb_af9005_debug,0x20,args) | |
37 | ||
38 | extern int dvb_usb_af9005_led; | |
39 | ||
40 | /* firmware */ | |
41 | #define FW_BULKOUT_SIZE 250 | |
42 | enum { | |
43 | FW_CONFIG, | |
44 | FW_CONFIRM, | |
45 | FW_BOOT | |
46 | }; | |
47 | ||
48 | /* af9005 commands */ | |
49 | #define AF9005_OFDM_REG 0 | |
50 | #define AF9005_TUNER_REG 1 | |
51 | ||
52 | #define AF9005_REGISTER_RW 0x20 | |
53 | #define AF9005_REGISTER_RW_ACK 0x21 | |
54 | ||
55 | #define AF9005_CMD_OFDM_REG 0x00 | |
56 | #define AF9005_CMD_TUNER 0x80 | |
57 | #define AF9005_CMD_BURST 0x02 | |
58 | #define AF9005_CMD_AUTOINC 0x04 | |
59 | #define AF9005_CMD_READ 0x00 | |
60 | #define AF9005_CMD_WRITE 0x01 | |
61 | ||
62 | /* af9005 registers */ | |
63 | #define APO_REG_RESET 0xAEFF | |
64 | ||
65 | #define APO_REG_I2C_RW_CAN_TUNER 0xF000 | |
66 | #define APO_REG_I2C_RW_SILICON_TUNER 0xF001 | |
67 | #define APO_REG_GPIO_RW_SILICON_TUNER 0xFFFE /* also for OFSM */ | |
68 | #define APO_REG_TRIGGER_OFSM 0xFFFF /* also for OFSM */ | |
69 | ||
70 | /*********************************************************************** | |
71 | * Apollo Registers from VLSI * | |
72 | ***********************************************************************/ | |
73 | #define xd_p_reg_aagc_inverted_agc 0xA000 | |
74 | #define reg_aagc_inverted_agc_pos 0 | |
75 | #define reg_aagc_inverted_agc_len 1 | |
76 | #define reg_aagc_inverted_agc_lsb 0 | |
77 | #define xd_p_reg_aagc_sign_only 0xA000 | |
78 | #define reg_aagc_sign_only_pos 1 | |
79 | #define reg_aagc_sign_only_len 1 | |
80 | #define reg_aagc_sign_only_lsb 0 | |
81 | #define xd_p_reg_aagc_slow_adc_en 0xA000 | |
82 | #define reg_aagc_slow_adc_en_pos 2 | |
83 | #define reg_aagc_slow_adc_en_len 1 | |
84 | #define reg_aagc_slow_adc_en_lsb 0 | |
85 | #define xd_p_reg_aagc_slow_adc_scale 0xA000 | |
86 | #define reg_aagc_slow_adc_scale_pos 3 | |
87 | #define reg_aagc_slow_adc_scale_len 5 | |
88 | #define reg_aagc_slow_adc_scale_lsb 0 | |
89 | #define xd_p_reg_aagc_check_slow_adc_lock 0xA001 | |
90 | #define reg_aagc_check_slow_adc_lock_pos 0 | |
91 | #define reg_aagc_check_slow_adc_lock_len 1 | |
92 | #define reg_aagc_check_slow_adc_lock_lsb 0 | |
93 | #define xd_p_reg_aagc_init_control 0xA001 | |
94 | #define reg_aagc_init_control_pos 1 | |
95 | #define reg_aagc_init_control_len 1 | |
96 | #define reg_aagc_init_control_lsb 0 | |
97 | #define xd_p_reg_aagc_total_gain_sel 0xA001 | |
98 | #define reg_aagc_total_gain_sel_pos 2 | |
99 | #define reg_aagc_total_gain_sel_len 2 | |
100 | #define reg_aagc_total_gain_sel_lsb 0 | |
101 | #define xd_p_reg_aagc_out_inv 0xA001 | |
102 | #define reg_aagc_out_inv_pos 5 | |
103 | #define reg_aagc_out_inv_len 1 | |
104 | #define reg_aagc_out_inv_lsb 0 | |
105 | #define xd_p_reg_aagc_int_en 0xA001 | |
106 | #define reg_aagc_int_en_pos 6 | |
107 | #define reg_aagc_int_en_len 1 | |
108 | #define reg_aagc_int_en_lsb 0 | |
109 | #define xd_p_reg_aagc_lock_change_flag 0xA001 | |
110 | #define reg_aagc_lock_change_flag_pos 7 | |
111 | #define reg_aagc_lock_change_flag_len 1 | |
112 | #define reg_aagc_lock_change_flag_lsb 0 | |
113 | #define xd_p_reg_aagc_rf_loop_bw_scale_acquire 0xA002 | |
114 | #define reg_aagc_rf_loop_bw_scale_acquire_pos 0 | |
115 | #define reg_aagc_rf_loop_bw_scale_acquire_len 5 | |
116 | #define reg_aagc_rf_loop_bw_scale_acquire_lsb 0 | |
117 | #define xd_p_reg_aagc_rf_loop_bw_scale_track 0xA003 | |
118 | #define reg_aagc_rf_loop_bw_scale_track_pos 0 | |
119 | #define reg_aagc_rf_loop_bw_scale_track_len 5 | |
120 | #define reg_aagc_rf_loop_bw_scale_track_lsb 0 | |
121 | #define xd_p_reg_aagc_if_loop_bw_scale_acquire 0xA004 | |
122 | #define reg_aagc_if_loop_bw_scale_acquire_pos 0 | |
123 | #define reg_aagc_if_loop_bw_scale_acquire_len 5 | |
124 | #define reg_aagc_if_loop_bw_scale_acquire_lsb 0 | |
125 | #define xd_p_reg_aagc_if_loop_bw_scale_track 0xA005 | |
126 | #define reg_aagc_if_loop_bw_scale_track_pos 0 | |
127 | #define reg_aagc_if_loop_bw_scale_track_len 5 | |
128 | #define reg_aagc_if_loop_bw_scale_track_lsb 0 | |
129 | #define xd_p_reg_aagc_max_rf_agc_7_0 0xA006 | |
130 | #define reg_aagc_max_rf_agc_7_0_pos 0 | |
131 | #define reg_aagc_max_rf_agc_7_0_len 8 | |
132 | #define reg_aagc_max_rf_agc_7_0_lsb 0 | |
133 | #define xd_p_reg_aagc_max_rf_agc_9_8 0xA007 | |
134 | #define reg_aagc_max_rf_agc_9_8_pos 0 | |
135 | #define reg_aagc_max_rf_agc_9_8_len 2 | |
136 | #define reg_aagc_max_rf_agc_9_8_lsb 8 | |
137 | #define xd_p_reg_aagc_min_rf_agc_7_0 0xA008 | |
138 | #define reg_aagc_min_rf_agc_7_0_pos 0 | |
139 | #define reg_aagc_min_rf_agc_7_0_len 8 | |
140 | #define reg_aagc_min_rf_agc_7_0_lsb 0 | |
141 | #define xd_p_reg_aagc_min_rf_agc_9_8 0xA009 | |
142 | #define reg_aagc_min_rf_agc_9_8_pos 0 | |
143 | #define reg_aagc_min_rf_agc_9_8_len 2 | |
144 | #define reg_aagc_min_rf_agc_9_8_lsb 8 | |
145 | #define xd_p_reg_aagc_max_if_agc_7_0 0xA00A | |
146 | #define reg_aagc_max_if_agc_7_0_pos 0 | |
147 | #define reg_aagc_max_if_agc_7_0_len 8 | |
148 | #define reg_aagc_max_if_agc_7_0_lsb 0 | |
149 | #define xd_p_reg_aagc_max_if_agc_9_8 0xA00B | |
150 | #define reg_aagc_max_if_agc_9_8_pos 0 | |
151 | #define reg_aagc_max_if_agc_9_8_len 2 | |
152 | #define reg_aagc_max_if_agc_9_8_lsb 8 | |
153 | #define xd_p_reg_aagc_min_if_agc_7_0 0xA00C | |
154 | #define reg_aagc_min_if_agc_7_0_pos 0 | |
155 | #define reg_aagc_min_if_agc_7_0_len 8 | |
156 | #define reg_aagc_min_if_agc_7_0_lsb 0 | |
157 | #define xd_p_reg_aagc_min_if_agc_9_8 0xA00D | |
158 | #define reg_aagc_min_if_agc_9_8_pos 0 | |
159 | #define reg_aagc_min_if_agc_9_8_len 2 | |
160 | #define reg_aagc_min_if_agc_9_8_lsb 8 | |
161 | #define xd_p_reg_aagc_lock_sample_scale 0xA00E | |
162 | #define reg_aagc_lock_sample_scale_pos 0 | |
163 | #define reg_aagc_lock_sample_scale_len 5 | |
164 | #define reg_aagc_lock_sample_scale_lsb 0 | |
165 | #define xd_p_reg_aagc_rf_agc_lock_scale_acquire 0xA00F | |
166 | #define reg_aagc_rf_agc_lock_scale_acquire_pos 0 | |
167 | #define reg_aagc_rf_agc_lock_scale_acquire_len 3 | |
168 | #define reg_aagc_rf_agc_lock_scale_acquire_lsb 0 | |
169 | #define xd_p_reg_aagc_rf_agc_lock_scale_track 0xA00F | |
170 | #define reg_aagc_rf_agc_lock_scale_track_pos 3 | |
171 | #define reg_aagc_rf_agc_lock_scale_track_len 3 | |
172 | #define reg_aagc_rf_agc_lock_scale_track_lsb 0 | |
173 | #define xd_p_reg_aagc_if_agc_lock_scale_acquire 0xA010 | |
174 | #define reg_aagc_if_agc_lock_scale_acquire_pos 0 | |
175 | #define reg_aagc_if_agc_lock_scale_acquire_len 3 | |
176 | #define reg_aagc_if_agc_lock_scale_acquire_lsb 0 | |
177 | #define xd_p_reg_aagc_if_agc_lock_scale_track 0xA010 | |
178 | #define reg_aagc_if_agc_lock_scale_track_pos 3 | |
179 | #define reg_aagc_if_agc_lock_scale_track_len 3 | |
180 | #define reg_aagc_if_agc_lock_scale_track_lsb 0 | |
181 | #define xd_p_reg_aagc_rf_top_numerator_7_0 0xA011 | |
182 | #define reg_aagc_rf_top_numerator_7_0_pos 0 | |
183 | #define reg_aagc_rf_top_numerator_7_0_len 8 | |
184 | #define reg_aagc_rf_top_numerator_7_0_lsb 0 | |
185 | #define xd_p_reg_aagc_rf_top_numerator_9_8 0xA012 | |
186 | #define reg_aagc_rf_top_numerator_9_8_pos 0 | |
187 | #define reg_aagc_rf_top_numerator_9_8_len 2 | |
188 | #define reg_aagc_rf_top_numerator_9_8_lsb 8 | |
189 | #define xd_p_reg_aagc_if_top_numerator_7_0 0xA013 | |
190 | #define reg_aagc_if_top_numerator_7_0_pos 0 | |
191 | #define reg_aagc_if_top_numerator_7_0_len 8 | |
192 | #define reg_aagc_if_top_numerator_7_0_lsb 0 | |
193 | #define xd_p_reg_aagc_if_top_numerator_9_8 0xA014 | |
194 | #define reg_aagc_if_top_numerator_9_8_pos 0 | |
195 | #define reg_aagc_if_top_numerator_9_8_len 2 | |
196 | #define reg_aagc_if_top_numerator_9_8_lsb 8 | |
197 | #define xd_p_reg_aagc_adc_out_desired_7_0 0xA015 | |
198 | #define reg_aagc_adc_out_desired_7_0_pos 0 | |
199 | #define reg_aagc_adc_out_desired_7_0_len 8 | |
200 | #define reg_aagc_adc_out_desired_7_0_lsb 0 | |
201 | #define xd_p_reg_aagc_adc_out_desired_8 0xA016 | |
202 | #define reg_aagc_adc_out_desired_8_pos 0 | |
203 | #define reg_aagc_adc_out_desired_8_len 1 | |
204 | #define reg_aagc_adc_out_desired_8_lsb 0 | |
205 | #define xd_p_reg_aagc_fixed_gain 0xA016 | |
206 | #define reg_aagc_fixed_gain_pos 3 | |
207 | #define reg_aagc_fixed_gain_len 1 | |
208 | #define reg_aagc_fixed_gain_lsb 0 | |
209 | #define xd_p_reg_aagc_lock_count_th 0xA016 | |
210 | #define reg_aagc_lock_count_th_pos 4 | |
211 | #define reg_aagc_lock_count_th_len 4 | |
212 | #define reg_aagc_lock_count_th_lsb 0 | |
213 | #define xd_p_reg_aagc_fixed_rf_agc_control_7_0 0xA017 | |
214 | #define reg_aagc_fixed_rf_agc_control_7_0_pos 0 | |
215 | #define reg_aagc_fixed_rf_agc_control_7_0_len 8 | |
216 | #define reg_aagc_fixed_rf_agc_control_7_0_lsb 0 | |
217 | #define xd_p_reg_aagc_fixed_rf_agc_control_15_8 0xA018 | |
218 | #define reg_aagc_fixed_rf_agc_control_15_8_pos 0 | |
219 | #define reg_aagc_fixed_rf_agc_control_15_8_len 8 | |
220 | #define reg_aagc_fixed_rf_agc_control_15_8_lsb 8 | |
221 | #define xd_p_reg_aagc_fixed_rf_agc_control_23_16 0xA019 | |
222 | #define reg_aagc_fixed_rf_agc_control_23_16_pos 0 | |
223 | #define reg_aagc_fixed_rf_agc_control_23_16_len 8 | |
224 | #define reg_aagc_fixed_rf_agc_control_23_16_lsb 16 | |
225 | #define xd_p_reg_aagc_fixed_rf_agc_control_30_24 0xA01A | |
226 | #define reg_aagc_fixed_rf_agc_control_30_24_pos 0 | |
227 | #define reg_aagc_fixed_rf_agc_control_30_24_len 7 | |
228 | #define reg_aagc_fixed_rf_agc_control_30_24_lsb 24 | |
229 | #define xd_p_reg_aagc_fixed_if_agc_control_7_0 0xA01B | |
230 | #define reg_aagc_fixed_if_agc_control_7_0_pos 0 | |
231 | #define reg_aagc_fixed_if_agc_control_7_0_len 8 | |
232 | #define reg_aagc_fixed_if_agc_control_7_0_lsb 0 | |
233 | #define xd_p_reg_aagc_fixed_if_agc_control_15_8 0xA01C | |
234 | #define reg_aagc_fixed_if_agc_control_15_8_pos 0 | |
235 | #define reg_aagc_fixed_if_agc_control_15_8_len 8 | |
236 | #define reg_aagc_fixed_if_agc_control_15_8_lsb 8 | |
237 | #define xd_p_reg_aagc_fixed_if_agc_control_23_16 0xA01D | |
238 | #define reg_aagc_fixed_if_agc_control_23_16_pos 0 | |
239 | #define reg_aagc_fixed_if_agc_control_23_16_len 8 | |
240 | #define reg_aagc_fixed_if_agc_control_23_16_lsb 16 | |
241 | #define xd_p_reg_aagc_fixed_if_agc_control_30_24 0xA01E | |
242 | #define reg_aagc_fixed_if_agc_control_30_24_pos 0 | |
243 | #define reg_aagc_fixed_if_agc_control_30_24_len 7 | |
244 | #define reg_aagc_fixed_if_agc_control_30_24_lsb 24 | |
245 | #define xd_p_reg_aagc_rf_agc_unlock_numerator 0xA01F | |
246 | #define reg_aagc_rf_agc_unlock_numerator_pos 0 | |
247 | #define reg_aagc_rf_agc_unlock_numerator_len 6 | |
248 | #define reg_aagc_rf_agc_unlock_numerator_lsb 0 | |
249 | #define xd_p_reg_aagc_if_agc_unlock_numerator 0xA020 | |
250 | #define reg_aagc_if_agc_unlock_numerator_pos 0 | |
251 | #define reg_aagc_if_agc_unlock_numerator_len 6 | |
252 | #define reg_aagc_if_agc_unlock_numerator_lsb 0 | |
253 | #define xd_p_reg_unplug_th 0xA021 | |
254 | #define reg_unplug_th_pos 0 | |
255 | #define reg_unplug_th_len 8 | |
256 | #define reg_aagc_rf_x0_lsb 0 | |
257 | #define xd_p_reg_weak_signal_rfagc_thr 0xA022 | |
258 | #define reg_weak_signal_rfagc_thr_pos 0 | |
259 | #define reg_weak_signal_rfagc_thr_len 8 | |
260 | #define reg_weak_signal_rfagc_thr_lsb 0 | |
261 | #define xd_p_reg_unplug_rf_gain_th 0xA023 | |
262 | #define reg_unplug_rf_gain_th_pos 0 | |
263 | #define reg_unplug_rf_gain_th_len 8 | |
264 | #define reg_unplug_rf_gain_th_lsb 0 | |
265 | #define xd_p_reg_unplug_dtop_rf_gain_th 0xA024 | |
266 | #define reg_unplug_dtop_rf_gain_th_pos 0 | |
267 | #define reg_unplug_dtop_rf_gain_th_len 8 | |
268 | #define reg_unplug_dtop_rf_gain_th_lsb 0 | |
269 | #define xd_p_reg_unplug_dtop_if_gain_th 0xA025 | |
270 | #define reg_unplug_dtop_if_gain_th_pos 0 | |
271 | #define reg_unplug_dtop_if_gain_th_len 8 | |
272 | #define reg_unplug_dtop_if_gain_th_lsb 0 | |
273 | #define xd_p_reg_top_recover_at_unplug_en 0xA026 | |
274 | #define reg_top_recover_at_unplug_en_pos 0 | |
275 | #define reg_top_recover_at_unplug_en_len 1 | |
276 | #define reg_top_recover_at_unplug_en_lsb 0 | |
277 | #define xd_p_reg_aagc_rf_x6 0xA027 | |
278 | #define reg_aagc_rf_x6_pos 0 | |
279 | #define reg_aagc_rf_x6_len 8 | |
280 | #define reg_aagc_rf_x6_lsb 0 | |
281 | #define xd_p_reg_aagc_rf_x7 0xA028 | |
282 | #define reg_aagc_rf_x7_pos 0 | |
283 | #define reg_aagc_rf_x7_len 8 | |
284 | #define reg_aagc_rf_x7_lsb 0 | |
285 | #define xd_p_reg_aagc_rf_x8 0xA029 | |
286 | #define reg_aagc_rf_x8_pos 0 | |
287 | #define reg_aagc_rf_x8_len 8 | |
288 | #define reg_aagc_rf_x8_lsb 0 | |
289 | #define xd_p_reg_aagc_rf_x9 0xA02A | |
290 | #define reg_aagc_rf_x9_pos 0 | |
291 | #define reg_aagc_rf_x9_len 8 | |
292 | #define reg_aagc_rf_x9_lsb 0 | |
293 | #define xd_p_reg_aagc_rf_x10 0xA02B | |
294 | #define reg_aagc_rf_x10_pos 0 | |
295 | #define reg_aagc_rf_x10_len 8 | |
296 | #define reg_aagc_rf_x10_lsb 0 | |
297 | #define xd_p_reg_aagc_rf_x11 0xA02C | |
298 | #define reg_aagc_rf_x11_pos 0 | |
299 | #define reg_aagc_rf_x11_len 8 | |
300 | #define reg_aagc_rf_x11_lsb 0 | |
301 | #define xd_p_reg_aagc_rf_x12 0xA02D | |
302 | #define reg_aagc_rf_x12_pos 0 | |
303 | #define reg_aagc_rf_x12_len 8 | |
304 | #define reg_aagc_rf_x12_lsb 0 | |
305 | #define xd_p_reg_aagc_rf_x13 0xA02E | |
306 | #define reg_aagc_rf_x13_pos 0 | |
307 | #define reg_aagc_rf_x13_len 8 | |
308 | #define reg_aagc_rf_x13_lsb 0 | |
309 | #define xd_p_reg_aagc_if_x0 0xA02F | |
310 | #define reg_aagc_if_x0_pos 0 | |
311 | #define reg_aagc_if_x0_len 8 | |
312 | #define reg_aagc_if_x0_lsb 0 | |
313 | #define xd_p_reg_aagc_if_x1 0xA030 | |
314 | #define reg_aagc_if_x1_pos 0 | |
315 | #define reg_aagc_if_x1_len 8 | |
316 | #define reg_aagc_if_x1_lsb 0 | |
317 | #define xd_p_reg_aagc_if_x2 0xA031 | |
318 | #define reg_aagc_if_x2_pos 0 | |
319 | #define reg_aagc_if_x2_len 8 | |
320 | #define reg_aagc_if_x2_lsb 0 | |
321 | #define xd_p_reg_aagc_if_x3 0xA032 | |
322 | #define reg_aagc_if_x3_pos 0 | |
323 | #define reg_aagc_if_x3_len 8 | |
324 | #define reg_aagc_if_x3_lsb 0 | |
325 | #define xd_p_reg_aagc_if_x4 0xA033 | |
326 | #define reg_aagc_if_x4_pos 0 | |
327 | #define reg_aagc_if_x4_len 8 | |
328 | #define reg_aagc_if_x4_lsb 0 | |
329 | #define xd_p_reg_aagc_if_x5 0xA034 | |
330 | #define reg_aagc_if_x5_pos 0 | |
331 | #define reg_aagc_if_x5_len 8 | |
332 | #define reg_aagc_if_x5_lsb 0 | |
333 | #define xd_p_reg_aagc_if_x6 0xA035 | |
334 | #define reg_aagc_if_x6_pos 0 | |
335 | #define reg_aagc_if_x6_len 8 | |
336 | #define reg_aagc_if_x6_lsb 0 | |
337 | #define xd_p_reg_aagc_if_x7 0xA036 | |
338 | #define reg_aagc_if_x7_pos 0 | |
339 | #define reg_aagc_if_x7_len 8 | |
340 | #define reg_aagc_if_x7_lsb 0 | |
341 | #define xd_p_reg_aagc_if_x8 0xA037 | |
342 | #define reg_aagc_if_x8_pos 0 | |
343 | #define reg_aagc_if_x8_len 8 | |
344 | #define reg_aagc_if_x8_lsb 0 | |
345 | #define xd_p_reg_aagc_if_x9 0xA038 | |
346 | #define reg_aagc_if_x9_pos 0 | |
347 | #define reg_aagc_if_x9_len 8 | |
348 | #define reg_aagc_if_x9_lsb 0 | |
349 | #define xd_p_reg_aagc_if_x10 0xA039 | |
350 | #define reg_aagc_if_x10_pos 0 | |
351 | #define reg_aagc_if_x10_len 8 | |
352 | #define reg_aagc_if_x10_lsb 0 | |
353 | #define xd_p_reg_aagc_if_x11 0xA03A | |
354 | #define reg_aagc_if_x11_pos 0 | |
355 | #define reg_aagc_if_x11_len 8 | |
356 | #define reg_aagc_if_x11_lsb 0 | |
357 | #define xd_p_reg_aagc_if_x12 0xA03B | |
358 | #define reg_aagc_if_x12_pos 0 | |
359 | #define reg_aagc_if_x12_len 8 | |
360 | #define reg_aagc_if_x12_lsb 0 | |
361 | #define xd_p_reg_aagc_if_x13 0xA03C | |
362 | #define reg_aagc_if_x13_pos 0 | |
363 | #define reg_aagc_if_x13_len 8 | |
364 | #define reg_aagc_if_x13_lsb 0 | |
365 | #define xd_p_reg_aagc_min_rf_ctl_8bit_for_dca 0xA03D | |
366 | #define reg_aagc_min_rf_ctl_8bit_for_dca_pos 0 | |
367 | #define reg_aagc_min_rf_ctl_8bit_for_dca_len 8 | |
368 | #define reg_aagc_min_rf_ctl_8bit_for_dca_lsb 0 | |
369 | #define xd_p_reg_aagc_min_if_ctl_8bit_for_dca 0xA03E | |
370 | #define reg_aagc_min_if_ctl_8bit_for_dca_pos 0 | |
371 | #define reg_aagc_min_if_ctl_8bit_for_dca_len 8 | |
372 | #define reg_aagc_min_if_ctl_8bit_for_dca_lsb 0 | |
373 | #define xd_r_reg_aagc_total_gain_7_0 0xA070 | |
374 | #define reg_aagc_total_gain_7_0_pos 0 | |
375 | #define reg_aagc_total_gain_7_0_len 8 | |
376 | #define reg_aagc_total_gain_7_0_lsb 0 | |
377 | #define xd_r_reg_aagc_total_gain_15_8 0xA071 | |
378 | #define reg_aagc_total_gain_15_8_pos 0 | |
379 | #define reg_aagc_total_gain_15_8_len 8 | |
380 | #define reg_aagc_total_gain_15_8_lsb 8 | |
381 | #define xd_p_reg_aagc_in_sat_cnt_7_0 0xA074 | |
382 | #define reg_aagc_in_sat_cnt_7_0_pos 0 | |
383 | #define reg_aagc_in_sat_cnt_7_0_len 8 | |
384 | #define reg_aagc_in_sat_cnt_7_0_lsb 0 | |
385 | #define xd_p_reg_aagc_in_sat_cnt_15_8 0xA075 | |
386 | #define reg_aagc_in_sat_cnt_15_8_pos 0 | |
387 | #define reg_aagc_in_sat_cnt_15_8_len 8 | |
388 | #define reg_aagc_in_sat_cnt_15_8_lsb 8 | |
389 | #define xd_p_reg_aagc_in_sat_cnt_23_16 0xA076 | |
390 | #define reg_aagc_in_sat_cnt_23_16_pos 0 | |
391 | #define reg_aagc_in_sat_cnt_23_16_len 8 | |
392 | #define reg_aagc_in_sat_cnt_23_16_lsb 16 | |
393 | #define xd_p_reg_aagc_in_sat_cnt_31_24 0xA077 | |
394 | #define reg_aagc_in_sat_cnt_31_24_pos 0 | |
395 | #define reg_aagc_in_sat_cnt_31_24_len 8 | |
396 | #define reg_aagc_in_sat_cnt_31_24_lsb 24 | |
397 | #define xd_r_reg_aagc_digital_rf_volt_7_0 0xA078 | |
398 | #define reg_aagc_digital_rf_volt_7_0_pos 0 | |
399 | #define reg_aagc_digital_rf_volt_7_0_len 8 | |
400 | #define reg_aagc_digital_rf_volt_7_0_lsb 0 | |
401 | #define xd_r_reg_aagc_digital_rf_volt_9_8 0xA079 | |
402 | #define reg_aagc_digital_rf_volt_9_8_pos 0 | |
403 | #define reg_aagc_digital_rf_volt_9_8_len 2 | |
404 | #define reg_aagc_digital_rf_volt_9_8_lsb 8 | |
405 | #define xd_r_reg_aagc_digital_if_volt_7_0 0xA07A | |
406 | #define reg_aagc_digital_if_volt_7_0_pos 0 | |
407 | #define reg_aagc_digital_if_volt_7_0_len 8 | |
408 | #define reg_aagc_digital_if_volt_7_0_lsb 0 | |
409 | #define xd_r_reg_aagc_digital_if_volt_9_8 0xA07B | |
410 | #define reg_aagc_digital_if_volt_9_8_pos 0 | |
411 | #define reg_aagc_digital_if_volt_9_8_len 2 | |
412 | #define reg_aagc_digital_if_volt_9_8_lsb 8 | |
413 | #define xd_r_reg_aagc_rf_gain 0xA07C | |
414 | #define reg_aagc_rf_gain_pos 0 | |
415 | #define reg_aagc_rf_gain_len 8 | |
416 | #define reg_aagc_rf_gain_lsb 0 | |
417 | #define xd_r_reg_aagc_if_gain 0xA07D | |
418 | #define reg_aagc_if_gain_pos 0 | |
419 | #define reg_aagc_if_gain_len 8 | |
420 | #define reg_aagc_if_gain_lsb 0 | |
421 | #define xd_p_tinr_imp_indicator 0xA080 | |
422 | #define tinr_imp_indicator_pos 0 | |
423 | #define tinr_imp_indicator_len 2 | |
424 | #define tinr_imp_indicator_lsb 0 | |
425 | #define xd_p_reg_tinr_fifo_size 0xA080 | |
426 | #define reg_tinr_fifo_size_pos 2 | |
427 | #define reg_tinr_fifo_size_len 5 | |
428 | #define reg_tinr_fifo_size_lsb 0 | |
429 | #define xd_p_reg_tinr_saturation_cnt_th 0xA081 | |
430 | #define reg_tinr_saturation_cnt_th_pos 0 | |
431 | #define reg_tinr_saturation_cnt_th_len 4 | |
432 | #define reg_tinr_saturation_cnt_th_lsb 0 | |
433 | #define xd_p_reg_tinr_saturation_th_3_0 0xA081 | |
434 | #define reg_tinr_saturation_th_3_0_pos 4 | |
435 | #define reg_tinr_saturation_th_3_0_len 4 | |
436 | #define reg_tinr_saturation_th_3_0_lsb 0 | |
437 | #define xd_p_reg_tinr_saturation_th_8_4 0xA082 | |
438 | #define reg_tinr_saturation_th_8_4_pos 0 | |
439 | #define reg_tinr_saturation_th_8_4_len 5 | |
440 | #define reg_tinr_saturation_th_8_4_lsb 4 | |
441 | #define xd_p_reg_tinr_imp_duration_th_2k_7_0 0xA083 | |
442 | #define reg_tinr_imp_duration_th_2k_7_0_pos 0 | |
443 | #define reg_tinr_imp_duration_th_2k_7_0_len 8 | |
444 | #define reg_tinr_imp_duration_th_2k_7_0_lsb 0 | |
445 | #define xd_p_reg_tinr_imp_duration_th_2k_8 0xA084 | |
446 | #define reg_tinr_imp_duration_th_2k_8_pos 0 | |
447 | #define reg_tinr_imp_duration_th_2k_8_len 1 | |
448 | #define reg_tinr_imp_duration_th_2k_8_lsb 0 | |
449 | #define xd_p_reg_tinr_imp_duration_th_8k_7_0 0xA085 | |
450 | #define reg_tinr_imp_duration_th_8k_7_0_pos 0 | |
451 | #define reg_tinr_imp_duration_th_8k_7_0_len 8 | |
452 | #define reg_tinr_imp_duration_th_8k_7_0_lsb 0 | |
453 | #define xd_p_reg_tinr_imp_duration_th_8k_10_8 0xA086 | |
454 | #define reg_tinr_imp_duration_th_8k_10_8_pos 0 | |
455 | #define reg_tinr_imp_duration_th_8k_10_8_len 3 | |
456 | #define reg_tinr_imp_duration_th_8k_10_8_lsb 8 | |
457 | #define xd_p_reg_tinr_freq_ratio_6m_7_0 0xA087 | |
458 | #define reg_tinr_freq_ratio_6m_7_0_pos 0 | |
459 | #define reg_tinr_freq_ratio_6m_7_0_len 8 | |
460 | #define reg_tinr_freq_ratio_6m_7_0_lsb 0 | |
461 | #define xd_p_reg_tinr_freq_ratio_6m_12_8 0xA088 | |
462 | #define reg_tinr_freq_ratio_6m_12_8_pos 0 | |
463 | #define reg_tinr_freq_ratio_6m_12_8_len 5 | |
464 | #define reg_tinr_freq_ratio_6m_12_8_lsb 8 | |
465 | #define xd_p_reg_tinr_freq_ratio_7m_7_0 0xA089 | |
466 | #define reg_tinr_freq_ratio_7m_7_0_pos 0 | |
467 | #define reg_tinr_freq_ratio_7m_7_0_len 8 | |
468 | #define reg_tinr_freq_ratio_7m_7_0_lsb 0 | |
469 | #define xd_p_reg_tinr_freq_ratio_7m_12_8 0xA08A | |
470 | #define reg_tinr_freq_ratio_7m_12_8_pos 0 | |
471 | #define reg_tinr_freq_ratio_7m_12_8_len 5 | |
472 | #define reg_tinr_freq_ratio_7m_12_8_lsb 8 | |
473 | #define xd_p_reg_tinr_freq_ratio_8m_7_0 0xA08B | |
474 | #define reg_tinr_freq_ratio_8m_7_0_pos 0 | |
475 | #define reg_tinr_freq_ratio_8m_7_0_len 8 | |
476 | #define reg_tinr_freq_ratio_8m_7_0_lsb 0 | |
477 | #define xd_p_reg_tinr_freq_ratio_8m_12_8 0xA08C | |
478 | #define reg_tinr_freq_ratio_8m_12_8_pos 0 | |
479 | #define reg_tinr_freq_ratio_8m_12_8_len 5 | |
480 | #define reg_tinr_freq_ratio_8m_12_8_lsb 8 | |
481 | #define xd_p_reg_tinr_imp_duration_th_low_2k 0xA08D | |
482 | #define reg_tinr_imp_duration_th_low_2k_pos 0 | |
483 | #define reg_tinr_imp_duration_th_low_2k_len 8 | |
484 | #define reg_tinr_imp_duration_th_low_2k_lsb 0 | |
485 | #define xd_p_reg_tinr_imp_duration_th_low_8k 0xA08E | |
486 | #define reg_tinr_imp_duration_th_low_8k_pos 0 | |
487 | #define reg_tinr_imp_duration_th_low_8k_len 8 | |
488 | #define reg_tinr_imp_duration_th_low_8k_lsb 0 | |
489 | #define xd_r_reg_tinr_counter_7_0 0xA090 | |
490 | #define reg_tinr_counter_7_0_pos 0 | |
491 | #define reg_tinr_counter_7_0_len 8 | |
492 | #define reg_tinr_counter_7_0_lsb 0 | |
493 | #define xd_r_reg_tinr_counter_15_8 0xA091 | |
494 | #define reg_tinr_counter_15_8_pos 0 | |
495 | #define reg_tinr_counter_15_8_len 8 | |
496 | #define reg_tinr_counter_15_8_lsb 8 | |
497 | #define xd_p_reg_tinr_adative_tinr_en 0xA093 | |
498 | #define reg_tinr_adative_tinr_en_pos 0 | |
499 | #define reg_tinr_adative_tinr_en_len 1 | |
500 | #define reg_tinr_adative_tinr_en_lsb 0 | |
501 | #define xd_p_reg_tinr_peak_fifo_size 0xA093 | |
502 | #define reg_tinr_peak_fifo_size_pos 1 | |
503 | #define reg_tinr_peak_fifo_size_len 5 | |
504 | #define reg_tinr_peak_fifo_size_lsb 0 | |
505 | #define xd_p_reg_tinr_counter_rst 0xA093 | |
506 | #define reg_tinr_counter_rst_pos 6 | |
507 | #define reg_tinr_counter_rst_len 1 | |
508 | #define reg_tinr_counter_rst_lsb 0 | |
509 | #define xd_p_reg_tinr_search_period_7_0 0xA094 | |
510 | #define reg_tinr_search_period_7_0_pos 0 | |
511 | #define reg_tinr_search_period_7_0_len 8 | |
512 | #define reg_tinr_search_period_7_0_lsb 0 | |
513 | #define xd_p_reg_tinr_search_period_15_8 0xA095 | |
514 | #define reg_tinr_search_period_15_8_pos 0 | |
515 | #define reg_tinr_search_period_15_8_len 8 | |
516 | #define reg_tinr_search_period_15_8_lsb 8 | |
517 | #define xd_p_reg_ccifs_fcw_7_0 0xA0A0 | |
518 | #define reg_ccifs_fcw_7_0_pos 0 | |
519 | #define reg_ccifs_fcw_7_0_len 8 | |
520 | #define reg_ccifs_fcw_7_0_lsb 0 | |
521 | #define xd_p_reg_ccifs_fcw_12_8 0xA0A1 | |
522 | #define reg_ccifs_fcw_12_8_pos 0 | |
523 | #define reg_ccifs_fcw_12_8_len 5 | |
524 | #define reg_ccifs_fcw_12_8_lsb 8 | |
525 | #define xd_p_reg_ccifs_spec_inv 0xA0A1 | |
526 | #define reg_ccifs_spec_inv_pos 5 | |
527 | #define reg_ccifs_spec_inv_len 1 | |
528 | #define reg_ccifs_spec_inv_lsb 0 | |
529 | #define xd_p_reg_gp_trigger 0xA0A2 | |
530 | #define reg_gp_trigger_pos 0 | |
531 | #define reg_gp_trigger_len 1 | |
532 | #define reg_gp_trigger_lsb 0 | |
533 | #define xd_p_reg_trigger_sel 0xA0A2 | |
534 | #define reg_trigger_sel_pos 1 | |
535 | #define reg_trigger_sel_len 2 | |
536 | #define reg_trigger_sel_lsb 0 | |
537 | #define xd_p_reg_debug_ofdm 0xA0A2 | |
538 | #define reg_debug_ofdm_pos 3 | |
539 | #define reg_debug_ofdm_len 2 | |
540 | #define reg_debug_ofdm_lsb 0 | |
541 | #define xd_p_reg_trigger_module_sel 0xA0A3 | |
542 | #define reg_trigger_module_sel_pos 0 | |
543 | #define reg_trigger_module_sel_len 6 | |
544 | #define reg_trigger_module_sel_lsb 0 | |
545 | #define xd_p_reg_trigger_set_sel 0xA0A4 | |
546 | #define reg_trigger_set_sel_pos 0 | |
547 | #define reg_trigger_set_sel_len 6 | |
548 | #define reg_trigger_set_sel_lsb 0 | |
549 | #define xd_p_reg_fw_int_mask_n 0xA0A4 | |
550 | #define reg_fw_int_mask_n_pos 6 | |
551 | #define reg_fw_int_mask_n_len 1 | |
552 | #define reg_fw_int_mask_n_lsb 0 | |
553 | #define xd_p_reg_debug_group 0xA0A5 | |
554 | #define reg_debug_group_pos 0 | |
555 | #define reg_debug_group_len 4 | |
556 | #define reg_debug_group_lsb 0 | |
557 | #define xd_p_reg_odbg_clk_sel 0xA0A5 | |
558 | #define reg_odbg_clk_sel_pos 4 | |
559 | #define reg_odbg_clk_sel_len 2 | |
560 | #define reg_odbg_clk_sel_lsb 0 | |
561 | #define xd_p_reg_ccif_sc 0xA0C0 | |
562 | #define reg_ccif_sc_pos 0 | |
563 | #define reg_ccif_sc_len 4 | |
564 | #define reg_ccif_sc_lsb 0 | |
565 | #define xd_r_reg_ccif_saturate 0xA0C1 | |
566 | #define reg_ccif_saturate_pos 0 | |
567 | #define reg_ccif_saturate_len 2 | |
568 | #define reg_ccif_saturate_lsb 0 | |
569 | #define xd_r_reg_antif_saturate 0xA0C1 | |
570 | #define reg_antif_saturate_pos 2 | |
571 | #define reg_antif_saturate_len 4 | |
572 | #define reg_antif_saturate_lsb 0 | |
573 | #define xd_r_reg_acif_saturate 0xA0C2 | |
574 | #define reg_acif_saturate_pos 0 | |
575 | #define reg_acif_saturate_len 8 | |
576 | #define reg_acif_saturate_lsb 0 | |
577 | #define xd_p_reg_tmr_timer0_threshold_7_0 0xA0C8 | |
578 | #define reg_tmr_timer0_threshold_7_0_pos 0 | |
579 | #define reg_tmr_timer0_threshold_7_0_len 8 | |
580 | #define reg_tmr_timer0_threshold_7_0_lsb 0 | |
581 | #define xd_p_reg_tmr_timer0_threshold_15_8 0xA0C9 | |
582 | #define reg_tmr_timer0_threshold_15_8_pos 0 | |
583 | #define reg_tmr_timer0_threshold_15_8_len 8 | |
584 | #define reg_tmr_timer0_threshold_15_8_lsb 8 | |
585 | #define xd_p_reg_tmr_timer0_enable 0xA0CA | |
586 | #define reg_tmr_timer0_enable_pos 0 | |
587 | #define reg_tmr_timer0_enable_len 1 | |
588 | #define reg_tmr_timer0_enable_lsb 0 | |
589 | #define xd_p_reg_tmr_timer0_clk_sel 0xA0CA | |
590 | #define reg_tmr_timer0_clk_sel_pos 1 | |
591 | #define reg_tmr_timer0_clk_sel_len 1 | |
592 | #define reg_tmr_timer0_clk_sel_lsb 0 | |
593 | #define xd_p_reg_tmr_timer0_int 0xA0CA | |
594 | #define reg_tmr_timer0_int_pos 2 | |
595 | #define reg_tmr_timer0_int_len 1 | |
596 | #define reg_tmr_timer0_int_lsb 0 | |
597 | #define xd_p_reg_tmr_timer0_rst 0xA0CA | |
598 | #define reg_tmr_timer0_rst_pos 3 | |
599 | #define reg_tmr_timer0_rst_len 1 | |
600 | #define reg_tmr_timer0_rst_lsb 0 | |
601 | #define xd_r_reg_tmr_timer0_count_7_0 0xA0CB | |
602 | #define reg_tmr_timer0_count_7_0_pos 0 | |
603 | #define reg_tmr_timer0_count_7_0_len 8 | |
604 | #define reg_tmr_timer0_count_7_0_lsb 0 | |
605 | #define xd_r_reg_tmr_timer0_count_15_8 0xA0CC | |
606 | #define reg_tmr_timer0_count_15_8_pos 0 | |
607 | #define reg_tmr_timer0_count_15_8_len 8 | |
608 | #define reg_tmr_timer0_count_15_8_lsb 8 | |
609 | #define xd_p_reg_suspend 0xA0CD | |
610 | #define reg_suspend_pos 0 | |
611 | #define reg_suspend_len 1 | |
612 | #define reg_suspend_lsb 0 | |
613 | #define xd_p_reg_suspend_rdy 0xA0CD | |
614 | #define reg_suspend_rdy_pos 1 | |
615 | #define reg_suspend_rdy_len 1 | |
616 | #define reg_suspend_rdy_lsb 0 | |
617 | #define xd_p_reg_resume 0xA0CD | |
618 | #define reg_resume_pos 2 | |
619 | #define reg_resume_len 1 | |
620 | #define reg_resume_lsb 0 | |
621 | #define xd_p_reg_resume_rdy 0xA0CD | |
622 | #define reg_resume_rdy_pos 3 | |
623 | #define reg_resume_rdy_len 1 | |
624 | #define reg_resume_rdy_lsb 0 | |
625 | #define xd_p_reg_fmf 0xA0CE | |
626 | #define reg_fmf_pos 0 | |
627 | #define reg_fmf_len 8 | |
628 | #define reg_fmf_lsb 0 | |
629 | #define xd_p_ccid_accumulate_num_2k_7_0 0xA100 | |
630 | #define ccid_accumulate_num_2k_7_0_pos 0 | |
631 | #define ccid_accumulate_num_2k_7_0_len 8 | |
632 | #define ccid_accumulate_num_2k_7_0_lsb 0 | |
633 | #define xd_p_ccid_accumulate_num_2k_12_8 0xA101 | |
634 | #define ccid_accumulate_num_2k_12_8_pos 0 | |
635 | #define ccid_accumulate_num_2k_12_8_len 5 | |
636 | #define ccid_accumulate_num_2k_12_8_lsb 8 | |
637 | #define xd_p_ccid_accumulate_num_8k_7_0 0xA102 | |
638 | #define ccid_accumulate_num_8k_7_0_pos 0 | |
639 | #define ccid_accumulate_num_8k_7_0_len 8 | |
640 | #define ccid_accumulate_num_8k_7_0_lsb 0 | |
641 | #define xd_p_ccid_accumulate_num_8k_14_8 0xA103 | |
642 | #define ccid_accumulate_num_8k_14_8_pos 0 | |
643 | #define ccid_accumulate_num_8k_14_8_len 7 | |
644 | #define ccid_accumulate_num_8k_14_8_lsb 8 | |
645 | #define xd_p_ccid_desired_level_0 0xA103 | |
646 | #define ccid_desired_level_0_pos 7 | |
647 | #define ccid_desired_level_0_len 1 | |
648 | #define ccid_desired_level_0_lsb 0 | |
649 | #define xd_p_ccid_desired_level_8_1 0xA104 | |
650 | #define ccid_desired_level_8_1_pos 0 | |
651 | #define ccid_desired_level_8_1_len 8 | |
652 | #define ccid_desired_level_8_1_lsb 1 | |
653 | #define xd_p_ccid_apply_delay 0xA105 | |
654 | #define ccid_apply_delay_pos 0 | |
655 | #define ccid_apply_delay_len 7 | |
656 | #define ccid_apply_delay_lsb 0 | |
657 | #define xd_p_ccid_CCID_Threshold1 0xA106 | |
658 | #define ccid_CCID_Threshold1_pos 0 | |
659 | #define ccid_CCID_Threshold1_len 8 | |
660 | #define ccid_CCID_Threshold1_lsb 0 | |
661 | #define xd_p_ccid_CCID_Threshold2 0xA107 | |
662 | #define ccid_CCID_Threshold2_pos 0 | |
663 | #define ccid_CCID_Threshold2_len 8 | |
664 | #define ccid_CCID_Threshold2_lsb 0 | |
665 | #define xd_p_reg_ccid_gain_scale 0xA108 | |
666 | #define reg_ccid_gain_scale_pos 0 | |
667 | #define reg_ccid_gain_scale_len 4 | |
668 | #define reg_ccid_gain_scale_lsb 0 | |
669 | #define xd_p_reg_ccid2_passband_gain_set 0xA108 | |
670 | #define reg_ccid2_passband_gain_set_pos 4 | |
671 | #define reg_ccid2_passband_gain_set_len 4 | |
672 | #define reg_ccid2_passband_gain_set_lsb 0 | |
673 | #define xd_r_ccid_multiplier_7_0 0xA109 | |
674 | #define ccid_multiplier_7_0_pos 0 | |
675 | #define ccid_multiplier_7_0_len 8 | |
676 | #define ccid_multiplier_7_0_lsb 0 | |
677 | #define xd_r_ccid_multiplier_15_8 0xA10A | |
678 | #define ccid_multiplier_15_8_pos 0 | |
679 | #define ccid_multiplier_15_8_len 8 | |
680 | #define ccid_multiplier_15_8_lsb 8 | |
681 | #define xd_r_ccid_right_shift_bits 0xA10B | |
682 | #define ccid_right_shift_bits_pos 0 | |
683 | #define ccid_right_shift_bits_len 4 | |
684 | #define ccid_right_shift_bits_lsb 0 | |
685 | #define xd_r_reg_ccid_sx_7_0 0xA10C | |
686 | #define reg_ccid_sx_7_0_pos 0 | |
687 | #define reg_ccid_sx_7_0_len 8 | |
688 | #define reg_ccid_sx_7_0_lsb 0 | |
689 | #define xd_r_reg_ccid_sx_15_8 0xA10D | |
690 | #define reg_ccid_sx_15_8_pos 0 | |
691 | #define reg_ccid_sx_15_8_len 8 | |
692 | #define reg_ccid_sx_15_8_lsb 8 | |
693 | #define xd_r_reg_ccid_sx_21_16 0xA10E | |
694 | #define reg_ccid_sx_21_16_pos 0 | |
695 | #define reg_ccid_sx_21_16_len 6 | |
696 | #define reg_ccid_sx_21_16_lsb 16 | |
697 | #define xd_r_reg_ccid_sy_7_0 0xA110 | |
698 | #define reg_ccid_sy_7_0_pos 0 | |
699 | #define reg_ccid_sy_7_0_len 8 | |
700 | #define reg_ccid_sy_7_0_lsb 0 | |
701 | #define xd_r_reg_ccid_sy_15_8 0xA111 | |
702 | #define reg_ccid_sy_15_8_pos 0 | |
703 | #define reg_ccid_sy_15_8_len 8 | |
704 | #define reg_ccid_sy_15_8_lsb 8 | |
705 | #define xd_r_reg_ccid_sy_23_16 0xA112 | |
706 | #define reg_ccid_sy_23_16_pos 0 | |
707 | #define reg_ccid_sy_23_16_len 8 | |
708 | #define reg_ccid_sy_23_16_lsb 16 | |
709 | #define xd_r_reg_ccid2_sz_7_0 0xA114 | |
710 | #define reg_ccid2_sz_7_0_pos 0 | |
711 | #define reg_ccid2_sz_7_0_len 8 | |
712 | #define reg_ccid2_sz_7_0_lsb 0 | |
713 | #define xd_r_reg_ccid2_sz_15_8 0xA115 | |
714 | #define reg_ccid2_sz_15_8_pos 0 | |
715 | #define reg_ccid2_sz_15_8_len 8 | |
716 | #define reg_ccid2_sz_15_8_lsb 8 | |
717 | #define xd_r_reg_ccid2_sz_23_16 0xA116 | |
718 | #define reg_ccid2_sz_23_16_pos 0 | |
719 | #define reg_ccid2_sz_23_16_len 8 | |
720 | #define reg_ccid2_sz_23_16_lsb 16 | |
721 | #define xd_r_reg_ccid2_sz_25_24 0xA117 | |
722 | #define reg_ccid2_sz_25_24_pos 0 | |
723 | #define reg_ccid2_sz_25_24_len 2 | |
724 | #define reg_ccid2_sz_25_24_lsb 24 | |
725 | #define xd_r_reg_ccid2_sy_7_0 0xA118 | |
726 | #define reg_ccid2_sy_7_0_pos 0 | |
727 | #define reg_ccid2_sy_7_0_len 8 | |
728 | #define reg_ccid2_sy_7_0_lsb 0 | |
729 | #define xd_r_reg_ccid2_sy_15_8 0xA119 | |
730 | #define reg_ccid2_sy_15_8_pos 0 | |
731 | #define reg_ccid2_sy_15_8_len 8 | |
732 | #define reg_ccid2_sy_15_8_lsb 8 | |
733 | #define xd_r_reg_ccid2_sy_23_16 0xA11A | |
734 | #define reg_ccid2_sy_23_16_pos 0 | |
735 | #define reg_ccid2_sy_23_16_len 8 | |
736 | #define reg_ccid2_sy_23_16_lsb 16 | |
737 | #define xd_r_reg_ccid2_sy_25_24 0xA11B | |
738 | #define reg_ccid2_sy_25_24_pos 0 | |
739 | #define reg_ccid2_sy_25_24_len 2 | |
740 | #define reg_ccid2_sy_25_24_lsb 24 | |
741 | #define xd_p_dagc1_accumulate_num_2k_7_0 0xA120 | |
742 | #define dagc1_accumulate_num_2k_7_0_pos 0 | |
743 | #define dagc1_accumulate_num_2k_7_0_len 8 | |
744 | #define dagc1_accumulate_num_2k_7_0_lsb 0 | |
745 | #define xd_p_dagc1_accumulate_num_2k_12_8 0xA121 | |
746 | #define dagc1_accumulate_num_2k_12_8_pos 0 | |
747 | #define dagc1_accumulate_num_2k_12_8_len 5 | |
748 | #define dagc1_accumulate_num_2k_12_8_lsb 8 | |
749 | #define xd_p_dagc1_accumulate_num_8k_7_0 0xA122 | |
750 | #define dagc1_accumulate_num_8k_7_0_pos 0 | |
751 | #define dagc1_accumulate_num_8k_7_0_len 8 | |
752 | #define dagc1_accumulate_num_8k_7_0_lsb 0 | |
753 | #define xd_p_dagc1_accumulate_num_8k_14_8 0xA123 | |
754 | #define dagc1_accumulate_num_8k_14_8_pos 0 | |
755 | #define dagc1_accumulate_num_8k_14_8_len 7 | |
756 | #define dagc1_accumulate_num_8k_14_8_lsb 8 | |
757 | #define xd_p_dagc1_desired_level_0 0xA123 | |
758 | #define dagc1_desired_level_0_pos 7 | |
759 | #define dagc1_desired_level_0_len 1 | |
760 | #define dagc1_desired_level_0_lsb 0 | |
761 | #define xd_p_dagc1_desired_level_8_1 0xA124 | |
762 | #define dagc1_desired_level_8_1_pos 0 | |
763 | #define dagc1_desired_level_8_1_len 8 | |
764 | #define dagc1_desired_level_8_1_lsb 1 | |
765 | #define xd_p_dagc1_apply_delay 0xA125 | |
766 | #define dagc1_apply_delay_pos 0 | |
767 | #define dagc1_apply_delay_len 7 | |
768 | #define dagc1_apply_delay_lsb 0 | |
769 | #define xd_p_dagc1_bypass_scale_ctl 0xA126 | |
770 | #define dagc1_bypass_scale_ctl_pos 0 | |
771 | #define dagc1_bypass_scale_ctl_len 2 | |
772 | #define dagc1_bypass_scale_ctl_lsb 0 | |
773 | #define xd_p_reg_dagc1_in_sat_cnt_7_0 0xA127 | |
774 | #define reg_dagc1_in_sat_cnt_7_0_pos 0 | |
775 | #define reg_dagc1_in_sat_cnt_7_0_len 8 | |
776 | #define reg_dagc1_in_sat_cnt_7_0_lsb 0 | |
777 | #define xd_p_reg_dagc1_in_sat_cnt_15_8 0xA128 | |
778 | #define reg_dagc1_in_sat_cnt_15_8_pos 0 | |
779 | #define reg_dagc1_in_sat_cnt_15_8_len 8 | |
780 | #define reg_dagc1_in_sat_cnt_15_8_lsb 8 | |
781 | #define xd_p_reg_dagc1_in_sat_cnt_23_16 0xA129 | |
782 | #define reg_dagc1_in_sat_cnt_23_16_pos 0 | |
783 | #define reg_dagc1_in_sat_cnt_23_16_len 8 | |
784 | #define reg_dagc1_in_sat_cnt_23_16_lsb 16 | |
785 | #define xd_p_reg_dagc1_in_sat_cnt_31_24 0xA12A | |
786 | #define reg_dagc1_in_sat_cnt_31_24_pos 0 | |
787 | #define reg_dagc1_in_sat_cnt_31_24_len 8 | |
788 | #define reg_dagc1_in_sat_cnt_31_24_lsb 24 | |
789 | #define xd_p_reg_dagc1_out_sat_cnt_7_0 0xA12B | |
790 | #define reg_dagc1_out_sat_cnt_7_0_pos 0 | |
791 | #define reg_dagc1_out_sat_cnt_7_0_len 8 | |
792 | #define reg_dagc1_out_sat_cnt_7_0_lsb 0 | |
793 | #define xd_p_reg_dagc1_out_sat_cnt_15_8 0xA12C | |
794 | #define reg_dagc1_out_sat_cnt_15_8_pos 0 | |
795 | #define reg_dagc1_out_sat_cnt_15_8_len 8 | |
796 | #define reg_dagc1_out_sat_cnt_15_8_lsb 8 | |
797 | #define xd_p_reg_dagc1_out_sat_cnt_23_16 0xA12D | |
798 | #define reg_dagc1_out_sat_cnt_23_16_pos 0 | |
799 | #define reg_dagc1_out_sat_cnt_23_16_len 8 | |
800 | #define reg_dagc1_out_sat_cnt_23_16_lsb 16 | |
801 | #define xd_p_reg_dagc1_out_sat_cnt_31_24 0xA12E | |
802 | #define reg_dagc1_out_sat_cnt_31_24_pos 0 | |
803 | #define reg_dagc1_out_sat_cnt_31_24_len 8 | |
804 | #define reg_dagc1_out_sat_cnt_31_24_lsb 24 | |
805 | #define xd_r_dagc1_multiplier_7_0 0xA136 | |
806 | #define dagc1_multiplier_7_0_pos 0 | |
807 | #define dagc1_multiplier_7_0_len 8 | |
808 | #define dagc1_multiplier_7_0_lsb 0 | |
809 | #define xd_r_dagc1_multiplier_15_8 0xA137 | |
810 | #define dagc1_multiplier_15_8_pos 0 | |
811 | #define dagc1_multiplier_15_8_len 8 | |
812 | #define dagc1_multiplier_15_8_lsb 8 | |
813 | #define xd_r_dagc1_right_shift_bits 0xA138 | |
814 | #define dagc1_right_shift_bits_pos 0 | |
815 | #define dagc1_right_shift_bits_len 4 | |
816 | #define dagc1_right_shift_bits_lsb 0 | |
817 | #define xd_p_reg_bfs_fcw_7_0 0xA140 | |
818 | #define reg_bfs_fcw_7_0_pos 0 | |
819 | #define reg_bfs_fcw_7_0_len 8 | |
820 | #define reg_bfs_fcw_7_0_lsb 0 | |
821 | #define xd_p_reg_bfs_fcw_15_8 0xA141 | |
822 | #define reg_bfs_fcw_15_8_pos 0 | |
823 | #define reg_bfs_fcw_15_8_len 8 | |
824 | #define reg_bfs_fcw_15_8_lsb 8 | |
825 | #define xd_p_reg_bfs_fcw_22_16 0xA142 | |
826 | #define reg_bfs_fcw_22_16_pos 0 | |
827 | #define reg_bfs_fcw_22_16_len 7 | |
828 | #define reg_bfs_fcw_22_16_lsb 16 | |
829 | #define xd_p_reg_antif_sf_7_0 0xA144 | |
830 | #define reg_antif_sf_7_0_pos 0 | |
831 | #define reg_antif_sf_7_0_len 8 | |
832 | #define reg_antif_sf_7_0_lsb 0 | |
833 | #define xd_p_reg_antif_sf_11_8 0xA145 | |
834 | #define reg_antif_sf_11_8_pos 0 | |
835 | #define reg_antif_sf_11_8_len 4 | |
836 | #define reg_antif_sf_11_8_lsb 8 | |
837 | #define xd_r_bfs_fcw_q_7_0 0xA150 | |
838 | #define bfs_fcw_q_7_0_pos 0 | |
839 | #define bfs_fcw_q_7_0_len 8 | |
840 | #define bfs_fcw_q_7_0_lsb 0 | |
841 | #define xd_r_bfs_fcw_q_15_8 0xA151 | |
842 | #define bfs_fcw_q_15_8_pos 0 | |
843 | #define bfs_fcw_q_15_8_len 8 | |
844 | #define bfs_fcw_q_15_8_lsb 8 | |
845 | #define xd_r_bfs_fcw_q_22_16 0xA152 | |
846 | #define bfs_fcw_q_22_16_pos 0 | |
847 | #define bfs_fcw_q_22_16_len 7 | |
848 | #define bfs_fcw_q_22_16_lsb 16 | |
849 | #define xd_p_reg_dca_enu 0xA160 | |
850 | #define reg_dca_enu_pos 0 | |
851 | #define reg_dca_enu_len 1 | |
852 | #define reg_dca_enu_lsb 0 | |
853 | #define xd_p_reg_dca_enl 0xA160 | |
854 | #define reg_dca_enl_pos 1 | |
855 | #define reg_dca_enl_len 1 | |
856 | #define reg_dca_enl_lsb 0 | |
857 | #define xd_p_reg_dca_lower_chip 0xA160 | |
858 | #define reg_dca_lower_chip_pos 2 | |
859 | #define reg_dca_lower_chip_len 1 | |
860 | #define reg_dca_lower_chip_lsb 0 | |
861 | #define xd_p_reg_dca_upper_chip 0xA160 | |
862 | #define reg_dca_upper_chip_pos 3 | |
863 | #define reg_dca_upper_chip_len 1 | |
864 | #define reg_dca_upper_chip_lsb 0 | |
865 | #define xd_p_reg_dca_platch 0xA160 | |
866 | #define reg_dca_platch_pos 4 | |
867 | #define reg_dca_platch_len 1 | |
868 | #define reg_dca_platch_lsb 0 | |
869 | #define xd_p_reg_dca_th 0xA161 | |
870 | #define reg_dca_th_pos 0 | |
871 | #define reg_dca_th_len 5 | |
872 | #define reg_dca_th_lsb 0 | |
873 | #define xd_p_reg_dca_scale 0xA162 | |
874 | #define reg_dca_scale_pos 0 | |
875 | #define reg_dca_scale_len 4 | |
876 | #define reg_dca_scale_lsb 0 | |
877 | #define xd_p_reg_dca_tone_7_0 0xA163 | |
878 | #define reg_dca_tone_7_0_pos 0 | |
879 | #define reg_dca_tone_7_0_len 8 | |
880 | #define reg_dca_tone_7_0_lsb 0 | |
881 | #define xd_p_reg_dca_tone_12_8 0xA164 | |
882 | #define reg_dca_tone_12_8_pos 0 | |
883 | #define reg_dca_tone_12_8_len 5 | |
884 | #define reg_dca_tone_12_8_lsb 8 | |
885 | #define xd_p_reg_dca_time_7_0 0xA165 | |
886 | #define reg_dca_time_7_0_pos 0 | |
887 | #define reg_dca_time_7_0_len 8 | |
888 | #define reg_dca_time_7_0_lsb 0 | |
889 | #define xd_p_reg_dca_time_15_8 0xA166 | |
890 | #define reg_dca_time_15_8_pos 0 | |
891 | #define reg_dca_time_15_8_len 8 | |
892 | #define reg_dca_time_15_8_lsb 8 | |
893 | #define xd_r_dcasm 0xA167 | |
894 | #define dcasm_pos 0 | |
895 | #define dcasm_len 3 | |
896 | #define dcasm_lsb 0 | |
897 | #define xd_p_reg_qnt_valuew_7_0 0xA168 | |
898 | #define reg_qnt_valuew_7_0_pos 0 | |
899 | #define reg_qnt_valuew_7_0_len 8 | |
900 | #define reg_qnt_valuew_7_0_lsb 0 | |
901 | #define xd_p_reg_qnt_valuew_10_8 0xA169 | |
902 | #define reg_qnt_valuew_10_8_pos 0 | |
903 | #define reg_qnt_valuew_10_8_len 3 | |
904 | #define reg_qnt_valuew_10_8_lsb 8 | |
905 | #define xd_p_dca_sbx_gain_diff_7_0 0xA16A | |
906 | #define dca_sbx_gain_diff_7_0_pos 0 | |
907 | #define dca_sbx_gain_diff_7_0_len 8 | |
908 | #define dca_sbx_gain_diff_7_0_lsb 0 | |
909 | #define xd_p_dca_sbx_gain_diff_9_8 0xA16B | |
910 | #define dca_sbx_gain_diff_9_8_pos 0 | |
911 | #define dca_sbx_gain_diff_9_8_len 2 | |
912 | #define dca_sbx_gain_diff_9_8_lsb 8 | |
913 | #define xd_p_reg_dca_stand_alone 0xA16C | |
914 | #define reg_dca_stand_alone_pos 0 | |
915 | #define reg_dca_stand_alone_len 1 | |
916 | #define reg_dca_stand_alone_lsb 0 | |
917 | #define xd_p_reg_dca_upper_out_en 0xA16C | |
918 | #define reg_dca_upper_out_en_pos 1 | |
919 | #define reg_dca_upper_out_en_len 1 | |
920 | #define reg_dca_upper_out_en_lsb 0 | |
921 | #define xd_p_reg_dca_rc_en 0xA16C | |
922 | #define reg_dca_rc_en_pos 2 | |
923 | #define reg_dca_rc_en_len 1 | |
924 | #define reg_dca_rc_en_lsb 0 | |
925 | #define xd_p_reg_dca_retrain_send 0xA16C | |
926 | #define reg_dca_retrain_send_pos 3 | |
927 | #define reg_dca_retrain_send_len 1 | |
928 | #define reg_dca_retrain_send_lsb 0 | |
929 | #define xd_p_reg_dca_retrain_rec 0xA16C | |
930 | #define reg_dca_retrain_rec_pos 4 | |
931 | #define reg_dca_retrain_rec_len 1 | |
932 | #define reg_dca_retrain_rec_lsb 0 | |
933 | #define xd_p_reg_dca_api_tpsrdy 0xA16C | |
934 | #define reg_dca_api_tpsrdy_pos 5 | |
935 | #define reg_dca_api_tpsrdy_len 1 | |
936 | #define reg_dca_api_tpsrdy_lsb 0 | |
937 | #define xd_p_reg_dca_symbol_gap 0xA16D | |
938 | #define reg_dca_symbol_gap_pos 0 | |
939 | #define reg_dca_symbol_gap_len 4 | |
940 | #define reg_dca_symbol_gap_lsb 0 | |
941 | #define xd_p_reg_qnt_nfvaluew_7_0 0xA16E | |
942 | #define reg_qnt_nfvaluew_7_0_pos 0 | |
943 | #define reg_qnt_nfvaluew_7_0_len 8 | |
944 | #define reg_qnt_nfvaluew_7_0_lsb 0 | |
945 | #define xd_p_reg_qnt_nfvaluew_10_8 0xA16F | |
946 | #define reg_qnt_nfvaluew_10_8_pos 0 | |
947 | #define reg_qnt_nfvaluew_10_8_len 3 | |
948 | #define reg_qnt_nfvaluew_10_8_lsb 8 | |
949 | #define xd_p_reg_qnt_flatness_thr_7_0 0xA170 | |
950 | #define reg_qnt_flatness_thr_7_0_pos 0 | |
951 | #define reg_qnt_flatness_thr_7_0_len 8 | |
952 | #define reg_qnt_flatness_thr_7_0_lsb 0 | |
953 | #define xd_p_reg_qnt_flatness_thr_9_8 0xA171 | |
954 | #define reg_qnt_flatness_thr_9_8_pos 0 | |
955 | #define reg_qnt_flatness_thr_9_8_len 2 | |
956 | #define reg_qnt_flatness_thr_9_8_lsb 8 | |
957 | #define xd_p_reg_dca_tone_idx_5_0 0xA171 | |
958 | #define reg_dca_tone_idx_5_0_pos 2 | |
959 | #define reg_dca_tone_idx_5_0_len 6 | |
960 | #define reg_dca_tone_idx_5_0_lsb 0 | |
961 | #define xd_p_reg_dca_tone_idx_12_6 0xA172 | |
962 | #define reg_dca_tone_idx_12_6_pos 0 | |
963 | #define reg_dca_tone_idx_12_6_len 7 | |
964 | #define reg_dca_tone_idx_12_6_lsb 6 | |
965 | #define xd_p_reg_dca_data_vld 0xA173 | |
966 | #define reg_dca_data_vld_pos 0 | |
967 | #define reg_dca_data_vld_len 1 | |
968 | #define reg_dca_data_vld_lsb 0 | |
969 | #define xd_p_reg_dca_read_update 0xA173 | |
970 | #define reg_dca_read_update_pos 1 | |
971 | #define reg_dca_read_update_len 1 | |
972 | #define reg_dca_read_update_lsb 0 | |
973 | #define xd_r_reg_dca_data_re_5_0 0xA173 | |
974 | #define reg_dca_data_re_5_0_pos 2 | |
975 | #define reg_dca_data_re_5_0_len 6 | |
976 | #define reg_dca_data_re_5_0_lsb 0 | |
977 | #define xd_r_reg_dca_data_re_10_6 0xA174 | |
978 | #define reg_dca_data_re_10_6_pos 0 | |
979 | #define reg_dca_data_re_10_6_len 5 | |
980 | #define reg_dca_data_re_10_6_lsb 6 | |
981 | #define xd_r_reg_dca_data_im_7_0 0xA175 | |
982 | #define reg_dca_data_im_7_0_pos 0 | |
983 | #define reg_dca_data_im_7_0_len 8 | |
984 | #define reg_dca_data_im_7_0_lsb 0 | |
985 | #define xd_r_reg_dca_data_im_10_8 0xA176 | |
986 | #define reg_dca_data_im_10_8_pos 0 | |
987 | #define reg_dca_data_im_10_8_len 3 | |
988 | #define reg_dca_data_im_10_8_lsb 8 | |
989 | #define xd_r_reg_dca_data_h2_7_0 0xA178 | |
990 | #define reg_dca_data_h2_7_0_pos 0 | |
991 | #define reg_dca_data_h2_7_0_len 8 | |
992 | #define reg_dca_data_h2_7_0_lsb 0 | |
993 | #define xd_r_reg_dca_data_h2_9_8 0xA179 | |
994 | #define reg_dca_data_h2_9_8_pos 0 | |
995 | #define reg_dca_data_h2_9_8_len 2 | |
996 | #define reg_dca_data_h2_9_8_lsb 8 | |
997 | #define xd_p_reg_f_adc_7_0 0xA180 | |
998 | #define reg_f_adc_7_0_pos 0 | |
999 | #define reg_f_adc_7_0_len 8 | |
1000 | #define reg_f_adc_7_0_lsb 0 | |
1001 | #define xd_p_reg_f_adc_15_8 0xA181 | |
1002 | #define reg_f_adc_15_8_pos 0 | |
1003 | #define reg_f_adc_15_8_len 8 | |
1004 | #define reg_f_adc_15_8_lsb 8 | |
1005 | #define xd_p_reg_f_adc_23_16 0xA182 | |
1006 | #define reg_f_adc_23_16_pos 0 | |
1007 | #define reg_f_adc_23_16_len 8 | |
1008 | #define reg_f_adc_23_16_lsb 16 | |
1009 | #define xd_r_intp_mu_7_0 0xA190 | |
1010 | #define intp_mu_7_0_pos 0 | |
1011 | #define intp_mu_7_0_len 8 | |
1012 | #define intp_mu_7_0_lsb 0 | |
1013 | #define xd_r_intp_mu_15_8 0xA191 | |
1014 | #define intp_mu_15_8_pos 0 | |
1015 | #define intp_mu_15_8_len 8 | |
1016 | #define intp_mu_15_8_lsb 8 | |
1017 | #define xd_r_intp_mu_19_16 0xA192 | |
1018 | #define intp_mu_19_16_pos 0 | |
1019 | #define intp_mu_19_16_len 4 | |
1020 | #define intp_mu_19_16_lsb 16 | |
1021 | #define xd_p_reg_agc_rst 0xA1A0 | |
1022 | #define reg_agc_rst_pos 0 | |
1023 | #define reg_agc_rst_len 1 | |
1024 | #define reg_agc_rst_lsb 0 | |
1025 | #define xd_p_rf_agc_en 0xA1A0 | |
1026 | #define rf_agc_en_pos 1 | |
1027 | #define rf_agc_en_len 1 | |
1028 | #define rf_agc_en_lsb 0 | |
1029 | #define xd_p_rf_agc_dis 0xA1A0 | |
1030 | #define rf_agc_dis_pos 2 | |
1031 | #define rf_agc_dis_len 1 | |
1032 | #define rf_agc_dis_lsb 0 | |
1033 | #define xd_p_if_agc_rst 0xA1A0 | |
1034 | #define if_agc_rst_pos 3 | |
1035 | #define if_agc_rst_len 1 | |
1036 | #define if_agc_rst_lsb 0 | |
1037 | #define xd_p_if_agc_en 0xA1A0 | |
1038 | #define if_agc_en_pos 4 | |
1039 | #define if_agc_en_len 1 | |
1040 | #define if_agc_en_lsb 0 | |
1041 | #define xd_p_if_agc_dis 0xA1A0 | |
1042 | #define if_agc_dis_pos 5 | |
1043 | #define if_agc_dis_len 1 | |
1044 | #define if_agc_dis_lsb 0 | |
1045 | #define xd_p_agc_lock 0xA1A0 | |
1046 | #define agc_lock_pos 6 | |
1047 | #define agc_lock_len 1 | |
1048 | #define agc_lock_lsb 0 | |
1049 | #define xd_p_reg_tinr_rst 0xA1A1 | |
1050 | #define reg_tinr_rst_pos 0 | |
1051 | #define reg_tinr_rst_len 1 | |
1052 | #define reg_tinr_rst_lsb 0 | |
1053 | #define xd_p_reg_tinr_en 0xA1A1 | |
1054 | #define reg_tinr_en_pos 1 | |
1055 | #define reg_tinr_en_len 1 | |
1056 | #define reg_tinr_en_lsb 0 | |
1057 | #define xd_p_reg_ccifs_en 0xA1A2 | |
1058 | #define reg_ccifs_en_pos 0 | |
1059 | #define reg_ccifs_en_len 1 | |
1060 | #define reg_ccifs_en_lsb 0 | |
1061 | #define xd_p_reg_ccifs_dis 0xA1A2 | |
1062 | #define reg_ccifs_dis_pos 1 | |
1063 | #define reg_ccifs_dis_len 1 | |
1064 | #define reg_ccifs_dis_lsb 0 | |
1065 | #define xd_p_reg_ccifs_rst 0xA1A2 | |
1066 | #define reg_ccifs_rst_pos 2 | |
1067 | #define reg_ccifs_rst_len 1 | |
1068 | #define reg_ccifs_rst_lsb 0 | |
1069 | #define xd_p_reg_ccifs_byp 0xA1A2 | |
1070 | #define reg_ccifs_byp_pos 3 | |
1071 | #define reg_ccifs_byp_len 1 | |
1072 | #define reg_ccifs_byp_lsb 0 | |
1073 | #define xd_p_reg_ccif_en 0xA1A3 | |
1074 | #define reg_ccif_en_pos 0 | |
1075 | #define reg_ccif_en_len 1 | |
1076 | #define reg_ccif_en_lsb 0 | |
1077 | #define xd_p_reg_ccif_dis 0xA1A3 | |
1078 | #define reg_ccif_dis_pos 1 | |
1079 | #define reg_ccif_dis_len 1 | |
1080 | #define reg_ccif_dis_lsb 0 | |
1081 | #define xd_p_reg_ccif_rst 0xA1A3 | |
1082 | #define reg_ccif_rst_pos 2 | |
1083 | #define reg_ccif_rst_len 1 | |
1084 | #define reg_ccif_rst_lsb 0 | |
1085 | #define xd_p_reg_ccif_byp 0xA1A3 | |
1086 | #define reg_ccif_byp_pos 3 | |
1087 | #define reg_ccif_byp_len 1 | |
1088 | #define reg_ccif_byp_lsb 0 | |
1089 | #define xd_p_dagc1_rst 0xA1A4 | |
1090 | #define dagc1_rst_pos 0 | |
1091 | #define dagc1_rst_len 1 | |
1092 | #define dagc1_rst_lsb 0 | |
1093 | #define xd_p_dagc1_en 0xA1A4 | |
1094 | #define dagc1_en_pos 1 | |
1095 | #define dagc1_en_len 1 | |
1096 | #define dagc1_en_lsb 0 | |
1097 | #define xd_p_dagc1_mode 0xA1A4 | |
1098 | #define dagc1_mode_pos 2 | |
1099 | #define dagc1_mode_len 2 | |
1100 | #define dagc1_mode_lsb 0 | |
1101 | #define xd_p_dagc1_done 0xA1A4 | |
1102 | #define dagc1_done_pos 4 | |
1103 | #define dagc1_done_len 1 | |
1104 | #define dagc1_done_lsb 0 | |
1105 | #define xd_p_ccid_rst 0xA1A5 | |
1106 | #define ccid_rst_pos 0 | |
1107 | #define ccid_rst_len 1 | |
1108 | #define ccid_rst_lsb 0 | |
1109 | #define xd_p_ccid_en 0xA1A5 | |
1110 | #define ccid_en_pos 1 | |
1111 | #define ccid_en_len 1 | |
1112 | #define ccid_en_lsb 0 | |
1113 | #define xd_p_ccid_mode 0xA1A5 | |
1114 | #define ccid_mode_pos 2 | |
1115 | #define ccid_mode_len 2 | |
1116 | #define ccid_mode_lsb 0 | |
1117 | #define xd_p_ccid_done 0xA1A5 | |
1118 | #define ccid_done_pos 4 | |
1119 | #define ccid_done_len 1 | |
1120 | #define ccid_done_lsb 0 | |
1121 | #define xd_r_ccid_deted 0xA1A5 | |
1122 | #define ccid_deted_pos 5 | |
1123 | #define ccid_deted_len 1 | |
1124 | #define ccid_deted_lsb 0 | |
1125 | #define xd_p_ccid2_en 0xA1A5 | |
1126 | #define ccid2_en_pos 6 | |
1127 | #define ccid2_en_len 1 | |
1128 | #define ccid2_en_lsb 0 | |
1129 | #define xd_p_ccid2_done 0xA1A5 | |
1130 | #define ccid2_done_pos 7 | |
1131 | #define ccid2_done_len 1 | |
1132 | #define ccid2_done_lsb 0 | |
1133 | #define xd_p_reg_bfs_en 0xA1A6 | |
1134 | #define reg_bfs_en_pos 0 | |
1135 | #define reg_bfs_en_len 1 | |
1136 | #define reg_bfs_en_lsb 0 | |
1137 | #define xd_p_reg_bfs_dis 0xA1A6 | |
1138 | #define reg_bfs_dis_pos 1 | |
1139 | #define reg_bfs_dis_len 1 | |
1140 | #define reg_bfs_dis_lsb 0 | |
1141 | #define xd_p_reg_bfs_rst 0xA1A6 | |
1142 | #define reg_bfs_rst_pos 2 | |
1143 | #define reg_bfs_rst_len 1 | |
1144 | #define reg_bfs_rst_lsb 0 | |
1145 | #define xd_p_reg_bfs_byp 0xA1A6 | |
1146 | #define reg_bfs_byp_pos 3 | |
1147 | #define reg_bfs_byp_len 1 | |
1148 | #define reg_bfs_byp_lsb 0 | |
1149 | #define xd_p_reg_antif_en 0xA1A7 | |
1150 | #define reg_antif_en_pos 0 | |
1151 | #define reg_antif_en_len 1 | |
1152 | #define reg_antif_en_lsb 0 | |
1153 | #define xd_p_reg_antif_dis 0xA1A7 | |
1154 | #define reg_antif_dis_pos 1 | |
1155 | #define reg_antif_dis_len 1 | |
1156 | #define reg_antif_dis_lsb 0 | |
1157 | #define xd_p_reg_antif_rst 0xA1A7 | |
1158 | #define reg_antif_rst_pos 2 | |
1159 | #define reg_antif_rst_len 1 | |
1160 | #define reg_antif_rst_lsb 0 | |
1161 | #define xd_p_reg_antif_byp 0xA1A7 | |
1162 | #define reg_antif_byp_pos 3 | |
1163 | #define reg_antif_byp_len 1 | |
1164 | #define reg_antif_byp_lsb 0 | |
1165 | #define xd_p_intp_en 0xA1A8 | |
1166 | #define intp_en_pos 0 | |
1167 | #define intp_en_len 1 | |
1168 | #define intp_en_lsb 0 | |
1169 | #define xd_p_intp_dis 0xA1A8 | |
1170 | #define intp_dis_pos 1 | |
1171 | #define intp_dis_len 1 | |
1172 | #define intp_dis_lsb 0 | |
1173 | #define xd_p_intp_rst 0xA1A8 | |
1174 | #define intp_rst_pos 2 | |
1175 | #define intp_rst_len 1 | |
1176 | #define intp_rst_lsb 0 | |
1177 | #define xd_p_intp_byp 0xA1A8 | |
1178 | #define intp_byp_pos 3 | |
1179 | #define intp_byp_len 1 | |
1180 | #define intp_byp_lsb 0 | |
1181 | #define xd_p_reg_acif_en 0xA1A9 | |
1182 | #define reg_acif_en_pos 0 | |
1183 | #define reg_acif_en_len 1 | |
1184 | #define reg_acif_en_lsb 0 | |
1185 | #define xd_p_reg_acif_dis 0xA1A9 | |
1186 | #define reg_acif_dis_pos 1 | |
1187 | #define reg_acif_dis_len 1 | |
1188 | #define reg_acif_dis_lsb 0 | |
1189 | #define xd_p_reg_acif_rst 0xA1A9 | |
1190 | #define reg_acif_rst_pos 2 | |
1191 | #define reg_acif_rst_len 1 | |
1192 | #define reg_acif_rst_lsb 0 | |
1193 | #define xd_p_reg_acif_byp 0xA1A9 | |
1194 | #define reg_acif_byp_pos 3 | |
1195 | #define reg_acif_byp_len 1 | |
1196 | #define reg_acif_byp_lsb 0 | |
1197 | #define xd_p_reg_acif_sync_mode 0xA1A9 | |
1198 | #define reg_acif_sync_mode_pos 4 | |
1199 | #define reg_acif_sync_mode_len 1 | |
1200 | #define reg_acif_sync_mode_lsb 0 | |
1201 | #define xd_p_dagc2_rst 0xA1AA | |
1202 | #define dagc2_rst_pos 0 | |
1203 | #define dagc2_rst_len 1 | |
1204 | #define dagc2_rst_lsb 0 | |
1205 | #define xd_p_dagc2_en 0xA1AA | |
1206 | #define dagc2_en_pos 1 | |
1207 | #define dagc2_en_len 1 | |
1208 | #define dagc2_en_lsb 0 | |
1209 | #define xd_p_dagc2_mode 0xA1AA | |
1210 | #define dagc2_mode_pos 2 | |
1211 | #define dagc2_mode_len 2 | |
1212 | #define dagc2_mode_lsb 0 | |
1213 | #define xd_p_dagc2_done 0xA1AA | |
1214 | #define dagc2_done_pos 4 | |
1215 | #define dagc2_done_len 1 | |
1216 | #define dagc2_done_lsb 0 | |
1217 | #define xd_p_reg_dca_en 0xA1AB | |
1218 | #define reg_dca_en_pos 0 | |
1219 | #define reg_dca_en_len 1 | |
1220 | #define reg_dca_en_lsb 0 | |
1221 | #define xd_p_dagc2_accumulate_num_2k_7_0 0xA1C0 | |
1222 | #define dagc2_accumulate_num_2k_7_0_pos 0 | |
1223 | #define dagc2_accumulate_num_2k_7_0_len 8 | |
1224 | #define dagc2_accumulate_num_2k_7_0_lsb 0 | |
1225 | #define xd_p_dagc2_accumulate_num_2k_12_8 0xA1C1 | |
1226 | #define dagc2_accumulate_num_2k_12_8_pos 0 | |
1227 | #define dagc2_accumulate_num_2k_12_8_len 5 | |
1228 | #define dagc2_accumulate_num_2k_12_8_lsb 8 | |
1229 | #define xd_p_dagc2_accumulate_num_8k_7_0 0xA1C2 | |
1230 | #define dagc2_accumulate_num_8k_7_0_pos 0 | |
1231 | #define dagc2_accumulate_num_8k_7_0_len 8 | |
1232 | #define dagc2_accumulate_num_8k_7_0_lsb 0 | |
1233 | #define xd_p_dagc2_accumulate_num_8k_12_8 0xA1C3 | |
1234 | #define dagc2_accumulate_num_8k_12_8_pos 0 | |
1235 | #define dagc2_accumulate_num_8k_12_8_len 5 | |
1236 | #define dagc2_accumulate_num_8k_12_8_lsb 8 | |
1237 | #define xd_p_dagc2_desired_level_2_0 0xA1C3 | |
1238 | #define dagc2_desired_level_2_0_pos 5 | |
1239 | #define dagc2_desired_level_2_0_len 3 | |
1240 | #define dagc2_desired_level_2_0_lsb 0 | |
1241 | #define xd_p_dagc2_desired_level_8_3 0xA1C4 | |
1242 | #define dagc2_desired_level_8_3_pos 0 | |
1243 | #define dagc2_desired_level_8_3_len 6 | |
1244 | #define dagc2_desired_level_8_3_lsb 3 | |
1245 | #define xd_p_dagc2_apply_delay 0xA1C5 | |
1246 | #define dagc2_apply_delay_pos 0 | |
1247 | #define dagc2_apply_delay_len 7 | |
1248 | #define dagc2_apply_delay_lsb 0 | |
1249 | #define xd_p_dagc2_bypass_scale_ctl 0xA1C6 | |
1250 | #define dagc2_bypass_scale_ctl_pos 0 | |
1251 | #define dagc2_bypass_scale_ctl_len 3 | |
1252 | #define dagc2_bypass_scale_ctl_lsb 0 | |
1253 | #define xd_p_dagc2_programmable_shift1 0xA1C7 | |
1254 | #define dagc2_programmable_shift1_pos 0 | |
1255 | #define dagc2_programmable_shift1_len 8 | |
1256 | #define dagc2_programmable_shift1_lsb 0 | |
1257 | #define xd_p_dagc2_programmable_shift2 0xA1C8 | |
1258 | #define dagc2_programmable_shift2_pos 0 | |
1259 | #define dagc2_programmable_shift2_len 8 | |
1260 | #define dagc2_programmable_shift2_lsb 0 | |
1261 | #define xd_p_reg_dagc2_in_sat_cnt_7_0 0xA1C9 | |
1262 | #define reg_dagc2_in_sat_cnt_7_0_pos 0 | |
1263 | #define reg_dagc2_in_sat_cnt_7_0_len 8 | |
1264 | #define reg_dagc2_in_sat_cnt_7_0_lsb 0 | |
1265 | #define xd_p_reg_dagc2_in_sat_cnt_15_8 0xA1CA | |
1266 | #define reg_dagc2_in_sat_cnt_15_8_pos 0 | |
1267 | #define reg_dagc2_in_sat_cnt_15_8_len 8 | |
1268 | #define reg_dagc2_in_sat_cnt_15_8_lsb 8 | |
1269 | #define xd_p_reg_dagc2_in_sat_cnt_23_16 0xA1CB | |
1270 | #define reg_dagc2_in_sat_cnt_23_16_pos 0 | |
1271 | #define reg_dagc2_in_sat_cnt_23_16_len 8 | |
1272 | #define reg_dagc2_in_sat_cnt_23_16_lsb 16 | |
1273 | #define xd_p_reg_dagc2_in_sat_cnt_31_24 0xA1CC | |
1274 | #define reg_dagc2_in_sat_cnt_31_24_pos 0 | |
1275 | #define reg_dagc2_in_sat_cnt_31_24_len 8 | |
1276 | #define reg_dagc2_in_sat_cnt_31_24_lsb 24 | |
1277 | #define xd_p_reg_dagc2_out_sat_cnt_7_0 0xA1CD | |
1278 | #define reg_dagc2_out_sat_cnt_7_0_pos 0 | |
1279 | #define reg_dagc2_out_sat_cnt_7_0_len 8 | |
1280 | #define reg_dagc2_out_sat_cnt_7_0_lsb 0 | |
1281 | #define xd_p_reg_dagc2_out_sat_cnt_15_8 0xA1CE | |
1282 | #define reg_dagc2_out_sat_cnt_15_8_pos 0 | |
1283 | #define reg_dagc2_out_sat_cnt_15_8_len 8 | |
1284 | #define reg_dagc2_out_sat_cnt_15_8_lsb 8 | |
1285 | #define xd_p_reg_dagc2_out_sat_cnt_23_16 0xA1CF | |
1286 | #define reg_dagc2_out_sat_cnt_23_16_pos 0 | |
1287 | #define reg_dagc2_out_sat_cnt_23_16_len 8 | |
1288 | #define reg_dagc2_out_sat_cnt_23_16_lsb 16 | |
1289 | #define xd_p_reg_dagc2_out_sat_cnt_31_24 0xA1D0 | |
1290 | #define reg_dagc2_out_sat_cnt_31_24_pos 0 | |
1291 | #define reg_dagc2_out_sat_cnt_31_24_len 8 | |
1292 | #define reg_dagc2_out_sat_cnt_31_24_lsb 24 | |
1293 | #define xd_r_dagc2_multiplier_7_0 0xA1D6 | |
1294 | #define dagc2_multiplier_7_0_pos 0 | |
1295 | #define dagc2_multiplier_7_0_len 8 | |
1296 | #define dagc2_multiplier_7_0_lsb 0 | |
1297 | #define xd_r_dagc2_multiplier_15_8 0xA1D7 | |
1298 | #define dagc2_multiplier_15_8_pos 0 | |
1299 | #define dagc2_multiplier_15_8_len 8 | |
1300 | #define dagc2_multiplier_15_8_lsb 8 | |
1301 | #define xd_r_dagc2_right_shift_bits 0xA1D8 | |
1302 | #define dagc2_right_shift_bits_pos 0 | |
1303 | #define dagc2_right_shift_bits_len 4 | |
1304 | #define dagc2_right_shift_bits_lsb 0 | |
1305 | #define xd_p_cfoe_NS_coeff1_7_0 0xA200 | |
1306 | #define cfoe_NS_coeff1_7_0_pos 0 | |
1307 | #define cfoe_NS_coeff1_7_0_len 8 | |
1308 | #define cfoe_NS_coeff1_7_0_lsb 0 | |
1309 | #define xd_p_cfoe_NS_coeff1_15_8 0xA201 | |
1310 | #define cfoe_NS_coeff1_15_8_pos 0 | |
1311 | #define cfoe_NS_coeff1_15_8_len 8 | |
1312 | #define cfoe_NS_coeff1_15_8_lsb 8 | |
1313 | #define xd_p_cfoe_NS_coeff1_23_16 0xA202 | |
1314 | #define cfoe_NS_coeff1_23_16_pos 0 | |
1315 | #define cfoe_NS_coeff1_23_16_len 8 | |
1316 | #define cfoe_NS_coeff1_23_16_lsb 16 | |
1317 | #define xd_p_cfoe_NS_coeff1_25_24 0xA203 | |
1318 | #define cfoe_NS_coeff1_25_24_pos 0 | |
1319 | #define cfoe_NS_coeff1_25_24_len 2 | |
1320 | #define cfoe_NS_coeff1_25_24_lsb 24 | |
1321 | #define xd_p_cfoe_NS_coeff2_5_0 0xA203 | |
1322 | #define cfoe_NS_coeff2_5_0_pos 2 | |
1323 | #define cfoe_NS_coeff2_5_0_len 6 | |
1324 | #define cfoe_NS_coeff2_5_0_lsb 0 | |
1325 | #define xd_p_cfoe_NS_coeff2_13_6 0xA204 | |
1326 | #define cfoe_NS_coeff2_13_6_pos 0 | |
1327 | #define cfoe_NS_coeff2_13_6_len 8 | |
1328 | #define cfoe_NS_coeff2_13_6_lsb 6 | |
1329 | #define xd_p_cfoe_NS_coeff2_21_14 0xA205 | |
1330 | #define cfoe_NS_coeff2_21_14_pos 0 | |
1331 | #define cfoe_NS_coeff2_21_14_len 8 | |
1332 | #define cfoe_NS_coeff2_21_14_lsb 14 | |
1333 | #define xd_p_cfoe_NS_coeff2_24_22 0xA206 | |
1334 | #define cfoe_NS_coeff2_24_22_pos 0 | |
1335 | #define cfoe_NS_coeff2_24_22_len 3 | |
1336 | #define cfoe_NS_coeff2_24_22_lsb 22 | |
1337 | #define xd_p_cfoe_lf_c1_4_0 0xA206 | |
1338 | #define cfoe_lf_c1_4_0_pos 3 | |
1339 | #define cfoe_lf_c1_4_0_len 5 | |
1340 | #define cfoe_lf_c1_4_0_lsb 0 | |
1341 | #define xd_p_cfoe_lf_c1_12_5 0xA207 | |
1342 | #define cfoe_lf_c1_12_5_pos 0 | |
1343 | #define cfoe_lf_c1_12_5_len 8 | |
1344 | #define cfoe_lf_c1_12_5_lsb 5 | |
1345 | #define xd_p_cfoe_lf_c1_20_13 0xA208 | |
1346 | #define cfoe_lf_c1_20_13_pos 0 | |
1347 | #define cfoe_lf_c1_20_13_len 8 | |
1348 | #define cfoe_lf_c1_20_13_lsb 13 | |
1349 | #define xd_p_cfoe_lf_c1_25_21 0xA209 | |
1350 | #define cfoe_lf_c1_25_21_pos 0 | |
1351 | #define cfoe_lf_c1_25_21_len 5 | |
1352 | #define cfoe_lf_c1_25_21_lsb 21 | |
1353 | #define xd_p_cfoe_lf_c2_2_0 0xA209 | |
1354 | #define cfoe_lf_c2_2_0_pos 5 | |
1355 | #define cfoe_lf_c2_2_0_len 3 | |
1356 | #define cfoe_lf_c2_2_0_lsb 0 | |
1357 | #define xd_p_cfoe_lf_c2_10_3 0xA20A | |
1358 | #define cfoe_lf_c2_10_3_pos 0 | |
1359 | #define cfoe_lf_c2_10_3_len 8 | |
1360 | #define cfoe_lf_c2_10_3_lsb 3 | |
1361 | #define xd_p_cfoe_lf_c2_18_11 0xA20B | |
1362 | #define cfoe_lf_c2_18_11_pos 0 | |
1363 | #define cfoe_lf_c2_18_11_len 8 | |
1364 | #define cfoe_lf_c2_18_11_lsb 11 | |
1365 | #define xd_p_cfoe_lf_c2_25_19 0xA20C | |
1366 | #define cfoe_lf_c2_25_19_pos 0 | |
1367 | #define cfoe_lf_c2_25_19_len 7 | |
1368 | #define cfoe_lf_c2_25_19_lsb 19 | |
1369 | #define xd_p_cfoe_ifod_7_0 0xA20D | |
1370 | #define cfoe_ifod_7_0_pos 0 | |
1371 | #define cfoe_ifod_7_0_len 8 | |
1372 | #define cfoe_ifod_7_0_lsb 0 | |
1373 | #define xd_p_cfoe_ifod_10_8 0xA20E | |
1374 | #define cfoe_ifod_10_8_pos 0 | |
1375 | #define cfoe_ifod_10_8_len 3 | |
1376 | #define cfoe_ifod_10_8_lsb 8 | |
1377 | #define xd_p_cfoe_Divg_ctr_th 0xA20E | |
1378 | #define cfoe_Divg_ctr_th_pos 4 | |
1379 | #define cfoe_Divg_ctr_th_len 4 | |
1380 | #define cfoe_Divg_ctr_th_lsb 0 | |
1381 | #define xd_p_cfoe_FOT_divg_th 0xA20F | |
1382 | #define cfoe_FOT_divg_th_pos 0 | |
1383 | #define cfoe_FOT_divg_th_len 8 | |
1384 | #define cfoe_FOT_divg_th_lsb 0 | |
1385 | #define xd_p_cfoe_FOT_cnvg_th 0xA210 | |
1386 | #define cfoe_FOT_cnvg_th_pos 0 | |
1387 | #define cfoe_FOT_cnvg_th_len 8 | |
1388 | #define cfoe_FOT_cnvg_th_lsb 0 | |
1389 | #define xd_p_reg_cfoe_offset_7_0 0xA211 | |
1390 | #define reg_cfoe_offset_7_0_pos 0 | |
1391 | #define reg_cfoe_offset_7_0_len 8 | |
1392 | #define reg_cfoe_offset_7_0_lsb 0 | |
1393 | #define xd_p_reg_cfoe_offset_9_8 0xA212 | |
1394 | #define reg_cfoe_offset_9_8_pos 0 | |
1395 | #define reg_cfoe_offset_9_8_len 2 | |
1396 | #define reg_cfoe_offset_9_8_lsb 8 | |
1397 | #define xd_p_reg_cfoe_ifoe_sign_corr 0xA212 | |
1398 | #define reg_cfoe_ifoe_sign_corr_pos 2 | |
1399 | #define reg_cfoe_ifoe_sign_corr_len 1 | |
1400 | #define reg_cfoe_ifoe_sign_corr_lsb 0 | |
1401 | #define xd_r_cfoe_fot_LF_output_7_0 0xA218 | |
1402 | #define cfoe_fot_LF_output_7_0_pos 0 | |
1403 | #define cfoe_fot_LF_output_7_0_len 8 | |
1404 | #define cfoe_fot_LF_output_7_0_lsb 0 | |
1405 | #define xd_r_cfoe_fot_LF_output_15_8 0xA219 | |
1406 | #define cfoe_fot_LF_output_15_8_pos 0 | |
1407 | #define cfoe_fot_LF_output_15_8_len 8 | |
1408 | #define cfoe_fot_LF_output_15_8_lsb 8 | |
1409 | #define xd_r_cfoe_ifo_metric_7_0 0xA21A | |
1410 | #define cfoe_ifo_metric_7_0_pos 0 | |
1411 | #define cfoe_ifo_metric_7_0_len 8 | |
1412 | #define cfoe_ifo_metric_7_0_lsb 0 | |
1413 | #define xd_r_cfoe_ifo_metric_15_8 0xA21B | |
1414 | #define cfoe_ifo_metric_15_8_pos 0 | |
1415 | #define cfoe_ifo_metric_15_8_len 8 | |
1416 | #define cfoe_ifo_metric_15_8_lsb 8 | |
1417 | #define xd_r_cfoe_ifo_metric_23_16 0xA21C | |
1418 | #define cfoe_ifo_metric_23_16_pos 0 | |
1419 | #define cfoe_ifo_metric_23_16_len 8 | |
1420 | #define cfoe_ifo_metric_23_16_lsb 16 | |
1421 | #define xd_p_ste_Nu 0xA220 | |
1422 | #define ste_Nu_pos 0 | |
1423 | #define ste_Nu_len 2 | |
1424 | #define ste_Nu_lsb 0 | |
1425 | #define xd_p_ste_GI 0xA220 | |
1426 | #define ste_GI_pos 2 | |
1427 | #define ste_GI_len 3 | |
1428 | #define ste_GI_lsb 0 | |
1429 | #define xd_p_ste_symbol_num 0xA221 | |
1430 | #define ste_symbol_num_pos 0 | |
1431 | #define ste_symbol_num_len 2 | |
1432 | #define ste_symbol_num_lsb 0 | |
1433 | #define xd_p_ste_sample_num 0xA221 | |
1434 | #define ste_sample_num_pos 2 | |
1435 | #define ste_sample_num_len 2 | |
1436 | #define ste_sample_num_lsb 0 | |
1437 | #define xd_p_reg_ste_buf_en 0xA221 | |
1438 | #define reg_ste_buf_en_pos 7 | |
1439 | #define reg_ste_buf_en_len 1 | |
1440 | #define reg_ste_buf_en_lsb 0 | |
1441 | #define xd_p_ste_FFT_offset_7_0 0xA222 | |
1442 | #define ste_FFT_offset_7_0_pos 0 | |
1443 | #define ste_FFT_offset_7_0_len 8 | |
1444 | #define ste_FFT_offset_7_0_lsb 0 | |
1445 | #define xd_p_ste_FFT_offset_11_8 0xA223 | |
1446 | #define ste_FFT_offset_11_8_pos 0 | |
1447 | #define ste_FFT_offset_11_8_len 4 | |
1448 | #define ste_FFT_offset_11_8_lsb 8 | |
1449 | #define xd_p_reg_ste_tstmod 0xA223 | |
1450 | #define reg_ste_tstmod_pos 5 | |
1451 | #define reg_ste_tstmod_len 1 | |
1452 | #define reg_ste_tstmod_lsb 0 | |
1453 | #define xd_p_ste_adv_start_7_0 0xA224 | |
1454 | #define ste_adv_start_7_0_pos 0 | |
1455 | #define ste_adv_start_7_0_len 8 | |
1456 | #define ste_adv_start_7_0_lsb 0 | |
1457 | #define xd_p_ste_adv_start_10_8 0xA225 | |
1458 | #define ste_adv_start_10_8_pos 0 | |
1459 | #define ste_adv_start_10_8_len 3 | |
1460 | #define ste_adv_start_10_8_lsb 8 | |
1461 | #define xd_p_ste_adv_stop 0xA226 | |
1462 | #define ste_adv_stop_pos 0 | |
1463 | #define ste_adv_stop_len 8 | |
1464 | #define ste_adv_stop_lsb 0 | |
1465 | #define xd_r_ste_P_value_7_0 0xA228 | |
1466 | #define ste_P_value_7_0_pos 0 | |
1467 | #define ste_P_value_7_0_len 8 | |
1468 | #define ste_P_value_7_0_lsb 0 | |
1469 | #define xd_r_ste_P_value_10_8 0xA229 | |
1470 | #define ste_P_value_10_8_pos 0 | |
1471 | #define ste_P_value_10_8_len 3 | |
1472 | #define ste_P_value_10_8_lsb 8 | |
1473 | #define xd_r_ste_M_value_7_0 0xA22A | |
1474 | #define ste_M_value_7_0_pos 0 | |
1475 | #define ste_M_value_7_0_len 8 | |
1476 | #define ste_M_value_7_0_lsb 0 | |
1477 | #define xd_r_ste_M_value_10_8 0xA22B | |
1478 | #define ste_M_value_10_8_pos 0 | |
1479 | #define ste_M_value_10_8_len 3 | |
1480 | #define ste_M_value_10_8_lsb 8 | |
1481 | #define xd_r_ste_H1 0xA22C | |
1482 | #define ste_H1_pos 0 | |
1483 | #define ste_H1_len 7 | |
1484 | #define ste_H1_lsb 0 | |
1485 | #define xd_r_ste_H2 0xA22D | |
1486 | #define ste_H2_pos 0 | |
1487 | #define ste_H2_len 7 | |
1488 | #define ste_H2_lsb 0 | |
1489 | #define xd_r_ste_H3 0xA22E | |
1490 | #define ste_H3_pos 0 | |
1491 | #define ste_H3_len 7 | |
1492 | #define ste_H3_lsb 0 | |
1493 | #define xd_r_ste_H4 0xA22F | |
1494 | #define ste_H4_pos 0 | |
1495 | #define ste_H4_len 7 | |
1496 | #define ste_H4_lsb 0 | |
1497 | #define xd_r_ste_Corr_value_I_7_0 0xA230 | |
1498 | #define ste_Corr_value_I_7_0_pos 0 | |
1499 | #define ste_Corr_value_I_7_0_len 8 | |
1500 | #define ste_Corr_value_I_7_0_lsb 0 | |
1501 | #define xd_r_ste_Corr_value_I_15_8 0xA231 | |
1502 | #define ste_Corr_value_I_15_8_pos 0 | |
1503 | #define ste_Corr_value_I_15_8_len 8 | |
1504 | #define ste_Corr_value_I_15_8_lsb 8 | |
1505 | #define xd_r_ste_Corr_value_I_23_16 0xA232 | |
1506 | #define ste_Corr_value_I_23_16_pos 0 | |
1507 | #define ste_Corr_value_I_23_16_len 8 | |
1508 | #define ste_Corr_value_I_23_16_lsb 16 | |
1509 | #define xd_r_ste_Corr_value_I_27_24 0xA233 | |
1510 | #define ste_Corr_value_I_27_24_pos 0 | |
1511 | #define ste_Corr_value_I_27_24_len 4 | |
1512 | #define ste_Corr_value_I_27_24_lsb 24 | |
1513 | #define xd_r_ste_Corr_value_Q_7_0 0xA234 | |
1514 | #define ste_Corr_value_Q_7_0_pos 0 | |
1515 | #define ste_Corr_value_Q_7_0_len 8 | |
1516 | #define ste_Corr_value_Q_7_0_lsb 0 | |
1517 | #define xd_r_ste_Corr_value_Q_15_8 0xA235 | |
1518 | #define ste_Corr_value_Q_15_8_pos 0 | |
1519 | #define ste_Corr_value_Q_15_8_len 8 | |
1520 | #define ste_Corr_value_Q_15_8_lsb 8 | |
1521 | #define xd_r_ste_Corr_value_Q_23_16 0xA236 | |
1522 | #define ste_Corr_value_Q_23_16_pos 0 | |
1523 | #define ste_Corr_value_Q_23_16_len 8 | |
1524 | #define ste_Corr_value_Q_23_16_lsb 16 | |
1525 | #define xd_r_ste_Corr_value_Q_27_24 0xA237 | |
1526 | #define ste_Corr_value_Q_27_24_pos 0 | |
1527 | #define ste_Corr_value_Q_27_24_len 4 | |
1528 | #define ste_Corr_value_Q_27_24_lsb 24 | |
1529 | #define xd_r_ste_J_num_7_0 0xA238 | |
1530 | #define ste_J_num_7_0_pos 0 | |
1531 | #define ste_J_num_7_0_len 8 | |
1532 | #define ste_J_num_7_0_lsb 0 | |
1533 | #define xd_r_ste_J_num_15_8 0xA239 | |
1534 | #define ste_J_num_15_8_pos 0 | |
1535 | #define ste_J_num_15_8_len 8 | |
1536 | #define ste_J_num_15_8_lsb 8 | |
1537 | #define xd_r_ste_J_num_23_16 0xA23A | |
1538 | #define ste_J_num_23_16_pos 0 | |
1539 | #define ste_J_num_23_16_len 8 | |
1540 | #define ste_J_num_23_16_lsb 16 | |
1541 | #define xd_r_ste_J_num_31_24 0xA23B | |
1542 | #define ste_J_num_31_24_pos 0 | |
1543 | #define ste_J_num_31_24_len 8 | |
1544 | #define ste_J_num_31_24_lsb 24 | |
1545 | #define xd_r_ste_J_den_7_0 0xA23C | |
1546 | #define ste_J_den_7_0_pos 0 | |
1547 | #define ste_J_den_7_0_len 8 | |
1548 | #define ste_J_den_7_0_lsb 0 | |
1549 | #define xd_r_ste_J_den_15_8 0xA23D | |
1550 | #define ste_J_den_15_8_pos 0 | |
1551 | #define ste_J_den_15_8_len 8 | |
1552 | #define ste_J_den_15_8_lsb 8 | |
1553 | #define xd_r_ste_J_den_18_16 0xA23E | |
1554 | #define ste_J_den_18_16_pos 0 | |
1555 | #define ste_J_den_18_16_len 3 | |
1556 | #define ste_J_den_18_16_lsb 16 | |
1557 | #define xd_r_ste_Beacon_Indicator 0xA23E | |
1558 | #define ste_Beacon_Indicator_pos 4 | |
1559 | #define ste_Beacon_Indicator_len 1 | |
1560 | #define ste_Beacon_Indicator_lsb 0 | |
1561 | #define xd_r_tpsd_Frame_Num 0xA250 | |
1562 | #define tpsd_Frame_Num_pos 0 | |
1563 | #define tpsd_Frame_Num_len 2 | |
1564 | #define tpsd_Frame_Num_lsb 0 | |
1565 | #define xd_r_tpsd_Constel 0xA250 | |
1566 | #define tpsd_Constel_pos 2 | |
1567 | #define tpsd_Constel_len 2 | |
1568 | #define tpsd_Constel_lsb 0 | |
1569 | #define xd_r_tpsd_GI 0xA250 | |
1570 | #define tpsd_GI_pos 4 | |
1571 | #define tpsd_GI_len 2 | |
1572 | #define tpsd_GI_lsb 0 | |
1573 | #define xd_r_tpsd_Mode 0xA250 | |
1574 | #define tpsd_Mode_pos 6 | |
1575 | #define tpsd_Mode_len 2 | |
1576 | #define tpsd_Mode_lsb 0 | |
1577 | #define xd_r_tpsd_CR_HP 0xA251 | |
1578 | #define tpsd_CR_HP_pos 0 | |
1579 | #define tpsd_CR_HP_len 3 | |
1580 | #define tpsd_CR_HP_lsb 0 | |
1581 | #define xd_r_tpsd_CR_LP 0xA251 | |
1582 | #define tpsd_CR_LP_pos 3 | |
1583 | #define tpsd_CR_LP_len 3 | |
1584 | #define tpsd_CR_LP_lsb 0 | |
1585 | #define xd_r_tpsd_Hie 0xA252 | |
1586 | #define tpsd_Hie_pos 0 | |
1587 | #define tpsd_Hie_len 3 | |
1588 | #define tpsd_Hie_lsb 0 | |
1589 | #define xd_r_tpsd_Res_Bits 0xA252 | |
1590 | #define tpsd_Res_Bits_pos 3 | |
1591 | #define tpsd_Res_Bits_len 5 | |
1592 | #define tpsd_Res_Bits_lsb 0 | |
1593 | #define xd_r_tpsd_Res_Bits_0 0xA253 | |
1594 | #define tpsd_Res_Bits_0_pos 0 | |
1595 | #define tpsd_Res_Bits_0_len 1 | |
1596 | #define tpsd_Res_Bits_0_lsb 0 | |
1597 | #define xd_r_tpsd_LengthInd 0xA253 | |
1598 | #define tpsd_LengthInd_pos 1 | |
1599 | #define tpsd_LengthInd_len 6 | |
1600 | #define tpsd_LengthInd_lsb 0 | |
1601 | #define xd_r_tpsd_Cell_Id_7_0 0xA254 | |
1602 | #define tpsd_Cell_Id_7_0_pos 0 | |
1603 | #define tpsd_Cell_Id_7_0_len 8 | |
1604 | #define tpsd_Cell_Id_7_0_lsb 0 | |
1605 | #define xd_r_tpsd_Cell_Id_15_8 0xA255 | |
1606 | #define tpsd_Cell_Id_15_8_pos 0 | |
1607 | #define tpsd_Cell_Id_15_8_len 8 | |
1608 | #define tpsd_Cell_Id_15_8_lsb 0 | |
1609 | #define xd_p_reg_fft_mask_tone0_7_0 0xA260 | |
1610 | #define reg_fft_mask_tone0_7_0_pos 0 | |
1611 | #define reg_fft_mask_tone0_7_0_len 8 | |
1612 | #define reg_fft_mask_tone0_7_0_lsb 0 | |
1613 | #define xd_p_reg_fft_mask_tone0_12_8 0xA261 | |
1614 | #define reg_fft_mask_tone0_12_8_pos 0 | |
1615 | #define reg_fft_mask_tone0_12_8_len 5 | |
1616 | #define reg_fft_mask_tone0_12_8_lsb 8 | |
1617 | #define xd_p_reg_fft_mask_tone1_7_0 0xA262 | |
1618 | #define reg_fft_mask_tone1_7_0_pos 0 | |
1619 | #define reg_fft_mask_tone1_7_0_len 8 | |
1620 | #define reg_fft_mask_tone1_7_0_lsb 0 | |
1621 | #define xd_p_reg_fft_mask_tone1_12_8 0xA263 | |
1622 | #define reg_fft_mask_tone1_12_8_pos 0 | |
1623 | #define reg_fft_mask_tone1_12_8_len 5 | |
1624 | #define reg_fft_mask_tone1_12_8_lsb 8 | |
1625 | #define xd_p_reg_fft_mask_tone2_7_0 0xA264 | |
1626 | #define reg_fft_mask_tone2_7_0_pos 0 | |
1627 | #define reg_fft_mask_tone2_7_0_len 8 | |
1628 | #define reg_fft_mask_tone2_7_0_lsb 0 | |
1629 | #define xd_p_reg_fft_mask_tone2_12_8 0xA265 | |
1630 | #define reg_fft_mask_tone2_12_8_pos 0 | |
1631 | #define reg_fft_mask_tone2_12_8_len 5 | |
1632 | #define reg_fft_mask_tone2_12_8_lsb 8 | |
1633 | #define xd_p_reg_fft_mask_tone3_7_0 0xA266 | |
1634 | #define reg_fft_mask_tone3_7_0_pos 0 | |
1635 | #define reg_fft_mask_tone3_7_0_len 8 | |
1636 | #define reg_fft_mask_tone3_7_0_lsb 0 | |
1637 | #define xd_p_reg_fft_mask_tone3_12_8 0xA267 | |
1638 | #define reg_fft_mask_tone3_12_8_pos 0 | |
1639 | #define reg_fft_mask_tone3_12_8_len 5 | |
1640 | #define reg_fft_mask_tone3_12_8_lsb 8 | |
1641 | #define xd_p_reg_fft_mask_from0_7_0 0xA268 | |
1642 | #define reg_fft_mask_from0_7_0_pos 0 | |
1643 | #define reg_fft_mask_from0_7_0_len 8 | |
1644 | #define reg_fft_mask_from0_7_0_lsb 0 | |
1645 | #define xd_p_reg_fft_mask_from0_12_8 0xA269 | |
1646 | #define reg_fft_mask_from0_12_8_pos 0 | |
1647 | #define reg_fft_mask_from0_12_8_len 5 | |
1648 | #define reg_fft_mask_from0_12_8_lsb 8 | |
1649 | #define xd_p_reg_fft_mask_to0_7_0 0xA26A | |
1650 | #define reg_fft_mask_to0_7_0_pos 0 | |
1651 | #define reg_fft_mask_to0_7_0_len 8 | |
1652 | #define reg_fft_mask_to0_7_0_lsb 0 | |
1653 | #define xd_p_reg_fft_mask_to0_12_8 0xA26B | |
1654 | #define reg_fft_mask_to0_12_8_pos 0 | |
1655 | #define reg_fft_mask_to0_12_8_len 5 | |
1656 | #define reg_fft_mask_to0_12_8_lsb 8 | |
1657 | #define xd_p_reg_fft_mask_from1_7_0 0xA26C | |
1658 | #define reg_fft_mask_from1_7_0_pos 0 | |
1659 | #define reg_fft_mask_from1_7_0_len 8 | |
1660 | #define reg_fft_mask_from1_7_0_lsb 0 | |
1661 | #define xd_p_reg_fft_mask_from1_12_8 0xA26D | |
1662 | #define reg_fft_mask_from1_12_8_pos 0 | |
1663 | #define reg_fft_mask_from1_12_8_len 5 | |
1664 | #define reg_fft_mask_from1_12_8_lsb 8 | |
1665 | #define xd_p_reg_fft_mask_to1_7_0 0xA26E | |
1666 | #define reg_fft_mask_to1_7_0_pos 0 | |
1667 | #define reg_fft_mask_to1_7_0_len 8 | |
1668 | #define reg_fft_mask_to1_7_0_lsb 0 | |
1669 | #define xd_p_reg_fft_mask_to1_12_8 0xA26F | |
1670 | #define reg_fft_mask_to1_12_8_pos 0 | |
1671 | #define reg_fft_mask_to1_12_8_len 5 | |
1672 | #define reg_fft_mask_to1_12_8_lsb 8 | |
1673 | #define xd_p_reg_cge_idx0_7_0 0xA280 | |
1674 | #define reg_cge_idx0_7_0_pos 0 | |
1675 | #define reg_cge_idx0_7_0_len 8 | |
1676 | #define reg_cge_idx0_7_0_lsb 0 | |
1677 | #define xd_p_reg_cge_idx0_12_8 0xA281 | |
1678 | #define reg_cge_idx0_12_8_pos 0 | |
1679 | #define reg_cge_idx0_12_8_len 5 | |
1680 | #define reg_cge_idx0_12_8_lsb 8 | |
1681 | #define xd_p_reg_cge_idx1_7_0 0xA282 | |
1682 | #define reg_cge_idx1_7_0_pos 0 | |
1683 | #define reg_cge_idx1_7_0_len 8 | |
1684 | #define reg_cge_idx1_7_0_lsb 0 | |
1685 | #define xd_p_reg_cge_idx1_12_8 0xA283 | |
1686 | #define reg_cge_idx1_12_8_pos 0 | |
1687 | #define reg_cge_idx1_12_8_len 5 | |
1688 | #define reg_cge_idx1_12_8_lsb 8 | |
1689 | #define xd_p_reg_cge_idx2_7_0 0xA284 | |
1690 | #define reg_cge_idx2_7_0_pos 0 | |
1691 | #define reg_cge_idx2_7_0_len 8 | |
1692 | #define reg_cge_idx2_7_0_lsb 0 | |
1693 | #define xd_p_reg_cge_idx2_12_8 0xA285 | |
1694 | #define reg_cge_idx2_12_8_pos 0 | |
1695 | #define reg_cge_idx2_12_8_len 5 | |
1696 | #define reg_cge_idx2_12_8_lsb 8 | |
1697 | #define xd_p_reg_cge_idx3_7_0 0xA286 | |
1698 | #define reg_cge_idx3_7_0_pos 0 | |
1699 | #define reg_cge_idx3_7_0_len 8 | |
1700 | #define reg_cge_idx3_7_0_lsb 0 | |
1701 | #define xd_p_reg_cge_idx3_12_8 0xA287 | |
1702 | #define reg_cge_idx3_12_8_pos 0 | |
1703 | #define reg_cge_idx3_12_8_len 5 | |
1704 | #define reg_cge_idx3_12_8_lsb 8 | |
1705 | #define xd_p_reg_cge_idx4_7_0 0xA288 | |
1706 | #define reg_cge_idx4_7_0_pos 0 | |
1707 | #define reg_cge_idx4_7_0_len 8 | |
1708 | #define reg_cge_idx4_7_0_lsb 0 | |
1709 | #define xd_p_reg_cge_idx4_12_8 0xA289 | |
1710 | #define reg_cge_idx4_12_8_pos 0 | |
1711 | #define reg_cge_idx4_12_8_len 5 | |
1712 | #define reg_cge_idx4_12_8_lsb 8 | |
1713 | #define xd_p_reg_cge_idx5_7_0 0xA28A | |
1714 | #define reg_cge_idx5_7_0_pos 0 | |
1715 | #define reg_cge_idx5_7_0_len 8 | |
1716 | #define reg_cge_idx5_7_0_lsb 0 | |
1717 | #define xd_p_reg_cge_idx5_12_8 0xA28B | |
1718 | #define reg_cge_idx5_12_8_pos 0 | |
1719 | #define reg_cge_idx5_12_8_len 5 | |
1720 | #define reg_cge_idx5_12_8_lsb 8 | |
1721 | #define xd_p_reg_cge_idx6_7_0 0xA28C | |
1722 | #define reg_cge_idx6_7_0_pos 0 | |
1723 | #define reg_cge_idx6_7_0_len 8 | |
1724 | #define reg_cge_idx6_7_0_lsb 0 | |
1725 | #define xd_p_reg_cge_idx6_12_8 0xA28D | |
1726 | #define reg_cge_idx6_12_8_pos 0 | |
1727 | #define reg_cge_idx6_12_8_len 5 | |
1728 | #define reg_cge_idx6_12_8_lsb 8 | |
1729 | #define xd_p_reg_cge_idx7_7_0 0xA28E | |
1730 | #define reg_cge_idx7_7_0_pos 0 | |
1731 | #define reg_cge_idx7_7_0_len 8 | |
1732 | #define reg_cge_idx7_7_0_lsb 0 | |
1733 | #define xd_p_reg_cge_idx7_12_8 0xA28F | |
1734 | #define reg_cge_idx7_12_8_pos 0 | |
1735 | #define reg_cge_idx7_12_8_len 5 | |
1736 | #define reg_cge_idx7_12_8_lsb 8 | |
1737 | #define xd_p_reg_cge_idx8_7_0 0xA290 | |
1738 | #define reg_cge_idx8_7_0_pos 0 | |
1739 | #define reg_cge_idx8_7_0_len 8 | |
1740 | #define reg_cge_idx8_7_0_lsb 0 | |
1741 | #define xd_p_reg_cge_idx8_12_8 0xA291 | |
1742 | #define reg_cge_idx8_12_8_pos 0 | |
1743 | #define reg_cge_idx8_12_8_len 5 | |
1744 | #define reg_cge_idx8_12_8_lsb 8 | |
1745 | #define xd_p_reg_cge_idx9_7_0 0xA292 | |
1746 | #define reg_cge_idx9_7_0_pos 0 | |
1747 | #define reg_cge_idx9_7_0_len 8 | |
1748 | #define reg_cge_idx9_7_0_lsb 0 | |
1749 | #define xd_p_reg_cge_idx9_12_8 0xA293 | |
1750 | #define reg_cge_idx9_12_8_pos 0 | |
1751 | #define reg_cge_idx9_12_8_len 5 | |
1752 | #define reg_cge_idx9_12_8_lsb 8 | |
1753 | #define xd_p_reg_cge_idx10_7_0 0xA294 | |
1754 | #define reg_cge_idx10_7_0_pos 0 | |
1755 | #define reg_cge_idx10_7_0_len 8 | |
1756 | #define reg_cge_idx10_7_0_lsb 0 | |
1757 | #define xd_p_reg_cge_idx10_12_8 0xA295 | |
1758 | #define reg_cge_idx10_12_8_pos 0 | |
1759 | #define reg_cge_idx10_12_8_len 5 | |
1760 | #define reg_cge_idx10_12_8_lsb 8 | |
1761 | #define xd_p_reg_cge_idx11_7_0 0xA296 | |
1762 | #define reg_cge_idx11_7_0_pos 0 | |
1763 | #define reg_cge_idx11_7_0_len 8 | |
1764 | #define reg_cge_idx11_7_0_lsb 0 | |
1765 | #define xd_p_reg_cge_idx11_12_8 0xA297 | |
1766 | #define reg_cge_idx11_12_8_pos 0 | |
1767 | #define reg_cge_idx11_12_8_len 5 | |
1768 | #define reg_cge_idx11_12_8_lsb 8 | |
1769 | #define xd_p_reg_cge_idx12_7_0 0xA298 | |
1770 | #define reg_cge_idx12_7_0_pos 0 | |
1771 | #define reg_cge_idx12_7_0_len 8 | |
1772 | #define reg_cge_idx12_7_0_lsb 0 | |
1773 | #define xd_p_reg_cge_idx12_12_8 0xA299 | |
1774 | #define reg_cge_idx12_12_8_pos 0 | |
1775 | #define reg_cge_idx12_12_8_len 5 | |
1776 | #define reg_cge_idx12_12_8_lsb 8 | |
1777 | #define xd_p_reg_cge_idx13_7_0 0xA29A | |
1778 | #define reg_cge_idx13_7_0_pos 0 | |
1779 | #define reg_cge_idx13_7_0_len 8 | |
1780 | #define reg_cge_idx13_7_0_lsb 0 | |
1781 | #define xd_p_reg_cge_idx13_12_8 0xA29B | |
1782 | #define reg_cge_idx13_12_8_pos 0 | |
1783 | #define reg_cge_idx13_12_8_len 5 | |
1784 | #define reg_cge_idx13_12_8_lsb 8 | |
1785 | #define xd_p_reg_cge_idx14_7_0 0xA29C | |
1786 | #define reg_cge_idx14_7_0_pos 0 | |
1787 | #define reg_cge_idx14_7_0_len 8 | |
1788 | #define reg_cge_idx14_7_0_lsb 0 | |
1789 | #define xd_p_reg_cge_idx14_12_8 0xA29D | |
1790 | #define reg_cge_idx14_12_8_pos 0 | |
1791 | #define reg_cge_idx14_12_8_len 5 | |
1792 | #define reg_cge_idx14_12_8_lsb 8 | |
1793 | #define xd_p_reg_cge_idx15_7_0 0xA29E | |
1794 | #define reg_cge_idx15_7_0_pos 0 | |
1795 | #define reg_cge_idx15_7_0_len 8 | |
1796 | #define reg_cge_idx15_7_0_lsb 0 | |
1797 | #define xd_p_reg_cge_idx15_12_8 0xA29F | |
1798 | #define reg_cge_idx15_12_8_pos 0 | |
1799 | #define reg_cge_idx15_12_8_len 5 | |
1800 | #define reg_cge_idx15_12_8_lsb 8 | |
1801 | #define xd_r_reg_fft_crc 0xA2A8 | |
1802 | #define reg_fft_crc_pos 0 | |
1803 | #define reg_fft_crc_len 8 | |
1804 | #define reg_fft_crc_lsb 0 | |
1805 | #define xd_p_fd_fft_shift_max 0xA2A9 | |
1806 | #define fd_fft_shift_max_pos 0 | |
1807 | #define fd_fft_shift_max_len 4 | |
1808 | #define fd_fft_shift_max_lsb 0 | |
1809 | #define xd_r_fd_fft_shift 0xA2A9 | |
1810 | #define fd_fft_shift_pos 4 | |
1811 | #define fd_fft_shift_len 4 | |
1812 | #define fd_fft_shift_lsb 0 | |
1813 | #define xd_r_fd_fft_frame_num 0xA2AA | |
1814 | #define fd_fft_frame_num_pos 0 | |
1815 | #define fd_fft_frame_num_len 2 | |
1816 | #define fd_fft_frame_num_lsb 0 | |
1817 | #define xd_r_fd_fft_symbol_count 0xA2AB | |
1818 | #define fd_fft_symbol_count_pos 0 | |
1819 | #define fd_fft_symbol_count_len 7 | |
1820 | #define fd_fft_symbol_count_lsb 0 | |
1821 | #define xd_r_reg_fft_idx_max_7_0 0xA2AC | |
1822 | #define reg_fft_idx_max_7_0_pos 0 | |
1823 | #define reg_fft_idx_max_7_0_len 8 | |
1824 | #define reg_fft_idx_max_7_0_lsb 0 | |
1825 | #define xd_r_reg_fft_idx_max_12_8 0xA2AD | |
1826 | #define reg_fft_idx_max_12_8_pos 0 | |
1827 | #define reg_fft_idx_max_12_8_len 5 | |
1828 | #define reg_fft_idx_max_12_8_lsb 8 | |
1829 | #define xd_p_reg_cge_program 0xA2AE | |
1830 | #define reg_cge_program_pos 0 | |
1831 | #define reg_cge_program_len 1 | |
1832 | #define reg_cge_program_lsb 0 | |
1833 | #define xd_p_reg_cge_fixed 0xA2AE | |
1834 | #define reg_cge_fixed_pos 1 | |
1835 | #define reg_cge_fixed_len 1 | |
1836 | #define reg_cge_fixed_lsb 0 | |
1837 | #define xd_p_reg_fft_rotate_en 0xA2AE | |
1838 | #define reg_fft_rotate_en_pos 2 | |
1839 | #define reg_fft_rotate_en_len 1 | |
1840 | #define reg_fft_rotate_en_lsb 0 | |
1841 | #define xd_p_reg_fft_rotate_base_4_0 0xA2AE | |
1842 | #define reg_fft_rotate_base_4_0_pos 3 | |
1843 | #define reg_fft_rotate_base_4_0_len 5 | |
1844 | #define reg_fft_rotate_base_4_0_lsb 0 | |
1845 | #define xd_p_reg_fft_rotate_base_12_5 0xA2AF | |
1846 | #define reg_fft_rotate_base_12_5_pos 0 | |
1847 | #define reg_fft_rotate_base_12_5_len 8 | |
1848 | #define reg_fft_rotate_base_12_5_lsb 5 | |
1849 | #define xd_p_reg_gp_trigger_fd 0xA2B8 | |
1850 | #define reg_gp_trigger_fd_pos 0 | |
1851 | #define reg_gp_trigger_fd_len 1 | |
1852 | #define reg_gp_trigger_fd_lsb 0 | |
1853 | #define xd_p_reg_trigger_sel_fd 0xA2B8 | |
1854 | #define reg_trigger_sel_fd_pos 1 | |
1855 | #define reg_trigger_sel_fd_len 2 | |
1856 | #define reg_trigger_sel_fd_lsb 0 | |
1857 | #define xd_p_reg_trigger_module_sel_fd 0xA2B9 | |
1858 | #define reg_trigger_module_sel_fd_pos 0 | |
1859 | #define reg_trigger_module_sel_fd_len 6 | |
1860 | #define reg_trigger_module_sel_fd_lsb 0 | |
1861 | #define xd_p_reg_trigger_set_sel_fd 0xA2BA | |
1862 | #define reg_trigger_set_sel_fd_pos 0 | |
1863 | #define reg_trigger_set_sel_fd_len 6 | |
1864 | #define reg_trigger_set_sel_fd_lsb 0 | |
1865 | #define xd_p_reg_fd_noname_7_0 0xA2BC | |
1866 | #define reg_fd_noname_7_0_pos 0 | |
1867 | #define reg_fd_noname_7_0_len 8 | |
1868 | #define reg_fd_noname_7_0_lsb 0 | |
1869 | #define xd_p_reg_fd_noname_15_8 0xA2BD | |
1870 | #define reg_fd_noname_15_8_pos 0 | |
1871 | #define reg_fd_noname_15_8_len 8 | |
1872 | #define reg_fd_noname_15_8_lsb 8 | |
1873 | #define xd_p_reg_fd_noname_23_16 0xA2BE | |
1874 | #define reg_fd_noname_23_16_pos 0 | |
1875 | #define reg_fd_noname_23_16_len 8 | |
1876 | #define reg_fd_noname_23_16_lsb 16 | |
1877 | #define xd_p_reg_fd_noname_31_24 0xA2BF | |
1878 | #define reg_fd_noname_31_24_pos 0 | |
1879 | #define reg_fd_noname_31_24_len 8 | |
1880 | #define reg_fd_noname_31_24_lsb 24 | |
1881 | #define xd_r_fd_fpcc_cp_corr_signn 0xA2C0 | |
1882 | #define fd_fpcc_cp_corr_signn_pos 0 | |
1883 | #define fd_fpcc_cp_corr_signn_len 8 | |
1884 | #define fd_fpcc_cp_corr_signn_lsb 0 | |
1885 | #define xd_p_reg_feq_s1 0xA2C1 | |
1886 | #define reg_feq_s1_pos 0 | |
1887 | #define reg_feq_s1_len 5 | |
1888 | #define reg_feq_s1_lsb 0 | |
1889 | #define xd_p_fd_fpcc_cp_corr_tone_th 0xA2C2 | |
1890 | #define fd_fpcc_cp_corr_tone_th_pos 0 | |
1891 | #define fd_fpcc_cp_corr_tone_th_len 6 | |
1892 | #define fd_fpcc_cp_corr_tone_th_lsb 0 | |
1893 | #define xd_p_fd_fpcc_cp_corr_symbol_log_th 0xA2C3 | |
1894 | #define fd_fpcc_cp_corr_symbol_log_th_pos 0 | |
1895 | #define fd_fpcc_cp_corr_symbol_log_th_len 4 | |
1896 | #define fd_fpcc_cp_corr_symbol_log_th_lsb 0 | |
1897 | #define xd_p_fd_fpcc_cp_corr_int 0xA2C4 | |
1898 | #define fd_fpcc_cp_corr_int_pos 0 | |
1899 | #define fd_fpcc_cp_corr_int_len 1 | |
1900 | #define fd_fpcc_cp_corr_int_lsb 0 | |
1901 | #define xd_p_reg_sfoe_ns_7_0 0xA320 | |
1902 | #define reg_sfoe_ns_7_0_pos 0 | |
1903 | #define reg_sfoe_ns_7_0_len 8 | |
1904 | #define reg_sfoe_ns_7_0_lsb 0 | |
1905 | #define xd_p_reg_sfoe_ns_14_8 0xA321 | |
1906 | #define reg_sfoe_ns_14_8_pos 0 | |
1907 | #define reg_sfoe_ns_14_8_len 7 | |
1908 | #define reg_sfoe_ns_14_8_lsb 8 | |
1909 | #define xd_p_reg_sfoe_c1_7_0 0xA322 | |
1910 | #define reg_sfoe_c1_7_0_pos 0 | |
1911 | #define reg_sfoe_c1_7_0_len 8 | |
1912 | #define reg_sfoe_c1_7_0_lsb 0 | |
1913 | #define xd_p_reg_sfoe_c1_15_8 0xA323 | |
1914 | #define reg_sfoe_c1_15_8_pos 0 | |
1915 | #define reg_sfoe_c1_15_8_len 8 | |
1916 | #define reg_sfoe_c1_15_8_lsb 8 | |
1917 | #define xd_p_reg_sfoe_c1_17_16 0xA324 | |
1918 | #define reg_sfoe_c1_17_16_pos 0 | |
1919 | #define reg_sfoe_c1_17_16_len 2 | |
1920 | #define reg_sfoe_c1_17_16_lsb 16 | |
1921 | #define xd_p_reg_sfoe_c2_7_0 0xA325 | |
1922 | #define reg_sfoe_c2_7_0_pos 0 | |
1923 | #define reg_sfoe_c2_7_0_len 8 | |
1924 | #define reg_sfoe_c2_7_0_lsb 0 | |
1925 | #define xd_p_reg_sfoe_c2_15_8 0xA326 | |
1926 | #define reg_sfoe_c2_15_8_pos 0 | |
1927 | #define reg_sfoe_c2_15_8_len 8 | |
1928 | #define reg_sfoe_c2_15_8_lsb 8 | |
1929 | #define xd_p_reg_sfoe_c2_17_16 0xA327 | |
1930 | #define reg_sfoe_c2_17_16_pos 0 | |
1931 | #define reg_sfoe_c2_17_16_len 2 | |
1932 | #define reg_sfoe_c2_17_16_lsb 16 | |
1933 | #define xd_r_reg_sfoe_out_9_2 0xA328 | |
1934 | #define reg_sfoe_out_9_2_pos 0 | |
1935 | #define reg_sfoe_out_9_2_len 8 | |
1936 | #define reg_sfoe_out_9_2_lsb 0 | |
1937 | #define xd_r_reg_sfoe_out_1_0 0xA329 | |
1938 | #define reg_sfoe_out_1_0_pos 0 | |
1939 | #define reg_sfoe_out_1_0_len 2 | |
1940 | #define reg_sfoe_out_1_0_lsb 0 | |
1941 | #define xd_p_reg_sfoe_lm_counter_th 0xA32A | |
1942 | #define reg_sfoe_lm_counter_th_pos 0 | |
1943 | #define reg_sfoe_lm_counter_th_len 4 | |
1944 | #define reg_sfoe_lm_counter_th_lsb 0 | |
1945 | #define xd_p_reg_sfoe_convg_th 0xA32B | |
1946 | #define reg_sfoe_convg_th_pos 0 | |
1947 | #define reg_sfoe_convg_th_len 8 | |
1948 | #define reg_sfoe_convg_th_lsb 0 | |
1949 | #define xd_p_reg_sfoe_divg_th 0xA32C | |
1950 | #define reg_sfoe_divg_th_pos 0 | |
1951 | #define reg_sfoe_divg_th_len 8 | |
1952 | #define reg_sfoe_divg_th_lsb 0 | |
1953 | #define xd_p_fd_tpsd_en 0xA330 | |
1954 | #define fd_tpsd_en_pos 0 | |
1955 | #define fd_tpsd_en_len 1 | |
1956 | #define fd_tpsd_en_lsb 0 | |
1957 | #define xd_p_fd_tpsd_dis 0xA330 | |
1958 | #define fd_tpsd_dis_pos 1 | |
1959 | #define fd_tpsd_dis_len 1 | |
1960 | #define fd_tpsd_dis_lsb 0 | |
1961 | #define xd_p_fd_tpsd_rst 0xA330 | |
1962 | #define fd_tpsd_rst_pos 2 | |
1963 | #define fd_tpsd_rst_len 1 | |
1964 | #define fd_tpsd_rst_lsb 0 | |
1965 | #define xd_p_fd_tpsd_lock 0xA330 | |
1966 | #define fd_tpsd_lock_pos 3 | |
1967 | #define fd_tpsd_lock_len 1 | |
1968 | #define fd_tpsd_lock_lsb 0 | |
1969 | #define xd_r_fd_tpsd_s19 0xA330 | |
1970 | #define fd_tpsd_s19_pos 4 | |
1971 | #define fd_tpsd_s19_len 1 | |
1972 | #define fd_tpsd_s19_lsb 0 | |
1973 | #define xd_r_fd_tpsd_s17 0xA330 | |
1974 | #define fd_tpsd_s17_pos 5 | |
1975 | #define fd_tpsd_s17_len 1 | |
1976 | #define fd_tpsd_s17_lsb 0 | |
1977 | #define xd_p_fd_sfr_ste_en 0xA331 | |
1978 | #define fd_sfr_ste_en_pos 0 | |
1979 | #define fd_sfr_ste_en_len 1 | |
1980 | #define fd_sfr_ste_en_lsb 0 | |
1981 | #define xd_p_fd_sfr_ste_dis 0xA331 | |
1982 | #define fd_sfr_ste_dis_pos 1 | |
1983 | #define fd_sfr_ste_dis_len 1 | |
1984 | #define fd_sfr_ste_dis_lsb 0 | |
1985 | #define xd_p_fd_sfr_ste_rst 0xA331 | |
1986 | #define fd_sfr_ste_rst_pos 2 | |
1987 | #define fd_sfr_ste_rst_len 1 | |
1988 | #define fd_sfr_ste_rst_lsb 0 | |
1989 | #define xd_p_fd_sfr_ste_mode 0xA331 | |
1990 | #define fd_sfr_ste_mode_pos 3 | |
1991 | #define fd_sfr_ste_mode_len 1 | |
1992 | #define fd_sfr_ste_mode_lsb 0 | |
1993 | #define xd_p_fd_sfr_ste_done 0xA331 | |
1994 | #define fd_sfr_ste_done_pos 4 | |
1995 | #define fd_sfr_ste_done_len 1 | |
1996 | #define fd_sfr_ste_done_lsb 0 | |
1997 | #define xd_p_reg_cfoe_ffoe_en 0xA332 | |
1998 | #define reg_cfoe_ffoe_en_pos 0 | |
1999 | #define reg_cfoe_ffoe_en_len 1 | |
2000 | #define reg_cfoe_ffoe_en_lsb 0 | |
2001 | #define xd_p_reg_cfoe_ffoe_dis 0xA332 | |
2002 | #define reg_cfoe_ffoe_dis_pos 1 | |
2003 | #define reg_cfoe_ffoe_dis_len 1 | |
2004 | #define reg_cfoe_ffoe_dis_lsb 0 | |
2005 | #define xd_p_reg_cfoe_ffoe_rst 0xA332 | |
2006 | #define reg_cfoe_ffoe_rst_pos 2 | |
2007 | #define reg_cfoe_ffoe_rst_len 1 | |
2008 | #define reg_cfoe_ffoe_rst_lsb 0 | |
2009 | #define xd_p_reg_cfoe_ifoe_en 0xA332 | |
2010 | #define reg_cfoe_ifoe_en_pos 3 | |
2011 | #define reg_cfoe_ifoe_en_len 1 | |
2012 | #define reg_cfoe_ifoe_en_lsb 0 | |
2013 | #define xd_p_reg_cfoe_ifoe_dis 0xA332 | |
2014 | #define reg_cfoe_ifoe_dis_pos 4 | |
2015 | #define reg_cfoe_ifoe_dis_len 1 | |
2016 | #define reg_cfoe_ifoe_dis_lsb 0 | |
2017 | #define xd_p_reg_cfoe_ifoe_rst 0xA332 | |
2018 | #define reg_cfoe_ifoe_rst_pos 5 | |
2019 | #define reg_cfoe_ifoe_rst_len 1 | |
2020 | #define reg_cfoe_ifoe_rst_lsb 0 | |
2021 | #define xd_p_reg_cfoe_fot_en 0xA332 | |
2022 | #define reg_cfoe_fot_en_pos 6 | |
2023 | #define reg_cfoe_fot_en_len 1 | |
2024 | #define reg_cfoe_fot_en_lsb 0 | |
2025 | #define xd_p_reg_cfoe_fot_lm_en 0xA332 | |
2026 | #define reg_cfoe_fot_lm_en_pos 7 | |
2027 | #define reg_cfoe_fot_lm_en_len 1 | |
2028 | #define reg_cfoe_fot_lm_en_lsb 0 | |
2029 | #define xd_p_reg_cfoe_fot_rst 0xA333 | |
2030 | #define reg_cfoe_fot_rst_pos 0 | |
2031 | #define reg_cfoe_fot_rst_len 1 | |
2032 | #define reg_cfoe_fot_rst_lsb 0 | |
2033 | #define xd_r_fd_cfoe_ffoe_done 0xA333 | |
2034 | #define fd_cfoe_ffoe_done_pos 1 | |
2035 | #define fd_cfoe_ffoe_done_len 1 | |
2036 | #define fd_cfoe_ffoe_done_lsb 0 | |
2037 | #define xd_p_fd_cfoe_metric_vld 0xA333 | |
2038 | #define fd_cfoe_metric_vld_pos 2 | |
2039 | #define fd_cfoe_metric_vld_len 1 | |
2040 | #define fd_cfoe_metric_vld_lsb 0 | |
2041 | #define xd_p_reg_cfoe_ifod_vld 0xA333 | |
2042 | #define reg_cfoe_ifod_vld_pos 3 | |
2043 | #define reg_cfoe_ifod_vld_len 1 | |
2044 | #define reg_cfoe_ifod_vld_lsb 0 | |
2045 | #define xd_r_fd_cfoe_ifoe_done 0xA333 | |
2046 | #define fd_cfoe_ifoe_done_pos 4 | |
2047 | #define fd_cfoe_ifoe_done_len 1 | |
2048 | #define fd_cfoe_ifoe_done_lsb 0 | |
2049 | #define xd_r_fd_cfoe_fot_valid 0xA333 | |
2050 | #define fd_cfoe_fot_valid_pos 5 | |
2051 | #define fd_cfoe_fot_valid_len 1 | |
2052 | #define fd_cfoe_fot_valid_lsb 0 | |
2053 | #define xd_p_reg_cfoe_divg_int 0xA333 | |
2054 | #define reg_cfoe_divg_int_pos 6 | |
2055 | #define reg_cfoe_divg_int_len 1 | |
2056 | #define reg_cfoe_divg_int_lsb 0 | |
2057 | #define xd_r_reg_cfoe_divg_flag 0xA333 | |
2058 | #define reg_cfoe_divg_flag_pos 7 | |
2059 | #define reg_cfoe_divg_flag_len 1 | |
2060 | #define reg_cfoe_divg_flag_lsb 0 | |
2061 | #define xd_p_reg_sfoe_en 0xA334 | |
2062 | #define reg_sfoe_en_pos 0 | |
2063 | #define reg_sfoe_en_len 1 | |
2064 | #define reg_sfoe_en_lsb 0 | |
2065 | #define xd_p_reg_sfoe_dis 0xA334 | |
2066 | #define reg_sfoe_dis_pos 1 | |
2067 | #define reg_sfoe_dis_len 1 | |
2068 | #define reg_sfoe_dis_lsb 0 | |
2069 | #define xd_p_reg_sfoe_rst 0xA334 | |
2070 | #define reg_sfoe_rst_pos 2 | |
2071 | #define reg_sfoe_rst_len 1 | |
2072 | #define reg_sfoe_rst_lsb 0 | |
2073 | #define xd_p_reg_sfoe_vld_int 0xA334 | |
2074 | #define reg_sfoe_vld_int_pos 3 | |
2075 | #define reg_sfoe_vld_int_len 1 | |
2076 | #define reg_sfoe_vld_int_lsb 0 | |
2077 | #define xd_p_reg_sfoe_lm_en 0xA334 | |
2078 | #define reg_sfoe_lm_en_pos 4 | |
2079 | #define reg_sfoe_lm_en_len 1 | |
2080 | #define reg_sfoe_lm_en_lsb 0 | |
2081 | #define xd_p_reg_sfoe_divg_int 0xA334 | |
2082 | #define reg_sfoe_divg_int_pos 5 | |
2083 | #define reg_sfoe_divg_int_len 1 | |
2084 | #define reg_sfoe_divg_int_lsb 0 | |
2085 | #define xd_r_reg_sfoe_divg_flag 0xA334 | |
2086 | #define reg_sfoe_divg_flag_pos 6 | |
2087 | #define reg_sfoe_divg_flag_len 1 | |
2088 | #define reg_sfoe_divg_flag_lsb 0 | |
2089 | #define xd_p_reg_fft_rst 0xA335 | |
2090 | #define reg_fft_rst_pos 0 | |
2091 | #define reg_fft_rst_len 1 | |
2092 | #define reg_fft_rst_lsb 0 | |
2093 | #define xd_p_reg_fft_fast_beacon 0xA335 | |
2094 | #define reg_fft_fast_beacon_pos 1 | |
2095 | #define reg_fft_fast_beacon_len 1 | |
2096 | #define reg_fft_fast_beacon_lsb 0 | |
2097 | #define xd_p_reg_fft_fast_valid 0xA335 | |
2098 | #define reg_fft_fast_valid_pos 2 | |
2099 | #define reg_fft_fast_valid_len 1 | |
2100 | #define reg_fft_fast_valid_lsb 0 | |
2101 | #define xd_p_reg_fft_mask_en 0xA335 | |
2102 | #define reg_fft_mask_en_pos 3 | |
2103 | #define reg_fft_mask_en_len 1 | |
2104 | #define reg_fft_mask_en_lsb 0 | |
2105 | #define xd_p_reg_fft_crc_en 0xA335 | |
2106 | #define reg_fft_crc_en_pos 4 | |
2107 | #define reg_fft_crc_en_len 1 | |
2108 | #define reg_fft_crc_en_lsb 0 | |
2109 | #define xd_p_reg_finr_en 0xA336 | |
2110 | #define reg_finr_en_pos 0 | |
2111 | #define reg_finr_en_len 1 | |
2112 | #define reg_finr_en_lsb 0 | |
2113 | #define xd_p_fd_fste_en 0xA337 | |
2114 | #define fd_fste_en_pos 1 | |
2115 | #define fd_fste_en_len 1 | |
2116 | #define fd_fste_en_lsb 0 | |
2117 | #define xd_p_fd_sqi_tps_level_shift 0xA338 | |
2118 | #define fd_sqi_tps_level_shift_pos 0 | |
2119 | #define fd_sqi_tps_level_shift_len 8 | |
2120 | #define fd_sqi_tps_level_shift_lsb 0 | |
2121 | #define xd_p_fd_pilot_ma_len 0xA339 | |
2122 | #define fd_pilot_ma_len_pos 0 | |
2123 | #define fd_pilot_ma_len_len 6 | |
2124 | #define fd_pilot_ma_len_lsb 0 | |
2125 | #define xd_p_fd_tps_ma_len 0xA33A | |
2126 | #define fd_tps_ma_len_pos 0 | |
2127 | #define fd_tps_ma_len_len 6 | |
2128 | #define fd_tps_ma_len_lsb 0 | |
2129 | #define xd_p_fd_sqi_s3 0xA33B | |
2130 | #define fd_sqi_s3_pos 0 | |
2131 | #define fd_sqi_s3_len 8 | |
2132 | #define fd_sqi_s3_lsb 0 | |
2133 | #define xd_p_fd_sqi_dummy_reg_0 0xA33C | |
2134 | #define fd_sqi_dummy_reg_0_pos 0 | |
2135 | #define fd_sqi_dummy_reg_0_len 1 | |
2136 | #define fd_sqi_dummy_reg_0_lsb 0 | |
2137 | #define xd_p_fd_sqi_debug_sel 0xA33C | |
2138 | #define fd_sqi_debug_sel_pos 1 | |
2139 | #define fd_sqi_debug_sel_len 2 | |
2140 | #define fd_sqi_debug_sel_lsb 0 | |
2141 | #define xd_p_fd_sqi_s2 0xA33C | |
2142 | #define fd_sqi_s2_pos 3 | |
2143 | #define fd_sqi_s2_len 5 | |
2144 | #define fd_sqi_s2_lsb 0 | |
2145 | #define xd_p_fd_sqi_dummy_reg_1 0xA33D | |
2146 | #define fd_sqi_dummy_reg_1_pos 0 | |
2147 | #define fd_sqi_dummy_reg_1_len 1 | |
2148 | #define fd_sqi_dummy_reg_1_lsb 0 | |
2149 | #define xd_p_fd_inr_ignore 0xA33D | |
2150 | #define fd_inr_ignore_pos 1 | |
2151 | #define fd_inr_ignore_len 1 | |
2152 | #define fd_inr_ignore_lsb 0 | |
2153 | #define xd_p_fd_pilot_ignore 0xA33D | |
2154 | #define fd_pilot_ignore_pos 2 | |
2155 | #define fd_pilot_ignore_len 1 | |
2156 | #define fd_pilot_ignore_lsb 0 | |
2157 | #define xd_p_fd_etps_ignore 0xA33D | |
2158 | #define fd_etps_ignore_pos 3 | |
2159 | #define fd_etps_ignore_len 1 | |
2160 | #define fd_etps_ignore_lsb 0 | |
2161 | #define xd_p_fd_sqi_s1 0xA33D | |
2162 | #define fd_sqi_s1_pos 4 | |
2163 | #define fd_sqi_s1_len 4 | |
2164 | #define fd_sqi_s1_lsb 0 | |
2165 | #define xd_p_reg_fste_ehw_7_0 0xA33E | |
2166 | #define reg_fste_ehw_7_0_pos 0 | |
2167 | #define reg_fste_ehw_7_0_len 8 | |
2168 | #define reg_fste_ehw_7_0_lsb 0 | |
2169 | #define xd_p_reg_fste_ehw_9_8 0xA33F | |
2170 | #define reg_fste_ehw_9_8_pos 0 | |
2171 | #define reg_fste_ehw_9_8_len 2 | |
2172 | #define reg_fste_ehw_9_8_lsb 8 | |
2173 | #define xd_p_reg_fste_i_adj_vld 0xA33F | |
2174 | #define reg_fste_i_adj_vld_pos 2 | |
2175 | #define reg_fste_i_adj_vld_len 1 | |
2176 | #define reg_fste_i_adj_vld_lsb 0 | |
2177 | #define xd_p_reg_fste_phase_ini_7_0 0xA340 | |
2178 | #define reg_fste_phase_ini_7_0_pos 0 | |
2179 | #define reg_fste_phase_ini_7_0_len 8 | |
2180 | #define reg_fste_phase_ini_7_0_lsb 0 | |
2181 | #define xd_p_reg_fste_phase_ini_11_8 0xA341 | |
2182 | #define reg_fste_phase_ini_11_8_pos 0 | |
2183 | #define reg_fste_phase_ini_11_8_len 4 | |
2184 | #define reg_fste_phase_ini_11_8_lsb 8 | |
2185 | #define xd_p_reg_fste_phase_inc_3_0 0xA341 | |
2186 | #define reg_fste_phase_inc_3_0_pos 4 | |
2187 | #define reg_fste_phase_inc_3_0_len 4 | |
2188 | #define reg_fste_phase_inc_3_0_lsb 0 | |
2189 | #define xd_p_reg_fste_phase_inc_11_4 0xA342 | |
2190 | #define reg_fste_phase_inc_11_4_pos 0 | |
2191 | #define reg_fste_phase_inc_11_4_len 8 | |
2192 | #define reg_fste_phase_inc_11_4_lsb 4 | |
2193 | #define xd_p_reg_fste_acum_cost_cnt_max 0xA343 | |
2194 | #define reg_fste_acum_cost_cnt_max_pos 0 | |
2195 | #define reg_fste_acum_cost_cnt_max_len 4 | |
2196 | #define reg_fste_acum_cost_cnt_max_lsb 0 | |
2197 | #define xd_p_reg_fste_step_size_std 0xA343 | |
2198 | #define reg_fste_step_size_std_pos 4 | |
2199 | #define reg_fste_step_size_std_len 4 | |
2200 | #define reg_fste_step_size_std_lsb 0 | |
2201 | #define xd_p_reg_fste_step_size_max 0xA344 | |
2202 | #define reg_fste_step_size_max_pos 0 | |
2203 | #define reg_fste_step_size_max_len 4 | |
2204 | #define reg_fste_step_size_max_lsb 0 | |
2205 | #define xd_p_reg_fste_step_size_min 0xA344 | |
2206 | #define reg_fste_step_size_min_pos 4 | |
2207 | #define reg_fste_step_size_min_len 4 | |
2208 | #define reg_fste_step_size_min_lsb 0 | |
2209 | #define xd_p_reg_fste_frac_step_size_7_0 0xA345 | |
2210 | #define reg_fste_frac_step_size_7_0_pos 0 | |
2211 | #define reg_fste_frac_step_size_7_0_len 8 | |
2212 | #define reg_fste_frac_step_size_7_0_lsb 0 | |
2213 | #define xd_p_reg_fste_frac_step_size_15_8 0xA346 | |
2214 | #define reg_fste_frac_step_size_15_8_pos 0 | |
2215 | #define reg_fste_frac_step_size_15_8_len 8 | |
2216 | #define reg_fste_frac_step_size_15_8_lsb 8 | |
2217 | #define xd_p_reg_fste_frac_step_size_19_16 0xA347 | |
2218 | #define reg_fste_frac_step_size_19_16_pos 0 | |
2219 | #define reg_fste_frac_step_size_19_16_len 4 | |
2220 | #define reg_fste_frac_step_size_19_16_lsb 16 | |
2221 | #define xd_p_reg_fste_rpd_dir_cnt_max 0xA347 | |
2222 | #define reg_fste_rpd_dir_cnt_max_pos 4 | |
2223 | #define reg_fste_rpd_dir_cnt_max_len 4 | |
2224 | #define reg_fste_rpd_dir_cnt_max_lsb 0 | |
2225 | #define xd_p_reg_fste_ehs 0xA348 | |
2226 | #define reg_fste_ehs_pos 0 | |
2227 | #define reg_fste_ehs_len 4 | |
2228 | #define reg_fste_ehs_lsb 0 | |
2229 | #define xd_p_reg_fste_frac_cost_cnt_max_3_0 0xA348 | |
2230 | #define reg_fste_frac_cost_cnt_max_3_0_pos 4 | |
2231 | #define reg_fste_frac_cost_cnt_max_3_0_len 4 | |
2232 | #define reg_fste_frac_cost_cnt_max_3_0_lsb 0 | |
2233 | #define xd_p_reg_fste_frac_cost_cnt_max_9_4 0xA349 | |
2234 | #define reg_fste_frac_cost_cnt_max_9_4_pos 0 | |
2235 | #define reg_fste_frac_cost_cnt_max_9_4_len 6 | |
2236 | #define reg_fste_frac_cost_cnt_max_9_4_lsb 4 | |
2237 | #define xd_p_reg_fste_w0_7_0 0xA34A | |
2238 | #define reg_fste_w0_7_0_pos 0 | |
2239 | #define reg_fste_w0_7_0_len 8 | |
2240 | #define reg_fste_w0_7_0_lsb 0 | |
2241 | #define xd_p_reg_fste_w0_11_8 0xA34B | |
2242 | #define reg_fste_w0_11_8_pos 0 | |
2243 | #define reg_fste_w0_11_8_len 4 | |
2244 | #define reg_fste_w0_11_8_lsb 8 | |
2245 | #define xd_p_reg_fste_w1_3_0 0xA34B | |
2246 | #define reg_fste_w1_3_0_pos 4 | |
2247 | #define reg_fste_w1_3_0_len 4 | |
2248 | #define reg_fste_w1_3_0_lsb 0 | |
2249 | #define xd_p_reg_fste_w1_11_4 0xA34C | |
2250 | #define reg_fste_w1_11_4_pos 0 | |
2251 | #define reg_fste_w1_11_4_len 8 | |
2252 | #define reg_fste_w1_11_4_lsb 4 | |
2253 | #define xd_p_reg_fste_w2_7_0 0xA34D | |
2254 | #define reg_fste_w2_7_0_pos 0 | |
2255 | #define reg_fste_w2_7_0_len 8 | |
2256 | #define reg_fste_w2_7_0_lsb 0 | |
2257 | #define xd_p_reg_fste_w2_11_8 0xA34E | |
2258 | #define reg_fste_w2_11_8_pos 0 | |
2259 | #define reg_fste_w2_11_8_len 4 | |
2260 | #define reg_fste_w2_11_8_lsb 8 | |
2261 | #define xd_p_reg_fste_w3_3_0 0xA34E | |
2262 | #define reg_fste_w3_3_0_pos 4 | |
2263 | #define reg_fste_w3_3_0_len 4 | |
2264 | #define reg_fste_w3_3_0_lsb 0 | |
2265 | #define xd_p_reg_fste_w3_11_4 0xA34F | |
2266 | #define reg_fste_w3_11_4_pos 0 | |
2267 | #define reg_fste_w3_11_4_len 8 | |
2268 | #define reg_fste_w3_11_4_lsb 4 | |
2269 | #define xd_p_reg_fste_w4_7_0 0xA350 | |
2270 | #define reg_fste_w4_7_0_pos 0 | |
2271 | #define reg_fste_w4_7_0_len 8 | |
2272 | #define reg_fste_w4_7_0_lsb 0 | |
2273 | #define xd_p_reg_fste_w4_11_8 0xA351 | |
2274 | #define reg_fste_w4_11_8_pos 0 | |
2275 | #define reg_fste_w4_11_8_len 4 | |
2276 | #define reg_fste_w4_11_8_lsb 8 | |
2277 | #define xd_p_reg_fste_w5_3_0 0xA351 | |
2278 | #define reg_fste_w5_3_0_pos 4 | |
2279 | #define reg_fste_w5_3_0_len 4 | |
2280 | #define reg_fste_w5_3_0_lsb 0 | |
2281 | #define xd_p_reg_fste_w5_11_4 0xA352 | |
2282 | #define reg_fste_w5_11_4_pos 0 | |
2283 | #define reg_fste_w5_11_4_len 8 | |
2284 | #define reg_fste_w5_11_4_lsb 4 | |
2285 | #define xd_p_reg_fste_w6_7_0 0xA353 | |
2286 | #define reg_fste_w6_7_0_pos 0 | |
2287 | #define reg_fste_w6_7_0_len 8 | |
2288 | #define reg_fste_w6_7_0_lsb 0 | |
2289 | #define xd_p_reg_fste_w6_11_8 0xA354 | |
2290 | #define reg_fste_w6_11_8_pos 0 | |
2291 | #define reg_fste_w6_11_8_len 4 | |
2292 | #define reg_fste_w6_11_8_lsb 8 | |
2293 | #define xd_p_reg_fste_w7_3_0 0xA354 | |
2294 | #define reg_fste_w7_3_0_pos 4 | |
2295 | #define reg_fste_w7_3_0_len 4 | |
2296 | #define reg_fste_w7_3_0_lsb 0 | |
2297 | #define xd_p_reg_fste_w7_11_4 0xA355 | |
2298 | #define reg_fste_w7_11_4_pos 0 | |
2299 | #define reg_fste_w7_11_4_len 8 | |
2300 | #define reg_fste_w7_11_4_lsb 4 | |
2301 | #define xd_p_reg_fste_w8_7_0 0xA356 | |
2302 | #define reg_fste_w8_7_0_pos 0 | |
2303 | #define reg_fste_w8_7_0_len 8 | |
2304 | #define reg_fste_w8_7_0_lsb 0 | |
2305 | #define xd_p_reg_fste_w8_11_8 0xA357 | |
2306 | #define reg_fste_w8_11_8_pos 0 | |
2307 | #define reg_fste_w8_11_8_len 4 | |
2308 | #define reg_fste_w8_11_8_lsb 8 | |
2309 | #define xd_p_reg_fste_w9_3_0 0xA357 | |
2310 | #define reg_fste_w9_3_0_pos 4 | |
2311 | #define reg_fste_w9_3_0_len 4 | |
2312 | #define reg_fste_w9_3_0_lsb 0 | |
2313 | #define xd_p_reg_fste_w9_11_4 0xA358 | |
2314 | #define reg_fste_w9_11_4_pos 0 | |
2315 | #define reg_fste_w9_11_4_len 8 | |
2316 | #define reg_fste_w9_11_4_lsb 4 | |
2317 | #define xd_p_reg_fste_wa_7_0 0xA359 | |
2318 | #define reg_fste_wa_7_0_pos 0 | |
2319 | #define reg_fste_wa_7_0_len 8 | |
2320 | #define reg_fste_wa_7_0_lsb 0 | |
2321 | #define xd_p_reg_fste_wa_11_8 0xA35A | |
2322 | #define reg_fste_wa_11_8_pos 0 | |
2323 | #define reg_fste_wa_11_8_len 4 | |
2324 | #define reg_fste_wa_11_8_lsb 8 | |
2325 | #define xd_p_reg_fste_wb_3_0 0xA35A | |
2326 | #define reg_fste_wb_3_0_pos 4 | |
2327 | #define reg_fste_wb_3_0_len 4 | |
2328 | #define reg_fste_wb_3_0_lsb 0 | |
2329 | #define xd_p_reg_fste_wb_11_4 0xA35B | |
2330 | #define reg_fste_wb_11_4_pos 0 | |
2331 | #define reg_fste_wb_11_4_len 8 | |
2332 | #define reg_fste_wb_11_4_lsb 4 | |
2333 | #define xd_r_fd_fste_i_adj 0xA35C | |
2334 | #define fd_fste_i_adj_pos 0 | |
2335 | #define fd_fste_i_adj_len 5 | |
2336 | #define fd_fste_i_adj_lsb 0 | |
2337 | #define xd_r_fd_fste_f_adj_7_0 0xA35D | |
2338 | #define fd_fste_f_adj_7_0_pos 0 | |
2339 | #define fd_fste_f_adj_7_0_len 8 | |
2340 | #define fd_fste_f_adj_7_0_lsb 0 | |
2341 | #define xd_r_fd_fste_f_adj_15_8 0xA35E | |
2342 | #define fd_fste_f_adj_15_8_pos 0 | |
2343 | #define fd_fste_f_adj_15_8_len 8 | |
2344 | #define fd_fste_f_adj_15_8_lsb 8 | |
2345 | #define xd_r_fd_fste_f_adj_19_16 0xA35F | |
2346 | #define fd_fste_f_adj_19_16_pos 0 | |
2347 | #define fd_fste_f_adj_19_16_len 4 | |
2348 | #define fd_fste_f_adj_19_16_lsb 16 | |
2349 | #define xd_p_reg_feq_Leak_Bypass 0xA366 | |
2350 | #define reg_feq_Leak_Bypass_pos 0 | |
2351 | #define reg_feq_Leak_Bypass_len 1 | |
2352 | #define reg_feq_Leak_Bypass_lsb 0 | |
2353 | #define xd_p_reg_feq_Leak_Mneg1 0xA366 | |
2354 | #define reg_feq_Leak_Mneg1_pos 1 | |
2355 | #define reg_feq_Leak_Mneg1_len 3 | |
2356 | #define reg_feq_Leak_Mneg1_lsb 0 | |
2357 | #define xd_p_reg_feq_Leak_B_ShiftQ 0xA366 | |
2358 | #define reg_feq_Leak_B_ShiftQ_pos 4 | |
2359 | #define reg_feq_Leak_B_ShiftQ_len 4 | |
2360 | #define reg_feq_Leak_B_ShiftQ_lsb 0 | |
2361 | #define xd_p_reg_feq_Leak_B_Float0 0xA367 | |
2362 | #define reg_feq_Leak_B_Float0_pos 0 | |
2363 | #define reg_feq_Leak_B_Float0_len 8 | |
2364 | #define reg_feq_Leak_B_Float0_lsb 0 | |
2365 | #define xd_p_reg_feq_Leak_B_Float1 0xA368 | |
2366 | #define reg_feq_Leak_B_Float1_pos 0 | |
2367 | #define reg_feq_Leak_B_Float1_len 8 | |
2368 | #define reg_feq_Leak_B_Float1_lsb 0 | |
2369 | #define xd_p_reg_feq_Leak_B_Float2 0xA369 | |
2370 | #define reg_feq_Leak_B_Float2_pos 0 | |
2371 | #define reg_feq_Leak_B_Float2_len 8 | |
2372 | #define reg_feq_Leak_B_Float2_lsb 0 | |
2373 | #define xd_p_reg_feq_Leak_B_Float3 0xA36A | |
2374 | #define reg_feq_Leak_B_Float3_pos 0 | |
2375 | #define reg_feq_Leak_B_Float3_len 8 | |
2376 | #define reg_feq_Leak_B_Float3_lsb 0 | |
2377 | #define xd_p_reg_feq_Leak_B_Float4 0xA36B | |
2378 | #define reg_feq_Leak_B_Float4_pos 0 | |
2379 | #define reg_feq_Leak_B_Float4_len 8 | |
2380 | #define reg_feq_Leak_B_Float4_lsb 0 | |
2381 | #define xd_p_reg_feq_Leak_B_Float5 0xA36C | |
2382 | #define reg_feq_Leak_B_Float5_pos 0 | |
2383 | #define reg_feq_Leak_B_Float5_len 8 | |
2384 | #define reg_feq_Leak_B_Float5_lsb 0 | |
2385 | #define xd_p_reg_feq_Leak_B_Float6 0xA36D | |
2386 | #define reg_feq_Leak_B_Float6_pos 0 | |
2387 | #define reg_feq_Leak_B_Float6_len 8 | |
2388 | #define reg_feq_Leak_B_Float6_lsb 0 | |
2389 | #define xd_p_reg_feq_Leak_B_Float7 0xA36E | |
2390 | #define reg_feq_Leak_B_Float7_pos 0 | |
2391 | #define reg_feq_Leak_B_Float7_len 8 | |
2392 | #define reg_feq_Leak_B_Float7_lsb 0 | |
2393 | #define xd_r_reg_feq_data_h2_7_0 0xA36F | |
2394 | #define reg_feq_data_h2_7_0_pos 0 | |
2395 | #define reg_feq_data_h2_7_0_len 8 | |
2396 | #define reg_feq_data_h2_7_0_lsb 0 | |
2397 | #define xd_r_reg_feq_data_h2_9_8 0xA370 | |
2398 | #define reg_feq_data_h2_9_8_pos 0 | |
2399 | #define reg_feq_data_h2_9_8_len 2 | |
2400 | #define reg_feq_data_h2_9_8_lsb 8 | |
2401 | #define xd_p_reg_feq_leak_use_slice_tps 0xA371 | |
2402 | #define reg_feq_leak_use_slice_tps_pos 0 | |
2403 | #define reg_feq_leak_use_slice_tps_len 1 | |
2404 | #define reg_feq_leak_use_slice_tps_lsb 0 | |
2405 | #define xd_p_reg_feq_read_update 0xA371 | |
2406 | #define reg_feq_read_update_pos 1 | |
2407 | #define reg_feq_read_update_len 1 | |
2408 | #define reg_feq_read_update_lsb 0 | |
2409 | #define xd_p_reg_feq_data_vld 0xA371 | |
2410 | #define reg_feq_data_vld_pos 2 | |
2411 | #define reg_feq_data_vld_len 1 | |
2412 | #define reg_feq_data_vld_lsb 0 | |
2413 | #define xd_p_reg_feq_tone_idx_4_0 0xA371 | |
2414 | #define reg_feq_tone_idx_4_0_pos 3 | |
2415 | #define reg_feq_tone_idx_4_0_len 5 | |
2416 | #define reg_feq_tone_idx_4_0_lsb 0 | |
2417 | #define xd_p_reg_feq_tone_idx_12_5 0xA372 | |
2418 | #define reg_feq_tone_idx_12_5_pos 0 | |
2419 | #define reg_feq_tone_idx_12_5_len 8 | |
2420 | #define reg_feq_tone_idx_12_5_lsb 5 | |
2421 | #define xd_r_reg_feq_data_re_7_0 0xA373 | |
2422 | #define reg_feq_data_re_7_0_pos 0 | |
2423 | #define reg_feq_data_re_7_0_len 8 | |
2424 | #define reg_feq_data_re_7_0_lsb 0 | |
2425 | #define xd_r_reg_feq_data_re_10_8 0xA374 | |
2426 | #define reg_feq_data_re_10_8_pos 0 | |
2427 | #define reg_feq_data_re_10_8_len 3 | |
2428 | #define reg_feq_data_re_10_8_lsb 8 | |
2429 | #define xd_r_reg_feq_data_im_7_0 0xA375 | |
2430 | #define reg_feq_data_im_7_0_pos 0 | |
2431 | #define reg_feq_data_im_7_0_len 8 | |
2432 | #define reg_feq_data_im_7_0_lsb 0 | |
2433 | #define xd_r_reg_feq_data_im_10_8 0xA376 | |
2434 | #define reg_feq_data_im_10_8_pos 0 | |
2435 | #define reg_feq_data_im_10_8_len 3 | |
2436 | #define reg_feq_data_im_10_8_lsb 8 | |
2437 | #define xd_r_reg_feq_y_re 0xA377 | |
2438 | #define reg_feq_y_re_pos 0 | |
2439 | #define reg_feq_y_re_len 8 | |
2440 | #define reg_feq_y_re_lsb 0 | |
2441 | #define xd_r_reg_feq_y_im 0xA378 | |
2442 | #define reg_feq_y_im_pos 0 | |
2443 | #define reg_feq_y_im_len 8 | |
2444 | #define reg_feq_y_im_lsb 0 | |
2445 | #define xd_r_reg_feq_h_re_7_0 0xA379 | |
2446 | #define reg_feq_h_re_7_0_pos 0 | |
2447 | #define reg_feq_h_re_7_0_len 8 | |
2448 | #define reg_feq_h_re_7_0_lsb 0 | |
2449 | #define xd_r_reg_feq_h_re_8 0xA37A | |
2450 | #define reg_feq_h_re_8_pos 0 | |
2451 | #define reg_feq_h_re_8_len 1 | |
2452 | #define reg_feq_h_re_8_lsb 0 | |
2453 | #define xd_r_reg_feq_h_im_7_0 0xA37B | |
2454 | #define reg_feq_h_im_7_0_pos 0 | |
2455 | #define reg_feq_h_im_7_0_len 8 | |
2456 | #define reg_feq_h_im_7_0_lsb 0 | |
2457 | #define xd_r_reg_feq_h_im_8 0xA37C | |
2458 | #define reg_feq_h_im_8_pos 0 | |
2459 | #define reg_feq_h_im_8_len 1 | |
2460 | #define reg_feq_h_im_8_lsb 0 | |
2461 | #define xd_p_fec_super_frm_unit_7_0 0xA380 | |
2462 | #define fec_super_frm_unit_7_0_pos 0 | |
2463 | #define fec_super_frm_unit_7_0_len 8 | |
2464 | #define fec_super_frm_unit_7_0_lsb 0 | |
2465 | #define xd_p_fec_super_frm_unit_15_8 0xA381 | |
2466 | #define fec_super_frm_unit_15_8_pos 0 | |
2467 | #define fec_super_frm_unit_15_8_len 8 | |
2468 | #define fec_super_frm_unit_15_8_lsb 8 | |
2469 | #define xd_r_fec_vtb_err_bit_cnt_7_0 0xA382 | |
2470 | #define fec_vtb_err_bit_cnt_7_0_pos 0 | |
2471 | #define fec_vtb_err_bit_cnt_7_0_len 8 | |
2472 | #define fec_vtb_err_bit_cnt_7_0_lsb 0 | |
2473 | #define xd_r_fec_vtb_err_bit_cnt_15_8 0xA383 | |
2474 | #define fec_vtb_err_bit_cnt_15_8_pos 0 | |
2475 | #define fec_vtb_err_bit_cnt_15_8_len 8 | |
2476 | #define fec_vtb_err_bit_cnt_15_8_lsb 8 | |
2477 | #define xd_r_fec_vtb_err_bit_cnt_23_16 0xA384 | |
2478 | #define fec_vtb_err_bit_cnt_23_16_pos 0 | |
2479 | #define fec_vtb_err_bit_cnt_23_16_len 8 | |
2480 | #define fec_vtb_err_bit_cnt_23_16_lsb 16 | |
2481 | #define xd_p_fec_rsd_packet_unit_7_0 0xA385 | |
2482 | #define fec_rsd_packet_unit_7_0_pos 0 | |
2483 | #define fec_rsd_packet_unit_7_0_len 8 | |
2484 | #define fec_rsd_packet_unit_7_0_lsb 0 | |
2485 | #define xd_p_fec_rsd_packet_unit_15_8 0xA386 | |
2486 | #define fec_rsd_packet_unit_15_8_pos 0 | |
2487 | #define fec_rsd_packet_unit_15_8_len 8 | |
2488 | #define fec_rsd_packet_unit_15_8_lsb 8 | |
2489 | #define xd_r_fec_rsd_bit_err_cnt_7_0 0xA387 | |
2490 | #define fec_rsd_bit_err_cnt_7_0_pos 0 | |
2491 | #define fec_rsd_bit_err_cnt_7_0_len 8 | |
2492 | #define fec_rsd_bit_err_cnt_7_0_lsb 0 | |
2493 | #define xd_r_fec_rsd_bit_err_cnt_15_8 0xA388 | |
2494 | #define fec_rsd_bit_err_cnt_15_8_pos 0 | |
2495 | #define fec_rsd_bit_err_cnt_15_8_len 8 | |
2496 | #define fec_rsd_bit_err_cnt_15_8_lsb 8 | |
2497 | #define xd_r_fec_rsd_bit_err_cnt_23_16 0xA389 | |
2498 | #define fec_rsd_bit_err_cnt_23_16_pos 0 | |
2499 | #define fec_rsd_bit_err_cnt_23_16_len 8 | |
2500 | #define fec_rsd_bit_err_cnt_23_16_lsb 16 | |
2501 | #define xd_r_fec_rsd_abort_packet_cnt_7_0 0xA38A | |
2502 | #define fec_rsd_abort_packet_cnt_7_0_pos 0 | |
2503 | #define fec_rsd_abort_packet_cnt_7_0_len 8 | |
2504 | #define fec_rsd_abort_packet_cnt_7_0_lsb 0 | |
2505 | #define xd_r_fec_rsd_abort_packet_cnt_15_8 0xA38B | |
2506 | #define fec_rsd_abort_packet_cnt_15_8_pos 0 | |
2507 | #define fec_rsd_abort_packet_cnt_15_8_len 8 | |
2508 | #define fec_rsd_abort_packet_cnt_15_8_lsb 8 | |
2509 | #define xd_p_fec_RSD_PKT_NUM_PER_UNIT_7_0 0xA38C | |
2510 | #define fec_RSD_PKT_NUM_PER_UNIT_7_0_pos 0 | |
2511 | #define fec_RSD_PKT_NUM_PER_UNIT_7_0_len 8 | |
2512 | #define fec_RSD_PKT_NUM_PER_UNIT_7_0_lsb 0 | |
2513 | #define xd_p_fec_RSD_PKT_NUM_PER_UNIT_15_8 0xA38D | |
2514 | #define fec_RSD_PKT_NUM_PER_UNIT_15_8_pos 0 | |
2515 | #define fec_RSD_PKT_NUM_PER_UNIT_15_8_len 8 | |
2516 | #define fec_RSD_PKT_NUM_PER_UNIT_15_8_lsb 8 | |
2517 | #define xd_p_fec_RS_TH_1_7_0 0xA38E | |
2518 | #define fec_RS_TH_1_7_0_pos 0 | |
2519 | #define fec_RS_TH_1_7_0_len 8 | |
2520 | #define fec_RS_TH_1_7_0_lsb 0 | |
2521 | #define xd_p_fec_RS_TH_1_15_8 0xA38F | |
2522 | #define fec_RS_TH_1_15_8_pos 0 | |
2523 | #define fec_RS_TH_1_15_8_len 8 | |
2524 | #define fec_RS_TH_1_15_8_lsb 8 | |
2525 | #define xd_p_fec_RS_TH_2 0xA390 | |
2526 | #define fec_RS_TH_2_pos 0 | |
2527 | #define fec_RS_TH_2_len 8 | |
2528 | #define fec_RS_TH_2_lsb 0 | |
2529 | #define xd_p_fec_mon_en 0xA391 | |
2530 | #define fec_mon_en_pos 0 | |
2531 | #define fec_mon_en_len 1 | |
2532 | #define fec_mon_en_lsb 0 | |
2533 | #define xd_p_reg_b8to47 0xA391 | |
2534 | #define reg_b8to47_pos 1 | |
2535 | #define reg_b8to47_len 1 | |
2536 | #define reg_b8to47_lsb 0 | |
2537 | #define xd_p_reg_rsd_sync_rep 0xA391 | |
2538 | #define reg_rsd_sync_rep_pos 2 | |
2539 | #define reg_rsd_sync_rep_len 1 | |
2540 | #define reg_rsd_sync_rep_lsb 0 | |
2541 | #define xd_p_fec_rsd_retrain_rst 0xA391 | |
2542 | #define fec_rsd_retrain_rst_pos 3 | |
2543 | #define fec_rsd_retrain_rst_len 1 | |
2544 | #define fec_rsd_retrain_rst_lsb 0 | |
2545 | #define xd_r_fec_rsd_ber_rdy 0xA391 | |
2546 | #define fec_rsd_ber_rdy_pos 4 | |
2547 | #define fec_rsd_ber_rdy_len 1 | |
2548 | #define fec_rsd_ber_rdy_lsb 0 | |
2549 | #define xd_p_fec_rsd_ber_rst 0xA391 | |
2550 | #define fec_rsd_ber_rst_pos 5 | |
2551 | #define fec_rsd_ber_rst_len 1 | |
2552 | #define fec_rsd_ber_rst_lsb 0 | |
2553 | #define xd_r_fec_vtb_ber_rdy 0xA391 | |
2554 | #define fec_vtb_ber_rdy_pos 6 | |
2555 | #define fec_vtb_ber_rdy_len 1 | |
2556 | #define fec_vtb_ber_rdy_lsb 0 | |
2557 | #define xd_p_fec_vtb_ber_rst 0xA391 | |
2558 | #define fec_vtb_ber_rst_pos 7 | |
2559 | #define fec_vtb_ber_rst_len 1 | |
2560 | #define fec_vtb_ber_rst_lsb 0 | |
2561 | #define xd_p_reg_vtb_clk40en 0xA392 | |
2562 | #define reg_vtb_clk40en_pos 0 | |
2563 | #define reg_vtb_clk40en_len 1 | |
2564 | #define reg_vtb_clk40en_lsb 0 | |
2565 | #define xd_p_fec_vtb_rsd_mon_en 0xA392 | |
2566 | #define fec_vtb_rsd_mon_en_pos 1 | |
2567 | #define fec_vtb_rsd_mon_en_len 1 | |
2568 | #define fec_vtb_rsd_mon_en_lsb 0 | |
2569 | #define xd_p_reg_fec_data_en 0xA392 | |
2570 | #define reg_fec_data_en_pos 2 | |
2571 | #define reg_fec_data_en_len 1 | |
2572 | #define reg_fec_data_en_lsb 0 | |
2573 | #define xd_p_fec_dummy_reg_2 0xA392 | |
2574 | #define fec_dummy_reg_2_pos 3 | |
2575 | #define fec_dummy_reg_2_len 3 | |
2576 | #define fec_dummy_reg_2_lsb 0 | |
2577 | #define xd_p_reg_sync_chk 0xA392 | |
2578 | #define reg_sync_chk_pos 6 | |
2579 | #define reg_sync_chk_len 1 | |
2580 | #define reg_sync_chk_lsb 0 | |
2581 | #define xd_p_fec_rsd_bypass 0xA392 | |
2582 | #define fec_rsd_bypass_pos 7 | |
2583 | #define fec_rsd_bypass_len 1 | |
2584 | #define fec_rsd_bypass_lsb 0 | |
2585 | #define xd_p_fec_sw_rst 0xA393 | |
2586 | #define fec_sw_rst_pos 0 | |
2587 | #define fec_sw_rst_len 1 | |
2588 | #define fec_sw_rst_lsb 0 | |
2589 | #define xd_r_fec_vtb_pm_crc 0xA394 | |
2590 | #define fec_vtb_pm_crc_pos 0 | |
2591 | #define fec_vtb_pm_crc_len 8 | |
2592 | #define fec_vtb_pm_crc_lsb 0 | |
2593 | #define xd_r_fec_vtb_tb_7_crc 0xA395 | |
2594 | #define fec_vtb_tb_7_crc_pos 0 | |
2595 | #define fec_vtb_tb_7_crc_len 8 | |
2596 | #define fec_vtb_tb_7_crc_lsb 0 | |
2597 | #define xd_r_fec_vtb_tb_6_crc 0xA396 | |
2598 | #define fec_vtb_tb_6_crc_pos 0 | |
2599 | #define fec_vtb_tb_6_crc_len 8 | |
2600 | #define fec_vtb_tb_6_crc_lsb 0 | |
2601 | #define xd_r_fec_vtb_tb_5_crc 0xA397 | |
2602 | #define fec_vtb_tb_5_crc_pos 0 | |
2603 | #define fec_vtb_tb_5_crc_len 8 | |
2604 | #define fec_vtb_tb_5_crc_lsb 0 | |
2605 | #define xd_r_fec_vtb_tb_4_crc 0xA398 | |
2606 | #define fec_vtb_tb_4_crc_pos 0 | |
2607 | #define fec_vtb_tb_4_crc_len 8 | |
2608 | #define fec_vtb_tb_4_crc_lsb 0 | |
2609 | #define xd_r_fec_vtb_tb_3_crc 0xA399 | |
2610 | #define fec_vtb_tb_3_crc_pos 0 | |
2611 | #define fec_vtb_tb_3_crc_len 8 | |
2612 | #define fec_vtb_tb_3_crc_lsb 0 | |
2613 | #define xd_r_fec_vtb_tb_2_crc 0xA39A | |
2614 | #define fec_vtb_tb_2_crc_pos 0 | |
2615 | #define fec_vtb_tb_2_crc_len 8 | |
2616 | #define fec_vtb_tb_2_crc_lsb 0 | |
2617 | #define xd_r_fec_vtb_tb_1_crc 0xA39B | |
2618 | #define fec_vtb_tb_1_crc_pos 0 | |
2619 | #define fec_vtb_tb_1_crc_len 8 | |
2620 | #define fec_vtb_tb_1_crc_lsb 0 | |
2621 | #define xd_r_fec_vtb_tb_0_crc 0xA39C | |
2622 | #define fec_vtb_tb_0_crc_pos 0 | |
2623 | #define fec_vtb_tb_0_crc_len 8 | |
2624 | #define fec_vtb_tb_0_crc_lsb 0 | |
2625 | #define xd_r_fec_rsd_bank0_crc 0xA39D | |
2626 | #define fec_rsd_bank0_crc_pos 0 | |
2627 | #define fec_rsd_bank0_crc_len 8 | |
2628 | #define fec_rsd_bank0_crc_lsb 0 | |
2629 | #define xd_r_fec_rsd_bank1_crc 0xA39E | |
2630 | #define fec_rsd_bank1_crc_pos 0 | |
2631 | #define fec_rsd_bank1_crc_len 8 | |
2632 | #define fec_rsd_bank1_crc_lsb 0 | |
2633 | #define xd_r_fec_idi_vtb_crc 0xA39F | |
2634 | #define fec_idi_vtb_crc_pos 0 | |
2635 | #define fec_idi_vtb_crc_len 8 | |
2636 | #define fec_idi_vtb_crc_lsb 0 | |
2637 | #define xd_g_reg_tpsd_txmod 0xA3C0 | |
2638 | #define reg_tpsd_txmod_pos 0 | |
2639 | #define reg_tpsd_txmod_len 2 | |
2640 | #define reg_tpsd_txmod_lsb 0 | |
2641 | #define xd_g_reg_tpsd_gi 0xA3C0 | |
2642 | #define reg_tpsd_gi_pos 2 | |
2643 | #define reg_tpsd_gi_len 2 | |
2644 | #define reg_tpsd_gi_lsb 0 | |
2645 | #define xd_g_reg_tpsd_hier 0xA3C0 | |
2646 | #define reg_tpsd_hier_pos 4 | |
2647 | #define reg_tpsd_hier_len 3 | |
2648 | #define reg_tpsd_hier_lsb 0 | |
2649 | #define xd_g_reg_bw 0xA3C1 | |
2650 | #define reg_bw_pos 2 | |
2651 | #define reg_bw_len 2 | |
2652 | #define reg_bw_lsb 0 | |
2653 | #define xd_g_reg_dec_pri 0xA3C1 | |
2654 | #define reg_dec_pri_pos 4 | |
2655 | #define reg_dec_pri_len 1 | |
2656 | #define reg_dec_pri_lsb 0 | |
2657 | #define xd_g_reg_tpsd_const 0xA3C1 | |
2658 | #define reg_tpsd_const_pos 6 | |
2659 | #define reg_tpsd_const_len 2 | |
2660 | #define reg_tpsd_const_lsb 0 | |
2661 | #define xd_g_reg_tpsd_hpcr 0xA3C2 | |
2662 | #define reg_tpsd_hpcr_pos 0 | |
2663 | #define reg_tpsd_hpcr_len 3 | |
2664 | #define reg_tpsd_hpcr_lsb 0 | |
2665 | #define xd_g_reg_tpsd_lpcr 0xA3C2 | |
2666 | #define reg_tpsd_lpcr_pos 3 | |
2667 | #define reg_tpsd_lpcr_len 3 | |
2668 | #define reg_tpsd_lpcr_lsb 0 | |
2669 | #define xd_g_reg_ofsm_clk 0xA3D0 | |
2670 | #define reg_ofsm_clk_pos 0 | |
2671 | #define reg_ofsm_clk_len 3 | |
2672 | #define reg_ofsm_clk_lsb 0 | |
2673 | #define xd_g_reg_fclk_cfg 0xA3D1 | |
2674 | #define reg_fclk_cfg_pos 0 | |
2675 | #define reg_fclk_cfg_len 1 | |
2676 | #define reg_fclk_cfg_lsb 0 | |
2677 | #define xd_g_reg_fclk_idi 0xA3D1 | |
2678 | #define reg_fclk_idi_pos 1 | |
2679 | #define reg_fclk_idi_len 1 | |
2680 | #define reg_fclk_idi_lsb 0 | |
2681 | #define xd_g_reg_fclk_odi 0xA3D1 | |
2682 | #define reg_fclk_odi_pos 2 | |
2683 | #define reg_fclk_odi_len 1 | |
2684 | #define reg_fclk_odi_lsb 0 | |
2685 | #define xd_g_reg_fclk_rsd 0xA3D1 | |
2686 | #define reg_fclk_rsd_pos 3 | |
2687 | #define reg_fclk_rsd_len 1 | |
2688 | #define reg_fclk_rsd_lsb 0 | |
2689 | #define xd_g_reg_fclk_vtb 0xA3D1 | |
2690 | #define reg_fclk_vtb_pos 4 | |
2691 | #define reg_fclk_vtb_len 1 | |
2692 | #define reg_fclk_vtb_lsb 0 | |
2693 | #define xd_g_reg_fclk_cste 0xA3D1 | |
2694 | #define reg_fclk_cste_pos 5 | |
2695 | #define reg_fclk_cste_len 1 | |
2696 | #define reg_fclk_cste_lsb 0 | |
2697 | #define xd_g_reg_fclk_mp2if 0xA3D1 | |
2698 | #define reg_fclk_mp2if_pos 6 | |
2699 | #define reg_fclk_mp2if_len 1 | |
2700 | #define reg_fclk_mp2if_lsb 0 | |
2701 | #define xd_I2C_i2c_m_slave_addr 0xA400 | |
2702 | #define i2c_m_slave_addr_pos 0 | |
2703 | #define i2c_m_slave_addr_len 8 | |
2704 | #define i2c_m_slave_addr_lsb 0 | |
2705 | #define xd_I2C_i2c_m_data1 0xA401 | |
2706 | #define i2c_m_data1_pos 0 | |
2707 | #define i2c_m_data1_len 8 | |
2708 | #define i2c_m_data1_lsb 0 | |
2709 | #define xd_I2C_i2c_m_data2 0xA402 | |
2710 | #define i2c_m_data2_pos 0 | |
2711 | #define i2c_m_data2_len 8 | |
2712 | #define i2c_m_data2_lsb 0 | |
2713 | #define xd_I2C_i2c_m_data3 0xA403 | |
2714 | #define i2c_m_data3_pos 0 | |
2715 | #define i2c_m_data3_len 8 | |
2716 | #define i2c_m_data3_lsb 0 | |
2717 | #define xd_I2C_i2c_m_data4 0xA404 | |
2718 | #define i2c_m_data4_pos 0 | |
2719 | #define i2c_m_data4_len 8 | |
2720 | #define i2c_m_data4_lsb 0 | |
2721 | #define xd_I2C_i2c_m_data5 0xA405 | |
2722 | #define i2c_m_data5_pos 0 | |
2723 | #define i2c_m_data5_len 8 | |
2724 | #define i2c_m_data5_lsb 0 | |
2725 | #define xd_I2C_i2c_m_data6 0xA406 | |
2726 | #define i2c_m_data6_pos 0 | |
2727 | #define i2c_m_data6_len 8 | |
2728 | #define i2c_m_data6_lsb 0 | |
2729 | #define xd_I2C_i2c_m_data7 0xA407 | |
2730 | #define i2c_m_data7_pos 0 | |
2731 | #define i2c_m_data7_len 8 | |
2732 | #define i2c_m_data7_lsb 0 | |
2733 | #define xd_I2C_i2c_m_data8 0xA408 | |
2734 | #define i2c_m_data8_pos 0 | |
2735 | #define i2c_m_data8_len 8 | |
2736 | #define i2c_m_data8_lsb 0 | |
2737 | #define xd_I2C_i2c_m_data9 0xA409 | |
2738 | #define i2c_m_data9_pos 0 | |
2739 | #define i2c_m_data9_len 8 | |
2740 | #define i2c_m_data9_lsb 0 | |
2741 | #define xd_I2C_i2c_m_data10 0xA40A | |
2742 | #define i2c_m_data10_pos 0 | |
2743 | #define i2c_m_data10_len 8 | |
2744 | #define i2c_m_data10_lsb 0 | |
2745 | #define xd_I2C_i2c_m_data11 0xA40B | |
2746 | #define i2c_m_data11_pos 0 | |
2747 | #define i2c_m_data11_len 8 | |
2748 | #define i2c_m_data11_lsb 0 | |
2749 | #define xd_I2C_i2c_m_cmd_rw 0xA40C | |
2750 | #define i2c_m_cmd_rw_pos 0 | |
2751 | #define i2c_m_cmd_rw_len 1 | |
2752 | #define i2c_m_cmd_rw_lsb 0 | |
2753 | #define xd_I2C_i2c_m_cmd_rwlen 0xA40C | |
2754 | #define i2c_m_cmd_rwlen_pos 3 | |
2755 | #define i2c_m_cmd_rwlen_len 4 | |
2756 | #define i2c_m_cmd_rwlen_lsb 0 | |
2757 | #define xd_I2C_i2c_m_status_cmd_exe 0xA40D | |
2758 | #define i2c_m_status_cmd_exe_pos 0 | |
2759 | #define i2c_m_status_cmd_exe_len 1 | |
2760 | #define i2c_m_status_cmd_exe_lsb 0 | |
2761 | #define xd_I2C_i2c_m_status_wdat_done 0xA40D | |
2762 | #define i2c_m_status_wdat_done_pos 1 | |
2763 | #define i2c_m_status_wdat_done_len 1 | |
2764 | #define i2c_m_status_wdat_done_lsb 0 | |
2765 | #define xd_I2C_i2c_m_status_wdat_fail 0xA40D | |
2766 | #define i2c_m_status_wdat_fail_pos 2 | |
2767 | #define i2c_m_status_wdat_fail_len 1 | |
2768 | #define i2c_m_status_wdat_fail_lsb 0 | |
2769 | #define xd_I2C_i2c_m_period 0xA40E | |
2770 | #define i2c_m_period_pos 0 | |
2771 | #define i2c_m_period_len 8 | |
2772 | #define i2c_m_period_lsb 0 | |
2773 | #define xd_I2C_i2c_m_reg_msb_lsb 0xA40F | |
2774 | #define i2c_m_reg_msb_lsb_pos 0 | |
2775 | #define i2c_m_reg_msb_lsb_len 1 | |
2776 | #define i2c_m_reg_msb_lsb_lsb 0 | |
2777 | #define xd_I2C_reg_ofdm_rst 0xA40F | |
2778 | #define reg_ofdm_rst_pos 1 | |
2779 | #define reg_ofdm_rst_len 1 | |
2780 | #define reg_ofdm_rst_lsb 0 | |
2781 | #define xd_I2C_reg_sample_period_on_tuner 0xA40F | |
2782 | #define reg_sample_period_on_tuner_pos 2 | |
2783 | #define reg_sample_period_on_tuner_len 1 | |
2784 | #define reg_sample_period_on_tuner_lsb 0 | |
2785 | #define xd_I2C_reg_rst_i2c 0xA40F | |
2786 | #define reg_rst_i2c_pos 3 | |
2787 | #define reg_rst_i2c_len 1 | |
2788 | #define reg_rst_i2c_lsb 0 | |
2789 | #define xd_I2C_reg_ofdm_rst_en 0xA40F | |
2790 | #define reg_ofdm_rst_en_pos 4 | |
2791 | #define reg_ofdm_rst_en_len 1 | |
2792 | #define reg_ofdm_rst_en_lsb 0 | |
2793 | #define xd_I2C_reg_tuner_sda_sync_on 0xA40F | |
2794 | #define reg_tuner_sda_sync_on_pos 5 | |
2795 | #define reg_tuner_sda_sync_on_len 1 | |
2796 | #define reg_tuner_sda_sync_on_lsb 0 | |
2797 | #define xd_p_mp2if_data_access_disable_ofsm 0xA500 | |
2798 | #define mp2if_data_access_disable_ofsm_pos 0 | |
2799 | #define mp2if_data_access_disable_ofsm_len 1 | |
2800 | #define mp2if_data_access_disable_ofsm_lsb 0 | |
2801 | #define xd_p_reg_mp2_sw_rst_ofsm 0xA500 | |
2802 | #define reg_mp2_sw_rst_ofsm_pos 1 | |
2803 | #define reg_mp2_sw_rst_ofsm_len 1 | |
2804 | #define reg_mp2_sw_rst_ofsm_lsb 0 | |
2805 | #define xd_p_reg_mp2if_clk_en_ofsm 0xA500 | |
2806 | #define reg_mp2if_clk_en_ofsm_pos 2 | |
2807 | #define reg_mp2if_clk_en_ofsm_len 1 | |
2808 | #define reg_mp2if_clk_en_ofsm_lsb 0 | |
2809 | #define xd_r_mp2if_sync_byte_locked 0xA500 | |
2810 | #define mp2if_sync_byte_locked_pos 3 | |
2811 | #define mp2if_sync_byte_locked_len 1 | |
2812 | #define mp2if_sync_byte_locked_lsb 0 | |
2813 | #define xd_r_mp2if_ts_not_188 0xA500 | |
2814 | #define mp2if_ts_not_188_pos 4 | |
2815 | #define mp2if_ts_not_188_len 1 | |
2816 | #define mp2if_ts_not_188_lsb 0 | |
2817 | #define xd_r_mp2if_psb_empty 0xA500 | |
2818 | #define mp2if_psb_empty_pos 5 | |
2819 | #define mp2if_psb_empty_len 1 | |
2820 | #define mp2if_psb_empty_lsb 0 | |
2821 | #define xd_r_mp2if_psb_overflow 0xA500 | |
2822 | #define mp2if_psb_overflow_pos 6 | |
2823 | #define mp2if_psb_overflow_len 1 | |
2824 | #define mp2if_psb_overflow_lsb 0 | |
2825 | #define xd_p_mp2if_keep_sf_sync_byte_ofsm 0xA500 | |
2826 | #define mp2if_keep_sf_sync_byte_ofsm_pos 7 | |
2827 | #define mp2if_keep_sf_sync_byte_ofsm_len 1 | |
2828 | #define mp2if_keep_sf_sync_byte_ofsm_lsb 0 | |
2829 | #define xd_r_mp2if_psb_mp2if_num_pkt 0xA501 | |
2830 | #define mp2if_psb_mp2if_num_pkt_pos 0 | |
2831 | #define mp2if_psb_mp2if_num_pkt_len 6 | |
2832 | #define mp2if_psb_mp2if_num_pkt_lsb 0 | |
2833 | #define xd_p_reg_mpeg_full_speed_ofsm 0xA501 | |
2834 | #define reg_mpeg_full_speed_ofsm_pos 6 | |
2835 | #define reg_mpeg_full_speed_ofsm_len 1 | |
2836 | #define reg_mpeg_full_speed_ofsm_lsb 0 | |
2837 | #define xd_p_mp2if_mpeg_ser_mode_ofsm 0xA501 | |
2838 | #define mp2if_mpeg_ser_mode_ofsm_pos 7 | |
2839 | #define mp2if_mpeg_ser_mode_ofsm_len 1 | |
2840 | #define mp2if_mpeg_ser_mode_ofsm_lsb 0 | |
2841 | #define xd_p_reg_sw_mon51 0xA600 | |
2842 | #define reg_sw_mon51_pos 0 | |
2843 | #define reg_sw_mon51_len 8 | |
2844 | #define reg_sw_mon51_lsb 0 | |
2845 | #define xd_p_reg_top_pcsel 0xA601 | |
2846 | #define reg_top_pcsel_pos 0 | |
2847 | #define reg_top_pcsel_len 1 | |
2848 | #define reg_top_pcsel_lsb 0 | |
2849 | #define xd_p_reg_top_rs232 0xA601 | |
2850 | #define reg_top_rs232_pos 1 | |
2851 | #define reg_top_rs232_len 1 | |
2852 | #define reg_top_rs232_lsb 0 | |
2853 | #define xd_p_reg_top_pcout 0xA601 | |
2854 | #define reg_top_pcout_pos 2 | |
2855 | #define reg_top_pcout_len 1 | |
2856 | #define reg_top_pcout_lsb 0 | |
2857 | #define xd_p_reg_top_debug 0xA601 | |
2858 | #define reg_top_debug_pos 3 | |
2859 | #define reg_top_debug_len 1 | |
2860 | #define reg_top_debug_lsb 0 | |
2861 | #define xd_p_reg_top_adcdly 0xA601 | |
2862 | #define reg_top_adcdly_pos 4 | |
2863 | #define reg_top_adcdly_len 2 | |
2864 | #define reg_top_adcdly_lsb 0 | |
2865 | #define xd_p_reg_top_pwrdw 0xA601 | |
2866 | #define reg_top_pwrdw_pos 6 | |
2867 | #define reg_top_pwrdw_len 1 | |
2868 | #define reg_top_pwrdw_lsb 0 | |
2869 | #define xd_p_reg_top_pwrdw_inv 0xA601 | |
2870 | #define reg_top_pwrdw_inv_pos 7 | |
2871 | #define reg_top_pwrdw_inv_len 1 | |
2872 | #define reg_top_pwrdw_inv_lsb 0 | |
2873 | #define xd_p_reg_top_int_inv 0xA602 | |
2874 | #define reg_top_int_inv_pos 0 | |
2875 | #define reg_top_int_inv_len 1 | |
2876 | #define reg_top_int_inv_lsb 0 | |
2877 | #define xd_p_reg_top_dio_sel 0xA602 | |
2878 | #define reg_top_dio_sel_pos 1 | |
2879 | #define reg_top_dio_sel_len 1 | |
2880 | #define reg_top_dio_sel_lsb 0 | |
2881 | #define xd_p_reg_top_gpioon0 0xA603 | |
2882 | #define reg_top_gpioon0_pos 0 | |
2883 | #define reg_top_gpioon0_len 1 | |
2884 | #define reg_top_gpioon0_lsb 0 | |
2885 | #define xd_p_reg_top_gpioon1 0xA603 | |
2886 | #define reg_top_gpioon1_pos 1 | |
2887 | #define reg_top_gpioon1_len 1 | |
2888 | #define reg_top_gpioon1_lsb 0 | |
2889 | #define xd_p_reg_top_gpioon2 0xA603 | |
2890 | #define reg_top_gpioon2_pos 2 | |
2891 | #define reg_top_gpioon2_len 1 | |
2892 | #define reg_top_gpioon2_lsb 0 | |
2893 | #define xd_p_reg_top_gpioon3 0xA603 | |
2894 | #define reg_top_gpioon3_pos 3 | |
2895 | #define reg_top_gpioon3_len 1 | |
2896 | #define reg_top_gpioon3_lsb 0 | |
2897 | #define xd_p_reg_top_lockon1 0xA603 | |
2898 | #define reg_top_lockon1_pos 4 | |
2899 | #define reg_top_lockon1_len 1 | |
2900 | #define reg_top_lockon1_lsb 0 | |
2901 | #define xd_p_reg_top_lockon2 0xA603 | |
2902 | #define reg_top_lockon2_pos 5 | |
2903 | #define reg_top_lockon2_len 1 | |
2904 | #define reg_top_lockon2_lsb 0 | |
2905 | #define xd_p_reg_top_gpioo0 0xA604 | |
2906 | #define reg_top_gpioo0_pos 0 | |
2907 | #define reg_top_gpioo0_len 1 | |
2908 | #define reg_top_gpioo0_lsb 0 | |
2909 | #define xd_p_reg_top_gpioo1 0xA604 | |
2910 | #define reg_top_gpioo1_pos 1 | |
2911 | #define reg_top_gpioo1_len 1 | |
2912 | #define reg_top_gpioo1_lsb 0 | |
2913 | #define xd_p_reg_top_gpioo2 0xA604 | |
2914 | #define reg_top_gpioo2_pos 2 | |
2915 | #define reg_top_gpioo2_len 1 | |
2916 | #define reg_top_gpioo2_lsb 0 | |
2917 | #define xd_p_reg_top_gpioo3 0xA604 | |
2918 | #define reg_top_gpioo3_pos 3 | |
2919 | #define reg_top_gpioo3_len 1 | |
2920 | #define reg_top_gpioo3_lsb 0 | |
2921 | #define xd_p_reg_top_lock1 0xA604 | |
2922 | #define reg_top_lock1_pos 4 | |
2923 | #define reg_top_lock1_len 1 | |
2924 | #define reg_top_lock1_lsb 0 | |
2925 | #define xd_p_reg_top_lock2 0xA604 | |
2926 | #define reg_top_lock2_pos 5 | |
2927 | #define reg_top_lock2_len 1 | |
2928 | #define reg_top_lock2_lsb 0 | |
2929 | #define xd_p_reg_top_gpioen0 0xA605 | |
2930 | #define reg_top_gpioen0_pos 0 | |
2931 | #define reg_top_gpioen0_len 1 | |
2932 | #define reg_top_gpioen0_lsb 0 | |
2933 | #define xd_p_reg_top_gpioen1 0xA605 | |
2934 | #define reg_top_gpioen1_pos 1 | |
2935 | #define reg_top_gpioen1_len 1 | |
2936 | #define reg_top_gpioen1_lsb 0 | |
2937 | #define xd_p_reg_top_gpioen2 0xA605 | |
2938 | #define reg_top_gpioen2_pos 2 | |
2939 | #define reg_top_gpioen2_len 1 | |
2940 | #define reg_top_gpioen2_lsb 0 | |
2941 | #define xd_p_reg_top_gpioen3 0xA605 | |
2942 | #define reg_top_gpioen3_pos 3 | |
2943 | #define reg_top_gpioen3_len 1 | |
2944 | #define reg_top_gpioen3_lsb 0 | |
2945 | #define xd_p_reg_top_locken1 0xA605 | |
2946 | #define reg_top_locken1_pos 4 | |
2947 | #define reg_top_locken1_len 1 | |
2948 | #define reg_top_locken1_lsb 0 | |
2949 | #define xd_p_reg_top_locken2 0xA605 | |
2950 | #define reg_top_locken2_pos 5 | |
2951 | #define reg_top_locken2_len 1 | |
2952 | #define reg_top_locken2_lsb 0 | |
2953 | #define xd_r_reg_top_gpioi0 0xA606 | |
2954 | #define reg_top_gpioi0_pos 0 | |
2955 | #define reg_top_gpioi0_len 1 | |
2956 | #define reg_top_gpioi0_lsb 0 | |
2957 | #define xd_r_reg_top_gpioi1 0xA606 | |
2958 | #define reg_top_gpioi1_pos 1 | |
2959 | #define reg_top_gpioi1_len 1 | |
2960 | #define reg_top_gpioi1_lsb 0 | |
2961 | #define xd_r_reg_top_gpioi2 0xA606 | |
2962 | #define reg_top_gpioi2_pos 2 | |
2963 | #define reg_top_gpioi2_len 1 | |
2964 | #define reg_top_gpioi2_lsb 0 | |
2965 | #define xd_r_reg_top_gpioi3 0xA606 | |
2966 | #define reg_top_gpioi3_pos 3 | |
2967 | #define reg_top_gpioi3_len 1 | |
2968 | #define reg_top_gpioi3_lsb 0 | |
2969 | #define xd_r_reg_top_locki1 0xA606 | |
2970 | #define reg_top_locki1_pos 4 | |
2971 | #define reg_top_locki1_len 1 | |
2972 | #define reg_top_locki1_lsb 0 | |
2973 | #define xd_r_reg_top_locki2 0xA606 | |
2974 | #define reg_top_locki2_pos 5 | |
2975 | #define reg_top_locki2_len 1 | |
2976 | #define reg_top_locki2_lsb 0 | |
2977 | #define xd_p_reg_dummy_7_0 0xA608 | |
2978 | #define reg_dummy_7_0_pos 0 | |
2979 | #define reg_dummy_7_0_len 8 | |
2980 | #define reg_dummy_7_0_lsb 0 | |
2981 | #define xd_p_reg_dummy_15_8 0xA609 | |
2982 | #define reg_dummy_15_8_pos 0 | |
2983 | #define reg_dummy_15_8_len 8 | |
2984 | #define reg_dummy_15_8_lsb 8 | |
2985 | #define xd_p_reg_dummy_23_16 0xA60A | |
2986 | #define reg_dummy_23_16_pos 0 | |
2987 | #define reg_dummy_23_16_len 8 | |
2988 | #define reg_dummy_23_16_lsb 16 | |
2989 | #define xd_p_reg_dummy_31_24 0xA60B | |
2990 | #define reg_dummy_31_24_pos 0 | |
2991 | #define reg_dummy_31_24_len 8 | |
2992 | #define reg_dummy_31_24_lsb 24 | |
2993 | #define xd_p_reg_dummy_39_32 0xA60C | |
2994 | #define reg_dummy_39_32_pos 0 | |
2995 | #define reg_dummy_39_32_len 8 | |
2996 | #define reg_dummy_39_32_lsb 32 | |
2997 | #define xd_p_reg_dummy_47_40 0xA60D | |
2998 | #define reg_dummy_47_40_pos 0 | |
2999 | #define reg_dummy_47_40_len 8 | |
3000 | #define reg_dummy_47_40_lsb 40 | |
3001 | #define xd_p_reg_dummy_55_48 0xA60E | |
3002 | #define reg_dummy_55_48_pos 0 | |
3003 | #define reg_dummy_55_48_len 8 | |
3004 | #define reg_dummy_55_48_lsb 48 | |
3005 | #define xd_p_reg_dummy_63_56 0xA60F | |
3006 | #define reg_dummy_63_56_pos 0 | |
3007 | #define reg_dummy_63_56_len 8 | |
3008 | #define reg_dummy_63_56_lsb 56 | |
3009 | #define xd_p_reg_dummy_71_64 0xA610 | |
3010 | #define reg_dummy_71_64_pos 0 | |
3011 | #define reg_dummy_71_64_len 8 | |
3012 | #define reg_dummy_71_64_lsb 64 | |
3013 | #define xd_p_reg_dummy_79_72 0xA611 | |
3014 | #define reg_dummy_79_72_pos 0 | |
3015 | #define reg_dummy_79_72_len 8 | |
3016 | #define reg_dummy_79_72_lsb 72 | |
3017 | #define xd_p_reg_dummy_87_80 0xA612 | |
3018 | #define reg_dummy_87_80_pos 0 | |
3019 | #define reg_dummy_87_80_len 8 | |
3020 | #define reg_dummy_87_80_lsb 80 | |
3021 | #define xd_p_reg_dummy_95_88 0xA613 | |
3022 | #define reg_dummy_95_88_pos 0 | |
3023 | #define reg_dummy_95_88_len 8 | |
3024 | #define reg_dummy_95_88_lsb 88 | |
3025 | #define xd_p_reg_dummy_103_96 0xA614 | |
3026 | #define reg_dummy_103_96_pos 0 | |
3027 | #define reg_dummy_103_96_len 8 | |
3028 | #define reg_dummy_103_96_lsb 96 | |
3029 | ||
3030 | #define xd_p_reg_unplug_flag 0xA615 | |
3031 | #define reg_unplug_flag_pos 0 | |
3032 | #define reg_unplug_flag_len 1 | |
3033 | #define reg_unplug_flag_lsb 104 | |
3034 | ||
3035 | #define xd_p_reg_api_dca_stes_request 0xA615 | |
3036 | #define reg_api_dca_stes_request_pos 1 | |
3037 | #define reg_api_dca_stes_request_len 1 | |
3038 | #define reg_api_dca_stes_request_lsb 0 | |
3039 | ||
3040 | #define xd_p_reg_back_to_dca_flag 0xA615 | |
3041 | #define reg_back_to_dca_flag_pos 2 | |
3042 | #define reg_back_to_dca_flag_len 1 | |
3043 | #define reg_back_to_dca_flag_lsb 106 | |
3044 | ||
3045 | #define xd_p_reg_api_retrain_request 0xA615 | |
3046 | #define reg_api_retrain_request_pos 3 | |
3047 | #define reg_api_retrain_request_len 1 | |
3048 | #define reg_api_retrain_request_lsb 0 | |
3049 | ||
3050 | #define xd_p_reg_Dyn_Top_Try_flag 0xA615 | |
3051 | #define reg_Dyn_Top_Try_flag_pos 3 | |
3052 | #define reg_Dyn_Top_Try_flag_len 1 | |
3053 | #define reg_Dyn_Top_Try_flag_lsb 107 | |
3054 | ||
3055 | #define xd_p_reg_API_retrain_freeze_flag 0xA615 | |
3056 | #define reg_API_retrain_freeze_flag_pos 4 | |
3057 | #define reg_API_retrain_freeze_flag_len 1 | |
3058 | #define reg_API_retrain_freeze_flag_lsb 108 | |
3059 | ||
3060 | #define xd_p_reg_dummy_111_104 0xA615 | |
3061 | #define reg_dummy_111_104_pos 0 | |
3062 | #define reg_dummy_111_104_len 8 | |
3063 | #define reg_dummy_111_104_lsb 104 | |
3064 | #define xd_p_reg_dummy_119_112 0xA616 | |
3065 | #define reg_dummy_119_112_pos 0 | |
3066 | #define reg_dummy_119_112_len 8 | |
3067 | #define reg_dummy_119_112_lsb 112 | |
3068 | #define xd_p_reg_dummy_127_120 0xA617 | |
3069 | #define reg_dummy_127_120_pos 0 | |
3070 | #define reg_dummy_127_120_len 8 | |
3071 | #define reg_dummy_127_120_lsb 120 | |
3072 | #define xd_p_reg_dummy_135_128 0xA618 | |
3073 | #define reg_dummy_135_128_pos 0 | |
3074 | #define reg_dummy_135_128_len 8 | |
3075 | #define reg_dummy_135_128_lsb 128 | |
3076 | ||
3077 | #define xd_p_reg_dummy_143_136 0xA619 | |
3078 | #define reg_dummy_143_136_pos 0 | |
3079 | #define reg_dummy_143_136_len 8 | |
3080 | #define reg_dummy_143_136_lsb 136 | |
3081 | ||
3082 | #define xd_p_reg_CCIR_dis 0xA619 | |
3083 | #define reg_CCIR_dis_pos 0 | |
3084 | #define reg_CCIR_dis_len 1 | |
3085 | #define reg_CCIR_dis_lsb 0 | |
3086 | ||
3087 | #define xd_p_reg_dummy_151_144 0xA61A | |
3088 | #define reg_dummy_151_144_pos 0 | |
3089 | #define reg_dummy_151_144_len 8 | |
3090 | #define reg_dummy_151_144_lsb 144 | |
3091 | ||
3092 | #define xd_p_reg_dummy_159_152 0xA61B | |
3093 | #define reg_dummy_159_152_pos 0 | |
3094 | #define reg_dummy_159_152_len 8 | |
3095 | #define reg_dummy_159_152_lsb 152 | |
3096 | ||
3097 | #define xd_p_reg_dummy_167_160 0xA61C | |
3098 | #define reg_dummy_167_160_pos 0 | |
3099 | #define reg_dummy_167_160_len 8 | |
3100 | #define reg_dummy_167_160_lsb 160 | |
3101 | ||
3102 | #define xd_p_reg_dummy_175_168 0xA61D | |
3103 | #define reg_dummy_175_168_pos 0 | |
3104 | #define reg_dummy_175_168_len 8 | |
3105 | #define reg_dummy_175_168_lsb 168 | |
3106 | ||
3107 | #define xd_p_reg_dummy_183_176 0xA61E | |
3108 | #define reg_dummy_183_176_pos 0 | |
3109 | #define reg_dummy_183_176_len 8 | |
3110 | #define reg_dummy_183_176_lsb 176 | |
3111 | ||
3112 | #define xd_p_reg_ofsm_read_rbc_en 0xA61E | |
3113 | #define reg_ofsm_read_rbc_en_pos 2 | |
3114 | #define reg_ofsm_read_rbc_en_len 1 | |
3115 | #define reg_ofsm_read_rbc_en_lsb 0 | |
3116 | ||
3117 | #define xd_p_reg_ce_filter_selection_dis 0xA61E | |
3118 | #define reg_ce_filter_selection_dis_pos 1 | |
3119 | #define reg_ce_filter_selection_dis_len 1 | |
3120 | #define reg_ce_filter_selection_dis_lsb 0 | |
3121 | ||
3122 | #define xd_p_reg_OFSM_version_control_7_0 0xA611 | |
3123 | #define reg_OFSM_version_control_7_0_pos 0 | |
3124 | #define reg_OFSM_version_control_7_0_len 8 | |
3125 | #define reg_OFSM_version_control_7_0_lsb 0 | |
3126 | ||
3127 | #define xd_p_reg_OFSM_version_control_15_8 0xA61F | |
3128 | #define reg_OFSM_version_control_15_8_pos 0 | |
3129 | #define reg_OFSM_version_control_15_8_len 8 | |
3130 | #define reg_OFSM_version_control_15_8_lsb 0 | |
3131 | ||
3132 | #define xd_p_reg_OFSM_version_control_23_16 0xA620 | |
3133 | #define reg_OFSM_version_control_23_16_pos 0 | |
3134 | #define reg_OFSM_version_control_23_16_len 8 | |
3135 | #define reg_OFSM_version_control_23_16_lsb 0 | |
3136 | ||
3137 | #define xd_p_reg_dummy_191_184 0xA61F | |
3138 | #define reg_dummy_191_184_pos 0 | |
3139 | #define reg_dummy_191_184_len 8 | |
3140 | #define reg_dummy_191_184_lsb 184 | |
3141 | ||
3142 | #define xd_p_reg_dummy_199_192 0xA620 | |
3143 | #define reg_dummy_199_192_pos 0 | |
3144 | #define reg_dummy_199_192_len 8 | |
3145 | #define reg_dummy_199_192_lsb 192 | |
3146 | ||
3147 | #define xd_p_reg_ce_en 0xABC0 | |
3148 | #define reg_ce_en_pos 0 | |
3149 | #define reg_ce_en_len 1 | |
3150 | #define reg_ce_en_lsb 0 | |
3151 | #define xd_p_reg_ce_fctrl_en 0xABC0 | |
3152 | #define reg_ce_fctrl_en_pos 1 | |
3153 | #define reg_ce_fctrl_en_len 1 | |
3154 | #define reg_ce_fctrl_en_lsb 0 | |
3155 | #define xd_p_reg_ce_fste_tdi 0xABC0 | |
3156 | #define reg_ce_fste_tdi_pos 2 | |
3157 | #define reg_ce_fste_tdi_len 1 | |
3158 | #define reg_ce_fste_tdi_lsb 0 | |
3159 | #define xd_p_reg_ce_dynamic 0xABC0 | |
3160 | #define reg_ce_dynamic_pos 3 | |
3161 | #define reg_ce_dynamic_len 1 | |
3162 | #define reg_ce_dynamic_lsb 0 | |
3163 | #define xd_p_reg_ce_conf 0xABC0 | |
3164 | #define reg_ce_conf_pos 4 | |
3165 | #define reg_ce_conf_len 2 | |
3166 | #define reg_ce_conf_lsb 0 | |
3167 | #define xd_p_reg_ce_dyn12 0xABC0 | |
3168 | #define reg_ce_dyn12_pos 6 | |
3169 | #define reg_ce_dyn12_len 1 | |
3170 | #define reg_ce_dyn12_lsb 0 | |
3171 | #define xd_p_reg_ce_derot_en 0xABC0 | |
3172 | #define reg_ce_derot_en_pos 7 | |
3173 | #define reg_ce_derot_en_len 1 | |
3174 | #define reg_ce_derot_en_lsb 0 | |
3175 | #define xd_p_reg_ce_dynamic_th_7_0 0xABC1 | |
3176 | #define reg_ce_dynamic_th_7_0_pos 0 | |
3177 | #define reg_ce_dynamic_th_7_0_len 8 | |
3178 | #define reg_ce_dynamic_th_7_0_lsb 0 | |
3179 | #define xd_p_reg_ce_dynamic_th_15_8 0xABC2 | |
3180 | #define reg_ce_dynamic_th_15_8_pos 0 | |
3181 | #define reg_ce_dynamic_th_15_8_len 8 | |
3182 | #define reg_ce_dynamic_th_15_8_lsb 8 | |
3183 | #define xd_p_reg_ce_s1 0xABC3 | |
3184 | #define reg_ce_s1_pos 0 | |
3185 | #define reg_ce_s1_len 5 | |
3186 | #define reg_ce_s1_lsb 0 | |
3187 | #define xd_p_reg_ce_var_forced_value 0xABC3 | |
3188 | #define reg_ce_var_forced_value_pos 5 | |
3189 | #define reg_ce_var_forced_value_len 3 | |
3190 | #define reg_ce_var_forced_value_lsb 0 | |
3191 | #define xd_p_reg_ce_data_im_7_0 0xABC4 | |
3192 | #define reg_ce_data_im_7_0_pos 0 | |
3193 | #define reg_ce_data_im_7_0_len 8 | |
3194 | #define reg_ce_data_im_7_0_lsb 0 | |
3195 | #define xd_p_reg_ce_data_im_8 0xABC5 | |
3196 | #define reg_ce_data_im_8_pos 0 | |
3197 | #define reg_ce_data_im_8_len 1 | |
3198 | #define reg_ce_data_im_8_lsb 0 | |
3199 | #define xd_p_reg_ce_data_re_6_0 0xABC5 | |
3200 | #define reg_ce_data_re_6_0_pos 1 | |
3201 | #define reg_ce_data_re_6_0_len 7 | |
3202 | #define reg_ce_data_re_6_0_lsb 0 | |
3203 | #define xd_p_reg_ce_data_re_8_7 0xABC6 | |
3204 | #define reg_ce_data_re_8_7_pos 0 | |
3205 | #define reg_ce_data_re_8_7_len 2 | |
3206 | #define reg_ce_data_re_8_7_lsb 7 | |
3207 | #define xd_p_reg_ce_tone_5_0 0xABC6 | |
3208 | #define reg_ce_tone_5_0_pos 2 | |
3209 | #define reg_ce_tone_5_0_len 6 | |
3210 | #define reg_ce_tone_5_0_lsb 0 | |
3211 | #define xd_p_reg_ce_tone_12_6 0xABC7 | |
3212 | #define reg_ce_tone_12_6_pos 0 | |
3213 | #define reg_ce_tone_12_6_len 7 | |
3214 | #define reg_ce_tone_12_6_lsb 6 | |
3215 | #define xd_p_reg_ce_centroid_drift_th 0xABC8 | |
3216 | #define reg_ce_centroid_drift_th_pos 0 | |
3217 | #define reg_ce_centroid_drift_th_len 8 | |
3218 | #define reg_ce_centroid_drift_th_lsb 0 | |
3219 | #define xd_p_reg_ce_centroid_count_max 0xABC9 | |
3220 | #define reg_ce_centroid_count_max_pos 0 | |
3221 | #define reg_ce_centroid_count_max_len 4 | |
3222 | #define reg_ce_centroid_count_max_lsb 0 | |
3223 | #define xd_p_reg_ce_centroid_bias_inc_7_0 0xABCA | |
3224 | #define reg_ce_centroid_bias_inc_7_0_pos 0 | |
3225 | #define reg_ce_centroid_bias_inc_7_0_len 8 | |
3226 | #define reg_ce_centroid_bias_inc_7_0_lsb 0 | |
3227 | #define xd_p_reg_ce_centroid_bias_inc_8 0xABCB | |
3228 | #define reg_ce_centroid_bias_inc_8_pos 0 | |
3229 | #define reg_ce_centroid_bias_inc_8_len 1 | |
3230 | #define reg_ce_centroid_bias_inc_8_lsb 0 | |
3231 | #define xd_p_reg_ce_var_th0_7_0 0xABCC | |
3232 | #define reg_ce_var_th0_7_0_pos 0 | |
3233 | #define reg_ce_var_th0_7_0_len 8 | |
3234 | #define reg_ce_var_th0_7_0_lsb 0 | |
3235 | #define xd_p_reg_ce_var_th0_15_8 0xABCD | |
3236 | #define reg_ce_var_th0_15_8_pos 0 | |
3237 | #define reg_ce_var_th0_15_8_len 8 | |
3238 | #define reg_ce_var_th0_15_8_lsb 8 | |
3239 | #define xd_p_reg_ce_var_th1_7_0 0xABCE | |
3240 | #define reg_ce_var_th1_7_0_pos 0 | |
3241 | #define reg_ce_var_th1_7_0_len 8 | |
3242 | #define reg_ce_var_th1_7_0_lsb 0 | |
3243 | #define xd_p_reg_ce_var_th1_15_8 0xABCF | |
3244 | #define reg_ce_var_th1_15_8_pos 0 | |
3245 | #define reg_ce_var_th1_15_8_len 8 | |
3246 | #define reg_ce_var_th1_15_8_lsb 8 | |
3247 | #define xd_p_reg_ce_var_th2_7_0 0xABD0 | |
3248 | #define reg_ce_var_th2_7_0_pos 0 | |
3249 | #define reg_ce_var_th2_7_0_len 8 | |
3250 | #define reg_ce_var_th2_7_0_lsb 0 | |
3251 | #define xd_p_reg_ce_var_th2_15_8 0xABD1 | |
3252 | #define reg_ce_var_th2_15_8_pos 0 | |
3253 | #define reg_ce_var_th2_15_8_len 8 | |
3254 | #define reg_ce_var_th2_15_8_lsb 8 | |
3255 | #define xd_p_reg_ce_var_th3_7_0 0xABD2 | |
3256 | #define reg_ce_var_th3_7_0_pos 0 | |
3257 | #define reg_ce_var_th3_7_0_len 8 | |
3258 | #define reg_ce_var_th3_7_0_lsb 0 | |
3259 | #define xd_p_reg_ce_var_th3_15_8 0xABD3 | |
3260 | #define reg_ce_var_th3_15_8_pos 0 | |
3261 | #define reg_ce_var_th3_15_8_len 8 | |
3262 | #define reg_ce_var_th3_15_8_lsb 8 | |
3263 | #define xd_p_reg_ce_var_th4_7_0 0xABD4 | |
3264 | #define reg_ce_var_th4_7_0_pos 0 | |
3265 | #define reg_ce_var_th4_7_0_len 8 | |
3266 | #define reg_ce_var_th4_7_0_lsb 0 | |
3267 | #define xd_p_reg_ce_var_th4_15_8 0xABD5 | |
3268 | #define reg_ce_var_th4_15_8_pos 0 | |
3269 | #define reg_ce_var_th4_15_8_len 8 | |
3270 | #define reg_ce_var_th4_15_8_lsb 8 | |
3271 | #define xd_p_reg_ce_var_th5_7_0 0xABD6 | |
3272 | #define reg_ce_var_th5_7_0_pos 0 | |
3273 | #define reg_ce_var_th5_7_0_len 8 | |
3274 | #define reg_ce_var_th5_7_0_lsb 0 | |
3275 | #define xd_p_reg_ce_var_th5_15_8 0xABD7 | |
3276 | #define reg_ce_var_th5_15_8_pos 0 | |
3277 | #define reg_ce_var_th5_15_8_len 8 | |
3278 | #define reg_ce_var_th5_15_8_lsb 8 | |
3279 | #define xd_p_reg_ce_var_th6_7_0 0xABD8 | |
3280 | #define reg_ce_var_th6_7_0_pos 0 | |
3281 | #define reg_ce_var_th6_7_0_len 8 | |
3282 | #define reg_ce_var_th6_7_0_lsb 0 | |
3283 | #define xd_p_reg_ce_var_th6_15_8 0xABD9 | |
3284 | #define reg_ce_var_th6_15_8_pos 0 | |
3285 | #define reg_ce_var_th6_15_8_len 8 | |
3286 | #define reg_ce_var_th6_15_8_lsb 8 | |
3287 | #define xd_p_reg_ce_fctrl_reset 0xABDA | |
3288 | #define reg_ce_fctrl_reset_pos 0 | |
3289 | #define reg_ce_fctrl_reset_len 1 | |
3290 | #define reg_ce_fctrl_reset_lsb 0 | |
3291 | #define xd_p_reg_ce_cent_auto_clr_en 0xABDA | |
3292 | #define reg_ce_cent_auto_clr_en_pos 1 | |
3293 | #define reg_ce_cent_auto_clr_en_len 1 | |
3294 | #define reg_ce_cent_auto_clr_en_lsb 0 | |
3295 | #define xd_p_reg_ce_fctrl_auto_reset_en 0xABDA | |
3296 | #define reg_ce_fctrl_auto_reset_en_pos 2 | |
3297 | #define reg_ce_fctrl_auto_reset_en_len 1 | |
3298 | #define reg_ce_fctrl_auto_reset_en_lsb 0 | |
3299 | #define xd_p_reg_ce_var_forced_en 0xABDA | |
3300 | #define reg_ce_var_forced_en_pos 3 | |
3301 | #define reg_ce_var_forced_en_len 1 | |
3302 | #define reg_ce_var_forced_en_lsb 0 | |
3303 | #define xd_p_reg_ce_cent_forced_en 0xABDA | |
3304 | #define reg_ce_cent_forced_en_pos 4 | |
3305 | #define reg_ce_cent_forced_en_len 1 | |
3306 | #define reg_ce_cent_forced_en_lsb 0 | |
3307 | #define xd_p_reg_ce_var_max 0xABDA | |
3308 | #define reg_ce_var_max_pos 5 | |
3309 | #define reg_ce_var_max_len 3 | |
3310 | #define reg_ce_var_max_lsb 0 | |
3311 | #define xd_p_reg_ce_cent_forced_value_7_0 0xABDB | |
3312 | #define reg_ce_cent_forced_value_7_0_pos 0 | |
3313 | #define reg_ce_cent_forced_value_7_0_len 8 | |
3314 | #define reg_ce_cent_forced_value_7_0_lsb 0 | |
3315 | #define xd_p_reg_ce_cent_forced_value_11_8 0xABDC | |
3316 | #define reg_ce_cent_forced_value_11_8_pos 0 | |
3317 | #define reg_ce_cent_forced_value_11_8_len 4 | |
3318 | #define reg_ce_cent_forced_value_11_8_lsb 8 | |
3319 | #define xd_p_reg_ce_fctrl_rd 0xABDD | |
3320 | #define reg_ce_fctrl_rd_pos 0 | |
3321 | #define reg_ce_fctrl_rd_len 1 | |
3322 | #define reg_ce_fctrl_rd_lsb 0 | |
3323 | #define xd_p_reg_ce_centroid_max_6_0 0xABDD | |
3324 | #define reg_ce_centroid_max_6_0_pos 1 | |
3325 | #define reg_ce_centroid_max_6_0_len 7 | |
3326 | #define reg_ce_centroid_max_6_0_lsb 0 | |
3327 | #define xd_p_reg_ce_centroid_max_11_7 0xABDE | |
3328 | #define reg_ce_centroid_max_11_7_pos 0 | |
3329 | #define reg_ce_centroid_max_11_7_len 5 | |
3330 | #define reg_ce_centroid_max_11_7_lsb 7 | |
3331 | #define xd_p_reg_ce_var 0xABDF | |
3332 | #define reg_ce_var_pos 0 | |
3333 | #define reg_ce_var_len 3 | |
3334 | #define reg_ce_var_lsb 0 | |
3335 | #define xd_p_reg_ce_fctrl_rdy 0xABDF | |
3336 | #define reg_ce_fctrl_rdy_pos 3 | |
3337 | #define reg_ce_fctrl_rdy_len 1 | |
3338 | #define reg_ce_fctrl_rdy_lsb 0 | |
3339 | #define xd_p_reg_ce_centroid_out_3_0 0xABDF | |
3340 | #define reg_ce_centroid_out_3_0_pos 4 | |
3341 | #define reg_ce_centroid_out_3_0_len 4 | |
3342 | #define reg_ce_centroid_out_3_0_lsb 0 | |
3343 | #define xd_p_reg_ce_centroid_out_11_4 0xABE0 | |
3344 | #define reg_ce_centroid_out_11_4_pos 0 | |
3345 | #define reg_ce_centroid_out_11_4_len 8 | |
3346 | #define reg_ce_centroid_out_11_4_lsb 4 | |
3347 | #define xd_p_reg_ce_bias_7_0 0xABE1 | |
3348 | #define reg_ce_bias_7_0_pos 0 | |
3349 | #define reg_ce_bias_7_0_len 8 | |
3350 | #define reg_ce_bias_7_0_lsb 0 | |
3351 | #define xd_p_reg_ce_bias_11_8 0xABE2 | |
3352 | #define reg_ce_bias_11_8_pos 0 | |
3353 | #define reg_ce_bias_11_8_len 4 | |
3354 | #define reg_ce_bias_11_8_lsb 8 | |
3355 | #define xd_p_reg_ce_m1_3_0 0xABE2 | |
3356 | #define reg_ce_m1_3_0_pos 4 | |
3357 | #define reg_ce_m1_3_0_len 4 | |
3358 | #define reg_ce_m1_3_0_lsb 0 | |
3359 | #define xd_p_reg_ce_m1_11_4 0xABE3 | |
3360 | #define reg_ce_m1_11_4_pos 0 | |
3361 | #define reg_ce_m1_11_4_len 8 | |
3362 | #define reg_ce_m1_11_4_lsb 4 | |
3363 | #define xd_p_reg_ce_rh0_7_0 0xABE4 | |
3364 | #define reg_ce_rh0_7_0_pos 0 | |
3365 | #define reg_ce_rh0_7_0_len 8 | |
3366 | #define reg_ce_rh0_7_0_lsb 0 | |
3367 | #define xd_p_reg_ce_rh0_15_8 0xABE5 | |
3368 | #define reg_ce_rh0_15_8_pos 0 | |
3369 | #define reg_ce_rh0_15_8_len 8 | |
3370 | #define reg_ce_rh0_15_8_lsb 8 | |
3371 | #define xd_p_reg_ce_rh0_23_16 0xABE6 | |
3372 | #define reg_ce_rh0_23_16_pos 0 | |
3373 | #define reg_ce_rh0_23_16_len 8 | |
3374 | #define reg_ce_rh0_23_16_lsb 16 | |
3375 | #define xd_p_reg_ce_rh0_31_24 0xABE7 | |
3376 | #define reg_ce_rh0_31_24_pos 0 | |
3377 | #define reg_ce_rh0_31_24_len 8 | |
3378 | #define reg_ce_rh0_31_24_lsb 24 | |
3379 | #define xd_p_reg_ce_rh3_real_7_0 0xABE8 | |
3380 | #define reg_ce_rh3_real_7_0_pos 0 | |
3381 | #define reg_ce_rh3_real_7_0_len 8 | |
3382 | #define reg_ce_rh3_real_7_0_lsb 0 | |
3383 | #define xd_p_reg_ce_rh3_real_15_8 0xABE9 | |
3384 | #define reg_ce_rh3_real_15_8_pos 0 | |
3385 | #define reg_ce_rh3_real_15_8_len 8 | |
3386 | #define reg_ce_rh3_real_15_8_lsb 8 | |
3387 | #define xd_p_reg_ce_rh3_real_23_16 0xABEA | |
3388 | #define reg_ce_rh3_real_23_16_pos 0 | |
3389 | #define reg_ce_rh3_real_23_16_len 8 | |
3390 | #define reg_ce_rh3_real_23_16_lsb 16 | |
3391 | #define xd_p_reg_ce_rh3_real_31_24 0xABEB | |
3392 | #define reg_ce_rh3_real_31_24_pos 0 | |
3393 | #define reg_ce_rh3_real_31_24_len 8 | |
3394 | #define reg_ce_rh3_real_31_24_lsb 24 | |
3395 | #define xd_p_reg_ce_rh3_imag_7_0 0xABEC | |
3396 | #define reg_ce_rh3_imag_7_0_pos 0 | |
3397 | #define reg_ce_rh3_imag_7_0_len 8 | |
3398 | #define reg_ce_rh3_imag_7_0_lsb 0 | |
3399 | #define xd_p_reg_ce_rh3_imag_15_8 0xABED | |
3400 | #define reg_ce_rh3_imag_15_8_pos 0 | |
3401 | #define reg_ce_rh3_imag_15_8_len 8 | |
3402 | #define reg_ce_rh3_imag_15_8_lsb 8 | |
3403 | #define xd_p_reg_ce_rh3_imag_23_16 0xABEE | |
3404 | #define reg_ce_rh3_imag_23_16_pos 0 | |
3405 | #define reg_ce_rh3_imag_23_16_len 8 | |
3406 | #define reg_ce_rh3_imag_23_16_lsb 16 | |
3407 | #define xd_p_reg_ce_rh3_imag_31_24 0xABEF | |
3408 | #define reg_ce_rh3_imag_31_24_pos 0 | |
3409 | #define reg_ce_rh3_imag_31_24_len 8 | |
3410 | #define reg_ce_rh3_imag_31_24_lsb 24 | |
3411 | #define xd_p_reg_feq_fix_eh2_7_0 0xABF0 | |
3412 | #define reg_feq_fix_eh2_7_0_pos 0 | |
3413 | #define reg_feq_fix_eh2_7_0_len 8 | |
3414 | #define reg_feq_fix_eh2_7_0_lsb 0 | |
3415 | #define xd_p_reg_feq_fix_eh2_15_8 0xABF1 | |
3416 | #define reg_feq_fix_eh2_15_8_pos 0 | |
3417 | #define reg_feq_fix_eh2_15_8_len 8 | |
3418 | #define reg_feq_fix_eh2_15_8_lsb 8 | |
3419 | #define xd_p_reg_feq_fix_eh2_23_16 0xABF2 | |
3420 | #define reg_feq_fix_eh2_23_16_pos 0 | |
3421 | #define reg_feq_fix_eh2_23_16_len 8 | |
3422 | #define reg_feq_fix_eh2_23_16_lsb 16 | |
3423 | #define xd_p_reg_feq_fix_eh2_31_24 0xABF3 | |
3424 | #define reg_feq_fix_eh2_31_24_pos 0 | |
3425 | #define reg_feq_fix_eh2_31_24_len 8 | |
3426 | #define reg_feq_fix_eh2_31_24_lsb 24 | |
3427 | #define xd_p_reg_ce_m2_central_7_0 0xABF4 | |
3428 | #define reg_ce_m2_central_7_0_pos 0 | |
3429 | #define reg_ce_m2_central_7_0_len 8 | |
3430 | #define reg_ce_m2_central_7_0_lsb 0 | |
3431 | #define xd_p_reg_ce_m2_central_15_8 0xABF5 | |
3432 | #define reg_ce_m2_central_15_8_pos 0 | |
3433 | #define reg_ce_m2_central_15_8_len 8 | |
3434 | #define reg_ce_m2_central_15_8_lsb 8 | |
3435 | #define xd_p_reg_ce_fftshift 0xABF6 | |
3436 | #define reg_ce_fftshift_pos 0 | |
3437 | #define reg_ce_fftshift_len 4 | |
3438 | #define reg_ce_fftshift_lsb 0 | |
3439 | #define xd_p_reg_ce_fftshift1 0xABF6 | |
3440 | #define reg_ce_fftshift1_pos 4 | |
3441 | #define reg_ce_fftshift1_len 4 | |
3442 | #define reg_ce_fftshift1_lsb 0 | |
3443 | #define xd_p_reg_ce_fftshift2 0xABF7 | |
3444 | #define reg_ce_fftshift2_pos 0 | |
3445 | #define reg_ce_fftshift2_len 4 | |
3446 | #define reg_ce_fftshift2_lsb 0 | |
3447 | #define xd_p_reg_ce_top_mobile 0xABF7 | |
3448 | #define reg_ce_top_mobile_pos 4 | |
3449 | #define reg_ce_top_mobile_len 1 | |
3450 | #define reg_ce_top_mobile_lsb 0 | |
3451 | #define xd_p_reg_strong_sginal_detected 0xA2BC | |
3452 | #define reg_strong_sginal_detected_pos 2 | |
3453 | #define reg_strong_sginal_detected_len 1 | |
3454 | #define reg_strong_sginal_detected_lsb 0 | |
3455 | ||
3456 | #define XD_MP2IF_BASE 0xB000 | |
3457 | #define XD_MP2IF_CSR (0x00 + XD_MP2IF_BASE) | |
3458 | #define XD_MP2IF_DMX_CTRL (0x03 + XD_MP2IF_BASE) | |
3459 | #define XD_MP2IF_PID_IDX (0x04 + XD_MP2IF_BASE) | |
3460 | #define XD_MP2IF_PID_DATA_L (0x05 + XD_MP2IF_BASE) | |
3461 | #define XD_MP2IF_PID_DATA_H (0x06 + XD_MP2IF_BASE) | |
3462 | #define XD_MP2IF_MISC (0x07 + XD_MP2IF_BASE) | |
3463 | ||
3464 | extern struct dvb_frontend *af9005_fe_attach(struct dvb_usb_device *d); | |
3465 | extern int af9005_read_ofdm_register(struct dvb_usb_device *d, u16 reg, | |
3466 | u8 * value); | |
3467 | extern int af9005_read_ofdm_registers(struct dvb_usb_device *d, u16 reg, | |
3468 | u8 * values, int len); | |
3469 | extern int af9005_write_ofdm_register(struct dvb_usb_device *d, u16 reg, | |
3470 | u8 value); | |
3471 | extern int af9005_write_ofdm_registers(struct dvb_usb_device *d, u16 reg, | |
3472 | u8 * values, int len); | |
3473 | extern int af9005_read_tuner_registers(struct dvb_usb_device *d, u16 reg, | |
3474 | u8 addr, u8 * values, int len); | |
3475 | extern int af9005_write_tuner_registers(struct dvb_usb_device *d, u16 reg, | |
3476 | u8 * values, int len); | |
3477 | extern int af9005_read_register_bits(struct dvb_usb_device *d, u16 reg, | |
3478 | u8 pos, u8 len, u8 * value); | |
3479 | extern int af9005_write_register_bits(struct dvb_usb_device *d, u16 reg, | |
3480 | u8 pos, u8 len, u8 value); | |
3481 | extern int af9005_send_command(struct dvb_usb_device *d, u8 command, | |
3482 | u8 * wbuf, int wlen, u8 * rbuf, int rlen); | |
3483 | extern int af9005_read_eeprom(struct dvb_usb_device *d, u8 address, | |
3484 | u8 * values, int len); | |
3485 | extern int af9005_tuner_attach(struct dvb_usb_adapter *adap); | |
3486 | extern int af9005_led_control(struct dvb_usb_device *d, int onoff); | |
3487 | ||
3488 | extern u8 regmask[8]; | |
3489 | ||
3490 | /* remote control decoder */ | |
3491 | extern int af9005_rc_decode(struct dvb_usb_device *d, u8 * data, int len, | |
3492 | u32 * event, int *state); | |
3493 | extern struct dvb_usb_rc_key af9005_rc_keys[]; | |
3494 | extern int af9005_rc_keys_size; | |
3495 | ||
3496 | #endif |