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V4L/DVB (7867): mxl5005s: Cleanup #4
[linux-2.6-block.git] / drivers / media / common / tuners / mxl5005s.c
CommitLineData
52c99bda
ST		 1/*
2 * For the Realtek RTL chip RTL2831U
3 * Realtek Release Date: 2008-03-14, ver 080314
4 * Realtek version RTL2831 Linux driver version 080314
5 * ver 080314
6 *
7 * for linux kernel version 2.6.21.4 - 2.6.22-14
8 * support MXL5005s and MT2060 tuners (support tuner auto-detecting)
9 * support two IR types -- RC5 and NEC
10 *
11 * Known boards with Realtek RTL chip RTL2821U
12 * Freecom USB stick 14aa:0160 (version 4)
13 * Conceptronic CTVDIGRCU
14 *
15 * Copyright (c) 2008 Realtek
16 * Copyright (c) 2008 Jan Hoogenraad, Barnaby Shearer, Andy Hasper
17 * This code is placed under the terms of the GNU General Public License
18 *
19 * Released by Realtek under GPLv2.
20 * Thanks to Realtek for a lot of support we received !
21 *
22 * Revision: 080314 - original version
23 */
24
2637d5b4 25#include "mxl5005s.h"
52c99bda 26
85d220d0
ST		 27static int debug;
28
29#define dprintk(level, arg...) do { \
30 if (debug >= level) \
31 printk(arg); \
32 } while (0)
33
34#define TUNER_REGS_NUM 104
35#define INITCTRL_NUM 40
36
37#ifdef _MXL_PRODUCTION
38#define CHCTRL_NUM 39
39#else
40#define CHCTRL_NUM 36
41#endif
42
43#define MXLCTRL_NUM 189
44#define MASTER_CONTROL_ADDR 9
45
46/* Enumeration of AGC Mode */
47typedef enum
48{
49 MXL_DUAL_AGC = 0,
50 MXL_SINGLE_AGC
51} AGC_Mode;
52
53/* Enumeration of Master Control Register State */
54typedef enum
55{
56 MC_LOAD_START = 1,
57 MC_POWER_DOWN,
58 MC_SYNTH_RESET,
59 MC_SEQ_OFF
60} Master_Control_State;
61
62/* Enumeration of MXL5005 Tuner Mode */
63typedef enum
64{
65 MXL_ANALOG_MODE = 0,
66 MXL_DIGITAL_MODE
67} Tuner_Mode;
68
69/* Enumeration of MXL5005 Tuner IF Mode */
70typedef enum
71{
72 MXL_ZERO_IF = 0,
73 MXL_LOW_IF
74} Tuner_IF_Mode;
75
76/* Enumeration of MXL5005 Tuner Clock Out Mode */
77typedef enum
78{
79 MXL_CLOCK_OUT_DISABLE = 0,
80 MXL_CLOCK_OUT_ENABLE
81} Tuner_Clock_Out;
82
83/* Enumeration of MXL5005 Tuner Div Out Mode */
84typedef enum
85{
86 MXL_DIV_OUT_1 = 0,
87 MXL_DIV_OUT_4
88
89} Tuner_Div_Out;
90
91/* Enumeration of MXL5005 Tuner Pull-up Cap Select Mode */
92typedef enum
93{
94 MXL_CAP_SEL_DISABLE = 0,
95 MXL_CAP_SEL_ENABLE
96
97} Tuner_Cap_Select;
98
99/* Enumeration of MXL5005 Tuner RSSI Mode */
100typedef enum
101{
102 MXL_RSSI_DISABLE = 0,
103 MXL_RSSI_ENABLE
104
105} Tuner_RSSI;
106
107/* Enumeration of MXL5005 Tuner Modulation Type */
108typedef enum
109{
110 MXL_DEFAULT_MODULATION = 0,
111 MXL_DVBT,
112 MXL_ATSC,
113 MXL_QAM,
114 MXL_ANALOG_CABLE,
115 MXL_ANALOG_OTA
116} Tuner_Modu_Type;
117
118/* Enumeration of MXL5005 Tuner Tracking Filter Type */
119typedef enum
120{
121 MXL_TF_DEFAULT = 0,
122 MXL_TF_OFF,
123 MXL_TF_C,
124 MXL_TF_C_H,
125 MXL_TF_D,
126 MXL_TF_D_L,
127 MXL_TF_E,
128 MXL_TF_F,
129 MXL_TF_E_2,
130 MXL_TF_E_NA,
131 MXL_TF_G
132} Tuner_TF_Type;
133
134/* MXL5005 Tuner Register Struct */
135typedef struct _TunerReg_struct
136{
137 u16 Reg_Num; /* Tuner Register Address */
138 u16 Reg_Val; /* Current sofware programmed value waiting to be writen */
139} TunerReg_struct;
140
141typedef enum
142{
143 /* Initialization Control Names */
144 DN_IQTN_AMP_CUT = 1, /* 1 */
145 BB_MODE, /* 2 */
146 BB_BUF, /* 3 */
147 BB_BUF_OA, /* 4 */
148 BB_ALPF_BANDSELECT, /* 5 */
149 BB_IQSWAP, /* 6 */
150 BB_DLPF_BANDSEL, /* 7 */
151 RFSYN_CHP_GAIN, /* 8 */
152 RFSYN_EN_CHP_HIGAIN, /* 9 */
153 AGC_IF, /* 10 */
154 AGC_RF, /* 11 */
155 IF_DIVVAL, /* 12 */
156 IF_VCO_BIAS, /* 13 */
157 CHCAL_INT_MOD_IF, /* 14 */
158 CHCAL_FRAC_MOD_IF, /* 15 */
159 DRV_RES_SEL, /* 16 */
160 I_DRIVER, /* 17 */
161 EN_AAF, /* 18 */
162 EN_3P, /* 19 */
163 EN_AUX_3P, /* 20 */
164 SEL_AAF_BAND, /* 21 */
165 SEQ_ENCLK16_CLK_OUT, /* 22 */
166 SEQ_SEL4_16B, /* 23 */
167 XTAL_CAPSELECT, /* 24 */
168 IF_SEL_DBL, /* 25 */
169 RFSYN_R_DIV, /* 26 */
170 SEQ_EXTSYNTHCALIF, /* 27 */
171 SEQ_EXTDCCAL, /* 28 */
172 AGC_EN_RSSI, /* 29 */
173 RFA_ENCLKRFAGC, /* 30 */
174 RFA_RSSI_REFH, /* 31 */
175 RFA_RSSI_REF, /* 32 */
176 RFA_RSSI_REFL, /* 33 */
177 RFA_FLR, /* 34 */
178 RFA_CEIL, /* 35 */
179 SEQ_EXTIQFSMPULSE, /* 36 */
180 OVERRIDE_1, /* 37 */
181 BB_INITSTATE_DLPF_TUNE, /* 38 */
182 TG_R_DIV, /* 39 */
183 EN_CHP_LIN_B, /* 40 */
184
185 /* Channel Change Control Names */
186 DN_POLY = 51, /* 51 */
187 DN_RFGAIN, /* 52 */
188 DN_CAP_RFLPF, /* 53 */
189 DN_EN_VHFUHFBAR, /* 54 */
190 DN_GAIN_ADJUST, /* 55 */
191 DN_IQTNBUF_AMP, /* 56 */
192 DN_IQTNGNBFBIAS_BST, /* 57 */
193 RFSYN_EN_OUTMUX, /* 58 */
194 RFSYN_SEL_VCO_OUT, /* 59 */
195 RFSYN_SEL_VCO_HI, /* 60 */
196 RFSYN_SEL_DIVM, /* 61 */
197 RFSYN_RF_DIV_BIAS, /* 62 */
198 DN_SEL_FREQ, /* 63 */
199 RFSYN_VCO_BIAS, /* 64 */
200 CHCAL_INT_MOD_RF, /* 65 */
201 CHCAL_FRAC_MOD_RF, /* 66 */
202 RFSYN_LPF_R, /* 67 */
203 CHCAL_EN_INT_RF, /* 68 */
204 TG_LO_DIVVAL, /* 69 */
205 TG_LO_SELVAL, /* 70 */
206 TG_DIV_VAL, /* 71 */
207 TG_VCO_BIAS, /* 72 */
208 SEQ_EXTPOWERUP, /* 73 */
209 OVERRIDE_2, /* 74 */
210 OVERRIDE_3, /* 75 */
211 OVERRIDE_4, /* 76 */
212 SEQ_FSM_PULSE, /* 77 */
213 GPIO_4B, /* 78 */
214 GPIO_3B, /* 79 */
215 GPIO_4, /* 80 */
216 GPIO_3, /* 81 */
217 GPIO_1B, /* 82 */
218 DAC_A_ENABLE, /* 83 */
219 DAC_B_ENABLE, /* 84 */
220 DAC_DIN_A, /* 85 */
221 DAC_DIN_B, /* 86 */
222#ifdef _MXL_PRODUCTION
223 RFSYN_EN_DIV, /* 87 */
224 RFSYN_DIVM, /* 88 */
225 DN_BYPASS_AGC_I2C /* 89 */
226#endif
227} MXL5005_ControlName;
228
229/*
230 * The following context is source code provided by MaxLinear.
231 * MaxLinear source code - Common_MXL.h (?)
232 */
233
234/* Constants */
235#define MXL5005S_REG_WRITING_TABLE_LEN_MAX 104
236#define MXL5005S_LATCH_BYTE 0xfe
237
238/* Register address, MSB, and LSB */
239#define MXL5005S_BB_IQSWAP_ADDR 59
240#define MXL5005S_BB_IQSWAP_MSB 0
241#define MXL5005S_BB_IQSWAP_LSB 0
242
243#define MXL5005S_BB_DLPF_BANDSEL_ADDR 53
244#define MXL5005S_BB_DLPF_BANDSEL_MSB 4
245#define MXL5005S_BB_DLPF_BANDSEL_LSB 3
246
247/* Standard modes */
248enum
249{
250 MXL5005S_STANDARD_DVBT,
251 MXL5005S_STANDARD_ATSC,
252};
253#define MXL5005S_STANDARD_MODE_NUM 2
254
255/* Bandwidth modes */
256enum
257{
258 MXL5005S_BANDWIDTH_6MHZ = 6000000,
259 MXL5005S_BANDWIDTH_7MHZ = 7000000,
260 MXL5005S_BANDWIDTH_8MHZ = 8000000,
261};
262#define MXL5005S_BANDWIDTH_MODE_NUM 3
263
264/* Top modes */
265enum
266{
267 MXL5005S_TOP_5P5 = 55,
268 MXL5005S_TOP_7P2 = 72,
269 MXL5005S_TOP_9P2 = 92,
270 MXL5005S_TOP_11P0 = 110,
271 MXL5005S_TOP_12P9 = 129,
272 MXL5005S_TOP_14P7 = 147,
273 MXL5005S_TOP_16P8 = 168,
274 MXL5005S_TOP_19P4 = 194,
275 MXL5005S_TOP_21P2 = 212,
276 MXL5005S_TOP_23P2 = 232,
277 MXL5005S_TOP_25P2 = 252,
278 MXL5005S_TOP_27P1 = 271,
279 MXL5005S_TOP_29P2 = 292,
280 MXL5005S_TOP_31P7 = 317,
281 MXL5005S_TOP_34P9 = 349,
282};
283
284/* IF output load */
285enum
286{
287 MXL5005S_IF_OUTPUT_LOAD_200_OHM = 200,
288 MXL5005S_IF_OUTPUT_LOAD_300_OHM = 300,
289};
290
3935c254
ST		 291/* MXL5005 Tuner Control Struct */
292typedef struct _TunerControl_struct {
293 u16 Ctrl_Num; /* Control Number */
294 u16 size; /* Number of bits to represent Value */
295 u16 addr[25]; /* Array of Tuner Register Address for each bit position */
296 u16 bit[25]; /* Array of bit position in Register Address for each bit position */
297 u16 val[25]; /* Binary representation of Value */
298} TunerControl_struct;
299
300/* MXL5005 Tuner Struct */
301struct mxl5005s_state
52c99bda 302{
3935c254
ST		 303 u8 Mode; /* 0: Analog Mode ; 1: Digital Mode */
304 u8 IF_Mode; /* for Analog Mode, 0: zero IF; 1: low IF */
305 u32 Chan_Bandwidth; /* filter channel bandwidth (6, 7, 8) */
306 u32 IF_OUT; /* Desired IF Out Frequency */
307 u16 IF_OUT_LOAD; /* IF Out Load Resistor (200/300 Ohms) */
308 u32 RF_IN; /* RF Input Frequency */
309 u32 Fxtal; /* XTAL Frequency */
310 u8 AGC_Mode; /* AGC Mode 0: Dual AGC; 1: Single AGC */
311 u16 TOP; /* Value: take over point */
312 u8 CLOCK_OUT; /* 0: turn off clock out; 1: turn on clock out */
313 u8 DIV_OUT; /* 4MHz or 16MHz */
314 u8 CAPSELECT; /* 0: disable On-Chip pulling cap; 1: enable */
315 u8 EN_RSSI; /* 0: disable RSSI; 1: enable RSSI */
316 u8 Mod_Type; /* Modulation Type; */
317 /* 0 - Default; 1 - DVB-T; 2 - ATSC; 3 - QAM; 4 - Analog Cable */
318 u8 TF_Type; /* Tracking Filter Type */
319 /* 0 - Default; 1 - Off; 2 - Type C; 3 - Type C-H */
320
321 /* Calculated Settings */
322 u32 RF_LO; /* Synth RF LO Frequency */
323 u32 IF_LO; /* Synth IF LO Frequency */
324 u32 TG_LO; /* Synth TG_LO Frequency */
325
326 /* Pointers to ControlName Arrays */
327 u16 Init_Ctrl_Num; /* Number of INIT Control Names */
328 TunerControl_struct
329 Init_Ctrl[INITCTRL_NUM]; /* INIT Control Names Array Pointer */
330
331 u16 CH_Ctrl_Num; /* Number of CH Control Names */
332 TunerControl_struct
333 CH_Ctrl[CHCTRL_NUM]; /* CH Control Name Array Pointer */
334
335 u16 MXL_Ctrl_Num; /* Number of MXL Control Names */
336 TunerControl_struct
337 MXL_Ctrl[MXLCTRL_NUM]; /* MXL Control Name Array Pointer */
338
339 /* Pointer to Tuner Register Array */
340 u16 TunerRegs_Num; /* Number of Tuner Registers */
341 TunerReg_struct
342 TunerRegs[TUNER_REGS_NUM]; /* Tuner Register Array Pointer */
52c99bda 343
85d220d0
ST		 344 /* Linux driver framework specific */
345 const struct mxl5005s_config *config;
52c99bda 346
85d220d0
ST		 347 struct dvb_frontend *frontend;
348 struct i2c_adapter *i2c;
349};
52c99bda 350
85d220d0
ST		 351// funcs
352u16 MXL_ControlWrite(struct dvb_frontend *fe, u16 ControlNum, u32 value);
353u16 MXL_ControlRead(struct dvb_frontend *fe, u16 controlNum, u32 *value);
354u16 MXL_GetMasterControl(u8 *MasterReg, int state);
355void MXL_RegWriteBit(struct dvb_frontend *fe, u8 address, u8 bit, u8 bitVal);
356u16 MXL_GetCHRegister(struct dvb_frontend *fe, u8 *RegNum, u8 *RegVal, int *count);
357u32 MXL_Ceiling(u32 value, u32 resolution);
358u16 MXL_RegRead(struct dvb_frontend *fe, u8 RegNum, u8 *RegVal);
359u16 MXL_RegWrite(struct dvb_frontend *fe, u8 RegNum, u8 RegVal);
360u16 MXL_ControlWrite_Group(struct dvb_frontend *fe, u16 controlNum, u32 value, u16 controlGroup);
361u16 MXL_SetGPIO(struct dvb_frontend *fe, u8 GPIO_Num, u8 GPIO_Val);
362u16 MXL_GetInitRegister(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, int *count);
363u32 MXL_GetXtalInt(u32 Xtal_Freq);
364u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq);
365void MXL_SynthIFLO_Calc(struct dvb_frontend *fe);
366void MXL_SynthRFTGLO_Calc(struct dvb_frontend *fe);
367u16 MXL_GetCHRegister_ZeroIF(struct dvb_frontend *fe, u8 *RegNum, u8 *RegVal, int *count);
368int mxl5005s_SetRegsWithTable(struct dvb_frontend *fe, u8 *pAddrTable, u8 *pByteTable, int TableLen);
369u16 MXL_IFSynthInit(struct dvb_frontend *fe);
370
371int mxl5005s_SetRfFreqHz(struct dvb_frontend *fe, unsigned long RfFreqHz)
52c99bda 372{
85d220d0
ST		 373 struct mxl5005s_state *state = fe->tuner_priv;
374 u8 AgcMasterByte = state->config->AgcMasterByte;
52c99bda
ST		 375 unsigned char AddrTable[MXL5005S_REG_WRITING_TABLE_LEN_MAX];
376 unsigned char ByteTable[MXL5005S_REG_WRITING_TABLE_LEN_MAX];
377 int TableLen;
378
85d220d0 379 u32 IfDivval;
52c99bda
ST		 380 unsigned char MasterControlByte;
381
85d220d0 382 dprintk(1, "%s() freq=%ld\n", __func__, RfFreqHz);
52c99bda
ST		 383
384 // Set MxL5005S tuner RF frequency according to MxL5005S tuner example code.
385
386 // Tuner RF frequency setting stage 0
387 MXL_GetMasterControl(ByteTable, MC_SYNTH_RESET) ;
388 AddrTable[0] = MASTER_CONTROL_ADDR;
85d220d0 389 ByteTable[0] |= state->config->AgcMasterByte;
52c99bda 390
85d220d0 391 mxl5005s_SetRegsWithTable(fe, AddrTable, ByteTable, 1);
52c99bda
ST		 392
393 // Tuner RF frequency setting stage 1
85d220d0 394 MXL_TuneRF(fe, RfFreqHz);
52c99bda 395
85d220d0 396 MXL_ControlRead(fe, IF_DIVVAL, &IfDivval);
52c99bda 397
85d220d0
ST		 398 MXL_ControlWrite(fe, SEQ_FSM_PULSE, 0);
399 MXL_ControlWrite(fe, SEQ_EXTPOWERUP, 1);
400 MXL_ControlWrite(fe, IF_DIVVAL, 8);
401 MXL_GetCHRegister(fe, AddrTable, ByteTable, &TableLen) ;
52c99bda
ST		 402
403 MXL_GetMasterControl(&MasterControlByte, MC_LOAD_START) ;
404 AddrTable[TableLen] = MASTER_CONTROL_ADDR ;
405 ByteTable[TableLen] = MasterControlByte | AgcMasterByte;
406 TableLen += 1;
407
85d220d0 408 mxl5005s_SetRegsWithTable(fe, AddrTable, ByteTable, TableLen);
52c99bda
ST		 409
410 // Wait 30 ms.
85d220d0 411 msleep(30);
52c99bda
ST		 412
413 // Tuner RF frequency setting stage 2
85d220d0
ST		 414 MXL_ControlWrite(fe, SEQ_FSM_PULSE, 1) ;
415 MXL_ControlWrite(fe, IF_DIVVAL, IfDivval) ;
416 MXL_GetCHRegister_ZeroIF(fe, AddrTable, ByteTable, &TableLen) ;
52c99bda
ST		 417
418 MXL_GetMasterControl(&MasterControlByte, MC_LOAD_START) ;
419 AddrTable[TableLen] = MASTER_CONTROL_ADDR ;
420 ByteTable[TableLen] = MasterControlByte | AgcMasterByte ;
421 TableLen += 1;
422
85d220d0 423 mxl5005s_SetRegsWithTable(fe, AddrTable, ByteTable, TableLen);
52c99bda 424
85d220d0 425 return 0;
52c99bda
ST		 426}
427
85d220d0
ST		 428/* Write a single byte to a single reg */
429static int mxl5005s_writereg(struct dvb_frontend *fe, u8 reg, u8 val)
52c99bda 430{
85d220d0
ST		 431 struct mxl5005s_state *state = fe->tuner_priv;
432 u8 buf[2] = { reg, val };
433 struct i2c_msg msg = { .addr = state->config->i2c_address, .flags = 0,
434 .buf = buf, .len = 2 };
435
436 if (i2c_transfer(state->i2c, &msg, 1) != 1) {
437 printk(KERN_WARNING "mxl5005s I2C write failed\n");
438 return -EREMOTEIO;
3935c254 439 }
85d220d0 440 return 0;
52c99bda
ST		 441}
442
85d220d0
ST		 443/* Write a word to a single reg */
444static int mxl5005s_writereg16(struct dvb_frontend *fe, u8 reg, u16 val)
52c99bda 445{
85d220d0
ST		 446 struct mxl5005s_state *state = fe->tuner_priv;
447 u8 buf[3] = { reg, val >> 8 , val & 0xff };
448 struct i2c_msg msg = { .addr = state->config->i2c_address, .flags = 0,
449 .buf = buf, .len = 3 };
450
451 if (i2c_transfer(state->i2c, &msg, 1) != 1) {
452 printk(KERN_WARNING "mxl5005s I2C write16 failed\n");
453 return -EREMOTEIO;
52c99bda 454 }
85d220d0 455 return 0;
52c99bda 456}
52c99bda 457
85d220d0 458int mxl5005s_SetRegsWithTable(struct dvb_frontend *fe, u8 *pAddrTable, u8 *pByteTable, int TableLen)
52c99bda 459{
85d220d0 460 int i, ret;
52c99bda 461 u8 end_two_bytes_buf[]={ 0 , 0 };
52c99bda
ST		 462
463 for( i = 0 ; i < TableLen - 1 ; i++)
464 {
85d220d0
ST		 465 ret = mxl5005s_writereg(fe, pAddrTable[i], pByteTable[i]);
466 if (!ret)
467 return ret;
52c99bda
ST		 468 }
469
470 end_two_bytes_buf[0] = pByteTable[i];
471 end_two_bytes_buf[1] = MXL5005S_LATCH_BYTE;
472
85d220d0 473 ret = mxl5005s_writereg16(fe, pAddrTable[i], (end_two_bytes_buf[0] << 8) | end_two_bytes_buf[1]);
52c99bda 474
85d220d0 475 return ret;
52c99bda
ST		 476}
477
3935c254 478int mxl5005s_SetRegMaskBits(struct dvb_frontend *fe,
52c99bda
ST		 479 unsigned char RegAddr,
480 unsigned char Msb,
481 unsigned char Lsb,
482 const unsigned char WritingValue
483 )
484{
52c99bda
ST		 485 int i;
486
487 unsigned char Mask;
488 unsigned char Shift;
52c99bda
ST		 489 unsigned char RegByte;
490
3935c254 491 /* Generate mask and shift according to MSB and LSB. */
52c99bda
ST		 492 Mask = 0;
493 for(i = Lsb; i < (unsigned char)(Msb + 1); i++)
494 Mask |= 0x1 << i;
495
496 Shift = Lsb;
497
3935c254 498 /* Get tuner register byte according to register adddress. */
85d220d0 499 MXL_RegRead(fe, RegAddr, &RegByte);
52c99bda 500
3935c254 501 /* Reserve register byte unmask bit with mask and inlay writing value into it. */
52c99bda
ST		 502 RegByte &= ~Mask;
503 RegByte |= (WritingValue << Shift) & Mask;
504
3935c254 505 /* Update tuner register byte table. */
85d220d0 506 MXL_RegWrite(fe, RegAddr, RegByte);
52c99bda 507
3935c254 508 /* Write tuner register byte with writing byte. */
85d220d0 509 return mxl5005s_SetRegsWithTable(fe, &RegAddr, &RegByte, 1);
52c99bda 510}
52c99bda
ST		 511
512// The following context is source code provided by MaxLinear.
52c99bda 513// MaxLinear source code - MXL5005_Initialize.cpp
3935c254
ST		 514// DONE
515u16 MXL5005_RegisterInit(struct dvb_frontend *fe)
52c99bda 516{
85d220d0 517 struct mxl5005s_state *state = fe->tuner_priv;
3935c254
ST		 518 state->TunerRegs_Num = TUNER_REGS_NUM ;
519// state->TunerRegs = (TunerReg_struct *) calloc( TUNER_REGS_NUM, sizeof(TunerReg_struct) ) ;
52c99bda 520
3935c254
ST		 521 state->TunerRegs[0].Reg_Num = 9 ;
522 state->TunerRegs[0].Reg_Val = 0x40 ;
52c99bda 523
3935c254
ST		 524 state->TunerRegs[1].Reg_Num = 11 ;
525 state->TunerRegs[1].Reg_Val = 0x19 ;
52c99bda 526
3935c254
ST		 527 state->TunerRegs[2].Reg_Num = 12 ;
528 state->TunerRegs[2].Reg_Val = 0x60 ;
52c99bda 529
3935c254
ST		 530 state->TunerRegs[3].Reg_Num = 13 ;
531 state->TunerRegs[3].Reg_Val = 0x00 ;
52c99bda 532
3935c254
ST		 533 state->TunerRegs[4].Reg_Num = 14 ;
534 state->TunerRegs[4].Reg_Val = 0x00 ;
52c99bda 535
3935c254
ST		 536 state->TunerRegs[5].Reg_Num = 15 ;
537 state->TunerRegs[5].Reg_Val = 0xC0 ;
52c99bda 538
3935c254
ST		 539 state->TunerRegs[6].Reg_Num = 16 ;
540 state->TunerRegs[6].Reg_Val = 0x00 ;
52c99bda 541
3935c254
ST		 542 state->TunerRegs[7].Reg_Num = 17 ;
543 state->TunerRegs[7].Reg_Val = 0x00 ;
52c99bda 544
3935c254
ST		 545 state->TunerRegs[8].Reg_Num = 18 ;
546 state->TunerRegs[8].Reg_Val = 0x00 ;
52c99bda 547
3935c254
ST		 548 state->TunerRegs[9].Reg_Num = 19 ;
549 state->TunerRegs[9].Reg_Val = 0x34 ;
52c99bda 550
3935c254
ST		 551 state->TunerRegs[10].Reg_Num = 21 ;
552 state->TunerRegs[10].Reg_Val = 0x00 ;
52c99bda 553
3935c254
ST		 554 state->TunerRegs[11].Reg_Num = 22 ;
555 state->TunerRegs[11].Reg_Val = 0x6B ;
52c99bda 556
3935c254
ST		 557 state->TunerRegs[12].Reg_Num = 23 ;
558 state->TunerRegs[12].Reg_Val = 0x35 ;
52c99bda 559
3935c254
ST		 560 state->TunerRegs[13].Reg_Num = 24 ;
561 state->TunerRegs[13].Reg_Val = 0x70 ;
52c99bda 562
3935c254
ST		 563 state->TunerRegs[14].Reg_Num = 25 ;
564 state->TunerRegs[14].Reg_Val = 0x3E ;
52c99bda 565
3935c254
ST		 566 state->TunerRegs[15].Reg_Num = 26 ;
567 state->TunerRegs[15].Reg_Val = 0x82 ;
52c99bda 568
3935c254
ST		 569 state->TunerRegs[16].Reg_Num = 31 ;
570 state->TunerRegs[16].Reg_Val = 0x00 ;
52c99bda 571
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ST		 572 state->TunerRegs[17].Reg_Num = 32 ;
573 state->TunerRegs[17].Reg_Val = 0x40 ;
52c99bda 574
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ST		 575 state->TunerRegs[18].Reg_Num = 33 ;
576 state->TunerRegs[18].Reg_Val = 0x53 ;
52c99bda 577
3935c254
ST		 578 state->TunerRegs[19].Reg_Num = 34 ;
579 state->TunerRegs[19].Reg_Val = 0x81 ;
52c99bda 580
3935c254
ST		 581 state->TunerRegs[20].Reg_Num = 35 ;
582 state->TunerRegs[20].Reg_Val = 0xC9 ;
52c99bda 583
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ST		 584 state->TunerRegs[21].Reg_Num = 36 ;
585 state->TunerRegs[21].Reg_Val = 0x01 ;
52c99bda 586
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ST		 587 state->TunerRegs[22].Reg_Num = 37 ;
588 state->TunerRegs[22].Reg_Val = 0x00 ;
52c99bda 589
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ST		 590 state->TunerRegs[23].Reg_Num = 41 ;
591 state->TunerRegs[23].Reg_Val = 0x00 ;
52c99bda 592
3935c254
ST		 593 state->TunerRegs[24].Reg_Num = 42 ;
594 state->TunerRegs[24].Reg_Val = 0xF8 ;
52c99bda 595
3935c254
ST		 596 state->TunerRegs[25].Reg_Num = 43 ;
597 state->TunerRegs[25].Reg_Val = 0x43 ;
52c99bda 598
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ST		 599 state->TunerRegs[26].Reg_Num = 44 ;
600 state->TunerRegs[26].Reg_Val = 0x20 ;
52c99bda 601
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ST		 602 state->TunerRegs[27].Reg_Num = 45 ;
603 state->TunerRegs[27].Reg_Val = 0x80 ;
52c99bda 604
3935c254
ST		 605 state->TunerRegs[28].Reg_Num = 46 ;
606 state->TunerRegs[28].Reg_Val = 0x88 ;
52c99bda 607
3935c254
ST		 608 state->TunerRegs[29].Reg_Num = 47 ;
609 state->TunerRegs[29].Reg_Val = 0x86 ;
52c99bda 610
3935c254
ST		 611 state->TunerRegs[30].Reg_Num = 48 ;
612 state->TunerRegs[30].Reg_Val = 0x00 ;
52c99bda 613
3935c254
ST		 614 state->TunerRegs[31].Reg_Num = 49 ;
615 state->TunerRegs[31].Reg_Val = 0x00 ;
52c99bda 616
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ST		 617 state->TunerRegs[32].Reg_Num = 53 ;
618 state->TunerRegs[32].Reg_Val = 0x94 ;
52c99bda 619
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ST		 620 state->TunerRegs[33].Reg_Num = 54 ;
621 state->TunerRegs[33].Reg_Val = 0xFA ;
52c99bda 622
3935c254
ST		 623 state->TunerRegs[34].Reg_Num = 55 ;
624 state->TunerRegs[34].Reg_Val = 0x92 ;
52c99bda 625
3935c254
ST		 626 state->TunerRegs[35].Reg_Num = 56 ;
627 state->TunerRegs[35].Reg_Val = 0x80 ;
52c99bda 628
3935c254
ST		 629 state->TunerRegs[36].Reg_Num = 57 ;
630 state->TunerRegs[36].Reg_Val = 0x41 ;
52c99bda 631
3935c254
ST		 632 state->TunerRegs[37].Reg_Num = 58 ;
633 state->TunerRegs[37].Reg_Val = 0xDB ;
52c99bda 634
3935c254
ST		 635 state->TunerRegs[38].Reg_Num = 59 ;
636 state->TunerRegs[38].Reg_Val = 0x00 ;
52c99bda 637
3935c254
ST		 638 state->TunerRegs[39].Reg_Num = 60 ;
639 state->TunerRegs[39].Reg_Val = 0x00 ;
52c99bda 640
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ST		 641 state->TunerRegs[40].Reg_Num = 61 ;
642 state->TunerRegs[40].Reg_Val = 0x00 ;
52c99bda 643
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ST		 644 state->TunerRegs[41].Reg_Num = 62 ;
645 state->TunerRegs[41].Reg_Val = 0x00 ;
52c99bda 646
3935c254
ST		 647 state->TunerRegs[42].Reg_Num = 65 ;
648 state->TunerRegs[42].Reg_Val = 0xF8 ;
52c99bda 649
3935c254
ST		 650 state->TunerRegs[43].Reg_Num = 66 ;
651 state->TunerRegs[43].Reg_Val = 0xE4 ;
52c99bda 652
3935c254
ST		 653 state->TunerRegs[44].Reg_Num = 67 ;
654 state->TunerRegs[44].Reg_Val = 0x90 ;
52c99bda 655
3935c254
ST		 656 state->TunerRegs[45].Reg_Num = 68 ;
657 state->TunerRegs[45].Reg_Val = 0xC0 ;
52c99bda 658
3935c254
ST		 659 state->TunerRegs[46].Reg_Num = 69 ;
660 state->TunerRegs[46].Reg_Val = 0x01 ;
52c99bda 661
3935c254
ST		 662 state->TunerRegs[47].Reg_Num = 70 ;
663 state->TunerRegs[47].Reg_Val = 0x50 ;
52c99bda 664
3935c254
ST		 665 state->TunerRegs[48].Reg_Num = 71 ;
666 state->TunerRegs[48].Reg_Val = 0x06 ;
52c99bda 667
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ST		 668 state->TunerRegs[49].Reg_Num = 72 ;
669 state->TunerRegs[49].Reg_Val = 0x00 ;
52c99bda 670
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ST		 671 state->TunerRegs[50].Reg_Num = 73 ;
672 state->TunerRegs[50].Reg_Val = 0x20 ;
52c99bda 673
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ST		 674 state->TunerRegs[51].Reg_Num = 76 ;
675 state->TunerRegs[51].Reg_Val = 0xBB ;
52c99bda 676
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ST		 677 state->TunerRegs[52].Reg_Num = 77 ;
678 state->TunerRegs[52].Reg_Val = 0x13 ;
52c99bda 679
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ST		 680 state->TunerRegs[53].Reg_Num = 81 ;
681 state->TunerRegs[53].Reg_Val = 0x04 ;
52c99bda 682
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ST		 683 state->TunerRegs[54].Reg_Num = 82 ;
684 state->TunerRegs[54].Reg_Val = 0x75 ;
52c99bda 685
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ST		 686 state->TunerRegs[55].Reg_Num = 83 ;
687 state->TunerRegs[55].Reg_Val = 0x00 ;
52c99bda 688
3935c254
ST		 689 state->TunerRegs[56].Reg_Num = 84 ;
690 state->TunerRegs[56].Reg_Val = 0x00 ;
52c99bda 691
3935c254
ST		 692 state->TunerRegs[57].Reg_Num = 85 ;
693 state->TunerRegs[57].Reg_Val = 0x00 ;
52c99bda 694
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ST		 695 state->TunerRegs[58].Reg_Num = 91 ;
696 state->TunerRegs[58].Reg_Val = 0x70 ;
52c99bda 697
3935c254
ST		 698 state->TunerRegs[59].Reg_Num = 92 ;
699 state->TunerRegs[59].Reg_Val = 0x00 ;
52c99bda 700
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ST		 701 state->TunerRegs[60].Reg_Num = 93 ;
702 state->TunerRegs[60].Reg_Val = 0x00 ;
52c99bda 703
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ST		 704 state->TunerRegs[61].Reg_Num = 94 ;
705 state->TunerRegs[61].Reg_Val = 0x00 ;
52c99bda 706
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ST		 707 state->TunerRegs[62].Reg_Num = 95 ;
708 state->TunerRegs[62].Reg_Val = 0x0C ;
52c99bda 709
3935c254
ST		 710 state->TunerRegs[63].Reg_Num = 96 ;
711 state->TunerRegs[63].Reg_Val = 0x00 ;
52c99bda 712
3935c254
ST		 713 state->TunerRegs[64].Reg_Num = 97 ;
714 state->TunerRegs[64].Reg_Val = 0x00 ;
52c99bda 715
3935c254
ST		 716 state->TunerRegs[65].Reg_Num = 98 ;
717 state->TunerRegs[65].Reg_Val = 0xE2 ;
52c99bda 718
3935c254
ST		 719 state->TunerRegs[66].Reg_Num = 99 ;
720 state->TunerRegs[66].Reg_Val = 0x00 ;
52c99bda 721
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ST		 722 state->TunerRegs[67].Reg_Num = 100 ;
723 state->TunerRegs[67].Reg_Val = 0x00 ;
52c99bda 724
3935c254
ST		 725 state->TunerRegs[68].Reg_Num = 101 ;
726 state->TunerRegs[68].Reg_Val = 0x12 ;
52c99bda 727
3935c254
ST		 728 state->TunerRegs[69].Reg_Num = 102 ;
729 state->TunerRegs[69].Reg_Val = 0x80 ;
52c99bda 730
3935c254
ST		 731 state->TunerRegs[70].Reg_Num = 103 ;
732 state->TunerRegs[70].Reg_Val = 0x32 ;
52c99bda 733
3935c254
ST		 734 state->TunerRegs[71].Reg_Num = 104 ;
735 state->TunerRegs[71].Reg_Val = 0xB4 ;
52c99bda 736
3935c254
ST		 737 state->TunerRegs[72].Reg_Num = 105 ;
738 state->TunerRegs[72].Reg_Val = 0x60 ;
52c99bda 739
3935c254
ST		 740 state->TunerRegs[73].Reg_Num = 106 ;
741 state->TunerRegs[73].Reg_Val = 0x83 ;
52c99bda 742
3935c254
ST		 743 state->TunerRegs[74].Reg_Num = 107 ;
744 state->TunerRegs[74].Reg_Val = 0x84 ;
52c99bda 745
3935c254
ST		 746 state->TunerRegs[75].Reg_Num = 108 ;
747 state->TunerRegs[75].Reg_Val = 0x9C ;
52c99bda 748
3935c254
ST		 749 state->TunerRegs[76].Reg_Num = 109 ;
750 state->TunerRegs[76].Reg_Val = 0x02 ;
52c99bda 751
3935c254
ST		 752 state->TunerRegs[77].Reg_Num = 110 ;
753 state->TunerRegs[77].Reg_Val = 0x81 ;
52c99bda 754
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ST		 755 state->TunerRegs[78].Reg_Num = 111 ;
756 state->TunerRegs[78].Reg_Val = 0xC0 ;
52c99bda 757
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ST		 758 state->TunerRegs[79].Reg_Num = 112 ;
759 state->TunerRegs[79].Reg_Val = 0x10 ;
52c99bda 760
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ST		 761 state->TunerRegs[80].Reg_Num = 131 ;
762 state->TunerRegs[80].Reg_Val = 0x8A ;
52c99bda 763
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ST		 764 state->TunerRegs[81].Reg_Num = 132 ;
765 state->TunerRegs[81].Reg_Val = 0x10 ;
52c99bda 766
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ST		 767 state->TunerRegs[82].Reg_Num = 133 ;
768 state->TunerRegs[82].Reg_Val = 0x24 ;
52c99bda 769
3935c254
ST		 770 state->TunerRegs[83].Reg_Num = 134 ;
771 state->TunerRegs[83].Reg_Val = 0x00 ;
52c99bda 772
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ST		 773 state->TunerRegs[84].Reg_Num = 135 ;
774 state->TunerRegs[84].Reg_Val = 0x00 ;
52c99bda 775
3935c254
ST		 776 state->TunerRegs[85].Reg_Num = 136 ;
777 state->TunerRegs[85].Reg_Val = 0x7E ;
52c99bda 778
3935c254
ST		 779 state->TunerRegs[86].Reg_Num = 137 ;
780 state->TunerRegs[86].Reg_Val = 0x40 ;
52c99bda 781
3935c254
ST		 782 state->TunerRegs[87].Reg_Num = 138 ;
783 state->TunerRegs[87].Reg_Val = 0x38 ;
52c99bda 784
3935c254
ST		 785 state->TunerRegs[88].Reg_Num = 146 ;
786 state->TunerRegs[88].Reg_Val = 0xF6 ;
52c99bda 787
3935c254
ST		 788 state->TunerRegs[89].Reg_Num = 147 ;
789 state->TunerRegs[89].Reg_Val = 0x1A ;
52c99bda 790
3935c254
ST		 791 state->TunerRegs[90].Reg_Num = 148 ;
792 state->TunerRegs[90].Reg_Val = 0x62 ;
52c99bda 793
3935c254
ST		 794 state->TunerRegs[91].Reg_Num = 149 ;
795 state->TunerRegs[91].Reg_Val = 0x33 ;
52c99bda 796
3935c254
ST		 797 state->TunerRegs[92].Reg_Num = 150 ;
798 state->TunerRegs[92].Reg_Val = 0x80 ;
52c99bda 799
3935c254
ST		 800 state->TunerRegs[93].Reg_Num = 156 ;
801 state->TunerRegs[93].Reg_Val = 0x56 ;
52c99bda 802
3935c254
ST		 803 state->TunerRegs[94].Reg_Num = 157 ;
804 state->TunerRegs[94].Reg_Val = 0x17 ;
52c99bda 805
3935c254
ST		 806 state->TunerRegs[95].Reg_Num = 158 ;
807 state->TunerRegs[95].Reg_Val = 0xA9 ;
52c99bda 808
3935c254
ST		 809 state->TunerRegs[96].Reg_Num = 159 ;
810 state->TunerRegs[96].Reg_Val = 0x00 ;
52c99bda 811
3935c254
ST		 812 state->TunerRegs[97].Reg_Num = 160 ;
813 state->TunerRegs[97].Reg_Val = 0x00 ;
52c99bda 814
3935c254
ST		 815 state->TunerRegs[98].Reg_Num = 161 ;
816 state->TunerRegs[98].Reg_Val = 0x00 ;
52c99bda 817
3935c254
ST		 818 state->TunerRegs[99].Reg_Num = 162 ;
819 state->TunerRegs[99].Reg_Val = 0x40 ;
52c99bda 820
3935c254
ST		 821 state->TunerRegs[100].Reg_Num = 166 ;
822 state->TunerRegs[100].Reg_Val = 0xAE ;
52c99bda 823
3935c254
ST		 824 state->TunerRegs[101].Reg_Num = 167 ;
825 state->TunerRegs[101].Reg_Val = 0x1B ;
52c99bda 826
3935c254
ST		 827 state->TunerRegs[102].Reg_Num = 168 ;
828 state->TunerRegs[102].Reg_Val = 0xF2 ;
52c99bda 829
3935c254
ST		 830 state->TunerRegs[103].Reg_Num = 195 ;
831 state->TunerRegs[103].Reg_Val = 0x00 ;
52c99bda
ST		 832
833 return 0 ;
834}
835
3935c254
ST		 836// DONE
837u16 MXL5005_ControlInit(struct dvb_frontend *fe)
52c99bda 838{
85d220d0 839 struct mxl5005s_state *state = fe->tuner_priv;
3935c254
ST		 840 state->Init_Ctrl_Num = INITCTRL_NUM;
841
842 state->Init_Ctrl[0].Ctrl_Num = DN_IQTN_AMP_CUT ;
843 state->Init_Ctrl[0].size = 1 ;
844 state->Init_Ctrl[0].addr[0] = 73;
845 state->Init_Ctrl[0].bit[0] = 7;
846 state->Init_Ctrl[0].val[0] = 0;
847
848 state->Init_Ctrl[1].Ctrl_Num = BB_MODE ;
849 state->Init_Ctrl[1].size = 1 ;
850 state->Init_Ctrl[1].addr[0] = 53;
851 state->Init_Ctrl[1].bit[0] = 2;
852 state->Init_Ctrl[1].val[0] = 1;
853
854 state->Init_Ctrl[2].Ctrl_Num = BB_BUF ;
855 state->Init_Ctrl[2].size = 2 ;
856 state->Init_Ctrl[2].addr[0] = 53;
857 state->Init_Ctrl[2].bit[0] = 1;
858 state->Init_Ctrl[2].val[0] = 0;
859 state->Init_Ctrl[2].addr[1] = 57;
860 state->Init_Ctrl[2].bit[1] = 0;
861 state->Init_Ctrl[2].val[1] = 1;
862
863 state->Init_Ctrl[3].Ctrl_Num = BB_BUF_OA ;
864 state->Init_Ctrl[3].size = 1 ;
865 state->Init_Ctrl[3].addr[0] = 53;
866 state->Init_Ctrl[3].bit[0] = 0;
867 state->Init_Ctrl[3].val[0] = 0;
868
869 state->Init_Ctrl[4].Ctrl_Num = BB_ALPF_BANDSELECT ;
870 state->Init_Ctrl[4].size = 3 ;
871 state->Init_Ctrl[4].addr[0] = 53;
872 state->Init_Ctrl[4].bit[0] = 5;
873 state->Init_Ctrl[4].val[0] = 0;
874 state->Init_Ctrl[4].addr[1] = 53;
875 state->Init_Ctrl[4].bit[1] = 6;
876 state->Init_Ctrl[4].val[1] = 0;
877 state->Init_Ctrl[4].addr[2] = 53;
878 state->Init_Ctrl[4].bit[2] = 7;
879 state->Init_Ctrl[4].val[2] = 1;
880
881 state->Init_Ctrl[5].Ctrl_Num = BB_IQSWAP ;
882 state->Init_Ctrl[5].size = 1 ;
883 state->Init_Ctrl[5].addr[0] = 59;
884 state->Init_Ctrl[5].bit[0] = 0;
885 state->Init_Ctrl[5].val[0] = 0;
886
887 state->Init_Ctrl[6].Ctrl_Num = BB_DLPF_BANDSEL ;
888 state->Init_Ctrl[6].size = 2 ;
889 state->Init_Ctrl[6].addr[0] = 53;
890 state->Init_Ctrl[6].bit[0] = 3;
891 state->Init_Ctrl[6].val[0] = 0;
892 state->Init_Ctrl[6].addr[1] = 53;
893 state->Init_Ctrl[6].bit[1] = 4;
894 state->Init_Ctrl[6].val[1] = 1;
895
896 state->Init_Ctrl[7].Ctrl_Num = RFSYN_CHP_GAIN ;
897 state->Init_Ctrl[7].size = 4 ;
898 state->Init_Ctrl[7].addr[0] = 22;
899 state->Init_Ctrl[7].bit[0] = 4;
900 state->Init_Ctrl[7].val[0] = 0;
901 state->Init_Ctrl[7].addr[1] = 22;
902 state->Init_Ctrl[7].bit[1] = 5;
903 state->Init_Ctrl[7].val[1] = 1;
904 state->Init_Ctrl[7].addr[2] = 22;
905 state->Init_Ctrl[7].bit[2] = 6;
906 state->Init_Ctrl[7].val[2] = 1;
907 state->Init_Ctrl[7].addr[3] = 22;
908 state->Init_Ctrl[7].bit[3] = 7;
909 state->Init_Ctrl[7].val[3] = 0;
910
911 state->Init_Ctrl[8].Ctrl_Num = RFSYN_EN_CHP_HIGAIN ;
912 state->Init_Ctrl[8].size = 1 ;
913 state->Init_Ctrl[8].addr[0] = 22;
914 state->Init_Ctrl[8].bit[0] = 2;
915 state->Init_Ctrl[8].val[0] = 0;
916
917 state->Init_Ctrl[9].Ctrl_Num = AGC_IF ;
918 state->Init_Ctrl[9].size = 4 ;
919 state->Init_Ctrl[9].addr[0] = 76;
920 state->Init_Ctrl[9].bit[0] = 0;
921 state->Init_Ctrl[9].val[0] = 1;
922 state->Init_Ctrl[9].addr[1] = 76;
923 state->Init_Ctrl[9].bit[1] = 1;
924 state->Init_Ctrl[9].val[1] = 1;
925 state->Init_Ctrl[9].addr[2] = 76;
926 state->Init_Ctrl[9].bit[2] = 2;
927 state->Init_Ctrl[9].val[2] = 0;
928 state->Init_Ctrl[9].addr[3] = 76;
929 state->Init_Ctrl[9].bit[3] = 3;
930 state->Init_Ctrl[9].val[3] = 1;
931
932 state->Init_Ctrl[10].Ctrl_Num = AGC_RF ;
933 state->Init_Ctrl[10].size = 4 ;
934 state->Init_Ctrl[10].addr[0] = 76;
935 state->Init_Ctrl[10].bit[0] = 4;
936 state->Init_Ctrl[10].val[0] = 1;
937 state->Init_Ctrl[10].addr[1] = 76;
938 state->Init_Ctrl[10].bit[1] = 5;
939 state->Init_Ctrl[10].val[1] = 1;
940 state->Init_Ctrl[10].addr[2] = 76;
941 state->Init_Ctrl[10].bit[2] = 6;
942 state->Init_Ctrl[10].val[2] = 0;
943 state->Init_Ctrl[10].addr[3] = 76;
944 state->Init_Ctrl[10].bit[3] = 7;
945 state->Init_Ctrl[10].val[3] = 1;
946
947 state->Init_Ctrl[11].Ctrl_Num = IF_DIVVAL ;
948 state->Init_Ctrl[11].size = 5 ;
949 state->Init_Ctrl[11].addr[0] = 43;
950 state->Init_Ctrl[11].bit[0] = 3;
951 state->Init_Ctrl[11].val[0] = 0;
952 state->Init_Ctrl[11].addr[1] = 43;
953 state->Init_Ctrl[11].bit[1] = 4;
954 state->Init_Ctrl[11].val[1] = 0;
955 state->Init_Ctrl[11].addr[2] = 43;
956 state->Init_Ctrl[11].bit[2] = 5;
957 state->Init_Ctrl[11].val[2] = 0;
958 state->Init_Ctrl[11].addr[3] = 43;
959 state->Init_Ctrl[11].bit[3] = 6;
960 state->Init_Ctrl[11].val[3] = 1;
961 state->Init_Ctrl[11].addr[4] = 43;
962 state->Init_Ctrl[11].bit[4] = 7;
963 state->Init_Ctrl[11].val[4] = 0;
964
965 state->Init_Ctrl[12].Ctrl_Num = IF_VCO_BIAS ;
966 state->Init_Ctrl[12].size = 6 ;
967 state->Init_Ctrl[12].addr[0] = 44;
968 state->Init_Ctrl[12].bit[0] = 2;
969 state->Init_Ctrl[12].val[0] = 0;
970 state->Init_Ctrl[12].addr[1] = 44;
971 state->Init_Ctrl[12].bit[1] = 3;
972 state->Init_Ctrl[12].val[1] = 0;
973 state->Init_Ctrl[12].addr[2] = 44;
974 state->Init_Ctrl[12].bit[2] = 4;
975 state->Init_Ctrl[12].val[2] = 0;
976 state->Init_Ctrl[12].addr[3] = 44;
977 state->Init_Ctrl[12].bit[3] = 5;
978 state->Init_Ctrl[12].val[3] = 1;
979 state->Init_Ctrl[12].addr[4] = 44;
980 state->Init_Ctrl[12].bit[4] = 6;
981 state->Init_Ctrl[12].val[4] = 0;
982 state->Init_Ctrl[12].addr[5] = 44;
983 state->Init_Ctrl[12].bit[5] = 7;
984 state->Init_Ctrl[12].val[5] = 0;
985
986 state->Init_Ctrl[13].Ctrl_Num = CHCAL_INT_MOD_IF ;
987 state->Init_Ctrl[13].size = 7 ;
988 state->Init_Ctrl[13].addr[0] = 11;
989 state->Init_Ctrl[13].bit[0] = 0;
990 state->Init_Ctrl[13].val[0] = 1;
991 state->Init_Ctrl[13].addr[1] = 11;
992 state->Init_Ctrl[13].bit[1] = 1;
993 state->Init_Ctrl[13].val[1] = 0;
994 state->Init_Ctrl[13].addr[2] = 11;
995 state->Init_Ctrl[13].bit[2] = 2;
996 state->Init_Ctrl[13].val[2] = 0;
997 state->Init_Ctrl[13].addr[3] = 11;
998 state->Init_Ctrl[13].bit[3] = 3;
999 state->Init_Ctrl[13].val[3] = 1;
1000 state->Init_Ctrl[13].addr[4] = 11;
1001 state->Init_Ctrl[13].bit[4] = 4;
1002 state->Init_Ctrl[13].val[4] = 1;
1003 state->Init_Ctrl[13].addr[5] = 11;
1004 state->Init_Ctrl[13].bit[5] = 5;
1005 state->Init_Ctrl[13].val[5] = 0;
1006 state->Init_Ctrl[13].addr[6] = 11;
1007 state->Init_Ctrl[13].bit[6] = 6;
1008 state->Init_Ctrl[13].val[6] = 0;
1009
1010 state->Init_Ctrl[14].Ctrl_Num = CHCAL_FRAC_MOD_IF ;
1011 state->Init_Ctrl[14].size = 16 ;
1012 state->Init_Ctrl[14].addr[0] = 13;
1013 state->Init_Ctrl[14].bit[0] = 0;
1014 state->Init_Ctrl[14].val[0] = 0;
1015 state->Init_Ctrl[14].addr[1] = 13;
1016 state->Init_Ctrl[14].bit[1] = 1;
1017 state->Init_Ctrl[14].val[1] = 0;
1018 state->Init_Ctrl[14].addr[2] = 13;
1019 state->Init_Ctrl[14].bit[2] = 2;
1020 state->Init_Ctrl[14].val[2] = 0;
1021 state->Init_Ctrl[14].addr[3] = 13;
1022 state->Init_Ctrl[14].bit[3] = 3;
1023 state->Init_Ctrl[14].val[3] = 0;
1024 state->Init_Ctrl[14].addr[4] = 13;
1025 state->Init_Ctrl[14].bit[4] = 4;
1026 state->Init_Ctrl[14].val[4] = 0;
1027 state->Init_Ctrl[14].addr[5] = 13;
1028 state->Init_Ctrl[14].bit[5] = 5;
1029 state->Init_Ctrl[14].val[5] = 0;
1030 state->Init_Ctrl[14].addr[6] = 13;
1031 state->Init_Ctrl[14].bit[6] = 6;
1032 state->Init_Ctrl[14].val[6] = 0;
1033 state->Init_Ctrl[14].addr[7] = 13;
1034 state->Init_Ctrl[14].bit[7] = 7;
1035 state->Init_Ctrl[14].val[7] = 0;
1036 state->Init_Ctrl[14].addr[8] = 12;
1037 state->Init_Ctrl[14].bit[8] = 0;
1038 state->Init_Ctrl[14].val[8] = 0;
1039 state->Init_Ctrl[14].addr[9] = 12;
1040 state->Init_Ctrl[14].bit[9] = 1;
1041 state->Init_Ctrl[14].val[9] = 0;
1042 state->Init_Ctrl[14].addr[10] = 12;
1043 state->Init_Ctrl[14].bit[10] = 2;
1044 state->Init_Ctrl[14].val[10] = 0;
1045 state->Init_Ctrl[14].addr[11] = 12;
1046 state->Init_Ctrl[14].bit[11] = 3;
1047 state->Init_Ctrl[14].val[11] = 0;
1048 state->Init_Ctrl[14].addr[12] = 12;
1049 state->Init_Ctrl[14].bit[12] = 4;
1050 state->Init_Ctrl[14].val[12] = 0;
1051 state->Init_Ctrl[14].addr[13] = 12;
1052 state->Init_Ctrl[14].bit[13] = 5;
1053 state->Init_Ctrl[14].val[13] = 1;
1054 state->Init_Ctrl[14].addr[14] = 12;
1055 state->Init_Ctrl[14].bit[14] = 6;
1056 state->Init_Ctrl[14].val[14] = 1;
1057 state->Init_Ctrl[14].addr[15] = 12;
1058 state->Init_Ctrl[14].bit[15] = 7;
1059 state->Init_Ctrl[14].val[15] = 0;
1060
1061 state->Init_Ctrl[15].Ctrl_Num = DRV_RES_SEL ;
1062 state->Init_Ctrl[15].size = 3 ;
1063 state->Init_Ctrl[15].addr[0] = 147;
1064 state->Init_Ctrl[15].bit[0] = 2;
1065 state->Init_Ctrl[15].val[0] = 0;
1066 state->Init_Ctrl[15].addr[1] = 147;
1067 state->Init_Ctrl[15].bit[1] = 3;
1068 state->Init_Ctrl[15].val[1] = 1;
1069 state->Init_Ctrl[15].addr[2] = 147;
1070 state->Init_Ctrl[15].bit[2] = 4;
1071 state->Init_Ctrl[15].val[2] = 1;
1072
1073 state->Init_Ctrl[16].Ctrl_Num = I_DRIVER ;
1074 state->Init_Ctrl[16].size = 2 ;
1075 state->Init_Ctrl[16].addr[0] = 147;
1076 state->Init_Ctrl[16].bit[0] = 0;
1077 state->Init_Ctrl[16].val[0] = 0;
1078 state->Init_Ctrl[16].addr[1] = 147;
1079 state->Init_Ctrl[16].bit[1] = 1;
1080 state->Init_Ctrl[16].val[1] = 1;
1081
1082 state->Init_Ctrl[17].Ctrl_Num = EN_AAF ;
1083 state->Init_Ctrl[17].size = 1 ;
1084 state->Init_Ctrl[17].addr[0] = 147;
1085 state->Init_Ctrl[17].bit[0] = 7;
1086 state->Init_Ctrl[17].val[0] = 0;
1087
1088 state->Init_Ctrl[18].Ctrl_Num = EN_3P ;
1089 state->Init_Ctrl[18].size = 1 ;
1090 state->Init_Ctrl[18].addr[0] = 147;
1091 state->Init_Ctrl[18].bit[0] = 6;
1092 state->Init_Ctrl[18].val[0] = 0;
1093
1094 state->Init_Ctrl[19].Ctrl_Num = EN_AUX_3P ;
1095 state->Init_Ctrl[19].size = 1 ;
1096 state->Init_Ctrl[19].addr[0] = 156;
1097 state->Init_Ctrl[19].bit[0] = 0;
1098 state->Init_Ctrl[19].val[0] = 0;
1099
1100 state->Init_Ctrl[20].Ctrl_Num = SEL_AAF_BAND ;
1101 state->Init_Ctrl[20].size = 1 ;
1102 state->Init_Ctrl[20].addr[0] = 147;
1103 state->Init_Ctrl[20].bit[0] = 5;
1104 state->Init_Ctrl[20].val[0] = 0;
1105
1106 state->Init_Ctrl[21].Ctrl_Num = SEQ_ENCLK16_CLK_OUT ;
1107 state->Init_Ctrl[21].size = 1 ;
1108 state->Init_Ctrl[21].addr[0] = 137;
1109 state->Init_Ctrl[21].bit[0] = 4;
1110 state->Init_Ctrl[21].val[0] = 0;
1111
1112 state->Init_Ctrl[22].Ctrl_Num = SEQ_SEL4_16B ;
1113 state->Init_Ctrl[22].size = 1 ;
1114 state->Init_Ctrl[22].addr[0] = 137;
1115 state->Init_Ctrl[22].bit[0] = 7;
1116 state->Init_Ctrl[22].val[0] = 0;
1117
1118 state->Init_Ctrl[23].Ctrl_Num = XTAL_CAPSELECT ;
1119 state->Init_Ctrl[23].size = 1 ;
1120 state->Init_Ctrl[23].addr[0] = 91;
1121 state->Init_Ctrl[23].bit[0] = 5;
1122 state->Init_Ctrl[23].val[0] = 1;
1123
1124 state->Init_Ctrl[24].Ctrl_Num = IF_SEL_DBL ;
1125 state->Init_Ctrl[24].size = 1 ;
1126 state->Init_Ctrl[24].addr[0] = 43;
1127 state->Init_Ctrl[24].bit[0] = 0;
1128 state->Init_Ctrl[24].val[0] = 1;
1129
1130 state->Init_Ctrl[25].Ctrl_Num = RFSYN_R_DIV ;
1131 state->Init_Ctrl[25].size = 2 ;
1132 state->Init_Ctrl[25].addr[0] = 22;
1133 state->Init_Ctrl[25].bit[0] = 0;
1134 state->Init_Ctrl[25].val[0] = 1;
1135 state->Init_Ctrl[25].addr[1] = 22;
1136 state->Init_Ctrl[25].bit[1] = 1;
1137 state->Init_Ctrl[25].val[1] = 1;
1138
1139 state->Init_Ctrl[26].Ctrl_Num = SEQ_EXTSYNTHCALIF ;
1140 state->Init_Ctrl[26].size = 1 ;
1141 state->Init_Ctrl[26].addr[0] = 134;
1142 state->Init_Ctrl[26].bit[0] = 2;
1143 state->Init_Ctrl[26].val[0] = 0;
1144
1145 state->Init_Ctrl[27].Ctrl_Num = SEQ_EXTDCCAL ;
1146 state->Init_Ctrl[27].size = 1 ;
1147 state->Init_Ctrl[27].addr[0] = 137;
1148 state->Init_Ctrl[27].bit[0] = 3;
1149 state->Init_Ctrl[27].val[0] = 0;
1150
1151 state->Init_Ctrl[28].Ctrl_Num = AGC_EN_RSSI ;
1152 state->Init_Ctrl[28].size = 1 ;
1153 state->Init_Ctrl[28].addr[0] = 77;
1154 state->Init_Ctrl[28].bit[0] = 7;
1155 state->Init_Ctrl[28].val[0] = 0;
1156
1157 state->Init_Ctrl[29].Ctrl_Num = RFA_ENCLKRFAGC ;
1158 state->Init_Ctrl[29].size = 1 ;
1159 state->Init_Ctrl[29].addr[0] = 166;
1160 state->Init_Ctrl[29].bit[0] = 7;
1161 state->Init_Ctrl[29].val[0] = 1;
1162
1163 state->Init_Ctrl[30].Ctrl_Num = RFA_RSSI_REFH ;
1164 state->Init_Ctrl[30].size = 3 ;
1165 state->Init_Ctrl[30].addr[0] = 166;
1166 state->Init_Ctrl[30].bit[0] = 0;
1167 state->Init_Ctrl[30].val[0] = 0;
1168 state->Init_Ctrl[30].addr[1] = 166;
1169 state->Init_Ctrl[30].bit[1] = 1;
1170 state->Init_Ctrl[30].val[1] = 1;
1171 state->Init_Ctrl[30].addr[2] = 166;
1172 state->Init_Ctrl[30].bit[2] = 2;
1173 state->Init_Ctrl[30].val[2] = 1;
1174
1175 state->Init_Ctrl[31].Ctrl_Num = RFA_RSSI_REF ;
1176 state->Init_Ctrl[31].size = 3 ;
1177 state->Init_Ctrl[31].addr[0] = 166;
1178 state->Init_Ctrl[31].bit[0] = 3;
1179 state->Init_Ctrl[31].val[0] = 1;
1180 state->Init_Ctrl[31].addr[1] = 166;
1181 state->Init_Ctrl[31].bit[1] = 4;
1182 state->Init_Ctrl[31].val[1] = 0;
1183 state->Init_Ctrl[31].addr[2] = 166;
1184 state->Init_Ctrl[31].bit[2] = 5;
1185 state->Init_Ctrl[31].val[2] = 1;
1186
1187 state->Init_Ctrl[32].Ctrl_Num = RFA_RSSI_REFL ;
1188 state->Init_Ctrl[32].size = 3 ;
1189 state->Init_Ctrl[32].addr[0] = 167;
1190 state->Init_Ctrl[32].bit[0] = 0;
1191 state->Init_Ctrl[32].val[0] = 1;
1192 state->Init_Ctrl[32].addr[1] = 167;
1193 state->Init_Ctrl[32].bit[1] = 1;
1194 state->Init_Ctrl[32].val[1] = 1;
1195 state->Init_Ctrl[32].addr[2] = 167;
1196 state->Init_Ctrl[32].bit[2] = 2;
1197 state->Init_Ctrl[32].val[2] = 0;
1198
1199 state->Init_Ctrl[33].Ctrl_Num = RFA_FLR ;
1200 state->Init_Ctrl[33].size = 4 ;
1201 state->Init_Ctrl[33].addr[0] = 168;
1202 state->Init_Ctrl[33].bit[0] = 0;
1203 state->Init_Ctrl[33].val[0] = 0;
1204 state->Init_Ctrl[33].addr[1] = 168;
1205 state->Init_Ctrl[33].bit[1] = 1;
1206 state->Init_Ctrl[33].val[1] = 1;
1207 state->Init_Ctrl[33].addr[2] = 168;
1208 state->Init_Ctrl[33].bit[2] = 2;
1209 state->Init_Ctrl[33].val[2] = 0;
1210 state->Init_Ctrl[33].addr[3] = 168;
1211 state->Init_Ctrl[33].bit[3] = 3;
1212 state->Init_Ctrl[33].val[3] = 0;
1213
1214 state->Init_Ctrl[34].Ctrl_Num = RFA_CEIL ;
1215 state->Init_Ctrl[34].size = 4 ;
1216 state->Init_Ctrl[34].addr[0] = 168;
1217 state->Init_Ctrl[34].bit[0] = 4;
1218 state->Init_Ctrl[34].val[0] = 1;
1219 state->Init_Ctrl[34].addr[1] = 168;
1220 state->Init_Ctrl[34].bit[1] = 5;
1221 state->Init_Ctrl[34].val[1] = 1;
1222 state->Init_Ctrl[34].addr[2] = 168;
1223 state->Init_Ctrl[34].bit[2] = 6;
1224 state->Init_Ctrl[34].val[2] = 1;
1225 state->Init_Ctrl[34].addr[3] = 168;
1226 state->Init_Ctrl[34].bit[3] = 7;
1227 state->Init_Ctrl[34].val[3] = 1;
1228
1229 state->Init_Ctrl[35].Ctrl_Num = SEQ_EXTIQFSMPULSE ;
1230 state->Init_Ctrl[35].size = 1 ;
1231 state->Init_Ctrl[35].addr[0] = 135;
1232 state->Init_Ctrl[35].bit[0] = 0;
1233 state->Init_Ctrl[35].val[0] = 0;
1234
1235 state->Init_Ctrl[36].Ctrl_Num = OVERRIDE_1 ;
1236 state->Init_Ctrl[36].size = 1 ;
1237 state->Init_Ctrl[36].addr[0] = 56;
1238 state->Init_Ctrl[36].bit[0] = 3;
1239 state->Init_Ctrl[36].val[0] = 0;
1240
1241 state->Init_Ctrl[37].Ctrl_Num = BB_INITSTATE_DLPF_TUNE ;
1242 state->Init_Ctrl[37].size = 7 ;
1243 state->Init_Ctrl[37].addr[0] = 59;
1244 state->Init_Ctrl[37].bit[0] = 1;
1245 state->Init_Ctrl[37].val[0] = 0;
1246 state->Init_Ctrl[37].addr[1] = 59;
1247 state->Init_Ctrl[37].bit[1] = 2;
1248 state->Init_Ctrl[37].val[1] = 0;
1249 state->Init_Ctrl[37].addr[2] = 59;
1250 state->Init_Ctrl[37].bit[2] = 3;
1251 state->Init_Ctrl[37].val[2] = 0;
1252 state->Init_Ctrl[37].addr[3] = 59;
1253 state->Init_Ctrl[37].bit[3] = 4;
1254 state->Init_Ctrl[37].val[3] = 0;
1255 state->Init_Ctrl[37].addr[4] = 59;
1256 state->Init_Ctrl[37].bit[4] = 5;
1257 state->Init_Ctrl[37].val[4] = 0;
1258 state->Init_Ctrl[37].addr[5] = 59;
1259 state->Init_Ctrl[37].bit[5] = 6;
1260 state->Init_Ctrl[37].val[5] = 0;
1261 state->Init_Ctrl[37].addr[6] = 59;
1262 state->Init_Ctrl[37].bit[6] = 7;
1263 state->Init_Ctrl[37].val[6] = 0;
1264
1265 state->Init_Ctrl[38].Ctrl_Num = TG_R_DIV ;
1266 state->Init_Ctrl[38].size = 6 ;
1267 state->Init_Ctrl[38].addr[0] = 32;
1268 state->Init_Ctrl[38].bit[0] = 2;
1269 state->Init_Ctrl[38].val[0] = 0;
1270 state->Init_Ctrl[38].addr[1] = 32;
1271 state->Init_Ctrl[38].bit[1] = 3;
1272 state->Init_Ctrl[38].val[1] = 0;
1273 state->Init_Ctrl[38].addr[2] = 32;
1274 state->Init_Ctrl[38].bit[2] = 4;
1275 state->Init_Ctrl[38].val[2] = 0;
1276 state->Init_Ctrl[38].addr[3] = 32;
1277 state->Init_Ctrl[38].bit[3] = 5;
1278 state->Init_Ctrl[38].val[3] = 0;
1279 state->Init_Ctrl[38].addr[4] = 32;
1280 state->Init_Ctrl[38].bit[4] = 6;
1281 state->Init_Ctrl[38].val[4] = 1;
1282 state->Init_Ctrl[38].addr[5] = 32;
1283 state->Init_Ctrl[38].bit[5] = 7;
1284 state->Init_Ctrl[38].val[5] = 0;
1285
1286 state->Init_Ctrl[39].Ctrl_Num = EN_CHP_LIN_B ;
1287 state->Init_Ctrl[39].size = 1 ;
1288 state->Init_Ctrl[39].addr[0] = 25;
1289 state->Init_Ctrl[39].bit[0] = 3;
1290 state->Init_Ctrl[39].val[0] = 1;
1291
1292
1293 state->CH_Ctrl_Num = CHCTRL_NUM ;
1294
1295 state->CH_Ctrl[0].Ctrl_Num = DN_POLY ;
1296 state->CH_Ctrl[0].size = 2 ;
1297 state->CH_Ctrl[0].addr[0] = 68;
1298 state->CH_Ctrl[0].bit[0] = 6;
1299 state->CH_Ctrl[0].val[0] = 1;
1300 state->CH_Ctrl[0].addr[1] = 68;
1301 state->CH_Ctrl[0].bit[1] = 7;
1302 state->CH_Ctrl[0].val[1] = 1;
1303
1304 state->CH_Ctrl[1].Ctrl_Num = DN_RFGAIN ;
1305 state->CH_Ctrl[1].size = 2 ;
1306 state->CH_Ctrl[1].addr[0] = 70;
1307 state->CH_Ctrl[1].bit[0] = 6;
1308 state->CH_Ctrl[1].val[0] = 1;
1309 state->CH_Ctrl[1].addr[1] = 70;
1310 state->CH_Ctrl[1].bit[1] = 7;
1311 state->CH_Ctrl[1].val[1] = 0;
1312
1313 state->CH_Ctrl[2].Ctrl_Num = DN_CAP_RFLPF ;
1314 state->CH_Ctrl[2].size = 9 ;
1315 state->CH_Ctrl[2].addr[0] = 69;
1316 state->CH_Ctrl[2].bit[0] = 5;
1317 state->CH_Ctrl[2].val[0] = 0;
1318 state->CH_Ctrl[2].addr[1] = 69;
1319 state->CH_Ctrl[2].bit[1] = 6;
1320 state->CH_Ctrl[2].val[1] = 0;
1321 state->CH_Ctrl[2].addr[2] = 69;
1322 state->CH_Ctrl[2].bit[2] = 7;
1323 state->CH_Ctrl[2].val[2] = 0;
1324 state->CH_Ctrl[2].addr[3] = 68;
1325 state->CH_Ctrl[2].bit[3] = 0;
1326 state->CH_Ctrl[2].val[3] = 0;
1327 state->CH_Ctrl[2].addr[4] = 68;
1328 state->CH_Ctrl[2].bit[4] = 1;
1329 state->CH_Ctrl[2].val[4] = 0;
1330 state->CH_Ctrl[2].addr[5] = 68;
1331 state->CH_Ctrl[2].bit[5] = 2;
1332 state->CH_Ctrl[2].val[5] = 0;
1333 state->CH_Ctrl[2].addr[6] = 68;
1334 state->CH_Ctrl[2].bit[6] = 3;
1335 state->CH_Ctrl[2].val[6] = 0;
1336 state->CH_Ctrl[2].addr[7] = 68;
1337 state->CH_Ctrl[2].bit[7] = 4;
1338 state->CH_Ctrl[2].val[7] = 0;
1339 state->CH_Ctrl[2].addr[8] = 68;
1340 state->CH_Ctrl[2].bit[8] = 5;
1341 state->CH_Ctrl[2].val[8] = 0;
1342
1343 state->CH_Ctrl[3].Ctrl_Num = DN_EN_VHFUHFBAR ;
1344 state->CH_Ctrl[3].size = 1 ;
1345 state->CH_Ctrl[3].addr[0] = 70;
1346 state->CH_Ctrl[3].bit[0] = 5;
1347 state->CH_Ctrl[3].val[0] = 0;
1348
1349 state->CH_Ctrl[4].Ctrl_Num = DN_GAIN_ADJUST ;
1350 state->CH_Ctrl[4].size = 3 ;
1351 state->CH_Ctrl[4].addr[0] = 73;
1352 state->CH_Ctrl[4].bit[0] = 4;
1353 state->CH_Ctrl[4].val[0] = 0;
1354 state->CH_Ctrl[4].addr[1] = 73;
1355 state->CH_Ctrl[4].bit[1] = 5;
1356 state->CH_Ctrl[4].val[1] = 1;
1357 state->CH_Ctrl[4].addr[2] = 73;
1358 state->CH_Ctrl[4].bit[2] = 6;
1359 state->CH_Ctrl[4].val[2] = 0;
1360
1361 state->CH_Ctrl[5].Ctrl_Num = DN_IQTNBUF_AMP ;
1362 state->CH_Ctrl[5].size = 4 ;
1363 state->CH_Ctrl[5].addr[0] = 70;
1364 state->CH_Ctrl[5].bit[0] = 0;
1365 state->CH_Ctrl[5].val[0] = 0;
1366 state->CH_Ctrl[5].addr[1] = 70;
1367 state->CH_Ctrl[5].bit[1] = 1;
1368 state->CH_Ctrl[5].val[1] = 0;
1369 state->CH_Ctrl[5].addr[2] = 70;
1370 state->CH_Ctrl[5].bit[2] = 2;
1371 state->CH_Ctrl[5].val[2] = 0;
1372 state->CH_Ctrl[5].addr[3] = 70;
1373 state->CH_Ctrl[5].bit[3] = 3;
1374 state->CH_Ctrl[5].val[3] = 0;
1375
1376 state->CH_Ctrl[6].Ctrl_Num = DN_IQTNGNBFBIAS_BST ;
1377 state->CH_Ctrl[6].size = 1 ;
1378 state->CH_Ctrl[6].addr[0] = 70;
1379 state->CH_Ctrl[6].bit[0] = 4;
1380 state->CH_Ctrl[6].val[0] = 1;
1381
1382 state->CH_Ctrl[7].Ctrl_Num = RFSYN_EN_OUTMUX ;
1383 state->CH_Ctrl[7].size = 1 ;
1384 state->CH_Ctrl[7].addr[0] = 111;
1385 state->CH_Ctrl[7].bit[0] = 4;
1386 state->CH_Ctrl[7].val[0] = 0;
1387
1388 state->CH_Ctrl[8].Ctrl_Num = RFSYN_SEL_VCO_OUT ;
1389 state->CH_Ctrl[8].size = 1 ;
1390 state->CH_Ctrl[8].addr[0] = 111;
1391 state->CH_Ctrl[8].bit[0] = 7;
1392 state->CH_Ctrl[8].val[0] = 1;
1393
1394 state->CH_Ctrl[9].Ctrl_Num = RFSYN_SEL_VCO_HI ;
1395 state->CH_Ctrl[9].size = 1 ;
1396 state->CH_Ctrl[9].addr[0] = 111;
1397 state->CH_Ctrl[9].bit[0] = 6;
1398 state->CH_Ctrl[9].val[0] = 1;
1399
1400 state->CH_Ctrl[10].Ctrl_Num = RFSYN_SEL_DIVM ;
1401 state->CH_Ctrl[10].size = 1 ;
1402 state->CH_Ctrl[10].addr[0] = 111;
1403 state->CH_Ctrl[10].bit[0] = 5;
1404 state->CH_Ctrl[10].val[0] = 0;
1405
1406 state->CH_Ctrl[11].Ctrl_Num = RFSYN_RF_DIV_BIAS ;
1407 state->CH_Ctrl[11].size = 2 ;
1408 state->CH_Ctrl[11].addr[0] = 110;
1409 state->CH_Ctrl[11].bit[0] = 0;
1410 state->CH_Ctrl[11].val[0] = 1;
1411 state->CH_Ctrl[11].addr[1] = 110;
1412 state->CH_Ctrl[11].bit[1] = 1;
1413 state->CH_Ctrl[11].val[1] = 0;
1414
1415 state->CH_Ctrl[12].Ctrl_Num = DN_SEL_FREQ ;
1416 state->CH_Ctrl[12].size = 3 ;
1417 state->CH_Ctrl[12].addr[0] = 69;
1418 state->CH_Ctrl[12].bit[0] = 2;
1419 state->CH_Ctrl[12].val[0] = 0;
1420 state->CH_Ctrl[12].addr[1] = 69;
1421 state->CH_Ctrl[12].bit[1] = 3;
1422 state->CH_Ctrl[12].val[1] = 0;
1423 state->CH_Ctrl[12].addr[2] = 69;
1424 state->CH_Ctrl[12].bit[2] = 4;
1425 state->CH_Ctrl[12].val[2] = 0;
1426
1427 state->CH_Ctrl[13].Ctrl_Num = RFSYN_VCO_BIAS ;
1428 state->CH_Ctrl[13].size = 6 ;
1429 state->CH_Ctrl[13].addr[0] = 110;
1430 state->CH_Ctrl[13].bit[0] = 2;
1431 state->CH_Ctrl[13].val[0] = 0;
1432 state->CH_Ctrl[13].addr[1] = 110;
1433 state->CH_Ctrl[13].bit[1] = 3;
1434 state->CH_Ctrl[13].val[1] = 0;
1435 state->CH_Ctrl[13].addr[2] = 110;
1436 state->CH_Ctrl[13].bit[2] = 4;
1437 state->CH_Ctrl[13].val[2] = 0;
1438 state->CH_Ctrl[13].addr[3] = 110;
1439 state->CH_Ctrl[13].bit[3] = 5;
1440 state->CH_Ctrl[13].val[3] = 0;
1441 state->CH_Ctrl[13].addr[4] = 110;
1442 state->CH_Ctrl[13].bit[4] = 6;
1443 state->CH_Ctrl[13].val[4] = 0;
1444 state->CH_Ctrl[13].addr[5] = 110;
1445 state->CH_Ctrl[13].bit[5] = 7;
1446 state->CH_Ctrl[13].val[5] = 1;
1447
1448 state->CH_Ctrl[14].Ctrl_Num = CHCAL_INT_MOD_RF ;
1449 state->CH_Ctrl[14].size = 7 ;
1450 state->CH_Ctrl[14].addr[0] = 14;
1451 state->CH_Ctrl[14].bit[0] = 0;
1452 state->CH_Ctrl[14].val[0] = 0;
1453 state->CH_Ctrl[14].addr[1] = 14;
1454 state->CH_Ctrl[14].bit[1] = 1;
1455 state->CH_Ctrl[14].val[1] = 0;
1456 state->CH_Ctrl[14].addr[2] = 14;
1457 state->CH_Ctrl[14].bit[2] = 2;
1458 state->CH_Ctrl[14].val[2] = 0;
1459 state->CH_Ctrl[14].addr[3] = 14;
1460 state->CH_Ctrl[14].bit[3] = 3;
1461 state->CH_Ctrl[14].val[3] = 0;
1462 state->CH_Ctrl[14].addr[4] = 14;
1463 state->CH_Ctrl[14].bit[4] = 4;
1464 state->CH_Ctrl[14].val[4] = 0;
1465 state->CH_Ctrl[14].addr[5] = 14;
1466 state->CH_Ctrl[14].bit[5] = 5;
1467 state->CH_Ctrl[14].val[5] = 0;
1468 state->CH_Ctrl[14].addr[6] = 14;
1469 state->CH_Ctrl[14].bit[6] = 6;
1470 state->CH_Ctrl[14].val[6] = 0;
1471
1472 state->CH_Ctrl[15].Ctrl_Num = CHCAL_FRAC_MOD_RF ;
1473 state->CH_Ctrl[15].size = 18 ;
1474 state->CH_Ctrl[15].addr[0] = 17;
1475 state->CH_Ctrl[15].bit[0] = 6;
1476 state->CH_Ctrl[15].val[0] = 0;
1477 state->CH_Ctrl[15].addr[1] = 17;
1478 state->CH_Ctrl[15].bit[1] = 7;
1479 state->CH_Ctrl[15].val[1] = 0;
1480 state->CH_Ctrl[15].addr[2] = 16;
1481 state->CH_Ctrl[15].bit[2] = 0;
1482 state->CH_Ctrl[15].val[2] = 0;
1483 state->CH_Ctrl[15].addr[3] = 16;
1484 state->CH_Ctrl[15].bit[3] = 1;
1485 state->CH_Ctrl[15].val[3] = 0;
1486 state->CH_Ctrl[15].addr[4] = 16;
1487 state->CH_Ctrl[15].bit[4] = 2;
1488 state->CH_Ctrl[15].val[4] = 0;
1489 state->CH_Ctrl[15].addr[5] = 16;
1490 state->CH_Ctrl[15].bit[5] = 3;
1491 state->CH_Ctrl[15].val[5] = 0;
1492 state->CH_Ctrl[15].addr[6] = 16;
1493 state->CH_Ctrl[15].bit[6] = 4;
1494 state->CH_Ctrl[15].val[6] = 0;
1495 state->CH_Ctrl[15].addr[7] = 16;
1496 state->CH_Ctrl[15].bit[7] = 5;
1497 state->CH_Ctrl[15].val[7] = 0;
1498 state->CH_Ctrl[15].addr[8] = 16;
1499 state->CH_Ctrl[15].bit[8] = 6;
1500 state->CH_Ctrl[15].val[8] = 0;
1501 state->CH_Ctrl[15].addr[9] = 16;
1502 state->CH_Ctrl[15].bit[9] = 7;
1503 state->CH_Ctrl[15].val[9] = 0;
1504 state->CH_Ctrl[15].addr[10] = 15;
1505 state->CH_Ctrl[15].bit[10] = 0;
1506 state->CH_Ctrl[15].val[10] = 0;
1507 state->CH_Ctrl[15].addr[11] = 15;
1508 state->CH_Ctrl[15].bit[11] = 1;
1509 state->CH_Ctrl[15].val[11] = 0;
1510 state->CH_Ctrl[15].addr[12] = 15;
1511 state->CH_Ctrl[15].bit[12] = 2;
1512 state->CH_Ctrl[15].val[12] = 0;
1513 state->CH_Ctrl[15].addr[13] = 15;
1514 state->CH_Ctrl[15].bit[13] = 3;
1515 state->CH_Ctrl[15].val[13] = 0;
1516 state->CH_Ctrl[15].addr[14] = 15;
1517 state->CH_Ctrl[15].bit[14] = 4;
1518 state->CH_Ctrl[15].val[14] = 0;
1519 state->CH_Ctrl[15].addr[15] = 15;
1520 state->CH_Ctrl[15].bit[15] = 5;
1521 state->CH_Ctrl[15].val[15] = 0;
1522 state->CH_Ctrl[15].addr[16] = 15;
1523 state->CH_Ctrl[15].bit[16] = 6;
1524 state->CH_Ctrl[15].val[16] = 1;
1525 state->CH_Ctrl[15].addr[17] = 15;
1526 state->CH_Ctrl[15].bit[17] = 7;
1527 state->CH_Ctrl[15].val[17] = 1;
1528
1529 state->CH_Ctrl[16].Ctrl_Num = RFSYN_LPF_R ;
1530 state->CH_Ctrl[16].size = 5 ;
1531 state->CH_Ctrl[16].addr[0] = 112;
1532 state->CH_Ctrl[16].bit[0] = 0;
1533 state->CH_Ctrl[16].val[0] = 0;
1534 state->CH_Ctrl[16].addr[1] = 112;
1535 state->CH_Ctrl[16].bit[1] = 1;
1536 state->CH_Ctrl[16].val[1] = 0;
1537 state->CH_Ctrl[16].addr[2] = 112;
1538 state->CH_Ctrl[16].bit[2] = 2;
1539 state->CH_Ctrl[16].val[2] = 0;
1540 state->CH_Ctrl[16].addr[3] = 112;
1541 state->CH_Ctrl[16].bit[3] = 3;
1542 state->CH_Ctrl[16].val[3] = 0;
1543 state->CH_Ctrl[16].addr[4] = 112;
1544 state->CH_Ctrl[16].bit[4] = 4;
1545 state->CH_Ctrl[16].val[4] = 1;
1546
1547 state->CH_Ctrl[17].Ctrl_Num = CHCAL_EN_INT_RF ;
1548 state->CH_Ctrl[17].size = 1 ;
1549 state->CH_Ctrl[17].addr[0] = 14;
1550 state->CH_Ctrl[17].bit[0] = 7;
1551 state->CH_Ctrl[17].val[0] = 0;
1552
1553 state->CH_Ctrl[18].Ctrl_Num = TG_LO_DIVVAL ;
1554 state->CH_Ctrl[18].size = 4 ;
1555 state->CH_Ctrl[18].addr[0] = 107;
1556 state->CH_Ctrl[18].bit[0] = 3;
1557 state->CH_Ctrl[18].val[0] = 0;
1558 state->CH_Ctrl[18].addr[1] = 107;
1559 state->CH_Ctrl[18].bit[1] = 4;
1560 state->CH_Ctrl[18].val[1] = 0;
1561 state->CH_Ctrl[18].addr[2] = 107;
1562 state->CH_Ctrl[18].bit[2] = 5;
1563 state->CH_Ctrl[18].val[2] = 0;
1564 state->CH_Ctrl[18].addr[3] = 107;
1565 state->CH_Ctrl[18].bit[3] = 6;
1566 state->CH_Ctrl[18].val[3] = 0;
1567
1568 state->CH_Ctrl[19].Ctrl_Num = TG_LO_SELVAL ;
1569 state->CH_Ctrl[19].size = 3 ;
1570 state->CH_Ctrl[19].addr[0] = 107;
1571 state->CH_Ctrl[19].bit[0] = 7;
1572 state->CH_Ctrl[19].val[0] = 1;
1573 state->CH_Ctrl[19].addr[1] = 106;
1574 state->CH_Ctrl[19].bit[1] = 0;
1575 state->CH_Ctrl[19].val[1] = 1;
1576 state->CH_Ctrl[19].addr[2] = 106;
1577 state->CH_Ctrl[19].bit[2] = 1;
1578 state->CH_Ctrl[19].val[2] = 1;
1579
1580 state->CH_Ctrl[20].Ctrl_Num = TG_DIV_VAL ;
1581 state->CH_Ctrl[20].size = 11 ;
1582 state->CH_Ctrl[20].addr[0] = 109;
1583 state->CH_Ctrl[20].bit[0] = 2;
1584 state->CH_Ctrl[20].val[0] = 0;
1585 state->CH_Ctrl[20].addr[1] = 109;
1586 state->CH_Ctrl[20].bit[1] = 3;
1587 state->CH_Ctrl[20].val[1] = 0;
1588 state->CH_Ctrl[20].addr[2] = 109;
1589 state->CH_Ctrl[20].bit[2] = 4;
1590 state->CH_Ctrl[20].val[2] = 0;
1591 state->CH_Ctrl[20].addr[3] = 109;
1592 state->CH_Ctrl[20].bit[3] = 5;
1593 state->CH_Ctrl[20].val[3] = 0;
1594 state->CH_Ctrl[20].addr[4] = 109;
1595 state->CH_Ctrl[20].bit[4] = 6;
1596 state->CH_Ctrl[20].val[4] = 0;
1597 state->CH_Ctrl[20].addr[5] = 109;
1598 state->CH_Ctrl[20].bit[5] = 7;
1599 state->CH_Ctrl[20].val[5] = 0;
1600 state->CH_Ctrl[20].addr[6] = 108;
1601 state->CH_Ctrl[20].bit[6] = 0;
1602 state->CH_Ctrl[20].val[6] = 0;
1603 state->CH_Ctrl[20].addr[7] = 108;
1604 state->CH_Ctrl[20].bit[7] = 1;
1605 state->CH_Ctrl[20].val[7] = 0;
1606 state->CH_Ctrl[20].addr[8] = 108;
1607 state->CH_Ctrl[20].bit[8] = 2;
1608 state->CH_Ctrl[20].val[8] = 1;
1609 state->CH_Ctrl[20].addr[9] = 108;
1610 state->CH_Ctrl[20].bit[9] = 3;
1611 state->CH_Ctrl[20].val[9] = 1;
1612 state->CH_Ctrl[20].addr[10] = 108;
1613 state->CH_Ctrl[20].bit[10] = 4;
1614 state->CH_Ctrl[20].val[10] = 1;
1615
1616 state->CH_Ctrl[21].Ctrl_Num = TG_VCO_BIAS ;
1617 state->CH_Ctrl[21].size = 6 ;
1618 state->CH_Ctrl[21].addr[0] = 106;
1619 state->CH_Ctrl[21].bit[0] = 2;
1620 state->CH_Ctrl[21].val[0] = 0;
1621 state->CH_Ctrl[21].addr[1] = 106;
1622 state->CH_Ctrl[21].bit[1] = 3;
1623 state->CH_Ctrl[21].val[1] = 0;
1624 state->CH_Ctrl[21].addr[2] = 106;
1625 state->CH_Ctrl[21].bit[2] = 4;
1626 state->CH_Ctrl[21].val[2] = 0;
1627 state->CH_Ctrl[21].addr[3] = 106;
1628 state->CH_Ctrl[21].bit[3] = 5;
1629 state->CH_Ctrl[21].val[3] = 0;
1630 state->CH_Ctrl[21].addr[4] = 106;
1631 state->CH_Ctrl[21].bit[4] = 6;
1632 state->CH_Ctrl[21].val[4] = 0;
1633 state->CH_Ctrl[21].addr[5] = 106;
1634 state->CH_Ctrl[21].bit[5] = 7;
1635 state->CH_Ctrl[21].val[5] = 1;
1636
1637 state->CH_Ctrl[22].Ctrl_Num = SEQ_EXTPOWERUP ;
1638 state->CH_Ctrl[22].size = 1 ;
1639 state->CH_Ctrl[22].addr[0] = 138;
1640 state->CH_Ctrl[22].bit[0] = 4;
1641 state->CH_Ctrl[22].val[0] = 1;
1642
1643 state->CH_Ctrl[23].Ctrl_Num = OVERRIDE_2 ;
1644 state->CH_Ctrl[23].size = 1 ;
1645 state->CH_Ctrl[23].addr[0] = 17;
1646 state->CH_Ctrl[23].bit[0] = 5;
1647 state->CH_Ctrl[23].val[0] = 0;
1648
1649 state->CH_Ctrl[24].Ctrl_Num = OVERRIDE_3 ;
1650 state->CH_Ctrl[24].size = 1 ;
1651 state->CH_Ctrl[24].addr[0] = 111;
1652 state->CH_Ctrl[24].bit[0] = 3;
1653 state->CH_Ctrl[24].val[0] = 0;
1654
1655 state->CH_Ctrl[25].Ctrl_Num = OVERRIDE_4 ;
1656 state->CH_Ctrl[25].size = 1 ;
1657 state->CH_Ctrl[25].addr[0] = 112;
1658 state->CH_Ctrl[25].bit[0] = 7;
1659 state->CH_Ctrl[25].val[0] = 0;
1660
1661 state->CH_Ctrl[26].Ctrl_Num = SEQ_FSM_PULSE ;
1662 state->CH_Ctrl[26].size = 1 ;
1663 state->CH_Ctrl[26].addr[0] = 136;
1664 state->CH_Ctrl[26].bit[0] = 7;
1665 state->CH_Ctrl[26].val[0] = 0;
1666
1667 state->CH_Ctrl[27].Ctrl_Num = GPIO_4B ;
1668 state->CH_Ctrl[27].size = 1 ;
1669 state->CH_Ctrl[27].addr[0] = 149;
1670 state->CH_Ctrl[27].bit[0] = 7;
1671 state->CH_Ctrl[27].val[0] = 0;
1672
1673 state->CH_Ctrl[28].Ctrl_Num = GPIO_3B ;
1674 state->CH_Ctrl[28].size = 1 ;
1675 state->CH_Ctrl[28].addr[0] = 149;
1676 state->CH_Ctrl[28].bit[0] = 6;
1677 state->CH_Ctrl[28].val[0] = 0;
1678
1679 state->CH_Ctrl[29].Ctrl_Num = GPIO_4 ;
1680 state->CH_Ctrl[29].size = 1 ;
1681 state->CH_Ctrl[29].addr[0] = 149;
1682 state->CH_Ctrl[29].bit[0] = 5;
1683 state->CH_Ctrl[29].val[0] = 1;
1684
1685 state->CH_Ctrl[30].Ctrl_Num = GPIO_3 ;
1686 state->CH_Ctrl[30].size = 1 ;
1687 state->CH_Ctrl[30].addr[0] = 149;
1688 state->CH_Ctrl[30].bit[0] = 4;
1689 state->CH_Ctrl[30].val[0] = 1;
1690
1691 state->CH_Ctrl[31].Ctrl_Num = GPIO_1B ;
1692 state->CH_Ctrl[31].size = 1 ;
1693 state->CH_Ctrl[31].addr[0] = 149;
1694 state->CH_Ctrl[31].bit[0] = 3;
1695 state->CH_Ctrl[31].val[0] = 0;
1696
1697 state->CH_Ctrl[32].Ctrl_Num = DAC_A_ENABLE ;
1698 state->CH_Ctrl[32].size = 1 ;
1699 state->CH_Ctrl[32].addr[0] = 93;
1700 state->CH_Ctrl[32].bit[0] = 1;
1701 state->CH_Ctrl[32].val[0] = 0;
1702
1703 state->CH_Ctrl[33].Ctrl_Num = DAC_B_ENABLE ;
1704 state->CH_Ctrl[33].size = 1 ;
1705 state->CH_Ctrl[33].addr[0] = 93;
1706 state->CH_Ctrl[33].bit[0] = 0;
1707 state->CH_Ctrl[33].val[0] = 0;
1708
1709 state->CH_Ctrl[34].Ctrl_Num = DAC_DIN_A ;
1710 state->CH_Ctrl[34].size = 6 ;
1711 state->CH_Ctrl[34].addr[0] = 92;
1712 state->CH_Ctrl[34].bit[0] = 2;
1713 state->CH_Ctrl[34].val[0] = 0;
1714 state->CH_Ctrl[34].addr[1] = 92;
1715 state->CH_Ctrl[34].bit[1] = 3;
1716 state->CH_Ctrl[34].val[1] = 0;
1717 state->CH_Ctrl[34].addr[2] = 92;
1718 state->CH_Ctrl[34].bit[2] = 4;
1719 state->CH_Ctrl[34].val[2] = 0;
1720 state->CH_Ctrl[34].addr[3] = 92;
1721 state->CH_Ctrl[34].bit[3] = 5;
1722 state->CH_Ctrl[34].val[3] = 0;
1723 state->CH_Ctrl[34].addr[4] = 92;
1724 state->CH_Ctrl[34].bit[4] = 6;
1725 state->CH_Ctrl[34].val[4] = 0;
1726 state->CH_Ctrl[34].addr[5] = 92;
1727 state->CH_Ctrl[34].bit[5] = 7;
1728 state->CH_Ctrl[34].val[5] = 0;
1729
1730 state->CH_Ctrl[35].Ctrl_Num = DAC_DIN_B ;
1731 state->CH_Ctrl[35].size = 6 ;
1732 state->CH_Ctrl[35].addr[0] = 93;
1733 state->CH_Ctrl[35].bit[0] = 2;
1734 state->CH_Ctrl[35].val[0] = 0;
1735 state->CH_Ctrl[35].addr[1] = 93;
1736 state->CH_Ctrl[35].bit[1] = 3;
1737 state->CH_Ctrl[35].val[1] = 0;
1738 state->CH_Ctrl[35].addr[2] = 93;
1739 state->CH_Ctrl[35].bit[2] = 4;
1740 state->CH_Ctrl[35].val[2] = 0;
1741 state->CH_Ctrl[35].addr[3] = 93;
1742 state->CH_Ctrl[35].bit[3] = 5;
1743 state->CH_Ctrl[35].val[3] = 0;
1744 state->CH_Ctrl[35].addr[4] = 93;
1745 state->CH_Ctrl[35].bit[4] = 6;
1746 state->CH_Ctrl[35].val[4] = 0;
1747 state->CH_Ctrl[35].addr[5] = 93;
1748 state->CH_Ctrl[35].bit[5] = 7;
1749 state->CH_Ctrl[35].val[5] = 0;
52c99bda
ST		 1750
1751#ifdef _MXL_PRODUCTION
3935c254
ST		 1752 state->CH_Ctrl[36].Ctrl_Num = RFSYN_EN_DIV ;
1753 state->CH_Ctrl[36].size = 1 ;
1754 state->CH_Ctrl[36].addr[0] = 109;
1755 state->CH_Ctrl[36].bit[0] = 1;
1756 state->CH_Ctrl[36].val[0] = 1;
1757
1758 state->CH_Ctrl[37].Ctrl_Num = RFSYN_DIVM ;
1759 state->CH_Ctrl[37].size = 2 ;
1760 state->CH_Ctrl[37].addr[0] = 112;
1761 state->CH_Ctrl[37].bit[0] = 5;
1762 state->CH_Ctrl[37].val[0] = 0;
1763 state->CH_Ctrl[37].addr[1] = 112;
1764 state->CH_Ctrl[37].bit[1] = 6;
1765 state->CH_Ctrl[37].val[1] = 0;
1766
1767 state->CH_Ctrl[38].Ctrl_Num = DN_BYPASS_AGC_I2C ;
1768 state->CH_Ctrl[38].size = 1 ;
1769 state->CH_Ctrl[38].addr[0] = 65;
1770 state->CH_Ctrl[38].bit[0] = 1;
1771 state->CH_Ctrl[38].val[0] = 0;
52c99bda
ST		 1772#endif
1773
1774 return 0 ;
1775}
1776
52c99bda 1777// MaxLinear source code - MXL5005_c.cpp
52c99bda
ST		 1778// MXL5005.cpp : Defines the initialization routines for the DLL.
1779// 2.6.12
3935c254
ST		 1780// DONE
1781void InitTunerControls(struct dvb_frontend *fe)
52c99bda 1782{
3935c254
ST		 1783 MXL5005_RegisterInit(fe);
1784 MXL5005_ControlInit(fe);
52c99bda 1785#ifdef _MXL_INTERNAL
3935c254 1786 MXL5005_MXLControlInit(fe);
52c99bda
ST		 1787#endif
1788}
1789
52c99bda
ST		 1790///////////////////////////////////////////////////////////////////////////////
1791// //
1792// Function: MXL_ConfigTuner //
1793// //
1794// Description: Configure MXL5005Tuner structure for desired //
1795// Channel Bandwidth/Channel Frequency //
1796// //
1797// //
1798// Functions used: //
a8214d48 1799// MXL_SynthIFLO_Calc //
52c99bda
ST		 1800// //
1801// Inputs: //
1802// Tuner_struct: structure defined at higher level //
1803// Mode: Tuner Mode (Analog/Digital) //
1804// IF_Mode: IF Mode ( Zero/Low ) //
3935c254 1805// Bandwidth: Filter Channel Bandwidth (in Hz) //
52c99bda
ST		 1806// IF_out: Desired IF out Frequency (in Hz) //
1807// Fxtal: Crystal Frerquency (in Hz) //
3935c254
ST		 1808// TOP: 0: Dual AGC; Value: take over point //
1809// IF_OUT_LOAD: IF out load resistor (200/300 Ohms) //
1810// CLOCK_OUT: 0: Turn off clock out; 1: turn on clock out //
1811// DIV_OUT: 0: Div-1; 1: Div-4 //
1812// CAPSELECT: 0: Disable On-chip pulling cap; 1: Enable //
1813// EN_RSSI: 0: Disable RSSI; 1: Enable RSSI //
52c99bda
ST		 1814// //
1815// Outputs: //
1816// Tuner //
1817// //
1818// Return: //
1819// 0 : Successful //
1820// > 0 : Failed //
1821// //
1822///////////////////////////////////////////////////////////////////////////////
3935c254
ST		 1823// DONE
1824u16 MXL5005_TunerConfig(struct dvb_frontend *fe,
1825 u8 Mode, /* 0: Analog Mode ; 1: Digital Mode */
1826 u8 IF_mode, /* for Analog Mode, 0: zero IF; 1: low IF */
1827 u32 Bandwidth, /* filter channel bandwidth (6, 7, 8) */
1828 u32 IF_out, /* Desired IF Out Frequency */
1829 u32 Fxtal, /* XTAL Frequency */
1830 u8 AGC_Mode, /* AGC Mode - Dual AGC: 0, Single AGC: 1 */
1831 u16 TOP, /* 0: Dual AGC; Value: take over point */
1832 u16 IF_OUT_LOAD, /* IF Out Load Resistor (200 / 300 Ohms) */
1833 u8 CLOCK_OUT, /* 0: turn off clock out; 1: turn on clock out */
1834 u8 DIV_OUT, /* 0: Div-1; 1: Div-4 */
1835 u8 CAPSELECT, /* 0: disable On-Chip pulling cap; 1: enable */
1836 u8 EN_RSSI, /* 0: disable RSSI; 1: enable RSSI */
1837 u8 Mod_Type, /* Modulation Type; */
1838 /* 0 - Default; 1 - DVB-T; 2 - ATSC; 3 - QAM; 4 - Analog Cable */
1839 u8 TF_Type /* Tracking Filter */
1840 /* 0 - Default; 1 - Off; 2 - Type C; 3 - Type C-H */
52c99bda
ST		 1841 )
1842{
85d220d0 1843 struct mxl5005s_state *state = fe->tuner_priv;
3935c254 1844 u16 status = 0;
52c99bda 1845
3935c254
ST		 1846 state->Mode = Mode;
1847 state->IF_Mode = IF_mode;
1848 state->Chan_Bandwidth = Bandwidth;
1849 state->IF_OUT = IF_out;
1850 state->Fxtal = Fxtal;
1851 state->AGC_Mode = AGC_Mode;
1852 state->TOP = TOP;
1853 state->IF_OUT_LOAD = IF_OUT_LOAD;
1854 state->CLOCK_OUT = CLOCK_OUT;
1855 state->DIV_OUT = DIV_OUT;
1856 state->CAPSELECT = CAPSELECT;
1857 state->EN_RSSI = EN_RSSI;
1858 state->Mod_Type = Mod_Type;
1859 state->TF_Type = TF_Type;
52c99bda 1860
a8214d48 1861 /* Initialize all the controls and registers */
3935c254 1862 InitTunerControls(fe);
a8214d48
ST		 1863
1864 /* Synthesizer LO frequency calculation */
3935c254 1865 MXL_SynthIFLO_Calc(fe);
52c99bda 1866
3935c254 1867 return status;
52c99bda
ST		 1868}
1869
1870///////////////////////////////////////////////////////////////////////////////
1871// //
1872// Function: MXL_SynthIFLO_Calc //
1873// //
1874// Description: Calculate Internal IF-LO Frequency //
1875// //
1876// Globals: //
1877// NONE //
1878// //
1879// Functions used: //
1880// NONE //
1881// //
1882// Inputs: //
1883// Tuner_struct: structure defined at higher level //
1884// //
1885// Outputs: //
1886// Tuner //
1887// //
1888// Return: //
1889// 0 : Successful //
1890// > 0 : Failed //
1891// //
1892///////////////////////////////////////////////////////////////////////////////
3935c254
ST		 1893// DONE
1894void MXL_SynthIFLO_Calc(struct dvb_frontend *fe)
52c99bda 1895{
85d220d0
ST		 1896 struct mxl5005s_state *state = fe->tuner_priv;
1897 if (state->Mode == 1) /* Digital Mode */
3935c254
ST		 1898 state->IF_LO = state->IF_OUT;
1899 else /* Analog Mode */
52c99bda 1900 {
3935c254
ST		 1901 if(state->IF_Mode == 0) /* Analog Zero IF mode */
1902 state->IF_LO = state->IF_OUT + 400000;
1903 else /* Analog Low IF mode */
1904 state->IF_LO = state->IF_OUT + state->Chan_Bandwidth/2;
52c99bda
ST		 1905 }
1906}
1907
1908///////////////////////////////////////////////////////////////////////////////
1909// //
1910// Function: MXL_SynthRFTGLO_Calc //
1911// //
1912// Description: Calculate Internal RF-LO frequency and //
1913// internal Tone-Gen(TG)-LO frequency //
1914// //
1915// Globals: //
1916// NONE //
1917// //
1918// Functions used: //
1919// NONE //
1920// //
1921// Inputs: //
1922// Tuner_struct: structure defined at higher level //
1923// //
1924// Outputs: //
1925// Tuner //
1926// //
1927// Return: //
1928// 0 : Successful //
1929// > 0 : Failed //
1930// //
1931///////////////////////////////////////////////////////////////////////////////
3935c254
ST		 1932// DONE
1933void MXL_SynthRFTGLO_Calc(struct dvb_frontend *fe)
52c99bda 1934{
85d220d0 1935 struct mxl5005s_state *state = fe->tuner_priv;
3935c254
ST		 1936
1937 if (state->Mode == 1) /* Digital Mode */ {
52c99bda 1938 //remove 20.48MHz setting for 2.6.10
3935c254
ST		 1939 state->RF_LO = state->RF_IN;
1940 state->TG_LO = state->RF_IN - 750000; //change for 2.6.6
1941 } else /* Analog Mode */ {
1942 if(state->IF_Mode == 0) /* Analog Zero IF mode */ {
1943 state->RF_LO = state->RF_IN - 400000;
1944 state->TG_LO = state->RF_IN - 1750000;
1945 } else /* Analog Low IF mode */ {
1946 state->RF_LO = state->RF_IN - state->Chan_Bandwidth/2;
1947 state->TG_LO = state->RF_IN - state->Chan_Bandwidth + 500000;
52c99bda
ST		 1948 }
1949 }
1950}
1951
1952///////////////////////////////////////////////////////////////////////////////
1953// //
1954// Function: MXL_OverwriteICDefault //
1955// //
1956// Description: Overwrite the Default Register Setting //
1957// //
1958// //
1959// Functions used: //
1960// //
1961// Inputs: //
1962// Tuner_struct: structure defined at higher level //
1963// Outputs: //
1964// Tuner //
1965// //
1966// Return: //
1967// 0 : Successful //
1968// > 0 : Failed //
1969// //
1970///////////////////////////////////////////////////////////////////////////////
3935c254
ST		 1971// DONE
1972u16 MXL_OverwriteICDefault(struct dvb_frontend *fe)
52c99bda 1973{
3935c254 1974 u16 status = 0;
52c99bda 1975
3935c254
ST		 1976 status += MXL_ControlWrite(fe, OVERRIDE_1, 1);
1977 status += MXL_ControlWrite(fe, OVERRIDE_2, 1);
1978 status += MXL_ControlWrite(fe, OVERRIDE_3, 1);
1979 status += MXL_ControlWrite(fe, OVERRIDE_4, 1);
52c99bda 1980
3935c254 1981 return status;
52c99bda
ST		 1982}
1983
1984///////////////////////////////////////////////////////////////////////////////
1985// //
1986// Function: MXL_BlockInit //
1987// //
1988// Description: Tuner Initialization as a function of 'User Settings' //
1989// * User settings in Tuner strcuture must be assigned //
1990// first //
1991// //
1992// Globals: //
1993// NONE //
1994// //
1995// Functions used: //
1996// Tuner_struct: structure defined at higher level //
1997// //
1998// Inputs: //
1999// Tuner : Tuner structure defined at higher level //
2000// //
2001// Outputs: //
2002// Tuner //
2003// //
2004// Return: //
2005// 0 : Successful //
2006// > 0 : Failed //
2007// //
2008///////////////////////////////////////////////////////////////////////////////
3935c254
ST		 2009// DONE
2010u16 MXL_BlockInit(struct dvb_frontend *fe)
52c99bda 2011{
85d220d0 2012 struct mxl5005s_state *state = fe->tuner_priv;
3935c254 2013 u16 status = 0;
52c99bda 2014
3935c254 2015 status += MXL_OverwriteICDefault(fe);
52c99bda 2016
3935c254
ST		 2017 /* Downconverter Control Dig Ana */
2018 status += MXL_ControlWrite(fe, DN_IQTN_AMP_CUT, state->Mode ? 1 : 0);
52c99bda 2019
3935c254
ST		 2020 /* Filter Control Dig Ana */
2021 status += MXL_ControlWrite(fe, BB_MODE, state->Mode ? 0 : 1);
2022 status += MXL_ControlWrite(fe, BB_BUF, state->Mode ? 3 : 2);
2023 status += MXL_ControlWrite(fe, BB_BUF_OA, state->Mode ? 1 : 0);
2024 status += MXL_ControlWrite(fe, BB_IQSWAP, state->Mode ? 0 : 1);
2025 status += MXL_ControlWrite(fe, BB_INITSTATE_DLPF_TUNE, 0);
2026
2027 /* Initialize Low-Pass Filter */
2028 if (state->Mode) { /* Digital Mode */
2029 switch (state->Chan_Bandwidth) {
52c99bda 2030 case 8000000:
3935c254
ST		 2031 status += MXL_ControlWrite(fe, BB_DLPF_BANDSEL, 0);
2032 break;
52c99bda 2033 case 7000000:
3935c254
ST		 2034 status += MXL_ControlWrite(fe, BB_DLPF_BANDSEL, 2);
2035 break;
52c99bda 2036 case 6000000:
3935c254
ST		 2037 status += MXL_ControlWrite(fe, BB_DLPF_BANDSEL, 3);
2038 break;
2039 }
2040 } else { /* Analog Mode */
2041 switch (state->Chan_Bandwidth) {
2042 case 8000000: /* Low Zero */
2043 status += MXL_ControlWrite(fe, BB_ALPF_BANDSELECT, (state->IF_Mode ? 0 : 3));
2044 break;
52c99bda 2045 case 7000000:
3935c254
ST		 2046 status += MXL_ControlWrite(fe, BB_ALPF_BANDSELECT, (state->IF_Mode ? 1 : 4));
2047 break;
52c99bda 2048 case 6000000:
3935c254
ST		 2049 status += MXL_ControlWrite(fe, BB_ALPF_BANDSELECT, (state->IF_Mode ? 2 : 5));
2050 break;
52c99bda
ST		 2051 }
2052 }
2053
3935c254
ST		 2054 /* Charge Pump Control Dig Ana */
2055 status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, state->Mode ? 5 : 8);
2056 status += MXL_ControlWrite(fe, RFSYN_EN_CHP_HIGAIN, state->Mode ? 1 : 1);
2057 status += MXL_ControlWrite(fe, EN_CHP_LIN_B, state->Mode ? 0 : 0);
52c99bda 2058
3935c254
ST		 2059 /* AGC TOP Control */
2060 if (state->AGC_Mode == 0) /* Dual AGC */ {
2061 status += MXL_ControlWrite(fe, AGC_IF, 15);
2062 status += MXL_ControlWrite(fe, AGC_RF, 15);
52c99bda 2063 }
3935c254
ST		 2064 else /* Single AGC Mode Dig Ana */
2065 status += MXL_ControlWrite(fe, AGC_RF, state->Mode ? 15 : 12);
52c99bda
ST		 2066
2067
3935c254
ST		 2068 if (state->TOP == 55) /* TOP == 5.5 */
2069 status += MXL_ControlWrite(fe, AGC_IF, 0x0);
52c99bda 2070
3935c254
ST		 2071 if (state->TOP == 72) /* TOP == 7.2 */
2072 status += MXL_ControlWrite(fe, AGC_IF, 0x1);
52c99bda 2073
3935c254
ST		 2074 if (state->TOP == 92) /* TOP == 9.2 */
2075 status += MXL_ControlWrite(fe, AGC_IF, 0x2);
52c99bda 2076
3935c254
ST		 2077 if (state->TOP == 110) /* TOP == 11.0 */
2078 status += MXL_ControlWrite(fe, AGC_IF, 0x3);
52c99bda 2079
3935c254
ST		 2080 if (state->TOP == 129) /* TOP == 12.9 */
2081 status += MXL_ControlWrite(fe, AGC_IF, 0x4);
52c99bda 2082
3935c254
ST		 2083 if (state->TOP == 147) /* TOP == 14.7 */
2084 status += MXL_ControlWrite(fe, AGC_IF, 0x5);
52c99bda 2085
3935c254
ST		 2086 if (state->TOP == 168) /* TOP == 16.8 */
2087 status += MXL_ControlWrite(fe, AGC_IF, 0x6);
52c99bda 2088
3935c254
ST		 2089 if (state->TOP == 194) /* TOP == 19.4 */
2090 status += MXL_ControlWrite(fe, AGC_IF, 0x7);
52c99bda 2091
3935c254
ST		 2092 if (state->TOP == 212) /* TOP == 21.2 */
2093 status += MXL_ControlWrite(fe, AGC_IF, 0x9);
52c99bda 2094
3935c254
ST		 2095 if (state->TOP == 232) /* TOP == 23.2 */
2096 status += MXL_ControlWrite(fe, AGC_IF, 0xA);
52c99bda 2097
3935c254
ST		 2098 if (state->TOP == 252) /* TOP == 25.2 */
2099 status += MXL_ControlWrite(fe, AGC_IF, 0xB);
52c99bda 2100
3935c254
ST		 2101 if (state->TOP == 271) /* TOP == 27.1 */
2102 status += MXL_ControlWrite(fe, AGC_IF, 0xC);
52c99bda 2103
3935c254
ST		 2104 if (state->TOP == 292) /* TOP == 29.2 */
2105 status += MXL_ControlWrite(fe, AGC_IF, 0xD);
52c99bda 2106
3935c254
ST		 2107 if (state->TOP == 317) /* TOP == 31.7 */
2108 status += MXL_ControlWrite(fe, AGC_IF, 0xE);
52c99bda 2109
3935c254
ST		 2110 if (state->TOP == 349) /* TOP == 34.9 */
2111 status += MXL_ControlWrite(fe, AGC_IF, 0xF);
52c99bda 2112
3935c254
ST		 2113 /* IF Synthesizer Control */
2114 status += MXL_IFSynthInit(fe);
52c99bda 2115
3935c254
ST		 2116 /* IF UpConverter Control */
2117 if (state->IF_OUT_LOAD == 200) {
2118 status += MXL_ControlWrite(fe, DRV_RES_SEL, 6);
2119 status += MXL_ControlWrite(fe, I_DRIVER, 2);
52c99bda 2120 }
3935c254
ST		 2121 if (state->IF_OUT_LOAD == 300) {
2122 status += MXL_ControlWrite(fe, DRV_RES_SEL, 4);
2123 status += MXL_ControlWrite(fe, I_DRIVER, 1);
52c99bda
ST		 2124 }
2125
3935c254
ST		 2126 /* Anti-Alias Filtering Control
2127 * initialise Anti-Aliasing Filter
2128 */
2129 if (state->Mode) { /* Digital Mode */
2130 if (state->IF_OUT >= 4000000UL && state->IF_OUT <= 6280000UL) {
2131 status += MXL_ControlWrite(fe, EN_AAF, 1);
2132 status += MXL_ControlWrite(fe, EN_3P, 1);
2133 status += MXL_ControlWrite(fe, EN_AUX_3P, 1);
2134 status += MXL_ControlWrite(fe, SEL_AAF_BAND, 0);
2135 }
2136 if ((state->IF_OUT == 36125000UL) || (state->IF_OUT == 36150000UL)) {
2137 status += MXL_ControlWrite(fe, EN_AAF, 1);
2138 status += MXL_ControlWrite(fe, EN_3P, 1);
2139 status += MXL_ControlWrite(fe, EN_AUX_3P, 1);
2140 status += MXL_ControlWrite(fe, SEL_AAF_BAND, 1);
2141 }
2142 if (state->IF_OUT > 36150000UL) {
2143 status += MXL_ControlWrite(fe, EN_AAF, 0);
2144 status += MXL_ControlWrite(fe, EN_3P, 1);
2145 status += MXL_ControlWrite(fe, EN_AUX_3P, 1);
2146 status += MXL_ControlWrite(fe, SEL_AAF_BAND, 1);
2147 }
2148 } else { /* Analog Mode */
2149 if (state->IF_OUT >= 4000000UL && state->IF_OUT <= 5000000UL)
52c99bda 2150 {
3935c254
ST		 2151 status += MXL_ControlWrite(fe, EN_AAF, 1);
2152 status += MXL_ControlWrite(fe, EN_3P, 1);
2153 status += MXL_ControlWrite(fe, EN_AUX_3P, 1);
2154 status += MXL_ControlWrite(fe, SEL_AAF_BAND, 0);
52c99bda 2155 }
3935c254 2156 if (state->IF_OUT > 5000000UL)
52c99bda 2157 {
3935c254
ST		 2158 status += MXL_ControlWrite(fe, EN_AAF, 0);
2159 status += MXL_ControlWrite(fe, EN_3P, 0);
2160 status += MXL_ControlWrite(fe, EN_AUX_3P, 0);
2161 status += MXL_ControlWrite(fe, SEL_AAF_BAND, 0);
52c99bda
ST		 2162 }
2163 }
2164
3935c254
ST		 2165 /* Demod Clock Out */
2166 if (state->CLOCK_OUT)
2167 status += MXL_ControlWrite(fe, SEQ_ENCLK16_CLK_OUT, 1);
52c99bda 2168 else
3935c254 2169 status += MXL_ControlWrite(fe, SEQ_ENCLK16_CLK_OUT, 0);
52c99bda 2170
3935c254
ST		 2171 if (state->DIV_OUT == 1)
2172 status += MXL_ControlWrite(fe, SEQ_SEL4_16B, 1);
2173 if (state->DIV_OUT == 0)
2174 status += MXL_ControlWrite(fe, SEQ_SEL4_16B, 0);
52c99bda 2175
3935c254
ST		 2176 /* Crystal Control */
2177 if (state->CAPSELECT)
2178 status += MXL_ControlWrite(fe, XTAL_CAPSELECT, 1);
52c99bda 2179 else
3935c254 2180 status += MXL_ControlWrite(fe, XTAL_CAPSELECT, 0);
52c99bda 2181
3935c254
ST		 2182 if (state->Fxtal >= 12000000UL && state->Fxtal <= 16000000UL)
2183 status += MXL_ControlWrite(fe, IF_SEL_DBL, 1);
2184 if (state->Fxtal > 16000000UL && state->Fxtal <= 32000000UL)
2185 status += MXL_ControlWrite(fe, IF_SEL_DBL, 0);
52c99bda 2186
3935c254
ST		 2187 if (state->Fxtal >= 12000000UL && state->Fxtal <= 22000000UL)
2188 status += MXL_ControlWrite(fe, RFSYN_R_DIV, 3);
2189 if (state->Fxtal > 22000000UL && state->Fxtal <= 32000000UL)
2190 status += MXL_ControlWrite(fe, RFSYN_R_DIV, 0);
52c99bda 2191
3935c254 2192 /* Misc Controls */
85d220d0 2193 if (state->Mode == 0 && state->IF_Mode == 1) /* Analog LowIF mode */
3935c254 2194 status += MXL_ControlWrite(fe, SEQ_EXTIQFSMPULSE, 0);
52c99bda 2195 else
3935c254 2196 status += MXL_ControlWrite(fe, SEQ_EXTIQFSMPULSE, 1);
52c99bda 2197
3935c254 2198 /* status += MXL_ControlRead(fe, IF_DIVVAL, &IF_DIVVAL_Val); */
52c99bda 2199
3935c254
ST		 2200 /* Set TG_R_DIV */
2201 status += MXL_ControlWrite(fe, TG_R_DIV, MXL_Ceiling(state->Fxtal, 1000000));
52c99bda 2202
3935c254 2203 /* Apply Default value to BB_INITSTATE_DLPF_TUNE */
52c99bda 2204
3935c254
ST		 2205 /* RSSI Control */
2206 if (state->EN_RSSI)
52c99bda 2207 {
3935c254
ST		 2208 status += MXL_ControlWrite(fe, SEQ_EXTSYNTHCALIF, 1);
2209 status += MXL_ControlWrite(fe, SEQ_EXTDCCAL, 1);
2210 status += MXL_ControlWrite(fe, AGC_EN_RSSI, 1);
2211 status += MXL_ControlWrite(fe, RFA_ENCLKRFAGC, 1);
2212
2213 /* RSSI reference point */
2214 status += MXL_ControlWrite(fe, RFA_RSSI_REF, 2);
2215 status += MXL_ControlWrite(fe, RFA_RSSI_REFH, 3);
2216 status += MXL_ControlWrite(fe, RFA_RSSI_REFL, 1);
2217
2218 /* TOP point */
2219 status += MXL_ControlWrite(fe, RFA_FLR, 0);
2220 status += MXL_ControlWrite(fe, RFA_CEIL, 12);
52c99bda
ST		 2221 }
2222
3935c254
ST		 2223 /* Modulation type bit settings
2224 * Override the control values preset
2225 */
2226 if (state->Mod_Type == MXL_DVBT) /* DVB-T Mode */
52c99bda 2227 {
3935c254
ST		 2228 state->AGC_Mode = 1; /* Single AGC Mode */
2229
2230 /* Enable RSSI */
2231 status += MXL_ControlWrite(fe, SEQ_EXTSYNTHCALIF, 1);
2232 status += MXL_ControlWrite(fe, SEQ_EXTDCCAL, 1);
2233 status += MXL_ControlWrite(fe, AGC_EN_RSSI, 1);
2234 status += MXL_ControlWrite(fe, RFA_ENCLKRFAGC, 1);
2235
2236 /* RSSI reference point */
2237 status += MXL_ControlWrite(fe, RFA_RSSI_REF, 3);
2238 status += MXL_ControlWrite(fe, RFA_RSSI_REFH, 5);
2239 status += MXL_ControlWrite(fe, RFA_RSSI_REFL, 1);
2240
2241 /* TOP point */
2242 status += MXL_ControlWrite(fe, RFA_FLR, 2);
2243 status += MXL_ControlWrite(fe, RFA_CEIL, 13);
2244 if (state->IF_OUT <= 6280000UL) /* Low IF */
2245 status += MXL_ControlWrite(fe, BB_IQSWAP, 0);
2246 else /* High IF */
2247 status += MXL_ControlWrite(fe, BB_IQSWAP, 1);
52c99bda
ST		 2248
2249 }
3935c254 2250 if (state->Mod_Type == MXL_ATSC) /* ATSC Mode */
52c99bda 2251 {
85d220d0 2252 state->AGC_Mode = 1; /* Single AGC Mode */
3935c254
ST		 2253
2254 /* Enable RSSI */
2255 status += MXL_ControlWrite(fe, SEQ_EXTSYNTHCALIF, 1);
2256 status += MXL_ControlWrite(fe, SEQ_EXTDCCAL, 1);
2257 status += MXL_ControlWrite(fe, AGC_EN_RSSI, 1);
2258 status += MXL_ControlWrite(fe, RFA_ENCLKRFAGC, 1);
2259
2260 /* RSSI reference point */
2261 status += MXL_ControlWrite(fe, RFA_RSSI_REF, 2);
2262 status += MXL_ControlWrite(fe, RFA_RSSI_REFH, 4);
2263 status += MXL_ControlWrite(fe, RFA_RSSI_REFL, 1);
2264
2265 /* TOP point */
2266 status += MXL_ControlWrite(fe, RFA_FLR, 2);
2267 status += MXL_ControlWrite(fe, RFA_CEIL, 13);
2268 status += MXL_ControlWrite(fe, BB_INITSTATE_DLPF_TUNE, 1);
2269 status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 5); /* Low Zero */
2270 if (state->IF_OUT <= 6280000UL) /* Low IF */
2271 status += MXL_ControlWrite(fe, BB_IQSWAP, 0);
2272 else /* High IF */
2273 status += MXL_ControlWrite(fe, BB_IQSWAP, 1);
52c99bda 2274 }
3935c254 2275 if (state->Mod_Type == MXL_QAM) /* QAM Mode */
52c99bda 2276 {
3935c254
ST		 2277 state->Mode = MXL_DIGITAL_MODE;
2278
2279 /* state->AGC_Mode = 1; */ /* Single AGC Mode */
2280
2281 /* Disable RSSI */ /* change here for v2.6.5 */
2282 status += MXL_ControlWrite(fe, SEQ_EXTSYNTHCALIF, 1);
2283 status += MXL_ControlWrite(fe, SEQ_EXTDCCAL, 1);
2284 status += MXL_ControlWrite(fe, AGC_EN_RSSI, 0);
2285 status += MXL_ControlWrite(fe, RFA_ENCLKRFAGC, 1);
2286
2287 /* RSSI reference point */
2288 status += MXL_ControlWrite(fe, RFA_RSSI_REFH, 5);
2289 status += MXL_ControlWrite(fe, RFA_RSSI_REF, 3);
2290 status += MXL_ControlWrite(fe, RFA_RSSI_REFL, 2);
2291 status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 3); /* change here for v2.6.5 */
2292
2293 if (state->IF_OUT <= 6280000UL) /* Low IF */
2294 status += MXL_ControlWrite(fe, BB_IQSWAP, 0);
2295 else /* High IF */
2296 status += MXL_ControlWrite(fe, BB_IQSWAP, 1);
52c99bda 2297 }
3935c254
ST		 2298 if (state->Mod_Type == MXL_ANALOG_CABLE) {
2299 /* Analog Cable Mode */
85d220d0 2300 /* state->Mode = MXL_DIGITAL_MODE; */
3935c254
ST		 2301
2302 state->AGC_Mode = 1; /* Single AGC Mode */
2303
2304 /* Disable RSSI */
2305 status += MXL_ControlWrite(fe, SEQ_EXTSYNTHCALIF, 1);
2306 status += MXL_ControlWrite(fe, SEQ_EXTDCCAL, 1);
2307 status += MXL_ControlWrite(fe, AGC_EN_RSSI, 0);
2308 status += MXL_ControlWrite(fe, RFA_ENCLKRFAGC, 1);
2309 status += MXL_ControlWrite(fe, AGC_IF, 1); /* change for 2.6.3 */
2310 status += MXL_ControlWrite(fe, AGC_RF, 15);
2311 status += MXL_ControlWrite(fe, BB_IQSWAP, 1);
52c99bda
ST		 2312 }
2313
3935c254
ST		 2314 if (state->Mod_Type == MXL_ANALOG_OTA) {
2315 /* Analog OTA Terrestrial mode add for 2.6.7 */
2316 /* state->Mode = MXL_ANALOG_MODE; */
2317
2318 /* Enable RSSI */
2319 status += MXL_ControlWrite(fe, SEQ_EXTSYNTHCALIF, 1);
2320 status += MXL_ControlWrite(fe, SEQ_EXTDCCAL, 1);
2321 status += MXL_ControlWrite(fe, AGC_EN_RSSI, 1);
2322 status += MXL_ControlWrite(fe, RFA_ENCLKRFAGC, 1);
2323
2324 /* RSSI reference point */
2325 status += MXL_ControlWrite(fe, RFA_RSSI_REFH, 5);
2326 status += MXL_ControlWrite(fe, RFA_RSSI_REF, 3);
2327 status += MXL_ControlWrite(fe, RFA_RSSI_REFL, 2);
2328 status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 3);
2329 status += MXL_ControlWrite(fe, BB_IQSWAP, 1);
52c99bda
ST		 2330 }
2331
3935c254
ST		 2332 /* RSSI disable */
2333 if(state->EN_RSSI==0) {
2334 status += MXL_ControlWrite(fe, SEQ_EXTSYNTHCALIF, 1);
2335 status += MXL_ControlWrite(fe, SEQ_EXTDCCAL, 1);
2336 status += MXL_ControlWrite(fe, AGC_EN_RSSI, 0);
2337 status += MXL_ControlWrite(fe, RFA_ENCLKRFAGC, 1);
52c99bda
ST		 2338 }
2339
3935c254 2340 return status;
52c99bda
ST		 2341}
2342
2343///////////////////////////////////////////////////////////////////////////////
2344// //
2345// Function: MXL_IFSynthInit //
2346// //
2347// Description: Tuner IF Synthesizer related register initialization //
2348// //
2349// Globals: //
2350// NONE //
2351// //
2352// Functions used: //
2353// Tuner_struct: structure defined at higher level //
2354// //
2355// Inputs: //
2356// Tuner : Tuner structure defined at higher level //
2357// //
2358// Outputs: //
2359// Tuner //
2360// //
2361// Return: //
2362// 0 : Successful //
2363// > 0 : Failed //
2364// //
2365///////////////////////////////////////////////////////////////////////////////
85d220d0 2366u16 MXL_IFSynthInit(struct dvb_frontend *fe)
52c99bda 2367{
85d220d0 2368 struct mxl5005s_state *state = fe->tuner_priv;
a8214d48 2369 u16 status = 0 ;
52c99bda 2370 // Declare Local Variables
a8214d48
ST		 2371 u32 Fref = 0 ;
2372 u32 Kdbl, intModVal ;
2373 u32 fracModVal ;
52c99bda
ST		 2374 Kdbl = 2 ;
2375
3935c254 2376 if (state->Fxtal >= 12000000UL && state->Fxtal <= 16000000UL)
52c99bda 2377 Kdbl = 2 ;
3935c254 2378 if (state->Fxtal > 16000000UL && state->Fxtal <= 32000000UL)
52c99bda
ST		 2379 Kdbl = 1 ;
2380
2381 //
2382 // IF Synthesizer Control
2383 //
85d220d0 2384 if (state->Mode == 0 && state->IF_Mode == 1) // Analog Low IF mode
52c99bda 2385 {
85d220d0 2386 if (state->IF_LO == 41000000UL) {
3935c254
ST		 2387 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08) ;
2388 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C) ;
52c99bda
ST		 2389 Fref = 328000000UL ;
2390 }
85d220d0 2391 if (state->IF_LO == 47000000UL) {
3935c254
ST		 2392 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08) ;
2393 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ;
52c99bda
ST		 2394 Fref = 376000000UL ;
2395 }
85d220d0 2396 if (state->IF_LO == 54000000UL) {
3935c254
ST		 2397 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x10) ;
2398 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C) ;
52c99bda
ST		 2399 Fref = 324000000UL ;
2400 }
85d220d0 2401 if (state->IF_LO == 60000000UL) {
3935c254
ST		 2402 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x10) ;
2403 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ;
52c99bda
ST		 2404 Fref = 360000000UL ;
2405 }
85d220d0 2406 if (state->IF_LO == 39250000UL) {
3935c254
ST		 2407 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08) ;
2408 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C) ;
52c99bda
ST		 2409 Fref = 314000000UL ;
2410 }
85d220d0 2411 if (state->IF_LO == 39650000UL) {
3935c254
ST		 2412 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08) ;
2413 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C) ;
52c99bda
ST		 2414 Fref = 317200000UL ;
2415 }
85d220d0 2416 if (state->IF_LO == 40150000UL) {
3935c254
ST		 2417 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08) ;
2418 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C) ;
52c99bda
ST		 2419 Fref = 321200000UL ;
2420 }
85d220d0 2421 if (state->IF_LO == 40650000UL) {
3935c254
ST		 2422 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08) ;
2423 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C) ;
52c99bda
ST		 2424 Fref = 325200000UL ;
2425 }
2426 }
2427
85d220d0 2428 if (state->Mode || (state->Mode == 0 && state->IF_Mode == 0))
52c99bda 2429 {
85d220d0 2430 if (state->IF_LO == 57000000UL) {
3935c254
ST		 2431 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x10) ;
2432 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ;
52c99bda
ST		 2433 Fref = 342000000UL ;
2434 }
85d220d0 2435 if (state->IF_LO == 44000000UL) {
3935c254
ST		 2436 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08) ;
2437 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ;
52c99bda
ST		 2438 Fref = 352000000UL ;
2439 }
85d220d0 2440 if (state->IF_LO == 43750000UL) {
3935c254
ST		 2441 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08) ;
2442 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ;
52c99bda
ST		 2443 Fref = 350000000UL ;
2444 }
85d220d0 2445 if (state->IF_LO == 36650000UL) {
3935c254
ST		 2446 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04) ;
2447 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ;
52c99bda
ST		 2448 Fref = 366500000UL ;
2449 }
85d220d0 2450 if (state->IF_LO == 36150000UL) {
3935c254
ST		 2451 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04) ;
2452 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ;
52c99bda
ST		 2453 Fref = 361500000UL ;
2454 }
85d220d0 2455 if (state->IF_LO == 36000000UL) {
3935c254
ST		 2456 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04) ;
2457 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ;
52c99bda
ST		 2458 Fref = 360000000UL ;
2459 }
85d220d0 2460 if (state->IF_LO == 35250000UL) {
3935c254
ST		 2461 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04) ;
2462 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ;
52c99bda
ST		 2463 Fref = 352500000UL ;
2464 }
85d220d0 2465 if (state->IF_LO == 34750000UL) {
3935c254
ST		 2466 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04) ;
2467 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ;
52c99bda
ST		 2468 Fref = 347500000UL ;
2469 }
85d220d0 2470 if (state->IF_LO == 6280000UL) {
3935c254
ST		 2471 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x07) ;
2472 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ;
52c99bda
ST		 2473 Fref = 376800000UL ;
2474 }
85d220d0 2475 if (state->IF_LO == 5000000UL) {
3935c254
ST		 2476 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x09) ;
2477 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ;
52c99bda
ST		 2478 Fref = 360000000UL ;
2479 }
85d220d0 2480 if (state->IF_LO == 4500000UL) {
3935c254
ST		 2481 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x06) ;
2482 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ;
52c99bda
ST		 2483 Fref = 360000000UL ;
2484 }
85d220d0 2485 if (state->IF_LO == 4570000UL) {
3935c254
ST		 2486 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x06) ;
2487 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ;
52c99bda
ST		 2488 Fref = 365600000UL ;
2489 }
85d220d0 2490 if (state->IF_LO == 4000000UL) {
3935c254
ST		 2491 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x05) ;
2492 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ;
52c99bda
ST		 2493 Fref = 360000000UL ;
2494 }
85d220d0 2495 if (state->IF_LO == 57400000UL)
52c99bda 2496 {
3935c254
ST		 2497 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x10) ;
2498 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ;
52c99bda
ST		 2499 Fref = 344400000UL ;
2500 }
85d220d0 2501 if (state->IF_LO == 44400000UL)
52c99bda 2502 {
3935c254
ST		 2503 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08) ;
2504 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ;
52c99bda
ST		 2505 Fref = 355200000UL ;
2506 }
85d220d0 2507 if (state->IF_LO == 44150000UL)
52c99bda 2508 {
3935c254
ST		 2509 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08) ;
2510 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ;
52c99bda
ST		 2511 Fref = 353200000UL ;
2512 }
85d220d0 2513 if (state->IF_LO == 37050000UL)
52c99bda 2514 {
3935c254
ST		 2515 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04) ;
2516 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ;
52c99bda
ST		 2517 Fref = 370500000UL ;
2518 }
85d220d0 2519 if (state->IF_LO == 36550000UL)
52c99bda 2520 {
3935c254
ST		 2521 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04) ;
2522 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ;
52c99bda
ST		 2523 Fref = 365500000UL ;
2524 }
85d220d0 2525 if (state->IF_LO == 36125000UL) {
3935c254
ST		 2526 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04) ;
2527 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ;
52c99bda
ST		 2528 Fref = 361250000UL ;
2529 }
85d220d0 2530 if (state->IF_LO == 6000000UL) {
3935c254
ST		 2531 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x07) ;
2532 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ;
52c99bda
ST		 2533 Fref = 360000000UL ;
2534 }
85d220d0 2535 if (state->IF_LO == 5400000UL)
52c99bda 2536 {
3935c254
ST		 2537 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x07) ;
2538 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C) ;
52c99bda
ST		 2539 Fref = 324000000UL ;
2540 }
85d220d0 2541 if (state->IF_LO == 5380000UL) {
3935c254
ST		 2542 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x07) ;
2543 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C) ;
52c99bda
ST		 2544 Fref = 322800000UL ;
2545 }
85d220d0 2546 if (state->IF_LO == 5200000UL) {
3935c254
ST		 2547 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x09) ;
2548 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ;
52c99bda
ST		 2549 Fref = 374400000UL ;
2550 }
85d220d0 2551 if (state->IF_LO == 4900000UL)
52c99bda 2552 {
3935c254
ST		 2553 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x09) ;
2554 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ;
52c99bda
ST		 2555 Fref = 352800000UL ;
2556 }
85d220d0 2557 if (state->IF_LO == 4400000UL)
52c99bda 2558 {
3935c254
ST		 2559 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x06) ;
2560 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ;
52c99bda
ST		 2561 Fref = 352000000UL ;
2562 }
85d220d0 2563 if (state->IF_LO == 4063000UL) //add for 2.6.8
52c99bda 2564 {
3935c254
ST		 2565 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x05) ;
2566 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ;
52c99bda
ST		 2567 Fref = 365670000UL ;
2568 }
2569 }
2570 // CHCAL_INT_MOD_IF
2571 // CHCAL_FRAC_MOD_IF
3935c254
ST		 2572 intModVal = Fref / (state->Fxtal * Kdbl/2) ;
2573 status += MXL_ControlWrite(fe, CHCAL_INT_MOD_IF, intModVal ) ;
52c99bda 2574
3935c254
ST		 2575 fracModVal = (2<<15)*(Fref/1000 - (state->Fxtal/1000 * Kdbl/2) * intModVal);
2576 fracModVal = fracModVal / ((state->Fxtal * Kdbl/2)/1000) ;
2577 status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_IF, fracModVal) ;
52c99bda 2578
52c99bda
ST		 2579 return status ;
2580}
2581
2582///////////////////////////////////////////////////////////////////////////////
2583// //
2584// Function: MXL_GetXtalInt //
2585// //
a8214d48
ST		 2586// Description: return the Crystal Integration Value for //
2587// TG_VCO_BIAS calculation //
52c99bda
ST		 2588// //
2589// Globals: //
2590// NONE //
2591// //
2592// Functions used: //
a8214d48 2593// NONE //
52c99bda
ST		 2594// //
2595// Inputs: //
2596// Crystal Frequency Value in Hz //
2597// //
2598// Outputs: //
2599// Calculated Crystal Frequency Integration Value //
2600// //
2601// Return: //
2602// 0 : Successful //
2603// > 0 : Failed //
2604// //
2605///////////////////////////////////////////////////////////////////////////////
a8214d48 2606u32 MXL_GetXtalInt(u32 Xtal_Freq)
52c99bda
ST		 2607{
2608 if ((Xtal_Freq % 1000000) == 0)
2609 return (Xtal_Freq / 10000) ;
2610 else
2611 return (((Xtal_Freq / 1000000) + 1)*100) ;
2612}
2613
2614///////////////////////////////////////////////////////////////////////////////
2615// //
2616// Function: MXL5005_TuneRF //
2617// //
2618// Description: Set control names to tune to requested RF_IN frequency //
2619// //
2620// Globals: //
2621// None //
2622// //
2623// Functions used: //
2624// MXL_SynthRFTGLO_Calc //
2625// MXL5005_ControlWrite //
3935c254 2626// MXL_GetXtalInt //
52c99bda
ST		 2627// //
2628// Inputs: //
2629// Tuner : Tuner structure defined at higher level //
2630// //
2631// Outputs: //
2632// Tuner //
2633// //
2634// Return: //
2635// 0 : Successful //
2636// 1 : Unsuccessful //
2637///////////////////////////////////////////////////////////////////////////////
3935c254 2638u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq)
52c99bda 2639{
85d220d0 2640 struct mxl5005s_state *state = fe->tuner_priv;
52c99bda 2641 // Declare Local Variables
3935c254
ST		 2642 u16 status = 0;
2643 u32 divider_val, E3, E4, E5, E5A;
2644 u32 Fmax, Fmin, FmaxBin, FminBin;
a8214d48 2645 u32 Kdbl_RF = 2;
3935c254
ST		 2646 u32 tg_divval;
2647 u32 tg_lo;
2648 u32 Xtal_Int;
52c99bda 2649
a8214d48
ST		 2650 u32 Fref_TG;
2651 u32 Fvco;
2652// u32 temp;
52c99bda
ST		 2653
2654
3935c254 2655 Xtal_Int = MXL_GetXtalInt(state->Fxtal);
52c99bda 2656
3935c254 2657 state->RF_IN = RF_Freq;
52c99bda 2658
3935c254 2659 MXL_SynthRFTGLO_Calc(fe);
52c99bda 2660
3935c254
ST		 2661 if (state->Fxtal >= 12000000UL && state->Fxtal <= 22000000UL)
2662 Kdbl_RF = 2;
2663 if (state->Fxtal > 22000000 && state->Fxtal <= 32000000)
2664 Kdbl_RF = 1;
52c99bda
ST		 2665
2666 //
2667 // Downconverter Controls
2668 //
2669 // Look-Up Table Implementation for:
2670 // DN_POLY
2671 // DN_RFGAIN
2672 // DN_CAP_RFLPF
2673 // DN_EN_VHFUHFBAR
2674 // DN_GAIN_ADJUST
2675 // Change the boundary reference from RF_IN to RF_LO
3935c254 2676 if (state->RF_LO < 40000000UL) {
52c99bda
ST		 2677 return -1;
2678 }
3935c254 2679 if (state->RF_LO >= 40000000UL && state->RF_LO <= 75000000UL) {
52c99bda 2680 // Look-Up Table implementation
3935c254
ST		 2681 status += MXL_ControlWrite(fe, DN_POLY, 2);
2682 status += MXL_ControlWrite(fe, DN_RFGAIN, 3);
2683 status += MXL_ControlWrite(fe, DN_CAP_RFLPF, 423);
2684 status += MXL_ControlWrite(fe, DN_EN_VHFUHFBAR, 1);
2685 status += MXL_ControlWrite(fe, DN_GAIN_ADJUST, 1);
52c99bda 2686 }
3935c254 2687 if (state->RF_LO > 75000000UL && state->RF_LO <= 100000000UL) {
52c99bda 2688 // Look-Up Table implementation
3935c254
ST		 2689 status += MXL_ControlWrite(fe, DN_POLY, 3);
2690 status += MXL_ControlWrite(fe, DN_RFGAIN, 3);
2691 status += MXL_ControlWrite(fe, DN_CAP_RFLPF, 222);
2692 status += MXL_ControlWrite(fe, DN_EN_VHFUHFBAR, 1);
2693 status += MXL_ControlWrite(fe, DN_GAIN_ADJUST, 1);
52c99bda 2694 }
3935c254 2695 if (state->RF_LO > 100000000UL && state->RF_LO <= 150000000UL) {
52c99bda 2696 // Look-Up Table implementation
3935c254
ST		 2697 status += MXL_ControlWrite(fe, DN_POLY, 3);
2698 status += MXL_ControlWrite(fe, DN_RFGAIN, 3);
2699 status += MXL_ControlWrite(fe, DN_CAP_RFLPF, 147);
2700 status += MXL_ControlWrite(fe, DN_EN_VHFUHFBAR, 1);
2701 status += MXL_ControlWrite(fe, DN_GAIN_ADJUST, 2);
52c99bda 2702 }
3935c254 2703 if (state->RF_LO > 150000000UL && state->RF_LO <= 200000000UL) {
52c99bda 2704 // Look-Up Table implementation
3935c254
ST		 2705 status += MXL_ControlWrite(fe, DN_POLY, 3);
2706 status += MXL_ControlWrite(fe, DN_RFGAIN, 3);
2707 status += MXL_ControlWrite(fe, DN_CAP_RFLPF, 9);
2708 status += MXL_ControlWrite(fe, DN_EN_VHFUHFBAR, 1);
2709 status += MXL_ControlWrite(fe, DN_GAIN_ADJUST, 2);
52c99bda 2710 }
3935c254 2711 if (state->RF_LO > 200000000UL && state->RF_LO <= 300000000UL) {
52c99bda 2712 // Look-Up Table implementation
3935c254
ST		 2713 status += MXL_ControlWrite(fe, DN_POLY, 3) ;
2714 status += MXL_ControlWrite(fe, DN_RFGAIN, 3) ;
2715 status += MXL_ControlWrite(fe, DN_CAP_RFLPF, 0) ;
2716 status += MXL_ControlWrite(fe, DN_EN_VHFUHFBAR, 1) ;
2717 status += MXL_ControlWrite(fe, DN_GAIN_ADJUST, 3) ;
52c99bda 2718 }
3935c254 2719 if (state->RF_LO > 300000000UL && state->RF_LO <= 650000000UL) {
52c99bda 2720 // Look-Up Table implementation
3935c254
ST		 2721 status += MXL_ControlWrite(fe, DN_POLY, 3) ;
2722 status += MXL_ControlWrite(fe, DN_RFGAIN, 1) ;
2723 status += MXL_ControlWrite(fe, DN_CAP_RFLPF, 0) ;
2724 status += MXL_ControlWrite(fe, DN_EN_VHFUHFBAR, 0) ;
2725 status += MXL_ControlWrite(fe, DN_GAIN_ADJUST, 3) ;
52c99bda 2726 }
3935c254 2727 if (state->RF_LO > 650000000UL && state->RF_LO <= 900000000UL) {
52c99bda 2728 // Look-Up Table implementation
3935c254
ST		 2729 status += MXL_ControlWrite(fe, DN_POLY, 3) ;
2730 status += MXL_ControlWrite(fe, DN_RFGAIN, 2) ;
2731 status += MXL_ControlWrite(fe, DN_CAP_RFLPF, 0) ;
2732 status += MXL_ControlWrite(fe, DN_EN_VHFUHFBAR, 0) ;
2733 status += MXL_ControlWrite(fe, DN_GAIN_ADJUST, 3) ;
52c99bda 2734 }
3935c254 2735 if (state->RF_LO > 900000000UL) {
52c99bda
ST		 2736 return -1;
2737 }
2738 // DN_IQTNBUF_AMP
2739 // DN_IQTNGNBFBIAS_BST
3935c254
ST		 2740 if (state->RF_LO >= 40000000UL && state->RF_LO <= 75000000UL) {
2741 status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1);
2742 status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0);
52c99bda 2743 }
3935c254
ST		 2744 if (state->RF_LO > 75000000UL && state->RF_LO <= 100000000UL) {
2745 status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1);
2746 status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0);
52c99bda 2747 }
3935c254
ST		 2748 if (state->RF_LO > 100000000UL && state->RF_LO <= 150000000UL) {
2749 status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1);
2750 status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0);
52c99bda 2751 }
3935c254
ST		 2752 if (state->RF_LO > 150000000UL && state->RF_LO <= 200000000UL) {
2753 status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1);
2754 status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0);
52c99bda 2755 }
3935c254
ST		 2756 if (state->RF_LO > 200000000UL && state->RF_LO <= 300000000UL) {
2757 status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1);
2758 status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0);
52c99bda 2759 }
3935c254
ST		 2760 if (state->RF_LO > 300000000UL && state->RF_LO <= 400000000UL) {
2761 status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1);
2762 status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0);
52c99bda 2763 }
3935c254
ST		 2764 if (state->RF_LO > 400000000UL && state->RF_LO <= 450000000UL) {
2765 status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1);
2766 status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0);
52c99bda 2767 }
3935c254
ST		 2768 if (state->RF_LO > 450000000UL && state->RF_LO <= 500000000UL) {
2769 status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1);
2770 status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0);
52c99bda 2771 }
3935c254
ST		 2772 if (state->RF_LO > 500000000UL && state->RF_LO <= 550000000UL) {
2773 status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1);
2774 status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0);
52c99bda 2775 }
3935c254
ST		 2776 if (state->RF_LO > 550000000UL && state->RF_LO <= 600000000UL) {
2777 status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1);
2778 status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0);
52c99bda 2779 }
3935c254
ST		 2780 if (state->RF_LO > 600000000UL && state->RF_LO <= 650000000UL) {
2781 status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1);
2782 status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0);
52c99bda 2783 }
3935c254
ST		 2784 if (state->RF_LO > 650000000UL && state->RF_LO <= 700000000UL) {
2785 status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1);
2786 status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0);
52c99bda 2787 }
3935c254
ST		 2788 if (state->RF_LO > 700000000UL && state->RF_LO <= 750000000UL) {
2789 status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1);
2790 status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0);
52c99bda 2791 }
3935c254
ST		 2792 if (state->RF_LO > 750000000UL && state->RF_LO <= 800000000UL) {
2793 status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1);
2794 status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0);
52c99bda 2795 }
3935c254
ST		 2796 if (state->RF_LO > 800000000UL && state->RF_LO <= 850000000UL) {
2797 status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 10);
2798 status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 1);
52c99bda 2799 }
3935c254
ST		 2800 if (state->RF_LO > 850000000UL && state->RF_LO <= 900000000UL) {
2801 status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 10);
2802 status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 1);
52c99bda
ST		 2803 }
2804
2805 //
2806 // Set RF Synth and LO Path Control
2807 //
2808 // Look-Up table implementation for:
2809 // RFSYN_EN_OUTMUX
2810 // RFSYN_SEL_VCO_OUT
2811 // RFSYN_SEL_VCO_HI
2812 // RFSYN_SEL_DIVM
2813 // RFSYN_RF_DIV_BIAS
2814 // DN_SEL_FREQ
2815 //
2816 // Set divider_val, Fmax, Fmix to use in Equations
2817 FminBin = 28000000UL ;
2818 FmaxBin = 42500000UL ;
3935c254
ST		 2819 if (state->RF_LO >= 40000000UL && state->RF_LO <= FmaxBin) {
2820 status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 1);
2821 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 0);
2822 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0);
2823 status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0);
2824 status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1);
2825 status += MXL_ControlWrite(fe, DN_SEL_FREQ, 1);
52c99bda
ST		 2826 divider_val = 64 ;
2827 Fmax = FmaxBin ;
2828 Fmin = FminBin ;
2829 }
2830 FminBin = 42500000UL ;
2831 FmaxBin = 56000000UL ;
3935c254
ST		 2832 if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) {
2833 status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 1);
2834 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 0);
2835 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1);
2836 status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0);
2837 status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1);
2838 status += MXL_ControlWrite(fe, DN_SEL_FREQ, 1);
52c99bda
ST		 2839 divider_val = 64 ;
2840 Fmax = FmaxBin ;
2841 Fmin = FminBin ;
2842 }
2843 FminBin = 56000000UL ;
2844 FmaxBin = 85000000UL ;
3935c254
ST		 2845 if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) {
2846 status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0) ;
2847 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1) ;
2848 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0) ;
2849 status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0) ;
2850 status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1) ;
2851 status += MXL_ControlWrite(fe, DN_SEL_FREQ, 1) ;
52c99bda
ST		 2852 divider_val = 32 ;
2853 Fmax = FmaxBin ;
2854 Fmin = FminBin ;
2855 }
2856 FminBin = 85000000UL ;
2857 FmaxBin = 112000000UL ;
3935c254
ST		 2858 if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) {
2859 status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0) ;
2860 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1) ;
2861 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1) ;
2862 status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0) ;
2863 status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1) ;
2864 status += MXL_ControlWrite(fe, DN_SEL_FREQ, 1) ;
52c99bda
ST		 2865 divider_val = 32 ;
2866 Fmax = FmaxBin ;
2867 Fmin = FminBin ;
2868 }
2869 FminBin = 112000000UL ;
2870 FmaxBin = 170000000UL ;
3935c254
ST		 2871 if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) {
2872 status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0) ;
2873 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1) ;
2874 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0) ;
2875 status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0) ;
2876 status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1) ;
2877 status += MXL_ControlWrite(fe, DN_SEL_FREQ, 2) ;
52c99bda
ST		 2878 divider_val = 16 ;
2879 Fmax = FmaxBin ;
2880 Fmin = FminBin ;
2881 }
2882 FminBin = 170000000UL ;
2883 FmaxBin = 225000000UL ;
3935c254
ST		 2884 if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) {
2885 status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0) ;
2886 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1) ;
2887 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1) ;
2888 status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0) ;
2889 status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1) ;
2890 status += MXL_ControlWrite(fe, DN_SEL_FREQ, 2) ;
52c99bda
ST		 2891 divider_val = 16 ;
2892 Fmax = FmaxBin ;
2893 Fmin = FminBin ;
2894 }
2895 FminBin = 225000000UL ;
2896 FmaxBin = 300000000UL ;
3935c254
ST		 2897 if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) {
2898 status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0) ;
2899 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1) ;
2900 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0) ;
2901 status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0) ;
2902 status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1) ;
2903 status += MXL_ControlWrite(fe, DN_SEL_FREQ, 4) ;
52c99bda
ST		 2904 divider_val = 8 ;
2905 Fmax = 340000000UL ;
2906 Fmin = FminBin ;
2907 }
2908 FminBin = 300000000UL ;
2909 FmaxBin = 340000000UL ;
3935c254
ST		 2910 if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) {
2911 status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 1) ;
2912 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 0) ;
2913 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0) ;
2914 status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0) ;
2915 status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1) ;
2916 status += MXL_ControlWrite(fe, DN_SEL_FREQ, 0) ;
52c99bda
ST		 2917 divider_val = 8 ;
2918 Fmax = FmaxBin ;
2919 Fmin = 225000000UL ;
2920 }
2921 FminBin = 340000000UL ;
2922 FmaxBin = 450000000UL ;
3935c254
ST		 2923 if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) {
2924 status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 1) ;
2925 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 0) ;
2926 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1) ;
2927 status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0) ;
2928 status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 2) ;
2929 status += MXL_ControlWrite(fe, DN_SEL_FREQ, 0) ;
52c99bda
ST		 2930 divider_val = 8 ;
2931 Fmax = FmaxBin ;
2932 Fmin = FminBin ;
2933 }
2934 FminBin = 450000000UL ;
2935 FmaxBin = 680000000UL ;
3935c254
ST		 2936 if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) {
2937 status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0) ;
2938 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1) ;
2939 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0) ;
2940 status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 1) ;
2941 status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1) ;
2942 status += MXL_ControlWrite(fe, DN_SEL_FREQ, 0) ;
52c99bda
ST		 2943 divider_val = 4 ;
2944 Fmax = FmaxBin ;
2945 Fmin = FminBin ;
2946 }
2947 FminBin = 680000000UL ;
2948 FmaxBin = 900000000UL ;
3935c254
ST		 2949 if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) {
2950 status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0) ;
2951 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1) ;
2952 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1) ;
2953 status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 1) ;
2954 status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1) ;
2955 status += MXL_ControlWrite(fe, DN_SEL_FREQ, 0) ;
52c99bda
ST		 2956 divider_val = 4 ;
2957 Fmax = FmaxBin ;
2958 Fmin = FminBin ;
2959 }
2960
2961 // CHCAL_INT_MOD_RF
2962 // CHCAL_FRAC_MOD_RF
2963 // RFSYN_LPF_R
2964 // CHCAL_EN_INT_RF
2965
2966 // Equation E3
2967 // RFSYN_VCO_BIAS
3935c254
ST		 2968 E3 = (((Fmax-state->RF_LO)/1000)*32)/((Fmax-Fmin)/1000) + 8 ;
2969 status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, E3) ;
52c99bda
ST		 2970
2971 // Equation E4
2972 // CHCAL_INT_MOD_RF
3935c254
ST		 2973 E4 = (state->RF_LO*divider_val/1000)/(2*state->Fxtal*Kdbl_RF/1000) ;
2974 MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, E4) ;
52c99bda
ST		 2975
2976 // Equation E5
2977 // CHCAL_FRAC_MOD_RF
2978 // CHCAL_EN_INT_RF
3935c254
ST		 2979 E5 = ((2<<17)*(state->RF_LO/10000*divider_val - (E4*(2*state->Fxtal*Kdbl_RF)/10000)))/(2*state->Fxtal*Kdbl_RF/10000) ;
2980 status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, E5) ;
52c99bda
ST		 2981
2982 // Equation E5A
2983 // RFSYN_LPF_R
3935c254
ST		 2984 E5A = (((Fmax - state->RF_LO)/1000)*4/((Fmax-Fmin)/1000)) + 1 ;
2985 status += MXL_ControlWrite(fe, RFSYN_LPF_R, E5A) ;
52c99bda
ST		 2986
2987 // Euqation E5B
2988 // CHCAL_EN_INIT_RF
3935c254 2989 status += MXL_ControlWrite(fe, CHCAL_EN_INT_RF, ((E5 == 0) ? 1 : 0));
52c99bda 2990 //if (E5 == 0)
3935c254 2991 // status += MXL_ControlWrite(fe, CHCAL_EN_INT_RF, 1);
52c99bda 2992 //else
3935c254 2993 // status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, E5) ;
52c99bda
ST		 2994
2995 //
2996 // Set TG Synth
2997 //
2998 // Look-Up table implementation for:
2999 // TG_LO_DIVVAL
3000 // TG_LO_SELVAL
3001 //
3002 // Set divider_val, Fmax, Fmix to use in Equations
3935c254 3003 if (state->TG_LO < 33000000UL) {
52c99bda
ST		 3004 return -1;
3005 }
3006 FminBin = 33000000UL ;
3007 FmaxBin = 50000000UL ;
3935c254
ST		 3008 if (state->TG_LO >= FminBin && state->TG_LO <= FmaxBin) {
3009 status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0x6) ;
3010 status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x0) ;
52c99bda
ST		 3011 divider_val = 36 ;
3012 Fmax = FmaxBin ;
3013 Fmin = FminBin ;
3014 }
3015 FminBin = 50000000UL ;
3016 FmaxBin = 67000000UL ;
3935c254
ST		 3017 if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) {
3018 status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0x1) ;
3019 status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x0) ;
52c99bda
ST		 3020 divider_val = 24 ;
3021 Fmax = FmaxBin ;
3022 Fmin = FminBin ;
3023 }
3024 FminBin = 67000000UL ;
3025 FmaxBin = 100000000UL ;
3935c254
ST		 3026 if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) {
3027 status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0xC) ;
3028 status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x2) ;
52c99bda
ST		 3029 divider_val = 18 ;
3030 Fmax = FmaxBin ;
3031 Fmin = FminBin ;
3032 }
3033 FminBin = 100000000UL ;
3034 FmaxBin = 150000000UL ;
3935c254
ST		 3035 if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) {
3036 status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0x8) ;
3037 status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x2) ;
52c99bda
ST		 3038 divider_val = 12 ;
3039 Fmax = FmaxBin ;
3040 Fmin = FminBin ;
3041 }
3042 FminBin = 150000000UL ;
3043 FmaxBin = 200000000UL ;
3935c254
ST		 3044 if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) {
3045 status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0x0) ;
3046 status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x2) ;
52c99bda
ST		 3047 divider_val = 8 ;
3048 Fmax = FmaxBin ;
3049 Fmin = FminBin ;
3050 }
3051 FminBin = 200000000UL ;
3052 FmaxBin = 300000000UL ;
3935c254
ST		 3053 if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) {
3054 status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0x8) ;
3055 status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x3) ;
52c99bda
ST		 3056 divider_val = 6 ;
3057 Fmax = FmaxBin ;
3058 Fmin = FminBin ;
3059 }
3060 FminBin = 300000000UL ;
3061 FmaxBin = 400000000UL ;
3935c254
ST		 3062 if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) {
3063 status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0x0) ;
3064 status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x3) ;
52c99bda
ST		 3065 divider_val = 4 ;
3066 Fmax = FmaxBin ;
3067 Fmin = FminBin ;
3068 }
3069 FminBin = 400000000UL ;
3070 FmaxBin = 600000000UL ;
3935c254
ST		 3071 if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) {
3072 status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0x8) ;
3073 status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x7) ;
52c99bda
ST		 3074 divider_val = 3 ;
3075 Fmax = FmaxBin ;
3076 Fmin = FminBin ;
3077 }
3078 FminBin = 600000000UL ;
3079 FmaxBin = 900000000UL ;
3935c254
ST		 3080 if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) {
3081 status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0x0) ;
3082 status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x7) ;
52c99bda
ST		 3083 divider_val = 2 ;
3084 Fmax = FmaxBin ;
3085 Fmin = FminBin ;
3086 }
3087
3088 // TG_DIV_VAL
3935c254
ST		 3089 tg_divval = (state->TG_LO*divider_val/100000)
3090 *(MXL_Ceiling(state->Fxtal,1000000) * 100) / (state->Fxtal/1000) ;
3091 status += MXL_ControlWrite(fe, TG_DIV_VAL, tg_divval) ;
52c99bda 3092
3935c254
ST		 3093 if (state->TG_LO > 600000000UL)
3094 status += MXL_ControlWrite(fe, TG_DIV_VAL, tg_divval + 1 ) ;
52c99bda
ST		 3095
3096 Fmax = 1800000000UL ;
3097 Fmin = 1200000000UL ;
3098
3099
3100
3101 // to prevent overflow of 32 bit unsigned integer, use following equation. Edit for v2.6.4
3935c254 3102 Fref_TG = (state->Fxtal/1000)/ MXL_Ceiling(state->Fxtal, 1000000) ; // Fref_TF = Fref_TG*1000
52c99bda 3103
3935c254 3104 Fvco = (state->TG_LO/10000) * divider_val * Fref_TG; //Fvco = Fvco/10
52c99bda
ST		 3105
3106 tg_lo = (((Fmax/10 - Fvco)/100)*32) / ((Fmax-Fmin)/1000)+8;
3107
3108 //below equation is same as above but much harder to debug.
3935c254 3109 //tg_lo = ( ((Fmax/10000 * Xtal_Int)/100) - ((state->TG_LO/10000)*divider_val*(state->Fxtal/10000)/100) )*32/((Fmax-Fmin)/10000 * Xtal_Int/100) + 8 ;
52c99bda
ST		 3110
3111
3935c254 3112 status += MXL_ControlWrite(fe, TG_VCO_BIAS , tg_lo) ;
52c99bda
ST		 3113
3114
3115
3116 //add for 2.6.5
3117 //Special setting for QAM
3935c254 3118 if(state->Mod_Type == MXL_QAM)
52c99bda 3119 {
3935c254
ST		 3120 if(state->RF_IN < 680000000)
3121 status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 3) ;
52c99bda 3122 else
3935c254 3123 status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 2) ;
52c99bda
ST		 3124 }
3125
3126
3127 //remove 20.48MHz setting for 2.6.10
3128
3129 //
3130 // Off Chip Tracking Filter Control
3131 //
85d220d0 3132 if (state->TF_Type == MXL_TF_OFF) // Tracking Filter Off State; turn off all the banks
52c99bda 3133 {
3935c254
ST		 3134 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0) ;
3135 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ;
52c99bda 3136
3935c254
ST		 3137 status += MXL_SetGPIO(fe, 3, 1) ; // turn off Bank 1
3138 status += MXL_SetGPIO(fe, 1, 1) ; // turn off Bank 2
3139 status += MXL_SetGPIO(fe, 4, 1) ; // turn off Bank 3
52c99bda
ST		 3140 }
3141
85d220d0 3142 if (state->TF_Type == MXL_TF_C) // Tracking Filter type C
52c99bda 3143 {
3935c254
ST		 3144 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1) ;
3145 status += MXL_ControlWrite(fe, DAC_DIN_A, 0) ;
52c99bda 3146
3935c254 3147 if (state->RF_IN >= 43000000 && state->RF_IN < 150000000)
52c99bda
ST		 3148 {
3149
3935c254
ST		 3150 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0) ; // Bank4 Off
3151 status += MXL_ControlWrite(fe, DAC_DIN_B, 0) ;
3152 status += MXL_SetGPIO(fe, 3, 0) ; // Bank1 On
3153 status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off
3154 status += MXL_SetGPIO(fe, 4, 1) ; // Bank3 Off
52c99bda 3155 }
3935c254 3156 if (state->RF_IN >= 150000000 && state->RF_IN < 280000000)
52c99bda 3157 {
3935c254
ST		 3158 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0) ; // Bank4 Off
3159 status += MXL_ControlWrite(fe, DAC_DIN_B, 0) ;
3160 status += MXL_SetGPIO(fe, 3, 1) ; // Bank1 Off
3161 status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On
3162 status += MXL_SetGPIO(fe, 4, 1) ; // Bank3 Off
52c99bda 3163 }
3935c254 3164 if (state->RF_IN >= 280000000 && state->RF_IN < 360000000)
52c99bda 3165 {
3935c254
ST		 3166 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0) ; // Bank4 Off
3167 status += MXL_ControlWrite(fe, DAC_DIN_B, 0) ;
3168 status += MXL_SetGPIO(fe, 3, 1) ; // Bank1 Off
3169 status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On
3170 status += MXL_SetGPIO(fe, 4, 0) ; // Bank3 On
52c99bda 3171 }
3935c254 3172 if (state->RF_IN >= 360000000 && state->RF_IN < 560000000)
52c99bda 3173 {
3935c254
ST		 3174 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0) ; // Bank4 Off
3175 status += MXL_ControlWrite(fe, DAC_DIN_B, 0) ;
3176 status += MXL_SetGPIO(fe, 3, 1) ; // Bank1 Off
3177 status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off
3178 status += MXL_SetGPIO(fe, 4, 0) ; // Bank3 On
52c99bda 3179 }
3935c254 3180 if (state->RF_IN >= 560000000 && state->RF_IN < 580000000)
52c99bda 3181 {
3935c254
ST		 3182 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1) ; // Bank4 On
3183 status += MXL_ControlWrite(fe, DAC_DIN_B, 29) ;
3184 status += MXL_SetGPIO(fe, 3, 1) ; // Bank1 Off
3185 status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off
3186 status += MXL_SetGPIO(fe, 4, 0) ; // Bank3 On
52c99bda 3187 }
3935c254 3188 if (state->RF_IN >= 580000000 && state->RF_IN < 630000000)
52c99bda 3189 {
3935c254
ST		 3190 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1) ; // Bank4 On
3191 status += MXL_ControlWrite(fe, DAC_DIN_B, 0) ;
3192 status += MXL_SetGPIO(fe, 3, 1) ; // Bank1 Off
3193 status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off
3194 status += MXL_SetGPIO(fe, 4, 0) ; // Bank3 On
52c99bda 3195 }
3935c254 3196 if (state->RF_IN >= 630000000 && state->RF_IN < 700000000)
52c99bda 3197 {
3935c254
ST		 3198 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1) ; // Bank4 On
3199 status += MXL_ControlWrite(fe, DAC_DIN_B, 16) ;
3200 status += MXL_SetGPIO(fe, 3, 1) ; // Bank1 Off
3201 status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off
3202 status += MXL_SetGPIO(fe, 4, 1) ; // Bank3 Off
52c99bda 3203 }
3935c254 3204 if (state->RF_IN >= 700000000 && state->RF_IN < 760000000)
52c99bda 3205 {
3935c254
ST		 3206 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1) ; // Bank4 On
3207 status += MXL_ControlWrite(fe, DAC_DIN_B, 7) ;
3208 status += MXL_SetGPIO(fe, 3, 1) ; // Bank1 Off
3209 status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off
3210 status += MXL_SetGPIO(fe, 4, 1) ; // Bank3 Off
52c99bda 3211 }
3935c254 3212 if (state->RF_IN >= 760000000 && state->RF_IN <= 900000000)
52c99bda 3213 {
3935c254
ST		 3214 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1) ; // Bank4 On
3215 status += MXL_ControlWrite(fe, DAC_DIN_B, 0) ;
3216 status += MXL_SetGPIO(fe, 3, 1) ; // Bank1 Off
3217 status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off
3218 status += MXL_SetGPIO(fe, 4, 1) ; // Bank3 Off
52c99bda
ST		 3219 }
3220 }
3221
85d220d0 3222 if (state->TF_Type == MXL_TF_C_H) // Tracking Filter type C-H for Hauppauge only
52c99bda 3223 {
3935c254 3224 status += MXL_ControlWrite(fe, DAC_DIN_A, 0) ;
52c99bda 3225
3935c254 3226 if (state->RF_IN >= 43000000 && state->RF_IN < 150000000)
52c99bda
ST		 3227 {
3228
3935c254
ST		 3229 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0) ; // Bank4 Off
3230 status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 On
3231 status += MXL_SetGPIO(fe, 3, 1) ; // Bank2 Off
3232 status += MXL_SetGPIO(fe, 1, 1) ; // Bank3 Off
52c99bda 3233 }
3935c254 3234 if (state->RF_IN >= 150000000 && state->RF_IN < 280000000)
52c99bda 3235 {
3935c254
ST		 3236 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0) ; // Bank4 Off
3237 status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off
3238 status += MXL_SetGPIO(fe, 3, 0) ; // Bank2 On
3239 status += MXL_SetGPIO(fe, 1, 1) ; // Bank3 Off
52c99bda 3240 }
3935c254 3241 if (state->RF_IN >= 280000000 && state->RF_IN < 360000000)
52c99bda 3242 {
3935c254
ST		 3243 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0) ; // Bank4 Off
3244 status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off
3245 status += MXL_SetGPIO(fe, 3, 0) ; // Bank2 On
3246 status += MXL_SetGPIO(fe, 1, 0) ; // Bank3 On
52c99bda 3247 }
3935c254 3248 if (state->RF_IN >= 360000000 && state->RF_IN < 560000000)
52c99bda 3249 {
3935c254
ST		 3250 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0) ; // Bank4 Off
3251 status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off
3252 status += MXL_SetGPIO(fe, 3, 1) ; // Bank2 Off
3253 status += MXL_SetGPIO(fe, 1, 0) ; // Bank3 On
52c99bda 3254 }
3935c254 3255 if (state->RF_IN >= 560000000 && state->RF_IN < 580000000)
52c99bda 3256 {
3935c254
ST		 3257 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1) ; // Bank4 On
3258 status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off
3259 status += MXL_SetGPIO(fe, 3, 1) ; // Bank2 Off
3260 status += MXL_SetGPIO(fe, 1, 0) ; // Bank3 On
52c99bda 3261 }
3935c254 3262 if (state->RF_IN >= 580000000 && state->RF_IN < 630000000)
52c99bda 3263 {
3935c254
ST		 3264 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1) ; // Bank4 On
3265 status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off
3266 status += MXL_SetGPIO(fe, 3, 1) ; // Bank2 Off
3267 status += MXL_SetGPIO(fe, 1, 0) ; // Bank3 On
52c99bda 3268 }
3935c254 3269 if (state->RF_IN >= 630000000 && state->RF_IN < 700000000)
52c99bda 3270 {
3935c254
ST		 3271 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1) ; // Bank4 On
3272 status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off
3273 status += MXL_SetGPIO(fe, 3, 1) ; // Bank2 Off
3274 status += MXL_SetGPIO(fe, 1, 1) ; // Bank3 Off
52c99bda 3275 }
3935c254 3276 if (state->RF_IN >= 700000000 && state->RF_IN < 760000000)
52c99bda 3277 {
3935c254
ST		 3278 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1) ; // Bank4 On
3279 status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off
3280 status += MXL_SetGPIO(fe, 3, 1) ; // Bank2 Off
3281 status += MXL_SetGPIO(fe, 1, 1) ; // Bank3 Off
52c99bda 3282 }
3935c254 3283 if (state->RF_IN >= 760000000 && state->RF_IN <= 900000000)
52c99bda 3284 {
3935c254
ST		 3285 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1) ; // Bank4 On
3286 status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off
3287 status += MXL_SetGPIO(fe, 3, 1) ; // Bank2 Off
3288 status += MXL_SetGPIO(fe, 1, 1) ; // Bank3 Off
52c99bda
ST		 3289 }
3290 }
3291
85d220d0 3292 if (state->TF_Type == MXL_TF_D) // Tracking Filter type D
52c99bda 3293 {
3935c254 3294 status += MXL_ControlWrite(fe, DAC_DIN_B, 0) ;
52c99bda 3295
3935c254 3296 if (state->RF_IN >= 43000000 && state->RF_IN < 174000000)
52c99bda
ST		 3297 {
3298
3935c254
ST		 3299 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off
3300 status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 On
3301 status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off
3302 status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off
52c99bda 3303 }
3935c254 3304 if (state->RF_IN >= 174000000 && state->RF_IN < 250000000)
52c99bda 3305 {
3935c254
ST		 3306 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off
3307 status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 On
3308 status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On
3309 status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off
52c99bda 3310 }
3935c254 3311 if (state->RF_IN >= 250000000 && state->RF_IN < 310000000)
52c99bda 3312 {
3935c254
ST		 3313 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off
3314 status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off
3315 status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On
3316 status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off
52c99bda 3317 }
3935c254 3318 if (state->RF_IN >= 310000000 && state->RF_IN < 360000000)
52c99bda 3319 {
3935c254
ST		 3320 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off
3321 status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off
3322 status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On
3323 status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On
52c99bda 3324 }
3935c254 3325 if (state->RF_IN >= 360000000 && state->RF_IN < 470000000)
52c99bda 3326 {
3935c254
ST		 3327 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off
3328 status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off
3329 status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off
3330 status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On
52c99bda 3331 }
3935c254 3332 if (state->RF_IN >= 470000000 && state->RF_IN < 640000000)
52c99bda 3333 {
3935c254
ST		 3334 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1) ; // Bank4 On
3335 status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off
3336 status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off
3337 status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On
52c99bda 3338 }
3935c254 3339 if (state->RF_IN >= 640000000 && state->RF_IN <= 900000000)
52c99bda 3340 {
3935c254
ST		 3341 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1) ; // Bank4 On
3342 status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off
3343 status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off
3344 status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off
52c99bda
ST		 3345 }
3346 }
3347
3348
85d220d0 3349 if (state->TF_Type == MXL_TF_D_L) // Tracking Filter type D-L for Lumanate ONLY change for 2.6.3
52c99bda 3350 {
3935c254 3351 status += MXL_ControlWrite(fe, DAC_DIN_A, 0) ;
52c99bda 3352
a8214d48 3353 // if UHF and terrestrial => Turn off Tracking Filter
3935c254 3354 if (state->RF_IN >= 471000000 && (state->RF_IN - 471000000)%6000000 != 0)
52c99bda
ST		 3355 {
3356 // Turn off all the banks
3935c254
ST		 3357 status += MXL_SetGPIO(fe, 3, 1) ;
3358 status += MXL_SetGPIO(fe, 1, 1) ;
3359 status += MXL_SetGPIO(fe, 4, 1) ;
3360 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0) ;
52c99bda 3361
3935c254 3362 status += MXL_ControlWrite(fe, AGC_IF, 10) ;
52c99bda
ST		 3363 }
3364
3365 else // if VHF or cable => Turn on Tracking Filter
3366 {
3935c254 3367 if (state->RF_IN >= 43000000 && state->RF_IN < 140000000)
52c99bda
ST		 3368 {
3369
3935c254
ST		 3370 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0) ; // Bank4 Off
3371 status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 On
3372 status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off
3373 status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 Off
52c99bda 3374 }
3935c254 3375 if (state->RF_IN >= 140000000 && state->RF_IN < 240000000)
52c99bda 3376 {
3935c254
ST		 3377 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0) ; // Bank4 Off
3378 status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 On
3379 status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On
3380 status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 Off
52c99bda 3381 }
3935c254 3382 if (state->RF_IN >= 240000000 && state->RF_IN < 340000000)
52c99bda 3383 {
3935c254
ST		 3384 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0) ; // Bank4 Off
3385 status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 Off
3386 status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 On
3387 status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 Off
52c99bda 3388 }
3935c254 3389 if (state->RF_IN >= 340000000 && state->RF_IN < 430000000)
52c99bda 3390 {
3935c254
ST		 3391 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0) ; // Bank4 Off
3392 status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 Off
3393 status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On
3394 status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 On
52c99bda 3395 }
3935c254 3396 if (state->RF_IN >= 430000000 && state->RF_IN < 470000000)
52c99bda 3397 {
3935c254
ST		 3398 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1) ; // Bank4 Off
3399 status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off
3400 status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 Off
3401 status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 On
52c99bda 3402 }
3935c254 3403 if (state->RF_IN >= 470000000 && state->RF_IN < 570000000)
52c99bda 3404 {
3935c254
ST		 3405 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1) ; // Bank4 On
3406 status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 Off
3407 status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 Off
3408 status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 On
52c99bda 3409 }
3935c254 3410 if (state->RF_IN >= 570000000 && state->RF_IN < 620000000)
52c99bda 3411 {
3935c254
ST		 3412 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0) ; // Bank4 On
3413 status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 Off
3414 status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off
3415 status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Offq
52c99bda 3416 }
3935c254 3417 if (state->RF_IN >= 620000000 && state->RF_IN < 760000000)
52c99bda 3418 {
3935c254
ST		 3419 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1) ; // Bank4 On
3420 status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 Off
3421 status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off
3422 status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off
52c99bda 3423 }
3935c254 3424 if (state->RF_IN >= 760000000 && state->RF_IN <= 900000000)
52c99bda 3425 {
3935c254
ST		 3426 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1) ; // Bank4 On
3427 status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off
3428 status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off
3429 status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off
52c99bda
ST		 3430 }
3431 }
3432 }
3433
85d220d0 3434 if (state->TF_Type == MXL_TF_E) // Tracking Filter type E
52c99bda 3435 {
3935c254 3436 status += MXL_ControlWrite(fe, DAC_DIN_B, 0) ;
52c99bda 3437
3935c254 3438 if (state->RF_IN >= 43000000 && state->RF_IN < 174000000)
52c99bda
ST		 3439 {
3440
3935c254
ST		 3441 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off
3442 status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 On
3443 status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off
3444 status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off
52c99bda 3445 }
3935c254 3446 if (state->RF_IN >= 174000000 && state->RF_IN < 250000000)
52c99bda 3447 {
3935c254
ST		 3448 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off
3449 status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 On
3450 status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On
3451 status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off
52c99bda 3452 }
3935c254 3453 if (state->RF_IN >= 250000000 && state->RF_IN < 310000000)
52c99bda 3454 {
3935c254
ST		 3455 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off
3456 status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off
3457 status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On
3458 status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off
52c99bda 3459 }
3935c254 3460 if (state->RF_IN >= 310000000 && state->RF_IN < 360000000)
52c99bda 3461 {
3935c254
ST		 3462 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off
3463 status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off
3464 status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On
3465 status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On
52c99bda 3466 }
3935c254 3467 if (state->RF_IN >= 360000000 && state->RF_IN < 470000000)
52c99bda 3468 {
3935c254
ST		 3469 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off
3470 status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off
3471 status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off
3472 status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On
52c99bda 3473 }
3935c254 3474 if (state->RF_IN >= 470000000 && state->RF_IN < 640000000)
52c99bda 3475 {
3935c254
ST		 3476 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1) ; // Bank4 On
3477 status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off
3478 status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off
3479 status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On
52c99bda 3480 }
3935c254 3481 if (state->RF_IN >= 640000000 && state->RF_IN <= 900000000)
52c99bda 3482 {
3935c254
ST		 3483 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1) ; // Bank4 On
3484 status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off
3485 status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off
3486 status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off
52c99bda
ST		 3487 }
3488 }
3489
85d220d0 3490 if (state->TF_Type == MXL_TF_F) // Tracking Filter type F
52c99bda 3491 {
3935c254 3492 status += MXL_ControlWrite(fe, DAC_DIN_B, 0) ;
52c99bda 3493
3935c254 3494 if (state->RF_IN >= 43000000 && state->RF_IN < 160000000)
52c99bda
ST		 3495 {
3496
3935c254
ST		 3497 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off
3498 status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 On
3499 status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off
3500 status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off
52c99bda 3501 }
3935c254 3502 if (state->RF_IN >= 160000000 && state->RF_IN < 210000000)
52c99bda 3503 {
3935c254
ST		 3504 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off
3505 status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 On
3506 status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On
3507 status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off
52c99bda 3508 }
3935c254 3509 if (state->RF_IN >= 210000000 && state->RF_IN < 300000000)
52c99bda 3510 {
3935c254
ST		 3511 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off
3512 status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off
3513 status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On
3514 status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off
52c99bda 3515 }
3935c254 3516 if (state->RF_IN >= 300000000 && state->RF_IN < 390000000)
52c99bda 3517 {
3935c254
ST		 3518 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off
3519 status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off
3520 status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On
3521 status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On
52c99bda 3522 }
3935c254 3523 if (state->RF_IN >= 390000000 && state->RF_IN < 515000000)
52c99bda 3524 {
3935c254
ST		 3525 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off
3526 status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off
3527 status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off
3528 status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On
52c99bda 3529 }
3935c254 3530 if (state->RF_IN >= 515000000 && state->RF_IN < 650000000)
52c99bda 3531 {
3935c254
ST		 3532 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1) ; // Bank4 On
3533 status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off
3534 status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off
3535 status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On
52c99bda 3536 }
3935c254 3537 if (state->RF_IN >= 650000000 && state->RF_IN <= 900000000)
52c99bda 3538 {
3935c254
ST		 3539 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1) ; // Bank4 On
3540 status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off
3541 status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off
3542 status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off
52c99bda
ST		 3543 }
3544 }
3545
85d220d0 3546 if (state->TF_Type == MXL_TF_E_2) // Tracking Filter type E_2
52c99bda 3547 {
3935c254 3548 status += MXL_ControlWrite(fe, DAC_DIN_B, 0) ;
52c99bda 3549
3935c254 3550 if (state->RF_IN >= 43000000 && state->RF_IN < 174000000)
52c99bda
ST		 3551 {
3552
3935c254
ST		 3553 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off
3554 status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 On
3555 status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off
3556 status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off
52c99bda 3557 }
3935c254 3558 if (state->RF_IN >= 174000000 && state->RF_IN < 250000000)
52c99bda 3559 {
3935c254
ST		 3560 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off
3561 status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 On
3562 status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On
3563 status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off
52c99bda 3564 }
3935c254 3565 if (state->RF_IN >= 250000000 && state->RF_IN < 350000000)
52c99bda 3566 {
3935c254
ST		 3567 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off
3568 status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off
3569 status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On
3570 status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off
52c99bda 3571 }
3935c254 3572 if (state->RF_IN >= 350000000 && state->RF_IN < 400000000)
52c99bda 3573 {
3935c254
ST		 3574 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off
3575 status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off
3576 status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On
3577 status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On
52c99bda 3578 }
3935c254 3579 if (state->RF_IN >= 400000000 && state->RF_IN < 570000000)
52c99bda 3580 {
3935c254
ST		 3581 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off
3582 status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off
3583 status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off
3584 status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On
52c99bda 3585 }
3935c254 3586 if (state->RF_IN >= 570000000 && state->RF_IN < 770000000)
52c99bda 3587 {
3935c254
ST		 3588 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1) ; // Bank4 On
3589 status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off
3590 status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off
3591 status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On
52c99bda 3592 }
3935c254 3593 if (state->RF_IN >= 770000000 && state->RF_IN <= 900000000)
52c99bda 3594 {
3935c254
ST		 3595 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1) ; // Bank4 On
3596 status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off
3597 status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off
3598 status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off
52c99bda
ST		 3599 }
3600 }
3601
85d220d0 3602 if (state->TF_Type == MXL_TF_G) // Tracking Filter type G add for v2.6.8
52c99bda 3603 {
3935c254 3604 status += MXL_ControlWrite(fe, DAC_DIN_B, 0) ;
52c99bda 3605
3935c254 3606 if (state->RF_IN >= 50000000 && state->RF_IN < 190000000)
52c99bda
ST		 3607 {
3608
3935c254
ST		 3609 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off
3610 status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 On
3611 status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off
3612 status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off
52c99bda 3613 }
3935c254 3614 if (state->RF_IN >= 190000000 && state->RF_IN < 280000000)
52c99bda 3615 {
3935c254
ST		 3616 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off
3617 status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 On
3618 status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On
3619 status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off
52c99bda 3620 }
3935c254 3621 if (state->RF_IN >= 280000000 && state->RF_IN < 350000000)
52c99bda 3622 {
3935c254
ST		 3623 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off
3624 status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off
3625 status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On
3626 status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off
52c99bda 3627 }
3935c254 3628 if (state->RF_IN >= 350000000 && state->RF_IN < 400000000)
52c99bda 3629 {
3935c254
ST		 3630 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off
3631 status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off
3632 status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On
3633 status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On
52c99bda 3634 }
3935c254 3635 if (state->RF_IN >= 400000000 && state->RF_IN < 470000000) //modified for 2.6.11
52c99bda 3636 {
3935c254
ST		 3637 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1) ; // Bank4 On
3638 status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 On
3639 status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 Off
3640 status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off
52c99bda 3641 }
3935c254 3642 if (state->RF_IN >= 470000000 && state->RF_IN < 640000000)
52c99bda 3643 {
3935c254
ST		 3644 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off
3645 status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off
3646 status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off
3647 status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On
52c99bda 3648 }
3935c254 3649 if (state->RF_IN >= 640000000 && state->RF_IN < 820000000)
52c99bda 3650 {
3935c254
ST		 3651 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1) ; // Bank4 On
3652 status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off
3653 status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off
3654 status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On
52c99bda 3655 }
3935c254 3656 if (state->RF_IN >= 820000000 && state->RF_IN <= 900000000)
52c99bda 3657 {
3935c254
ST		 3658 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1) ; // Bank4 On
3659 status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off
3660 status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off
3661 status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off
52c99bda
ST		 3662 }
3663 }
3664
85d220d0 3665 if (state->TF_Type == MXL_TF_E_NA) // Tracking Filter type E-NA for Empia ONLY change for 2.6.8
52c99bda 3666 {
3935c254 3667 status += MXL_ControlWrite(fe, DAC_DIN_B, 0) ;
52c99bda 3668
a8214d48 3669 // if UHF and terrestrial=> Turn off Tracking Filter
3935c254 3670 if (state->RF_IN >= 471000000 && (state->RF_IN - 471000000)%6000000 != 0)
52c99bda
ST		 3671 {
3672 // Turn off all the banks
3935c254
ST		 3673 status += MXL_SetGPIO(fe, 3, 1) ;
3674 status += MXL_SetGPIO(fe, 1, 1) ;
3675 status += MXL_SetGPIO(fe, 4, 1) ;
3676 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ;
52c99bda
ST		 3677
3678 //2.6.12
3679 //Turn on RSSI
3935c254
ST		 3680 status += MXL_ControlWrite(fe, SEQ_EXTSYNTHCALIF, 1) ;
3681 status += MXL_ControlWrite(fe, SEQ_EXTDCCAL, 1) ;
3682 status += MXL_ControlWrite(fe, AGC_EN_RSSI, 1) ;
3683 status += MXL_ControlWrite(fe, RFA_ENCLKRFAGC, 1) ;
52c99bda
ST		 3684
3685 // RSSI reference point
3935c254
ST		 3686 status += MXL_ControlWrite(fe, RFA_RSSI_REFH, 5) ;
3687 status += MXL_ControlWrite(fe, RFA_RSSI_REF, 3) ;
3688 status += MXL_ControlWrite(fe, RFA_RSSI_REFL, 2) ;
52c99bda
ST		 3689
3690
3935c254 3691 //status += MXL_ControlWrite(fe, AGC_IF, 10) ; //doesn't matter since RSSI is turn on
52c99bda
ST		 3692
3693 //following parameter is from analog OTA mode, can be change to seek better performance
3935c254 3694 status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 3) ;
52c99bda
ST		 3695 }
3696
3697 else //if VHF or Cable => Turn on Tracking Filter
3698 {
3699 //2.6.12
3700 //Turn off RSSI
3935c254 3701 status += MXL_ControlWrite(fe, AGC_EN_RSSI, 0) ;
52c99bda
ST		 3702
3703 //change back from above condition
3935c254 3704 status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 5) ;
52c99bda
ST		 3705
3706
3935c254 3707 if (state->RF_IN >= 43000000 && state->RF_IN < 174000000)
52c99bda
ST		 3708 {
3709
3935c254
ST		 3710 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off
3711 status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 On
3712 status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off
3713 status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off
52c99bda 3714 }
3935c254 3715 if (state->RF_IN >= 174000000 && state->RF_IN < 250000000)
52c99bda 3716 {
3935c254
ST		 3717 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off
3718 status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 On
3719 status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On
3720 status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off
52c99bda 3721 }
3935c254 3722 if (state->RF_IN >= 250000000 && state->RF_IN < 350000000)
52c99bda 3723 {
3935c254
ST		 3724 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off
3725 status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off
3726 status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On
3727 status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off
52c99bda 3728 }
3935c254 3729 if (state->RF_IN >= 350000000 && state->RF_IN < 400000000)
52c99bda 3730 {
3935c254
ST		 3731 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off
3732 status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off
3733 status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On
3734 status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On
52c99bda 3735 }
3935c254 3736 if (state->RF_IN >= 400000000 && state->RF_IN < 570000000)
52c99bda 3737 {
3935c254
ST		 3738 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off
3739 status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off
3740 status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off
3741 status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On
52c99bda 3742 }
3935c254 3743 if (state->RF_IN >= 570000000 && state->RF_IN < 770000000)
52c99bda 3744 {
3935c254
ST		 3745 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1) ; // Bank4 On
3746 status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off
3747 status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off
3748 status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On
52c99bda 3749 }
3935c254 3750 if (state->RF_IN >= 770000000 && state->RF_IN <= 900000000)
52c99bda 3751 {
3935c254
ST		 3752 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1) ; // Bank4 On
3753 status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off
3754 status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off
3755 status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off
52c99bda
ST		 3756 }
3757 }
3758 }
3759 return status ;
3760}
3761
3935c254
ST		 3762// DONE
3763u16 MXL_SetGPIO(struct dvb_frontend *fe, u8 GPIO_Num, u8 GPIO_Val)
52c99bda 3764{
3935c254 3765 u16 status = 0;
52c99bda
ST		 3766
3767 if (GPIO_Num == 1)
3935c254
ST		 3768 status += MXL_ControlWrite(fe, GPIO_1B, GPIO_Val ? 0 : 1);
3769
3770 /* GPIO2 is not available */
3771
3772 if (GPIO_Num == 3) {
52c99bda 3773 if (GPIO_Val == 1) {
3935c254
ST		 3774 status += MXL_ControlWrite(fe, GPIO_3, 0);
3775 status += MXL_ControlWrite(fe, GPIO_3B, 0);
52c99bda
ST		 3776 }
3777 if (GPIO_Val == 0) {
3935c254
ST		 3778 status += MXL_ControlWrite(fe, GPIO_3, 1);
3779 status += MXL_ControlWrite(fe, GPIO_3B, 1);
52c99bda 3780 }
3935c254
ST		 3781 if (GPIO_Val == 3) { /* tri-state */
3782 status += MXL_ControlWrite(fe, GPIO_3, 0);
3783 status += MXL_ControlWrite(fe, GPIO_3B, 1);
52c99bda
ST		 3784 }
3785 }
3935c254 3786 if (GPIO_Num == 4) {
52c99bda 3787 if (GPIO_Val == 1) {
3935c254
ST		 3788 status += MXL_ControlWrite(fe, GPIO_4, 0);
3789 status += MXL_ControlWrite(fe, GPIO_4B, 0);
52c99bda
ST		 3790 }
3791 if (GPIO_Val == 0) {
3935c254
ST		 3792 status += MXL_ControlWrite(fe, GPIO_4, 1);
3793 status += MXL_ControlWrite(fe, GPIO_4B, 1);
52c99bda 3794 }
3935c254
ST		 3795 if (GPIO_Val == 3) { /* tri-state */
3796 status += MXL_ControlWrite(fe, GPIO_4, 0);
3797 status += MXL_ControlWrite(fe, GPIO_4B, 1);
52c99bda
ST		 3798 }
3799 }
3800
3935c254 3801 return status;
52c99bda
ST		 3802}
3803
3804///////////////////////////////////////////////////////////////////////////////
3805// //
3806// Function: MXL_ControlWrite //
3807// //
3808// Description: Update control name value //
3809// //
3810// Globals: //
3811// NONE //
3812// //
3813// Functions used: //
3814// MXL_ControlWrite( Tuner, controlName, value, Group ) //
3815// //
3816// Inputs: //
3817// Tuner : Tuner structure //
3818// ControlName : Control name to be updated //
3819// value : Value to be written //
3820// //
3821// Outputs: //
3822// Tuner : Tuner structure defined at higher level //
3823// //
3824// Return: //
3825// 0 : Successful write //
3826// >0 : Value exceed maximum allowed for control number //
3827// //
3828///////////////////////////////////////////////////////////////////////////////
3935c254
ST		 3829// DONE
3830u16 MXL_ControlWrite(struct dvb_frontend *fe, u16 ControlNum, u32 value)
52c99bda 3831{
3935c254
ST		 3832 u16 status = 0;
3833
3834 /* Will write ALL Matching Control Name */
85d220d0
ST		 3835 status += MXL_ControlWrite_Group(fe, ControlNum, value, 1); /* Write Matching INIT Control */
3836 status += MXL_ControlWrite_Group(fe, ControlNum, value, 2); /* Write Matching CH Control */
52c99bda 3837#ifdef _MXL_INTERNAL
85d220d0 3838 status += MXL_ControlWrite_Group(fe, ControlNum, value, 3); /* Write Matching MXL Control */
52c99bda 3839#endif
3935c254 3840 return status;
52c99bda
ST		 3841}
3842
3843///////////////////////////////////////////////////////////////////////////////
3844// //
3845// Function: MXL_ControlWrite //
3846// //
3847// Description: Update control name value //
3848// //
3849// Globals: //
3850// NONE //
3851// //
3852// Functions used: //
3853// strcmp //
3854// //
3855// Inputs: //
3856// Tuner_struct: structure defined at higher level //
3857// ControlName : Control Name //
3858// value : Value Assigned to Control Name //
3859// controlGroup : Control Register Group //
3860// //
3861// Outputs: //
3862// NONE //
3863// //
3864// Return: //
3865// 0 : Successful write //
3866// 1 : Value exceed maximum allowed for control name //
3867// 2 : Control name not found //
3868// //
3869///////////////////////////////////////////////////////////////////////////////
3935c254
ST		 3870// DONE
3871u16 MXL_ControlWrite_Group(struct dvb_frontend *fe, u16 controlNum, u32 value, u16 controlGroup)
52c99bda 3872{
85d220d0 3873 struct mxl5005s_state *state = fe->tuner_priv;
3935c254
ST		 3874 u16 i, j, k;
3875 u32 highLimit;
3876 u32 ctrlVal;
52c99bda 3877
3935c254
ST		 3878 if (controlGroup == 1) /* Initial Control */ {
3879
3880 for (i = 0; i < state->Init_Ctrl_Num; i++) {
3881
3882 if (controlNum == state->Init_Ctrl[i].Ctrl_Num) {
3883
3884 highLimit = 1 << state->Init_Ctrl[i].size;
3885 if (value < highLimit) {
3886 for (j = 0; j < state->Init_Ctrl[i].size; j++) {
3887 state->Init_Ctrl[i].val[j] = (u8)((value >> j) & 0x01);
3888 MXL_RegWriteBit(fe, (u8)(state->Init_Ctrl[i].addr[j]),
3889 (u8)(state->Init_Ctrl[i].bit[j]),
3890 (u8)((value>>j) & 0x01) );
52c99bda 3891 }
3935c254
ST		 3892 ctrlVal = 0;
3893 for (k = 0; k < state->Init_Ctrl[i].size; k++)
3894 ctrlVal += state->Init_Ctrl[i].val[k] * (1 << k);
52c99bda
ST		 3895 }
3896 else
3935c254 3897 return -1;
52c99bda
ST		 3898 }
3899 }
3900 }
3935c254
ST		 3901 if (controlGroup == 2) /* Chan change Control */ {
3902
3903 for (i = 0; i < state->CH_Ctrl_Num; i++) {
3904
3905 if (controlNum == state->CH_Ctrl[i].Ctrl_Num ) {
3906
3907 highLimit = 1 << state->CH_Ctrl[i].size;
3908 if (value < highLimit) {
3909 for (j = 0; j < state->CH_Ctrl[i].size; j++) {
3910 state->CH_Ctrl[i].val[j] = (u8)((value >> j) & 0x01);
3911 MXL_RegWriteBit(fe, (u8)(state->CH_Ctrl[i].addr[j]),
3912 (u8)(state->CH_Ctrl[i].bit[j]),
3913 (u8)((value>>j) & 0x01) );
52c99bda 3914 }
3935c254
ST		 3915 ctrlVal = 0;
3916 for (k = 0; k < state->CH_Ctrl[i].size; k++)
3917 ctrlVal += state->CH_Ctrl[i].val[k] * (1 << k);
52c99bda
ST		 3918 }
3919 else
3935c254 3920 return -1;
52c99bda
ST		 3921 }
3922 }
3923 }
3924#ifdef _MXL_INTERNAL
3935c254
ST		 3925 if (controlGroup == 3) /* Maxlinear Control */ {
3926
3927 for (i = 0; i < state->MXL_Ctrl_Num; i++) {
3928
3929 if (controlNum == state->MXL_Ctrl[i].Ctrl_Num ) {
3930
3931 highLimit = (1 << state->MXL_Ctrl[i].size) ;
3932 if (value < highLimit) {
3933 for (j = 0; j < state->MXL_Ctrl[i].size; j++) {
3934 state->MXL_Ctrl[i].val[j] = (u8)((value >> j) & 0x01);
3935 MXL_RegWriteBit(fe, (u8)(state->MXL_Ctrl[i].addr[j]),
3936 (u8)(state->MXL_Ctrl[i].bit[j]),
3937 (u8)((value>>j) & 0x01) );
52c99bda 3938 }
3935c254
ST		 3939 ctrlVal = 0;
3940 for(k = 0; k < state->MXL_Ctrl[i].size; k++)
3941 ctrlVal += state->MXL_Ctrl[i].val[k] * (1 << k);
52c99bda
ST		 3942 }
3943 else
3935c254 3944 return -1;
52c99bda
ST		 3945 }
3946 }
3947 }
3948#endif
3935c254 3949 return 0 ; /* successful return */
52c99bda
ST		 3950}
3951
3952///////////////////////////////////////////////////////////////////////////////
3953// //
3954// Function: MXL_RegWrite //
3955// //
3956// Description: Update tuner register value //
3957// //
3958// Globals: //
3959// NONE //
3960// //
3961// Functions used: //
3962// NONE //
3963// //
3964// Inputs: //
3965// Tuner_struct: structure defined at higher level //
3966// RegNum : Register address to be assigned a value //
3967// RegVal : Register value to write //
3968// //
3969// Outputs: //
3970// NONE //
3971// //
3972// Return: //
3973// 0 : Successful write //
3974// -1 : Invalid Register Address //
3975// //
3976///////////////////////////////////////////////////////////////////////////////
3935c254
ST		 3977// DONE
3978u16 MXL_RegWrite(struct dvb_frontend *fe, u8 RegNum, u8 RegVal)
52c99bda 3979{
85d220d0 3980 struct mxl5005s_state *state = fe->tuner_priv;
52c99bda
ST		 3981 int i ;
3982
3935c254
ST		 3983 for (i = 0; i < 104; i++) {
3984 if (RegNum == state->TunerRegs[i].Reg_Num) {
3985 state->TunerRegs[i].Reg_Val = RegVal;
3986 return 0;
52c99bda
ST		 3987 }
3988 }
3989
3935c254 3990 return 1;
52c99bda
ST		 3991}
3992
3993///////////////////////////////////////////////////////////////////////////////
3994// //
3995// Function: MXL_RegRead //
3996// //
3997// Description: Retrieve tuner register value //
3998// //
3999// Globals: //
4000// NONE //
4001// //
4002// Functions used: //
4003// NONE //
4004// //
4005// Inputs: //
4006// Tuner_struct: structure defined at higher level //
4007// RegNum : Register address to be assigned a value //
4008// //
4009// Outputs: //
4010// RegVal : Retrieved register value //
4011// //
4012// Return: //
4013// 0 : Successful read //
4014// -1 : Invalid Register Address //
4015// //
4016///////////////////////////////////////////////////////////////////////////////
3935c254
ST		 4017// DONE
4018u16 MXL_RegRead(struct dvb_frontend *fe, u8 RegNum, u8 *RegVal)
52c99bda 4019{
85d220d0 4020 struct mxl5005s_state *state = fe->tuner_priv;
52c99bda
ST		 4021 int i ;
4022
3935c254
ST		 4023 for (i = 0; i < 104; i++) {
4024 if (RegNum == state->TunerRegs[i].Reg_Num ) {
4025 *RegVal = (u8)(state->TunerRegs[i].Reg_Val);
4026 return 0;
52c99bda
ST		 4027 }
4028 }
4029
3935c254 4030 return 1;
52c99bda
ST		 4031}
4032
4033///////////////////////////////////////////////////////////////////////////////
4034// //
4035// Function: MXL_ControlRead //
4036// //
4037// Description: Retrieve the control value based on the control name //
4038// //
4039// Globals: //
4040// NONE //
4041// //
4042// Inputs: //
4043// Tuner_struct : structure defined at higher level //
4044// ControlName : Control Name //
4045// //
4046// Outputs: //
4047// value : returned control value //
4048// //
4049// Return: //
4050// 0 : Successful read //
4051// -1 : Invalid control name //
4052// //
4053///////////////////////////////////////////////////////////////////////////////
3935c254 4054// DONE
85d220d0 4055u16 MXL_ControlRead(struct dvb_frontend *fe, u16 controlNum, u32 *value)
52c99bda 4056{
85d220d0 4057 struct mxl5005s_state *state = fe->tuner_priv;
a8214d48
ST		 4058 u32 ctrlVal ;
4059 u16 i, k ;
52c99bda 4060
3935c254
ST		 4061 for (i = 0; i < state->Init_Ctrl_Num ; i++) {
4062
4063 if (controlNum == state->Init_Ctrl[i].Ctrl_Num) {
4064
4065 ctrlVal = 0;
4066 for (k = 0; k < state->Init_Ctrl[i].size; k++)
4067 ctrlVal += state->Init_Ctrl[i].val[k] * (1 << k);
4068 *value = ctrlVal;
4069 return 0;
52c99bda
ST		 4070 }
4071 }
3935c254
ST		 4072
4073 for (i = 0; i < state->CH_Ctrl_Num ; i++) {
4074
4075 if (controlNum == state->CH_Ctrl[i].Ctrl_Num) {
4076
4077 ctrlVal = 0;
4078 for (k = 0; k < state->CH_Ctrl[i].size; k++)
4079 ctrlVal += state->CH_Ctrl[i].val[k] * (1 << k);
4080 *value = ctrlVal;
4081 return 0;
4082
52c99bda
ST		 4083 }
4084 }
4085
4086#ifdef _MXL_INTERNAL
3935c254
ST		 4087 for (i = 0; i < state->MXL_Ctrl_Num ; i++) {
4088
4089 if (controlNum == state->MXL_Ctrl[i].Ctrl_Num) {
4090
4091 ctrlVal = 0;
4092 for (k = 0; k < state->MXL_Ctrl[i].size; k++)
4093 ctrlVal += state->MXL_Ctrl[i].val[k] * (1<<k);
4094 *value = ctrlVal;
4095 return 0;
4096
52c99bda
ST		 4097 }
4098 }
4099#endif
3935c254 4100 return 1;
52c99bda
ST		 4101}
4102
4103///////////////////////////////////////////////////////////////////////////////
4104// //
4105// Function: MXL_ControlRegRead //
4106// //
4107// Description: Retrieve the register addresses and count related to a //
a8214d48 4108// a specific control name //
52c99bda
ST		 4109// //
4110// Globals: //
4111// NONE //
4112// //
4113// Inputs: //
4114// Tuner_struct : structure defined at higher level //
4115// ControlName : Control Name //
4116// //
4117// Outputs: //
4118// RegNum : returned register address array //
a8214d48 4119// count : returned register count related to a control //
52c99bda
ST		 4120// //
4121// Return: //
4122// 0 : Successful read //
4123// -1 : Invalid control name //
4124// //
4125///////////////////////////////////////////////////////////////////////////////
3935c254
ST		 4126// DONE
4127u16 MXL_ControlRegRead(struct dvb_frontend *fe, u16 controlNum, u8 *RegNum, int * count)
52c99bda 4128{
85d220d0 4129 struct mxl5005s_state *state = fe->tuner_priv;
a8214d48
ST		 4130 u16 i, j, k ;
4131 u16 Count ;
52c99bda 4132
3935c254
ST		 4133 for (i = 0; i < state->Init_Ctrl_Num ; i++) {
4134
4135 if ( controlNum == state->Init_Ctrl[i].Ctrl_Num ) {
4136
4137 Count = 1;
4138 RegNum[0] = (u8)(state->Init_Ctrl[i].addr[0]);
4139
4140 for (k = 1; k < state->Init_Ctrl[i].size; k++) {
4141
4142 for (j = 0; j < Count; j++) {
4143
4144 if (state->Init_Ctrl[i].addr[k] != RegNum[j]) {
4145
4146 Count ++;
4147 RegNum[Count-1] = (u8)(state->Init_Ctrl[i].addr[k]);
52c99bda 4148
52c99bda
ST		 4149 }
4150 }
4151
4152 }
3935c254
ST		 4153 *count = Count;
4154 return 0;
52c99bda
ST		 4155 }
4156 }
3935c254
ST		 4157 for (i = 0; i < state->CH_Ctrl_Num ; i++) {
4158
4159 if ( controlNum == state->CH_Ctrl[i].Ctrl_Num ) {
4160
4161 Count = 1;
4162 RegNum[0] = (u8)(state->CH_Ctrl[i].addr[0]);
4163
4164 for (k = 1; k < state->CH_Ctrl[i].size; k++) {
4165
4166 for (j= 0; j<Count; j++) {
4167
4168 if (state->CH_Ctrl[i].addr[k] != RegNum[j]) {
4169
4170 Count ++;
4171 RegNum[Count-1] = (u8)(state->CH_Ctrl[i].addr[k]);
52c99bda 4172
52c99bda
ST		 4173 }
4174 }
4175 }
3935c254
ST		 4176 *count = Count;
4177 return 0;
52c99bda
ST		 4178 }
4179 }
4180#ifdef _MXL_INTERNAL
3935c254
ST		 4181 for (i = 0; i < state->MXL_Ctrl_Num ; i++) {
4182
4183 if ( controlNum == state->MXL_Ctrl[i].Ctrl_Num ) {
4184
4185 Count = 1;
4186 RegNum[0] = (u8)(state->MXL_Ctrl[i].addr[0]);
4187
4188 for (k = 1; k < state->MXL_Ctrl[i].size; k++) {
4189
4190 for (j = 0; j<Count; j++) {
4191
4192 if (state->MXL_Ctrl[i].addr[k] != RegNum[j]) {
4193
4194 Count ++;
4195 RegNum[Count-1] = (u8)state->MXL_Ctrl[i].addr[k];
52c99bda 4196
52c99bda
ST		 4197 }
4198 }
4199 }
3935c254
ST		 4200 *count = Count;
4201 return 0;
52c99bda
ST		 4202 }
4203 }
4204#endif
3935c254
ST		 4205 *count = 0;
4206 return 1;
52c99bda
ST		 4207}
4208
4209///////////////////////////////////////////////////////////////////////////////
4210// //
4211// Function: MXL_RegWriteBit //
4212// //
4213// Description: Write a register for specified register address, //
4214// register bit and register bit value //
4215// //
4216// Globals: //
4217// NONE //
4218// //
4219// Inputs: //
4220// Tuner_struct : structure defined at higher level //
4221// address : register address //
3935c254 4222// bit : register bit number //
a8214d48 4223// bitVal : register bit value //
52c99bda
ST		 4224// //
4225// Outputs: //
4226// NONE //
4227// //
4228// Return: //
4229// NONE //
4230// //
4231///////////////////////////////////////////////////////////////////////////////
3935c254
ST		 4232// DONE
4233void MXL_RegWriteBit(struct dvb_frontend *fe, u8 address, u8 bit, u8 bitVal)
52c99bda 4234{
85d220d0 4235 struct mxl5005s_state *state = fe->tuner_priv;
52c99bda
ST		 4236 int i ;
4237
a8214d48 4238 const u8 AND_MAP[8] = {
52c99bda
ST		 4239 0xFE, 0xFD, 0xFB, 0xF7,
4240 0xEF, 0xDF, 0xBF, 0x7F } ;
4241
a8214d48 4242 const u8 OR_MAP[8] = {
52c99bda
ST		 4243 0x01, 0x02, 0x04, 0x08,
4244 0x10, 0x20, 0x40, 0x80 } ;
4245
3935c254
ST		 4246 for (i = 0; i < state->TunerRegs_Num; i++) {
4247 if (state->TunerRegs[i].Reg_Num == address) {
52c99bda 4248 if (bitVal)
3935c254 4249 state->TunerRegs[i].Reg_Val |= OR_MAP[bit];
52c99bda 4250 else
3935c254 4251 state->TunerRegs[i].Reg_Val &= AND_MAP[bit];
52c99bda
ST		 4252 break ;
4253 }
4254 }
3935c254 4255}
52c99bda
ST		 4256
4257///////////////////////////////////////////////////////////////////////////////
4258// //
4259// Function: MXL_Ceiling //
4260// //
4261// Description: Complete to closest increment of resolution //
4262// //
4263// Globals: //
4264// NONE //
4265// //
4266// Functions used: //
4267// NONE //
4268// //
4269// Inputs: //
4270// value : Input number to compute //
4271// resolution : Increment step //
4272// //
4273// Outputs: //
4274// NONE //
4275// //
4276// Return: //
4277// Computed value //
4278// //
4279///////////////////////////////////////////////////////////////////////////////
3935c254
ST		 4280// DONE
4281u32 MXL_Ceiling(u32 value, u32 resolution)
52c99bda 4282{
3935c254
ST		 4283 return (value/resolution + (value % resolution > 0 ? 1 : 0));
4284}
52c99bda
ST		 4285
4286//
4287// Retrieve the Initialzation Registers
4288//
3935c254
ST		 4289// DONE
4290u16 MXL_GetInitRegister(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, int *count)
52c99bda 4291{
a8214d48 4292 u16 status = 0;
52c99bda
ST		 4293 int i ;
4294
3935c254
ST		 4295 u8 RegAddr[] = {
4296 11, 12, 13, 22, 32, 43, 44, 53, 56, 59, 73,
4297 76, 77, 91, 134, 135, 137, 147,
4298 156, 166, 167, 168, 25 };
52c99bda 4299
3935c254 4300 *count = sizeof(RegAddr) / sizeof(u8);
52c99bda 4301
3935c254
ST		 4302 status += MXL_BlockInit(fe);
4303
4304 for (i = 0 ; i < *count; i++) {
4305 RegNum[i] = RegAddr[i];
4306 status += MXL_RegRead(fe, RegNum[i], &RegVal[i]);
52c99bda
ST		 4307 }
4308
3935c254 4309 return status;
52c99bda
ST		 4310}
4311
3935c254
ST		 4312// DONE
4313u16 MXL_GetCHRegister(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, int *count)
52c99bda 4314{
a8214d48 4315 u16 status = 0;
52c99bda
ST		 4316 int i ;
4317
4318//add 77, 166, 167, 168 register for 2.6.12
4319#ifdef _MXL_PRODUCTION
a8214d48
ST		 4320 u8 RegAddr[] = {14, 15, 16, 17, 22, 43, 65, 68, 69, 70, 73, 92, 93, 106,
4321 107, 108, 109, 110, 111, 112, 136, 138, 149, 77, 166, 167, 168 } ;
52c99bda 4322#else
a8214d48
ST		 4323 u8 RegAddr[] = {14, 15, 16, 17, 22, 43, 68, 69, 70, 73, 92, 93, 106,
4324 107, 108, 109, 110, 111, 112, 136, 138, 149, 77, 166, 167, 168 } ;
4325 //u8 RegAddr[171];
52c99bda
ST		 4326 //for (i=0; i<=170; i++)
4327 // RegAddr[i] = i;
4328#endif
4329
3935c254 4330 *count = sizeof(RegAddr) / sizeof(u8);
52c99bda 4331
3935c254
ST		 4332 for (i = 0 ; i < *count; i++) {
4333 RegNum[i] = RegAddr[i];
4334 status += MXL_RegRead(fe, RegNum[i], &RegVal[i]);
52c99bda
ST		 4335 }
4336
3935c254 4337 return status;
52c99bda
ST		 4338}
4339
3935c254
ST		 4340// DONE
4341u16 MXL_GetCHRegister_ZeroIF(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, int *count)
52c99bda 4342{
3935c254
ST		 4343 u16 status = 0;
4344 int i;
52c99bda 4345
3935c254 4346 u8 RegAddr[] = {43, 136};
52c99bda 4347
3935c254 4348 *count = sizeof(RegAddr) / sizeof(u8);
52c99bda 4349
3935c254
ST		 4350 for (i = 0; i < *count; i++) {
4351 RegNum[i] = RegAddr[i];
4352 status += MXL_RegRead(fe, RegNum[i], &RegVal[i]);
52c99bda 4353 }
52c99bda 4354
3935c254 4355 return status;
52c99bda
ST		 4356}
4357
3935c254
ST		 4358// DONE
4359u16 MXL_GetCHRegister_LowIF(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, int *count)
52c99bda 4360{
3935c254
ST		 4361 u16 status = 0;
4362 int i;
52c99bda 4363
3935c254 4364 u8 RegAddr[] = { 138 };
52c99bda 4365
3935c254 4366 *count = sizeof(RegAddr) / sizeof(u8);
52c99bda 4367
3935c254
ST		 4368 for (i = 0; i < *count; i++) {
4369 RegNum[i] = RegAddr[i];
4370 status += MXL_RegRead(fe, RegNum[i], &RegVal[i]);
52c99bda 4371 }
52c99bda 4372
3935c254 4373 return status;
52c99bda
ST		 4374}
4375
3935c254 4376// DONE
a8214d48 4377u16 MXL_GetMasterControl(u8 *MasterReg, int state)
52c99bda 4378{
3935c254
ST		 4379 if (state == 1) /* Load_Start */
4380 *MasterReg = 0xF3;
4381 if (state == 2) /* Power_Down */
4382 *MasterReg = 0x41;
4383 if (state == 3) /* Synth_Reset */
4384 *MasterReg = 0xB1;
4385 if (state == 4) /* Seq_Off */
4386 *MasterReg = 0xF1;
4387
4388 return 0;
52c99bda
ST		 4389}
4390
4391#ifdef _MXL_PRODUCTION
3935c254 4392u16 MXL_VCORange_Test(struct dvb_frontend *fe, int VCO_Range)
52c99bda 4393{
85d220d0 4394 struct mxl5005s_state *state = fe->tuner_priv;
a8214d48
ST		 4395 u16 status = 0 ;
4396
4397 if (VCO_Range == 1) {
3935c254
ST		 4398 status += MXL_ControlWrite(fe, RFSYN_EN_DIV, 1);
4399 status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0);
4400 status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0);
4401 status += MXL_ControlWrite(fe, RFSYN_DIVM, 1);
4402 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1);
4403 status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1);
4404 status += MXL_ControlWrite(fe, DN_SEL_FREQ, 0);
4405 if (state->Mode == 0 && state->IF_Mode == 1) /* Analog Low IF Mode */ {
4406 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1);
4407 status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 8);
4408 status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 56);
4409 status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, 180224);
4410 }
4411 if (state->Mode == 0 && state->IF_Mode == 0) /* Analog Zero IF Mode */ {
4412 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1);
4413 status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 8);
4414 status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 56);
4415 status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, 222822);
4416 }
4417 if (state->Mode == 1) /* Digital Mode */ {
4418 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1);
4419 status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 8);
4420 status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 56);
4421 status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, 229376);
a8214d48
ST		 4422 }
4423 }
52c99bda 4424
a8214d48 4425 if (VCO_Range == 2) {
3935c254
ST		 4426 status += MXL_ControlWrite(fe, RFSYN_EN_DIV, 1);
4427 status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0);
4428 status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0);
4429 status += MXL_ControlWrite(fe, RFSYN_DIVM, 1);
4430 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1);
4431 status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1);
4432 status += MXL_ControlWrite(fe, DN_SEL_FREQ, 0);
4433 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1);
4434 status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40);
4435 status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 41);
4436 if (state->Mode == 0 && state->IF_Mode == 1) /* Analog Low IF Mode */ {
4437 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1);
4438 status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40);
4439 status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 42);
4440 status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, 206438);
4441 }
4442 if (state->Mode == 0 && state->IF_Mode == 0) /* Analog Zero IF Mode */ {
4443 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1);
4444 status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40);
4445 status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 42);
4446 status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, 206438);
4447 }
4448 if (state->Mode == 1) /* Digital Mode */ {
4449 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1);
4450 status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40);
4451 status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 41);
4452 status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, 16384);
a8214d48
ST		 4453 }
4454 }
52c99bda 4455
a8214d48 4456 if (VCO_Range == 3) {
3935c254
ST		 4457 status += MXL_ControlWrite(fe, RFSYN_EN_DIV, 1);
4458 status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0);
4459 status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0);
4460 status += MXL_ControlWrite(fe, RFSYN_DIVM, 1);
4461 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1);
4462 status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1);
4463 status += MXL_ControlWrite(fe, DN_SEL_FREQ, 0);
4464 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0);
4465 status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 8);
4466 status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 42);
4467 if (state->Mode == 0 && state->IF_Mode == 1) /* Analog Low IF Mode */ {
4468 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0);
4469 status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 8);
4470 status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 44);
4471 status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, 173670);
4472 }
4473 if (state->Mode == 0 && state->IF_Mode == 0) /* Analog Zero IF Mode */ {
4474 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0);
4475 status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 8);
4476 status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 44);
4477 status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, 173670);
4478 }
4479 if (state->Mode == 1) /* Digital Mode */ {
4480 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0);
4481 status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 8);
4482 status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 42);
4483 status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, 245760);
a8214d48
ST		 4484 }
4485 }
52c99bda 4486
a8214d48 4487 if (VCO_Range == 4) {
3935c254
ST		 4488 status += MXL_ControlWrite(fe, RFSYN_EN_DIV, 1);
4489 status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0);
4490 status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0);
4491 status += MXL_ControlWrite(fe, RFSYN_DIVM, 1);
4492 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1);
4493 status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1);
4494 status += MXL_ControlWrite(fe, DN_SEL_FREQ, 0);
4495 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0);
4496 status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40);
4497 status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 27);
4498 if (state->Mode == 0 && state->IF_Mode == 1) /* Analog Low IF Mode */ {
4499 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0);
4500 status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40);
4501 status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 27);
4502 status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, 206438);
4503 }
4504 if (state->Mode == 0 && state->IF_Mode == 0) /* Analog Zero IF Mode */ {
4505 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0);
4506 status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40);
4507 status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 27);
4508 status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, 206438);
4509 }
4510 if (state->Mode == 1) /* Digital Mode */ {
4511 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0);
4512 status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40);
4513 status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 27);
4514 status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, 212992);
a8214d48
ST		 4515 }
4516 }
52c99bda 4517
a8214d48
ST		 4518 return status;
4519}
52c99bda 4520
3935c254
ST		 4521// DONE
4522u16 MXL_Hystersis_Test(struct dvb_frontend *fe, int Hystersis)
a8214d48 4523{
85d220d0 4524 struct mxl5005s_state *state = fe->tuner_priv;
a8214d48 4525 u16 status = 0;
52c99bda 4526
a8214d48 4527 if (Hystersis == 1)
3935c254 4528 status += MXL_ControlWrite(fe, DN_BYPASS_AGC_I2C, 1);
52c99bda 4529
a8214d48
ST		 4530 return status;
4531}
52c99bda 4532
a8214d48 4533#endif
52c99bda 4534
85d220d0
ST		 4535/* Linux driver related functions */
4536
4537
4538int mxl5005s_init2(struct dvb_frontend *fe)
4539{
4540 int MxlModMode;
4541 int MxlIfMode;
4542 unsigned long MxlBandwitdh;
4543 unsigned long MxlIfFreqHz;
4544 unsigned long MxlCrystalFreqHz;
4545 int MxlAgcMode;
4546 unsigned short MxlTop;
4547 unsigned short MxlIfOutputLoad;
4548 int MxlClockOut;
4549 int MxlDivOut;
4550 int MxlCapSel;
4551 int MxlRssiOnOff;
4552 unsigned char MxlStandard;
4553 unsigned char MxlTfType;
4554
4555 /* Set MxL5005S parameters. */
4556 MxlModMode = MXL_DIGITAL_MODE;
4557 MxlIfMode = MXL_ZERO_IF;
4558// steve
4559 //MxlBandwitdh = MXL5005S_BANDWIDTH_8MHZ;
4560 //MxlIfFreqHz = IF_FREQ_4570000HZ;
4561 MxlBandwitdh = MXL5005S_BANDWIDTH_6MHZ; // config
4562 MxlIfFreqHz = IF_FREQ_5380000HZ; // config
4563 MxlCrystalFreqHz = CRYSTAL_FREQ_16000000HZ; // config
4564 MxlAgcMode = MXL_SINGLE_AGC;
4565 MxlTop = MXL5005S_TOP_25P2;
4566 MxlIfOutputLoad = MXL5005S_IF_OUTPUT_LOAD_200_OHM;
4567 MxlClockOut = MXL_CLOCK_OUT_DISABLE;
4568 MxlDivOut = MXL_DIV_OUT_4;
4569 MxlCapSel = MXL_CAP_SEL_ENABLE;
4570 MxlRssiOnOff = MXL_RSSI_ENABLE; // config
4571 MxlTfType = MXL_TF_C_H; // config
4572
4573 MxlStandard = MXL_ATSC; // config
4574
4575 // TODO: this is bad, it trashes other configs
4576 // Set MxL5005S extra module.
4577 //pExtra->AgcMasterByte = (MxlAgcMode == MXL_DUAL_AGC) ? 0x4 : 0x0;
4578
4579 MXL5005_TunerConfig(
4580 fe,
4581 (unsigned char)MxlModMode,
4582 (unsigned char)MxlIfMode,
4583 MxlBandwitdh,
4584 MxlIfFreqHz,
4585 MxlCrystalFreqHz,
4586 (unsigned char)MxlAgcMode,
4587 MxlTop,
4588 MxlIfOutputLoad,
4589 (unsigned char)MxlClockOut,
4590 (unsigned char)MxlDivOut,
4591 (unsigned char)MxlCapSel,
4592 (unsigned char)MxlRssiOnOff,
4593 MxlStandard, MxlTfType);
4594
4595 return 0;
4596}
4597
4598static int mxl5005s_set_params(struct dvb_frontend *fe,
4599 struct dvb_frontend_parameters *params)
4600{
4601 u32 freq;
4602 u32 bw;
4603
4604 if (fe->ops.info.type == FE_OFDM)
4605 bw = params->u.ofdm.bandwidth;
4606 else
4607 bw = MXL5005S_BANDWIDTH_6MHZ;
4608
4609 freq = params->frequency; /* Hz */
4610 dprintk(1, "%s() freq=%d bw=%d\n", __func__, freq, bw);
4611
4612 return mxl5005s_SetRfFreqHz(fe, freq);
4613}
4614
4615static int mxl5005s_get_frequency(struct dvb_frontend *fe, u32 *frequency)
4616{
4617 struct mxl5005s_state *state = fe->tuner_priv;
4618 dprintk(1, "%s()\n", __func__);
4619
4620 *frequency = state->RF_IN;
4621
4622 return 0;
4623}
4624
4625static int mxl5005s_get_bandwidth(struct dvb_frontend *fe, u32 *bandwidth)
4626{
4627 struct mxl5005s_state *state = fe->tuner_priv;
4628 dprintk(1, "%s()\n", __func__);
4629
4630 *bandwidth = state->Chan_Bandwidth;
4631
4632 return 0;
4633}
4634
4635static int mxl5005s_get_status(struct dvb_frontend *fe, u32 *status)
4636{
4637 dprintk(1, "%s()\n", __func__);
4638
4639 *status = 0;
4640 // *status = TUNER_STATUS_LOCKED;
4641
4642 return 0;
4643}
4644
4645static int mxl5005s_init(struct dvb_frontend *fe)
4646{
4647 struct mxl5005s_state *state = fe->tuner_priv;
4648 u8 AddrTable[MXL5005S_REG_WRITING_TABLE_LEN_MAX];
4649 u8 ByteTable[MXL5005S_REG_WRITING_TABLE_LEN_MAX];
4650 int TableLen;
4651
4652 dprintk(1, "%s()\n", __func__);
4653
4654 /* Initialize MxL5005S tuner according to MxL5005S tuner example code. */
4655
4656 /* Tuner initialization stage 0 */
4657 MXL_GetMasterControl(ByteTable, MC_SYNTH_RESET);
4658 AddrTable[0] = MASTER_CONTROL_ADDR;
4659 ByteTable[0] |= state->config->AgcMasterByte;
4660
4661 mxl5005s_SetRegsWithTable(fe, AddrTable, ByteTable, 1);
4662
4663 /* Tuner initialization stage 1 */
4664 MXL_GetInitRegister(fe, AddrTable, ByteTable, &TableLen);
4665
4666 mxl5005s_SetRegsWithTable(fe, AddrTable, ByteTable, TableLen);
4667
4668 return mxl5005s_init2(fe);
4669}
4670
4671static int mxl5005s_release(struct dvb_frontend *fe)
4672{
4673 dprintk(1, "%s()\n", __func__);
4674 kfree(fe->tuner_priv);
4675 fe->tuner_priv = NULL;
4676 return 0;
4677}
4678
4679static const struct dvb_tuner_ops mxl5005s_tuner_ops = {
4680 .info = {
4681 .name = "MaxLinear MXL5005S",
4682 .frequency_min = 48000000,
4683 .frequency_max = 860000000,
4684 .frequency_step = 50000,
4685 },
4686
4687 .release = mxl5005s_release,
4688 .init = mxl5005s_init,
4689
4690 .set_params = mxl5005s_set_params,
4691 .get_frequency = mxl5005s_get_frequency,
4692 .get_bandwidth = mxl5005s_get_bandwidth,
4693 .get_status = mxl5005s_get_status
4694};
4695
4696struct dvb_frontend *mxl5005s_attach(struct dvb_frontend *fe,
4697 struct i2c_adapter *i2c,
4698 struct mxl5005s_config *config)
4699{
4700 struct mxl5005s_state *state = NULL;
4701 dprintk(1, "%s()\n", __func__);
4702
4703 state = kzalloc(sizeof(struct mxl5005s_state), GFP_KERNEL);
4704 if (state == NULL)
4705 return NULL;
4706
4707 state->frontend = fe;
4708 state->config = config;
4709 state->i2c = i2c;
4710
4711 printk(KERN_INFO "MXL5005S: Attached at address 0x%02x\n", config->i2c_address);
4712
4713 memcpy(&fe->ops.tuner_ops, &mxl5005s_tuner_ops, sizeof(struct dvb_tuner_ops));
4714
4715 fe->tuner_priv = state;
4716 return fe;
4717}
4718EXPORT_SYMBOL(mxl5005s_attach);
4719
4720MODULE_DESCRIPTION("MaxLinear MXL5005S silicon tuner driver");
4721MODULE_AUTHOR("Jan Hoogenraad");
4722MODULE_AUTHOR("Barnaby Shearer");
4723MODULE_AUTHOR("Andy Hasper");
4724MODULE_AUTHOR("Steven Toth");
4725MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)