[linux-block.git] / drivers / media / cec / platform / sti / stih-cec.c

// SPDX-License-Identifier: GPL-2.0
/*
 * STIH4xx CEC driver
 * Copyright (C) STMicroelectronics SA 2016
 *
 */
#include <linux/clk.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/mfd/syscon.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_platform.h>
#include <linux/platform_device.h>

#include <media/cec.h>
#include <media/cec-notifier.h>

#define CEC_NAME	"stih-cec"

/* CEC registers  */
#define CEC_CLK_DIV           0x0
#define CEC_CTRL              0x4
#define CEC_IRQ_CTRL          0x8
#define CEC_STATUS            0xC
#define CEC_EXT_STATUS        0x10
#define CEC_TX_CTRL           0x14
#define CEC_FREE_TIME_THRESH  0x18
#define CEC_BIT_TOUT_THRESH   0x1C
#define CEC_BIT_PULSE_THRESH  0x20
#define CEC_DATA              0x24
#define CEC_TX_ARRAY_CTRL     0x28
#define CEC_CTRL2             0x2C
#define CEC_TX_ERROR_STS      0x30
#define CEC_ADDR_TABLE        0x34
#define CEC_DATA_ARRAY_CTRL   0x38
#define CEC_DATA_ARRAY_STATUS 0x3C
#define CEC_TX_DATA_BASE      0x40
#define CEC_TX_DATA_TOP       0x50
#define CEC_TX_DATA_SIZE      0x1
#define CEC_RX_DATA_BASE      0x54
#define CEC_RX_DATA_TOP       0x64
#define CEC_RX_DATA_SIZE      0x1

/* CEC_CTRL2 */
#define CEC_LINE_INACTIVE_EN   BIT(0)
#define CEC_AUTO_BUS_ERR_EN    BIT(1)
#define CEC_STOP_ON_ARB_ERR_EN BIT(2)
#define CEC_TX_REQ_WAIT_EN     BIT(3)

/* CEC_DATA_ARRAY_CTRL */
#define CEC_TX_ARRAY_EN          BIT(0)
#define CEC_RX_ARRAY_EN          BIT(1)
#define CEC_TX_ARRAY_RESET       BIT(2)
#define CEC_RX_ARRAY_RESET       BIT(3)
#define CEC_TX_N_OF_BYTES_IRQ_EN BIT(4)
#define CEC_TX_STOP_ON_NACK      BIT(7)

/* CEC_TX_ARRAY_CTRL */
#define CEC_TX_N_OF_BYTES  0x1F
#define CEC_TX_START       BIT(5)
#define CEC_TX_AUTO_SOM_EN BIT(6)
#define CEC_TX_AUTO_EOM_EN BIT(7)

/* CEC_IRQ_CTRL */
#define CEC_TX_DONE_IRQ_EN   BIT(0)
#define CEC_ERROR_IRQ_EN     BIT(2)
#define CEC_RX_DONE_IRQ_EN   BIT(3)
#define CEC_RX_SOM_IRQ_EN    BIT(4)
#define CEC_RX_EOM_IRQ_EN    BIT(5)
#define CEC_FREE_TIME_IRQ_EN BIT(6)
#define CEC_PIN_STS_IRQ_EN   BIT(7)

/* CEC_CTRL */
#define CEC_IN_FILTER_EN    BIT(0)
#define CEC_PWR_SAVE_EN     BIT(1)
#define CEC_EN              BIT(4)
#define CEC_ACK_CTRL        BIT(5)
#define CEC_RX_RESET_EN     BIT(6)
#define CEC_IGNORE_RX_ERROR BIT(7)

/* CEC_STATUS */
#define CEC_TX_DONE_STS       BIT(0)
#define CEC_TX_ACK_GET_STS    BIT(1)
#define CEC_ERROR_STS         BIT(2)
#define CEC_RX_DONE_STS       BIT(3)
#define CEC_RX_SOM_STS        BIT(4)
#define CEC_RX_EOM_STS        BIT(5)
#define CEC_FREE_TIME_IRQ_STS BIT(6)
#define CEC_PIN_STS           BIT(7)
#define CEC_SBIT_TOUT_STS     BIT(8)
#define CEC_DBIT_TOUT_STS     BIT(9)
#define CEC_LPULSE_ERROR_STS  BIT(10)
#define CEC_HPULSE_ERROR_STS  BIT(11)
#define CEC_TX_ERROR          BIT(12)
#define CEC_TX_ARB_ERROR      BIT(13)
#define CEC_RX_ERROR_MIN      BIT(14)
#define CEC_RX_ERROR_MAX      BIT(15)

/* Signal free time in bit periods (2.4ms) */
#define CEC_PRESENT_INIT_SFT 7
#define CEC_NEW_INIT_SFT     5
#define CEC_RETRANSMIT_SFT   3

/* Constants for CEC_BIT_TOUT_THRESH register */
#define CEC_SBIT_TOUT_47MS BIT(1)
#define CEC_SBIT_TOUT_48MS (BIT(0) | BIT(1))
#define CEC_SBIT_TOUT_50MS BIT(2)
#define CEC_DBIT_TOUT_27MS BIT(0)
#define CEC_DBIT_TOUT_28MS BIT(1)
#define CEC_DBIT_TOUT_29MS (BIT(0) | BIT(1))

/* Constants for CEC_BIT_PULSE_THRESH register */
#define CEC_BIT_LPULSE_03MS BIT(1)
#define CEC_BIT_HPULSE_03MS BIT(3)

/* Constants for CEC_DATA_ARRAY_STATUS register */
#define CEC_RX_N_OF_BYTES                     0x1F
#define CEC_TX_N_OF_BYTES_SENT                BIT(5)
#define CEC_RX_OVERRUN                        BIT(6)

struct stih_cec {
	struct cec_adapter	*adap;
	struct device		*dev;
	struct clk		*clk;
	void __iomem		*regs;
	int			irq;
	u32			irq_status;
	struct cec_notifier	*notifier;
};

static int stih_cec_adap_enable(struct cec_adapter *adap, bool enable)
{
	struct stih_cec *cec = cec_get_drvdata(adap);

	if (enable) {
		/* The doc says (input TCLK_PERIOD * CEC_CLK_DIV) = 0.1ms */
		unsigned long clk_freq = clk_get_rate(cec->clk);
		u32 cec_clk_div = clk_freq / 10000;

		writel(cec_clk_div, cec->regs + CEC_CLK_DIV);

		/* Configuration of the durations activating a timeout */
		writel(CEC_SBIT_TOUT_47MS | (CEC_DBIT_TOUT_28MS << 4),
		       cec->regs + CEC_BIT_TOUT_THRESH);

		/* Configuration of the smallest allowed duration for pulses */
		writel(CEC_BIT_LPULSE_03MS | CEC_BIT_HPULSE_03MS,
		       cec->regs + CEC_BIT_PULSE_THRESH);

		/* Minimum received bit period threshold */
		writel(BIT(5) | BIT(7), cec->regs + CEC_TX_CTRL);

		/* Configuration of transceiver data arrays */
		writel(CEC_TX_ARRAY_EN | CEC_RX_ARRAY_EN | CEC_TX_STOP_ON_NACK,
		       cec->regs + CEC_DATA_ARRAY_CTRL);

		/* Configuration of the control bits for CEC Transceiver */
		writel(CEC_IN_FILTER_EN | CEC_EN | CEC_RX_RESET_EN,
		       cec->regs + CEC_CTRL);

		/* Clear logical addresses */
		writel(0, cec->regs + CEC_ADDR_TABLE);

		/* Clear the status register */
		writel(0x0, cec->regs + CEC_STATUS);

		/* Enable the interrupts */
		writel(CEC_TX_DONE_IRQ_EN | CEC_RX_DONE_IRQ_EN |
		       CEC_RX_SOM_IRQ_EN | CEC_RX_EOM_IRQ_EN |
		       CEC_ERROR_IRQ_EN,
		       cec->regs + CEC_IRQ_CTRL);

	} else {
		/* Clear logical addresses */
		writel(0, cec->regs + CEC_ADDR_TABLE);

		/* Clear the status register */
		writel(0x0, cec->regs + CEC_STATUS);

		/* Disable the interrupts */
		writel(0, cec->regs + CEC_IRQ_CTRL);
	}

	return 0;
}

static int stih_cec_adap_log_addr(struct cec_adapter *adap, u8 logical_addr)
{
	struct stih_cec *cec = cec_get_drvdata(adap);
	u32 reg = readl(cec->regs + CEC_ADDR_TABLE);

	reg |= 1 << logical_addr;

	if (logical_addr == CEC_LOG_ADDR_INVALID)
		reg = 0;

	writel(reg, cec->regs + CEC_ADDR_TABLE);

	return 0;
}

static int stih_cec_adap_transmit(struct cec_adapter *adap, u8 attempts,
				  u32 signal_free_time, struct cec_msg *msg)
{
	struct stih_cec *cec = cec_get_drvdata(adap);
	int i;

	/* Copy message into registers */
	for (i = 0; i < msg->len; i++)
		writeb(msg->msg[i], cec->regs + CEC_TX_DATA_BASE + i);

	/*
	 * Start transmission, configure hardware to add start and stop bits
	 * Signal free time is handled by the hardware
	 */
	writel(CEC_TX_AUTO_SOM_EN | CEC_TX_AUTO_EOM_EN | CEC_TX_START |
	       msg->len, cec->regs + CEC_TX_ARRAY_CTRL);

	return 0;
}

static void stih_tx_done(struct stih_cec *cec, u32 status)
{
	if (status & CEC_TX_ERROR) {
		cec_transmit_attempt_done(cec->adap, CEC_TX_STATUS_ERROR);
		return;
	}

	if (status & CEC_TX_ARB_ERROR) {
		cec_transmit_attempt_done(cec->adap, CEC_TX_STATUS_ARB_LOST);
		return;
	}

	if (!(status & CEC_TX_ACK_GET_STS)) {
		cec_transmit_attempt_done(cec->adap, CEC_TX_STATUS_NACK);
		return;
	}

	cec_transmit_attempt_done(cec->adap, CEC_TX_STATUS_OK);
}

static void stih_rx_done(struct stih_cec *cec, u32 status)
{
	struct cec_msg msg = {};
	u8 i;

	if (status & CEC_RX_ERROR_MIN)
		return;

	if (status & CEC_RX_ERROR_MAX)
		return;

	msg.len = readl(cec->regs + CEC_DATA_ARRAY_STATUS) & 0x1f;

	if (!msg.len)
		return;

	if (msg.len > CEC_MAX_MSG_SIZE)
		msg.len = CEC_MAX_MSG_SIZE;

	for (i = 0; i < msg.len; i++)
		msg.msg[i] = readl(cec->regs + CEC_RX_DATA_BASE + i);

	cec_received_msg(cec->adap, &msg);
}

static irqreturn_t stih_cec_irq_handler_thread(int irq, void *priv)
{
	struct stih_cec *cec = priv;

	if (cec->irq_status & CEC_TX_DONE_STS)
		stih_tx_done(cec, cec->irq_status);

	if (cec->irq_status & CEC_RX_DONE_STS)
		stih_rx_done(cec, cec->irq_status);

	cec->irq_status = 0;

	return IRQ_HANDLED;
}

static irqreturn_t stih_cec_irq_handler(int irq, void *priv)
{
	struct stih_cec *cec = priv;

	cec->irq_status = readl(cec->regs + CEC_STATUS);
	writel(cec->irq_status, cec->regs + CEC_STATUS);

	return IRQ_WAKE_THREAD;
}

static const struct cec_adap_ops sti_cec_adap_ops = {
	.adap_enable = stih_cec_adap_enable,
	.adap_log_addr = stih_cec_adap_log_addr,
	.adap_transmit = stih_cec_adap_transmit,
};

static int stih_cec_probe(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
	struct stih_cec *cec;
	struct device *hdmi_dev;
	int ret;

	hdmi_dev = cec_notifier_parse_hdmi_phandle(dev);

	if (IS_ERR(hdmi_dev))
		return PTR_ERR(hdmi_dev);

	cec = devm_kzalloc(dev, sizeof(*cec), GFP_KERNEL);
	if (!cec)
		return -ENOMEM;

	cec->dev = dev;

	cec->regs = devm_platform_ioremap_resource(pdev, 0);
	if (IS_ERR(cec->regs))
		return PTR_ERR(cec->regs);

	cec->irq = platform_get_irq(pdev, 0);
	if (cec->irq < 0)
		return cec->irq;

	ret = devm_request_threaded_irq(dev, cec->irq, stih_cec_irq_handler,
					stih_cec_irq_handler_thread, 0,
					pdev->name, cec);
	if (ret)
		return ret;

	cec->clk = devm_clk_get(dev, "cec-clk");
	if (IS_ERR(cec->clk)) {
		dev_err(dev, "Cannot get cec clock\n");
		return PTR_ERR(cec->clk);
	}

	cec->adap = cec_allocate_adapter(&sti_cec_adap_ops, cec, CEC_NAME,
					 CEC_CAP_DEFAULTS |
					 CEC_CAP_CONNECTOR_INFO,
					 CEC_MAX_LOG_ADDRS);
	ret = PTR_ERR_OR_ZERO(cec->adap);
	if (ret)
		return ret;

	cec->notifier = cec_notifier_cec_adap_register(hdmi_dev, NULL,
						       cec->adap);
	if (!cec->notifier) {
		ret = -ENOMEM;
		goto err_delete_adapter;
	}

	ret = cec_register_adapter(cec->adap, &pdev->dev);
	if (ret)
		goto err_notifier;

	platform_set_drvdata(pdev, cec);
	return 0;

err_notifier:
	cec_notifier_cec_adap_unregister(cec->notifier, cec->adap);

err_delete_adapter:
	cec_delete_adapter(cec->adap);
	return ret;
}

static void stih_cec_remove(struct platform_device *pdev)
{
	struct stih_cec *cec = platform_get_drvdata(pdev);

	cec_notifier_cec_adap_unregister(cec->notifier, cec->adap);
	cec_unregister_adapter(cec->adap);
}

static const struct of_device_id stih_cec_match[] = {
	{
		.compatible	= "st,stih-cec",
	},
	{},
};
MODULE_DEVICE_TABLE(of, stih_cec_match);

static struct platform_driver stih_cec_pdrv = {
	.probe	= stih_cec_probe,
	.remove_new = stih_cec_remove,
	.driver = {
		.name		= CEC_NAME,
		.of_match_table	= stih_cec_match,
	},
};

module_platform_driver(stih_cec_pdrv);

MODULE_AUTHOR("Benjamin Gaignard <benjamin.gaignard@linaro.org>");
MODULE_LICENSE("GPL");
MODULE_DESCRIPTION("STIH4xx CEC driver");
Commit	Line	Data
9ed785a9	1	// SPDX-License-Identifier: GPL-2.0
60fe2bda	2	/*
60fe2bda	3	* STIH4xx CEC driver
fd47bc41	4	* Copyright (C) STMicroelectronics SA 2016
60fe2bda	5	*
60fe2bda BG	6	*/
	7	#include <linux/clk.h>
	8	#include <linux/interrupt.h>
495ae16a	9	#include <linux/io.h>
60fe2bda BG	10	#include <linux/kernel.h>
	11	#include <linux/mfd/syscon.h>
	12	#include <linux/module.h>
	13	#include <linux/of.h>
fc4e009c	14	#include <linux/of_platform.h>
60fe2bda	15	#include <linux/platform_device.h>
60fe2bda BG	16
60fe2bda BG	17	#include <media/cec.h>
fc4e009c	18	#include <media/cec-notifier.h>
60fe2bda BG	19
	20	#define CEC_NAME "stih-cec"
	21
	22	/* CEC registers */
	23	#define CEC_CLK_DIV 0x0
	24	#define CEC_CTRL 0x4
	25	#define CEC_IRQ_CTRL 0x8
	26	#define CEC_STATUS 0xC
	27	#define CEC_EXT_STATUS 0x10
	28	#define CEC_TX_CTRL 0x14
	29	#define CEC_FREE_TIME_THRESH 0x18
	30	#define CEC_BIT_TOUT_THRESH 0x1C
	31	#define CEC_BIT_PULSE_THRESH 0x20
	32	#define CEC_DATA 0x24
	33	#define CEC_TX_ARRAY_CTRL 0x28
	34	#define CEC_CTRL2 0x2C
	35	#define CEC_TX_ERROR_STS 0x30
	36	#define CEC_ADDR_TABLE 0x34
	37	#define CEC_DATA_ARRAY_CTRL 0x38
	38	#define CEC_DATA_ARRAY_STATUS 0x3C
	39	#define CEC_TX_DATA_BASE 0x40
	40	#define CEC_TX_DATA_TOP 0x50
	41	#define CEC_TX_DATA_SIZE 0x1
	42	#define CEC_RX_DATA_BASE 0x54
	43	#define CEC_RX_DATA_TOP 0x64
	44	#define CEC_RX_DATA_SIZE 0x1
	45
	46	/* CEC_CTRL2 */
	47	#define CEC_LINE_INACTIVE_EN BIT(0)
	48	#define CEC_AUTO_BUS_ERR_EN BIT(1)
	49	#define CEC_STOP_ON_ARB_ERR_EN BIT(2)
	50	#define CEC_TX_REQ_WAIT_EN BIT(3)
	51
	52	/* CEC_DATA_ARRAY_CTRL */
	53	#define CEC_TX_ARRAY_EN BIT(0)
	54	#define CEC_RX_ARRAY_EN BIT(1)
	55	#define CEC_TX_ARRAY_RESET BIT(2)
	56	#define CEC_RX_ARRAY_RESET BIT(3)
	57	#define CEC_TX_N_OF_BYTES_IRQ_EN BIT(4)
	58	#define CEC_TX_STOP_ON_NACK BIT(7)
	59
	60	/* CEC_TX_ARRAY_CTRL */
	61	#define CEC_TX_N_OF_BYTES 0x1F
	62	#define CEC_TX_START BIT(5)
	63	#define CEC_TX_AUTO_SOM_EN BIT(6)
	64	#define CEC_TX_AUTO_EOM_EN BIT(7)
	65
	66	/* CEC_IRQ_CTRL */
	67	#define CEC_TX_DONE_IRQ_EN BIT(0)
	68	#define CEC_ERROR_IRQ_EN BIT(2)
	69	#define CEC_RX_DONE_IRQ_EN BIT(3)
	70	#define CEC_RX_SOM_IRQ_EN BIT(4)
	71	#define CEC_RX_EOM_IRQ_EN BIT(5)
	72	#define CEC_FREE_TIME_IRQ_EN BIT(6)
	73	#define CEC_PIN_STS_IRQ_EN BIT(7)
	74
	75	/* CEC_CTRL */
	76	#define CEC_IN_FILTER_EN BIT(0)
	77	#define CEC_PWR_SAVE_EN BIT(1)
	78	#define CEC_EN BIT(4)
	79	#define CEC_ACK_CTRL BIT(5)
	80	#define CEC_RX_RESET_EN BIT(6)
	81	#define CEC_IGNORE_RX_ERROR BIT(7)
	82
83	/* CEC_STATUS */
84	#define CEC_TX_DONE_STS BIT(0)
85	#define CEC_TX_ACK_GET_STS BIT(1)
86	#define CEC_ERROR_STS BIT(2)
87	#define CEC_RX_DONE_STS BIT(3)
88	#define CEC_RX_SOM_STS BIT(4)
89	#define CEC_RX_EOM_STS BIT(5)
90	#define CEC_FREE_TIME_IRQ_STS BIT(6)
91	#define CEC_PIN_STS BIT(7)
92	#define CEC_SBIT_TOUT_STS BIT(8)
93	#define CEC_DBIT_TOUT_STS BIT(9)
94	#define CEC_LPULSE_ERROR_STS BIT(10)
95	#define CEC_HPULSE_ERROR_STS BIT(11)
96	#define CEC_TX_ERROR BIT(12)
97	#define CEC_TX_ARB_ERROR BIT(13)
98	#define CEC_RX_ERROR_MIN BIT(14)
99	#define CEC_RX_ERROR_MAX BIT(15)
100
101	/* Signal free time in bit periods (2.4ms) */
102	#define CEC_PRESENT_INIT_SFT 7
103	#define CEC_NEW_INIT_SFT 5
104	#define CEC_RETRANSMIT_SFT 3
105
106	/* Constants for CEC_BIT_TOUT_THRESH register */
107	#define CEC_SBIT_TOUT_47MS BIT(1)
64bab1a2	108	#define CEC_SBIT_TOUT_48MS (BIT(0) \| BIT(1))
60fe2bda BG	109	#define CEC_SBIT_TOUT_50MS BIT(2)
	110	#define CEC_DBIT_TOUT_27MS BIT(0)
	111	#define CEC_DBIT_TOUT_28MS BIT(1)
64bab1a2	112	#define CEC_DBIT_TOUT_29MS (BIT(0) \| BIT(1))
60fe2bda BG	113
	114	/* Constants for CEC_BIT_PULSE_THRESH register */
	115	#define CEC_BIT_LPULSE_03MS BIT(1)
	116	#define CEC_BIT_HPULSE_03MS BIT(3)
	117
	118	/* Constants for CEC_DATA_ARRAY_STATUS register */
	119	#define CEC_RX_N_OF_BYTES 0x1F
	120	#define CEC_TX_N_OF_BYTES_SENT BIT(5)
	121	#define CEC_RX_OVERRUN BIT(6)
	122
	123	struct stih_cec {
	124	struct cec_adapter *adap;
	125	struct device *dev;
	126	struct clk *clk;
	127	void __iomem *regs;
	128	int irq;
	129	u32 irq_status;
fc4e009c	130	struct cec_notifier *notifier;
60fe2bda BG	131	};
	132
	133	static int stih_cec_adap_enable(struct cec_adapter *adap, bool enable)
	134	{
2524490c	135	struct stih_cec *cec = cec_get_drvdata(adap);
60fe2bda BG	136
	137	if (enable) {
	138	/* The doc says (input TCLK_PERIOD * CEC_CLK_DIV) = 0.1ms */
	139	unsigned long clk_freq = clk_get_rate(cec->clk);
	140	u32 cec_clk_div = clk_freq / 10000;
	141
	142	writel(cec_clk_div, cec->regs + CEC_CLK_DIV);
	143
	144	/* Configuration of the durations activating a timeout */
	145	writel(CEC_SBIT_TOUT_47MS \| (CEC_DBIT_TOUT_28MS << 4),
	146	cec->regs + CEC_BIT_TOUT_THRESH);
	147
	148	/* Configuration of the smallest allowed duration for pulses */
	149	writel(CEC_BIT_LPULSE_03MS \| CEC_BIT_HPULSE_03MS,
	150	cec->regs + CEC_BIT_PULSE_THRESH);
	151
	152	/* Minimum received bit period threshold */
	153	writel(BIT(5) \| BIT(7), cec->regs + CEC_TX_CTRL);
	154
	155	/* Configuration of transceiver data arrays */
	156	writel(CEC_TX_ARRAY_EN \| CEC_RX_ARRAY_EN \| CEC_TX_STOP_ON_NACK,
	157	cec->regs + CEC_DATA_ARRAY_CTRL);
	158
	159	/* Configuration of the control bits for CEC Transceiver */
	160	writel(CEC_IN_FILTER_EN \| CEC_EN \| CEC_RX_RESET_EN,
	161	cec->regs + CEC_CTRL);
	162
	163	/* Clear logical addresses */
	164	writel(0, cec->regs + CEC_ADDR_TABLE);
	165
	166	/* Clear the status register */
	167	writel(0x0, cec->regs + CEC_STATUS);
	168
	169	/* Enable the interrupts */
	170	writel(CEC_TX_DONE_IRQ_EN \| CEC_RX_DONE_IRQ_EN \|
	171	CEC_RX_SOM_IRQ_EN \| CEC_RX_EOM_IRQ_EN \|
	172	CEC_ERROR_IRQ_EN,
	173	cec->regs + CEC_IRQ_CTRL);
	174
	175	} else {
	176	/* Clear logical addresses */
	177	writel(0, cec->regs + CEC_ADDR_TABLE);
	178
	179	/* Clear the status register */
	180	writel(0x0, cec->regs + CEC_STATUS);
	181
	182	/* Disable the interrupts */
	183	writel(0, cec->regs + CEC_IRQ_CTRL);
	184	}
	185
	186	return 0;
	187	}
	188
	189	static int stih_cec_adap_log_addr(struct cec_adapter *adap, u8 logical_addr)
	190	{
2524490c	191	struct stih_cec *cec = cec_get_drvdata(adap);
60fe2bda BG	192	u32 reg = readl(cec->regs + CEC_ADDR_TABLE);
	193
	194	reg \|= 1 << logical_addr;
	195
	196	if (logical_addr == CEC_LOG_ADDR_INVALID)
	197	reg = 0;
	198
	199	writel(reg, cec->regs + CEC_ADDR_TABLE);
	200
	201	return 0;
	202	}
	203
	204	static int stih_cec_adap_transmit(struct cec_adapter *adap, u8 attempts,
	205	u32 signal_free_time, struct cec_msg *msg)
	206	{
2524490c	207	struct stih_cec *cec = cec_get_drvdata(adap);
60fe2bda BG	208	int i;
	209
	210	/* Copy message into registers */
	211	for (i = 0; i < msg->len; i++)
	212	writeb(msg->msg[i], cec->regs + CEC_TX_DATA_BASE + i);
	213
fd47bc41 BG	214	/*
fd47bc41 BG	215	* Start transmission, configure hardware to add start and stop bits
60fe2bda BG	216	* Signal free time is handled by the hardware
	217	*/
	218	writel(CEC_TX_AUTO_SOM_EN \| CEC_TX_AUTO_EOM_EN \| CEC_TX_START \|
	219	msg->len, cec->regs + CEC_TX_ARRAY_CTRL);
	220
	221	return 0;
	222	}
	223
	224	static void stih_tx_done(struct stih_cec *cec, u32 status)
	225	{
	226	if (status & CEC_TX_ERROR) {
2613cc6f	227	cec_transmit_attempt_done(cec->adap, CEC_TX_STATUS_ERROR);
60fe2bda BG	228	return;
	229	}
	230
	231	if (status & CEC_TX_ARB_ERROR) {
2613cc6f	232	cec_transmit_attempt_done(cec->adap, CEC_TX_STATUS_ARB_LOST);
60fe2bda BG	233	return;
	234	}
	235
	236	if (!(status & CEC_TX_ACK_GET_STS)) {
2613cc6f	237	cec_transmit_attempt_done(cec->adap, CEC_TX_STATUS_NACK);
60fe2bda BG	238	return;
	239	}
	240
2613cc6f	241	cec_transmit_attempt_done(cec->adap, CEC_TX_STATUS_OK);
60fe2bda BG	242	}
	243
	244	static void stih_rx_done(struct stih_cec *cec, u32 status)
	245	{
	246	struct cec_msg msg = {};
	247	u8 i;
	248
	249	if (status & CEC_RX_ERROR_MIN)
	250	return;
	251
	252	if (status & CEC_RX_ERROR_MAX)
	253	return;
	254
	255	msg.len = readl(cec->regs + CEC_DATA_ARRAY_STATUS) & 0x1f;
	256
	257	if (!msg.len)
	258	return;
	259
05c480f4 HV	260	if (msg.len > CEC_MAX_MSG_SIZE)
05c480f4 HV	261	msg.len = CEC_MAX_MSG_SIZE;
60fe2bda BG	262
	263	for (i = 0; i < msg.len; i++)
	264	msg.msg[i] = readl(cec->regs + CEC_RX_DATA_BASE + i);
	265
	266	cec_received_msg(cec->adap, &msg);
	267	}
	268
	269	static irqreturn_t stih_cec_irq_handler_thread(int irq, void *priv)
	270	{
	271	struct stih_cec *cec = priv;
	272
	273	if (cec->irq_status & CEC_TX_DONE_STS)
	274	stih_tx_done(cec, cec->irq_status);
	275
	276	if (cec->irq_status & CEC_RX_DONE_STS)
	277	stih_rx_done(cec, cec->irq_status);
	278
	279	cec->irq_status = 0;
	280
	281	return IRQ_HANDLED;
	282	}
	283
	284	static irqreturn_t stih_cec_irq_handler(int irq, void *priv)
	285	{
	286	struct stih_cec *cec = priv;
	287
	288	cec->irq_status = readl(cec->regs + CEC_STATUS);
	289	writel(cec->irq_status, cec->regs + CEC_STATUS);
	290
	291	return IRQ_WAKE_THREAD;
	292	}
	293
	294	static const struct cec_adap_ops sti_cec_adap_ops = {
	295	.adap_enable = stih_cec_adap_enable,
	296	.adap_log_addr = stih_cec_adap_log_addr,
	297	.adap_transmit = stih_cec_adap_transmit,
	298	};
	299
	300	static int stih_cec_probe(struct platform_device *pdev)
	301	{
	302	struct device *dev = &pdev->dev;
60fe2bda	303	struct stih_cec *cec;
e3a7c52d	304	struct device *hdmi_dev;
60fe2bda BG	305	int ret;
60fe2bda BG	306
e3a7c52d HV	307	hdmi_dev = cec_notifier_parse_hdmi_phandle(dev);
	308
	309	if (IS_ERR(hdmi_dev))
	310	return PTR_ERR(hdmi_dev);
	311
60fe2bda BG	312	cec = devm_kzalloc(dev, sizeof(*cec), GFP_KERNEL);
	313	if (!cec)
	314	return -ENOMEM;
	315
	316	cec->dev = dev;
	317
beabb243	318	cec->regs = devm_platform_ioremap_resource(pdev, 0);
60fe2bda BG	319	if (IS_ERR(cec->regs))
	320	return PTR_ERR(cec->regs);
	321
	322	cec->irq = platform_get_irq(pdev, 0);
	323	if (cec->irq < 0)
	324	return cec->irq;
	325
	326	ret = devm_request_threaded_irq(dev, cec->irq, stih_cec_irq_handler,
	327	stih_cec_irq_handler_thread, 0,
	328	pdev->name, cec);
	329	if (ret)
	330	return ret;
	331
	332	cec->clk = devm_clk_get(dev, "cec-clk");
	333	if (IS_ERR(cec->clk)) {
	334	dev_err(dev, "Cannot get cec clock\n");
	335	return PTR_ERR(cec->clk);
	336	}
	337
72a171d7 HV	338	cec->adap = cec_allocate_adapter(&sti_cec_adap_ops, cec, CEC_NAME,
	339	CEC_CAP_DEFAULTS \|
	340	CEC_CAP_CONNECTOR_INFO,
	341	CEC_MAX_LOG_ADDRS);
60fe2bda BG	342	ret = PTR_ERR_OR_ZERO(cec->adap);
	343	if (ret)
	344	return ret;
	345
72a171d7 HV	346	cec->notifier = cec_notifier_cec_adap_register(hdmi_dev, NULL,
	347	cec->adap);
	348	if (!cec->notifier) {
	349	ret = -ENOMEM;
	350	goto err_delete_adapter;
60fe2bda BG	351	}
60fe2bda BG	352
72a171d7 HV	353	ret = cec_register_adapter(cec->adap, &pdev->dev);
	354	if (ret)
	355	goto err_notifier;
fc4e009c	356
60fe2bda BG	357	platform_set_drvdata(pdev, cec);
60fe2bda BG	358	return 0;
72a171d7 HV	359
72a171d7 HV	360	err_notifier:
10d8f308	361	cec_notifier_cec_adap_unregister(cec->notifier, cec->adap);
72a171d7 HV	362
	363	err_delete_adapter:
	364	cec_delete_adapter(cec->adap);
	365	return ret;
60fe2bda BG	366	}
60fe2bda BG	367
3cdae5bf	368	static void stih_cec_remove(struct platform_device *pdev)
60fe2bda	369	{
fc4e009c BG	370	struct stih_cec *cec = platform_get_drvdata(pdev);
fc4e009c BG	371
10d8f308	372	cec_notifier_cec_adap_unregister(cec->notifier, cec->adap);
fc4e009c	373	cec_unregister_adapter(cec->adap);
60fe2bda BG	374	}
	375
	376	static const struct of_device_id stih_cec_match[] = {
	377	{
	378	.compatible = "st,stih-cec",
	379	},
	380	{},
	381	};
2411434a	382	MODULE_DEVICE_TABLE(of, stih_cec_match);
60fe2bda BG	383
	384	static struct platform_driver stih_cec_pdrv = {
	385	.probe = stih_cec_probe,
3cdae5bf	386	.remove_new = stih_cec_remove,
60fe2bda BG	387	.driver = {
	388	.name = CEC_NAME,
	389	.of_match_table = stih_cec_match,
	390	},
	391	};
	392
	393	module_platform_driver(stih_cec_pdrv);
	394
	395	MODULE_AUTHOR("Benjamin Gaignard <benjamin.gaignard@linaro.org>");
	396	MODULE_LICENSE("GPL");
	397	MODULE_DESCRIPTION("STIH4xx CEC driver");