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4f0ceb87 | 1 | // SPDX-License-Identifier: GPL-2.0 |
aace66b1 NM |
2 | /* |
3 | * Texas Instruments' Message Manager Driver | |
4 | * | |
4f0ceb87 | 5 | * Copyright (C) 2015-2017 Texas Instruments Incorporated - http://www.ti.com/ |
aace66b1 | 6 | * Nishanth Menon |
aace66b1 NM |
7 | */ |
8 | ||
9 | #define pr_fmt(fmt) "%s: " fmt, __func__ | |
10 | ||
11 | #include <linux/device.h> | |
12 | #include <linux/interrupt.h> | |
13 | #include <linux/io.h> | |
14 | #include <linux/kernel.h> | |
15 | #include <linux/mailbox_controller.h> | |
16 | #include <linux/module.h> | |
17 | #include <linux/of_device.h> | |
18 | #include <linux/of.h> | |
19 | #include <linux/of_irq.h> | |
20 | #include <linux/platform_device.h> | |
21 | #include <linux/soc/ti/ti-msgmgr.h> | |
22 | ||
23 | #define Q_DATA_OFFSET(proxy, queue, reg) \ | |
24 | ((0x10000 * (proxy)) + (0x80 * (queue)) + ((reg) * 4)) | |
25 | #define Q_STATE_OFFSET(queue) ((queue) * 0x4) | |
26 | #define Q_STATE_ENTRY_COUNT_MASK (0xFFF000) | |
27 | ||
a2b79838 NM |
28 | #define SPROXY_THREAD_OFFSET(tid) (0x1000 * (tid)) |
29 | #define SPROXY_THREAD_DATA_OFFSET(tid, reg) \ | |
30 | (SPROXY_THREAD_OFFSET(tid) + ((reg) * 0x4) + 0x4) | |
31 | ||
32 | #define SPROXY_THREAD_STATUS_OFFSET(tid) (SPROXY_THREAD_OFFSET(tid)) | |
33 | ||
34 | #define SPROXY_THREAD_STATUS_COUNT_MASK (0xFF) | |
35 | ||
36 | #define SPROXY_THREAD_CTRL_OFFSET(tid) (0x1000 + SPROXY_THREAD_OFFSET(tid)) | |
37 | #define SPROXY_THREAD_CTRL_DIR_MASK (0x1 << 31) | |
38 | ||
aace66b1 NM |
39 | /** |
40 | * struct ti_msgmgr_valid_queue_desc - SoC valid queues meant for this processor | |
41 | * @queue_id: Queue Number for this path | |
42 | * @proxy_id: Proxy ID representing the processor in SoC | |
43 | * @is_tx: Is this a receive path? | |
44 | */ | |
45 | struct ti_msgmgr_valid_queue_desc { | |
46 | u8 queue_id; | |
47 | u8 proxy_id; | |
48 | bool is_tx; | |
49 | }; | |
50 | ||
51 | /** | |
52 | * struct ti_msgmgr_desc - Description of message manager integration | |
53 | * @queue_count: Number of Queues | |
54 | * @max_message_size: Message size in bytes | |
55 | * @max_messages: Number of messages | |
aace66b1 NM |
56 | * @data_first_reg: First data register for proxy data region |
57 | * @data_last_reg: Last data register for proxy data region | |
8e560862 | 58 | * @status_cnt_mask: Mask for getting the status value |
a2b79838 | 59 | * @status_err_mask: Mask for getting the error value, if applicable |
aace66b1 NM |
60 | * @tx_polled: Do I need to use polled mechanism for tx |
61 | * @tx_poll_timeout_ms: Timeout in ms if polled | |
62 | * @valid_queues: List of Valid queues that the processor can access | |
89c976c2 NM |
63 | * @data_region_name: Name of the proxy data region |
64 | * @status_region_name: Name of the proxy status region | |
a2b79838 | 65 | * @ctrl_region_name: Name of the proxy control region |
aace66b1 | 66 | * @num_valid_queues: Number of valid queues |
a2b79838 | 67 | * @is_sproxy: Is this an Secure Proxy instance? |
aace66b1 NM |
68 | * |
69 | * This structure is used in of match data to describe how integration | |
70 | * for a specific compatible SoC is done. | |
71 | */ | |
72 | struct ti_msgmgr_desc { | |
73 | u8 queue_count; | |
74 | u8 max_message_size; | |
75 | u8 max_messages; | |
aace66b1 NM |
76 | u8 data_first_reg; |
77 | u8 data_last_reg; | |
8e560862 | 78 | u32 status_cnt_mask; |
a2b79838 | 79 | u32 status_err_mask; |
aace66b1 NM |
80 | bool tx_polled; |
81 | int tx_poll_timeout_ms; | |
82 | const struct ti_msgmgr_valid_queue_desc *valid_queues; | |
89c976c2 NM |
83 | const char *data_region_name; |
84 | const char *status_region_name; | |
a2b79838 | 85 | const char *ctrl_region_name; |
aace66b1 | 86 | int num_valid_queues; |
a2b79838 | 87 | bool is_sproxy; |
aace66b1 NM |
88 | }; |
89 | ||
90 | /** | |
91 | * struct ti_queue_inst - Description of a queue instance | |
92 | * @name: Queue Name | |
93 | * @queue_id: Queue Identifier as mapped on SoC | |
94 | * @proxy_id: Proxy Identifier as mapped on SoC | |
95 | * @irq: IRQ for Rx Queue | |
96 | * @is_tx: 'true' if transmit queue, else, 'false' | |
97 | * @queue_buff_start: First register of Data Buffer | |
98 | * @queue_buff_end: Last (or confirmation) register of Data buffer | |
99 | * @queue_state: Queue status register | |
a2b79838 | 100 | * @queue_ctrl: Queue Control register |
aace66b1 NM |
101 | * @chan: Mailbox channel |
102 | * @rx_buff: Receive buffer pointer allocated at probe, max_message_size | |
103 | */ | |
104 | struct ti_queue_inst { | |
105 | char name[30]; | |
106 | u8 queue_id; | |
107 | u8 proxy_id; | |
108 | int irq; | |
109 | bool is_tx; | |
110 | void __iomem *queue_buff_start; | |
111 | void __iomem *queue_buff_end; | |
112 | void __iomem *queue_state; | |
a2b79838 | 113 | void __iomem *queue_ctrl; |
aace66b1 NM |
114 | struct mbox_chan *chan; |
115 | u32 *rx_buff; | |
116 | }; | |
117 | ||
118 | /** | |
119 | * struct ti_msgmgr_inst - Description of a Message Manager Instance | |
120 | * @dev: device pointer corresponding to the Message Manager instance | |
121 | * @desc: Description of the SoC integration | |
122 | * @queue_proxy_region: Queue proxy region where queue buffers are located | |
123 | * @queue_state_debug_region: Queue status register regions | |
a2b79838 | 124 | * @queue_ctrl_region: Queue Control register regions |
aace66b1 NM |
125 | * @num_valid_queues: Number of valid queues defined for the processor |
126 | * Note: other queues are probably reserved for other processors | |
127 | * in the SoC. | |
128 | * @qinsts: Array of valid Queue Instances for the Processor | |
129 | * @mbox: Mailbox Controller | |
130 | * @chans: Array for channels corresponding to the Queue Instances. | |
131 | */ | |
132 | struct ti_msgmgr_inst { | |
133 | struct device *dev; | |
134 | const struct ti_msgmgr_desc *desc; | |
135 | void __iomem *queue_proxy_region; | |
136 | void __iomem *queue_state_debug_region; | |
a2b79838 | 137 | void __iomem *queue_ctrl_region; |
aace66b1 NM |
138 | u8 num_valid_queues; |
139 | struct ti_queue_inst *qinsts; | |
140 | struct mbox_controller mbox; | |
141 | struct mbox_chan *chans; | |
142 | }; | |
143 | ||
144 | /** | |
145 | * ti_msgmgr_queue_get_num_messages() - Get the number of pending messages | |
8e560862 | 146 | * @d: Description of message manager |
aace66b1 NM |
147 | * @qinst: Queue instance for which we check the number of pending messages |
148 | * | |
149 | * Return: number of messages pending in the queue (0 == no pending messages) | |
150 | */ | |
8e560862 NM |
151 | static inline int |
152 | ti_msgmgr_queue_get_num_messages(const struct ti_msgmgr_desc *d, | |
153 | struct ti_queue_inst *qinst) | |
aace66b1 NM |
154 | { |
155 | u32 val; | |
8e560862 | 156 | u32 status_cnt_mask = d->status_cnt_mask; |
aace66b1 NM |
157 | |
158 | /* | |
159 | * We cannot use relaxed operation here - update may happen | |
160 | * real-time. | |
161 | */ | |
8e560862 NM |
162 | val = readl(qinst->queue_state) & status_cnt_mask; |
163 | val >>= __ffs(status_cnt_mask); | |
aace66b1 NM |
164 | |
165 | return val; | |
166 | } | |
167 | ||
a2b79838 NM |
168 | /** |
169 | * ti_msgmgr_queue_is_error() - Check to see if there is queue error | |
170 | * @d: Description of message manager | |
171 | * @qinst: Queue instance for which we check the number of pending messages | |
172 | * | |
173 | * Return: true if error, else false | |
174 | */ | |
175 | static inline bool ti_msgmgr_queue_is_error(const struct ti_msgmgr_desc *d, | |
176 | struct ti_queue_inst *qinst) | |
177 | { | |
178 | u32 val; | |
179 | ||
180 | /* Msgmgr has no error detection */ | |
181 | if (!d->is_sproxy) | |
182 | return false; | |
183 | ||
184 | /* | |
185 | * We cannot use relaxed operation here - update may happen | |
186 | * real-time. | |
187 | */ | |
188 | val = readl(qinst->queue_state) & d->status_err_mask; | |
189 | ||
190 | return val ? true : false; | |
191 | } | |
192 | ||
aace66b1 NM |
193 | /** |
194 | * ti_msgmgr_queue_rx_interrupt() - Interrupt handler for receive Queue | |
195 | * @irq: Interrupt number | |
196 | * @p: Channel Pointer | |
197 | * | |
198 | * Return: -EINVAL if there is no instance | |
199 | * IRQ_NONE if the interrupt is not ours. | |
200 | * IRQ_HANDLED if the rx interrupt was successfully handled. | |
201 | */ | |
202 | static irqreturn_t ti_msgmgr_queue_rx_interrupt(int irq, void *p) | |
203 | { | |
204 | struct mbox_chan *chan = p; | |
205 | struct device *dev = chan->mbox->dev; | |
206 | struct ti_msgmgr_inst *inst = dev_get_drvdata(dev); | |
207 | struct ti_queue_inst *qinst = chan->con_priv; | |
208 | const struct ti_msgmgr_desc *desc; | |
209 | int msg_count, num_words; | |
210 | struct ti_msgmgr_message message; | |
211 | void __iomem *data_reg; | |
212 | u32 *word_data; | |
213 | ||
214 | if (WARN_ON(!inst)) { | |
215 | dev_err(dev, "no platform drv data??\n"); | |
216 | return -EINVAL; | |
217 | } | |
218 | ||
219 | /* Do I have an invalid interrupt source? */ | |
220 | if (qinst->is_tx) { | |
221 | dev_err(dev, "Cannot handle rx interrupt on tx channel %s\n", | |
222 | qinst->name); | |
223 | return IRQ_NONE; | |
224 | } | |
225 | ||
8e560862 | 226 | desc = inst->desc; |
a2b79838 NM |
227 | if (ti_msgmgr_queue_is_error(desc, qinst)) { |
228 | dev_err(dev, "Error on Rx channel %s\n", qinst->name); | |
229 | return IRQ_NONE; | |
230 | } | |
231 | ||
aace66b1 | 232 | /* Do I actually have messages to read? */ |
8e560862 | 233 | msg_count = ti_msgmgr_queue_get_num_messages(desc, qinst); |
aace66b1 NM |
234 | if (!msg_count) { |
235 | /* Shared IRQ? */ | |
236 | dev_dbg(dev, "Spurious event - 0 pending data!\n"); | |
237 | return IRQ_NONE; | |
238 | } | |
239 | ||
240 | /* | |
241 | * I have no idea about the protocol being used to communicate with the | |
242 | * remote producer - 0 could be valid data, so I wont make a judgement | |
243 | * of how many bytes I should be reading. Let the client figure this | |
244 | * out.. I just read the full message and pass it on.. | |
245 | */ | |
aace66b1 NM |
246 | message.len = desc->max_message_size; |
247 | message.buf = (u8 *)qinst->rx_buff; | |
248 | ||
249 | /* | |
250 | * NOTE about register access involved here: | |
251 | * the hardware block is implemented with 32bit access operations and no | |
252 | * support for data splitting. We don't want the hardware to misbehave | |
253 | * with sub 32bit access - For example: if the last register read is | |
254 | * split into byte wise access, it can result in the queue getting | |
255 | * stuck or indeterminate behavior. An out of order read operation may | |
256 | * result in weird data results as well. | |
257 | * Hence, we do not use memcpy_fromio or __ioread32_copy here, instead | |
258 | * we depend on readl for the purpose. | |
259 | * | |
260 | * Also note that the final register read automatically marks the | |
261 | * queue message as read. | |
262 | */ | |
263 | for (data_reg = qinst->queue_buff_start, word_data = qinst->rx_buff, | |
264 | num_words = (desc->max_message_size / sizeof(u32)); | |
265 | num_words; num_words--, data_reg += sizeof(u32), word_data++) | |
266 | *word_data = readl(data_reg); | |
267 | ||
268 | /* | |
269 | * Last register read automatically clears the IRQ if only 1 message | |
270 | * is pending - so send the data up the stack.. | |
271 | * NOTE: Client is expected to be as optimal as possible, since | |
272 | * we invoke the handler in IRQ context. | |
273 | */ | |
274 | mbox_chan_received_data(chan, (void *)&message); | |
275 | ||
276 | return IRQ_HANDLED; | |
277 | } | |
278 | ||
279 | /** | |
280 | * ti_msgmgr_queue_peek_data() - Peek to see if there are any rx messages. | |
281 | * @chan: Channel Pointer | |
282 | * | |
283 | * Return: 'true' if there is pending rx data, 'false' if there is none. | |
284 | */ | |
285 | static bool ti_msgmgr_queue_peek_data(struct mbox_chan *chan) | |
286 | { | |
287 | struct ti_queue_inst *qinst = chan->con_priv; | |
8e560862 NM |
288 | struct device *dev = chan->mbox->dev; |
289 | struct ti_msgmgr_inst *inst = dev_get_drvdata(dev); | |
a2b79838 | 290 | const struct ti_msgmgr_desc *desc = inst->desc; |
aace66b1 NM |
291 | int msg_count; |
292 | ||
293 | if (qinst->is_tx) | |
294 | return false; | |
295 | ||
a2b79838 NM |
296 | if (ti_msgmgr_queue_is_error(desc, qinst)) { |
297 | dev_err(dev, "Error on channel %s\n", qinst->name); | |
298 | return false; | |
299 | } | |
300 | ||
301 | msg_count = ti_msgmgr_queue_get_num_messages(desc, qinst); | |
aace66b1 NM |
302 | |
303 | return msg_count ? true : false; | |
304 | } | |
305 | ||
306 | /** | |
307 | * ti_msgmgr_last_tx_done() - See if all the tx messages are sent | |
308 | * @chan: Channel pointer | |
309 | * | |
310 | * Return: 'true' is no pending tx data, 'false' if there are any. | |
311 | */ | |
312 | static bool ti_msgmgr_last_tx_done(struct mbox_chan *chan) | |
313 | { | |
314 | struct ti_queue_inst *qinst = chan->con_priv; | |
8e560862 NM |
315 | struct device *dev = chan->mbox->dev; |
316 | struct ti_msgmgr_inst *inst = dev_get_drvdata(dev); | |
a2b79838 | 317 | const struct ti_msgmgr_desc *desc = inst->desc; |
aace66b1 NM |
318 | int msg_count; |
319 | ||
320 | if (!qinst->is_tx) | |
321 | return false; | |
322 | ||
a2b79838 NM |
323 | if (ti_msgmgr_queue_is_error(desc, qinst)) { |
324 | dev_err(dev, "Error on channel %s\n", qinst->name); | |
325 | return false; | |
326 | } | |
327 | ||
328 | msg_count = ti_msgmgr_queue_get_num_messages(desc, qinst); | |
329 | ||
330 | if (desc->is_sproxy) { | |
331 | /* In secure proxy, msg_count indicates how many we can send */ | |
332 | return msg_count ? true : false; | |
333 | } | |
aace66b1 NM |
334 | |
335 | /* if we have any messages pending.. */ | |
336 | return msg_count ? false : true; | |
337 | } | |
338 | ||
339 | /** | |
340 | * ti_msgmgr_send_data() - Send data | |
341 | * @chan: Channel Pointer | |
342 | * @data: ti_msgmgr_message * Message Pointer | |
343 | * | |
344 | * Return: 0 if all goes good, else appropriate error messages. | |
345 | */ | |
346 | static int ti_msgmgr_send_data(struct mbox_chan *chan, void *data) | |
347 | { | |
348 | struct device *dev = chan->mbox->dev; | |
349 | struct ti_msgmgr_inst *inst = dev_get_drvdata(dev); | |
350 | const struct ti_msgmgr_desc *desc; | |
351 | struct ti_queue_inst *qinst = chan->con_priv; | |
352 | int num_words, trail_bytes; | |
353 | struct ti_msgmgr_message *message = data; | |
354 | void __iomem *data_reg; | |
355 | u32 *word_data; | |
356 | ||
357 | if (WARN_ON(!inst)) { | |
358 | dev_err(dev, "no platform drv data??\n"); | |
359 | return -EINVAL; | |
360 | } | |
361 | desc = inst->desc; | |
362 | ||
a2b79838 NM |
363 | if (ti_msgmgr_queue_is_error(desc, qinst)) { |
364 | dev_err(dev, "Error on channel %s\n", qinst->name); | |
365 | return false; | |
366 | } | |
367 | ||
aace66b1 | 368 | if (desc->max_message_size < message->len) { |
ca64af43 | 369 | dev_err(dev, "Queue %s message length %zu > max %d\n", |
aace66b1 NM |
370 | qinst->name, message->len, desc->max_message_size); |
371 | return -EINVAL; | |
372 | } | |
373 | ||
374 | /* NOTE: Constraints similar to rx path exists here as well */ | |
375 | for (data_reg = qinst->queue_buff_start, | |
376 | num_words = message->len / sizeof(u32), | |
377 | word_data = (u32 *)message->buf; | |
378 | num_words; num_words--, data_reg += sizeof(u32), word_data++) | |
379 | writel(*word_data, data_reg); | |
380 | ||
381 | trail_bytes = message->len % sizeof(u32); | |
382 | if (trail_bytes) { | |
383 | u32 data_trail = *word_data; | |
384 | ||
385 | /* Ensure all unused data is 0 */ | |
386 | data_trail &= 0xFFFFFFFF >> (8 * (sizeof(u32) - trail_bytes)); | |
387 | writel(data_trail, data_reg); | |
388 | data_reg++; | |
389 | } | |
390 | /* | |
391 | * 'data_reg' indicates next register to write. If we did not already | |
392 | * write on tx complete reg(last reg), we must do so for transmit | |
393 | */ | |
394 | if (data_reg <= qinst->queue_buff_end) | |
395 | writel(0, qinst->queue_buff_end); | |
396 | ||
397 | return 0; | |
398 | } | |
399 | ||
5ab935e1 NM |
400 | /** |
401 | * ti_msgmgr_queue_rx_irq_req() - RX IRQ request | |
402 | * @dev: device pointer | |
a2b79838 | 403 | * @d: descriptor for ti_msgmgr |
5ab935e1 NM |
404 | * @qinst: Queue instance |
405 | * @chan: Channel pointer | |
406 | */ | |
407 | static int ti_msgmgr_queue_rx_irq_req(struct device *dev, | |
a2b79838 | 408 | const struct ti_msgmgr_desc *d, |
5ab935e1 NM |
409 | struct ti_queue_inst *qinst, |
410 | struct mbox_chan *chan) | |
411 | { | |
412 | int ret = 0; | |
413 | char of_rx_irq_name[7]; | |
414 | struct device_node *np; | |
415 | ||
416 | snprintf(of_rx_irq_name, sizeof(of_rx_irq_name), | |
a2b79838 | 417 | "rx_%03d", d->is_sproxy ? qinst->proxy_id : qinst->queue_id); |
5ab935e1 NM |
418 | |
419 | /* Get the IRQ if not found */ | |
420 | if (qinst->irq < 0) { | |
421 | np = of_node_get(dev->of_node); | |
422 | if (!np) | |
423 | return -ENODATA; | |
424 | qinst->irq = of_irq_get_byname(np, of_rx_irq_name); | |
425 | of_node_put(np); | |
426 | ||
427 | if (qinst->irq < 0) { | |
428 | dev_err(dev, | |
429 | "QID %d PID %d:No IRQ[%s]: %d\n", | |
430 | qinst->queue_id, qinst->proxy_id, | |
431 | of_rx_irq_name, qinst->irq); | |
432 | return qinst->irq; | |
433 | } | |
434 | } | |
435 | ||
436 | /* With the expectation that the IRQ might be shared in SoC */ | |
437 | ret = request_irq(qinst->irq, ti_msgmgr_queue_rx_interrupt, | |
438 | IRQF_SHARED, qinst->name, chan); | |
439 | if (ret) { | |
440 | dev_err(dev, "Unable to get IRQ %d on %s(res=%d)\n", | |
441 | qinst->irq, qinst->name, ret); | |
442 | } | |
443 | ||
444 | return ret; | |
445 | } | |
446 | ||
aace66b1 NM |
447 | /** |
448 | * ti_msgmgr_queue_startup() - Startup queue | |
449 | * @chan: Channel pointer | |
450 | * | |
451 | * Return: 0 if all goes good, else return corresponding error message | |
452 | */ | |
453 | static int ti_msgmgr_queue_startup(struct mbox_chan *chan) | |
454 | { | |
aace66b1 | 455 | struct device *dev = chan->mbox->dev; |
5ab935e1 NM |
456 | struct ti_msgmgr_inst *inst = dev_get_drvdata(dev); |
457 | struct ti_queue_inst *qinst = chan->con_priv; | |
458 | const struct ti_msgmgr_desc *d = inst->desc; | |
aace66b1 | 459 | int ret; |
a2b79838 NM |
460 | int msg_count; |
461 | ||
462 | /* | |
463 | * If sproxy is starting and can send messages, we are a Tx thread, | |
464 | * else Rx | |
465 | */ | |
466 | if (d->is_sproxy) { | |
467 | qinst->is_tx = (readl(qinst->queue_ctrl) & | |
468 | SPROXY_THREAD_CTRL_DIR_MASK) ? false : true; | |
469 | ||
470 | msg_count = ti_msgmgr_queue_get_num_messages(d, qinst); | |
471 | ||
472 | if (!msg_count && qinst->is_tx) { | |
473 | dev_err(dev, "%s: Cannot transmit with 0 credits!\n", | |
474 | qinst->name); | |
475 | return -EINVAL; | |
476 | } | |
477 | } | |
aace66b1 NM |
478 | |
479 | if (!qinst->is_tx) { | |
5ab935e1 NM |
480 | /* Allocate usage buffer for rx */ |
481 | qinst->rx_buff = kzalloc(d->max_message_size, GFP_KERNEL); | |
482 | if (!qinst->rx_buff) | |
483 | return -ENOMEM; | |
484 | /* Request IRQ */ | |
a2b79838 | 485 | ret = ti_msgmgr_queue_rx_irq_req(dev, d, qinst, chan); |
aace66b1 | 486 | if (ret) { |
5ab935e1 | 487 | kfree(qinst->rx_buff); |
aace66b1 NM |
488 | return ret; |
489 | } | |
490 | } | |
491 | ||
492 | return 0; | |
493 | } | |
494 | ||
495 | /** | |
496 | * ti_msgmgr_queue_shutdown() - Shutdown the queue | |
497 | * @chan: Channel pointer | |
498 | */ | |
499 | static void ti_msgmgr_queue_shutdown(struct mbox_chan *chan) | |
500 | { | |
501 | struct ti_queue_inst *qinst = chan->con_priv; | |
502 | ||
5ab935e1 | 503 | if (!qinst->is_tx) { |
aace66b1 | 504 | free_irq(qinst->irq, chan); |
5ab935e1 NM |
505 | kfree(qinst->rx_buff); |
506 | } | |
aace66b1 NM |
507 | } |
508 | ||
509 | /** | |
510 | * ti_msgmgr_of_xlate() - Translation of phandle to queue | |
511 | * @mbox: Mailbox controller | |
512 | * @p: phandle pointer | |
513 | * | |
514 | * Return: Mailbox channel corresponding to the queue, else return error | |
515 | * pointer. | |
516 | */ | |
517 | static struct mbox_chan *ti_msgmgr_of_xlate(struct mbox_controller *mbox, | |
518 | const struct of_phandle_args *p) | |
519 | { | |
520 | struct ti_msgmgr_inst *inst; | |
521 | int req_qid, req_pid; | |
522 | struct ti_queue_inst *qinst; | |
a2b79838 NM |
523 | const struct ti_msgmgr_desc *d; |
524 | int i, ncells; | |
aace66b1 NM |
525 | |
526 | inst = container_of(mbox, struct ti_msgmgr_inst, mbox); | |
527 | if (WARN_ON(!inst)) | |
528 | return ERR_PTR(-EINVAL); | |
529 | ||
a2b79838 NM |
530 | d = inst->desc; |
531 | ||
532 | if (d->is_sproxy) | |
533 | ncells = 1; | |
534 | else | |
535 | ncells = 2; | |
536 | if (p->args_count != ncells) { | |
537 | dev_err(inst->dev, "Invalid arguments in dt[%d]. Must be %d\n", | |
538 | p->args_count, ncells); | |
aace66b1 NM |
539 | return ERR_PTR(-EINVAL); |
540 | } | |
a2b79838 NM |
541 | if (ncells == 1) { |
542 | req_qid = 0; | |
543 | req_pid = p->args[0]; | |
544 | } else { | |
545 | req_qid = p->args[0]; | |
546 | req_pid = p->args[1]; | |
547 | } | |
548 | ||
549 | if (d->is_sproxy) { | |
78f3ff52 | 550 | if (req_pid >= d->num_valid_queues) |
a2b79838 NM |
551 | goto err; |
552 | qinst = &inst->qinsts[req_pid]; | |
553 | return qinst->chan; | |
554 | } | |
aace66b1 NM |
555 | |
556 | for (qinst = inst->qinsts, i = 0; i < inst->num_valid_queues; | |
557 | i++, qinst++) { | |
558 | if (req_qid == qinst->queue_id && req_pid == qinst->proxy_id) | |
559 | return qinst->chan; | |
560 | } | |
561 | ||
a2b79838 | 562 | err: |
94927676 RH |
563 | dev_err(inst->dev, "Queue ID %d, Proxy ID %d is wrong on %pOFn\n", |
564 | req_qid, req_pid, p->np); | |
aace66b1 NM |
565 | return ERR_PTR(-ENOENT); |
566 | } | |
567 | ||
568 | /** | |
569 | * ti_msgmgr_queue_setup() - Setup data structures for each queue instance | |
570 | * @idx: index of the queue | |
571 | * @dev: pointer to the message manager device | |
572 | * @np: pointer to the of node | |
573 | * @inst: Queue instance pointer | |
574 | * @d: Message Manager instance description data | |
575 | * @qd: Queue description data | |
576 | * @qinst: Queue instance pointer | |
577 | * @chan: pointer to mailbox channel | |
578 | * | |
579 | * Return: 0 if all went well, else return corresponding error | |
580 | */ | |
581 | static int ti_msgmgr_queue_setup(int idx, struct device *dev, | |
582 | struct device_node *np, | |
583 | struct ti_msgmgr_inst *inst, | |
584 | const struct ti_msgmgr_desc *d, | |
585 | const struct ti_msgmgr_valid_queue_desc *qd, | |
586 | struct ti_queue_inst *qinst, | |
587 | struct mbox_chan *chan) | |
588 | { | |
a2b79838 NM |
589 | char *dir; |
590 | ||
aace66b1 NM |
591 | qinst->proxy_id = qd->proxy_id; |
592 | qinst->queue_id = qd->queue_id; | |
593 | ||
594 | if (qinst->queue_id > d->queue_count) { | |
595 | dev_err(dev, "Queue Data [idx=%d] queuid %d > %d\n", | |
596 | idx, qinst->queue_id, d->queue_count); | |
597 | return -ERANGE; | |
598 | } | |
599 | ||
a2b79838 NM |
600 | if (d->is_sproxy) { |
601 | qinst->queue_buff_start = inst->queue_proxy_region + | |
602 | SPROXY_THREAD_DATA_OFFSET(qinst->proxy_id, | |
603 | d->data_first_reg); | |
604 | qinst->queue_buff_end = inst->queue_proxy_region + | |
605 | SPROXY_THREAD_DATA_OFFSET(qinst->proxy_id, | |
606 | d->data_last_reg); | |
607 | qinst->queue_state = inst->queue_state_debug_region + | |
608 | SPROXY_THREAD_STATUS_OFFSET(qinst->proxy_id); | |
609 | qinst->queue_ctrl = inst->queue_ctrl_region + | |
610 | SPROXY_THREAD_CTRL_OFFSET(qinst->proxy_id); | |
611 | ||
612 | /* XXX: DONOT read registers here!.. Some may be unusable */ | |
613 | dir = "thr"; | |
614 | snprintf(qinst->name, sizeof(qinst->name), "%s %s_%03d", | |
615 | dev_name(dev), dir, qinst->proxy_id); | |
616 | } else { | |
617 | qinst->queue_buff_start = inst->queue_proxy_region + | |
618 | Q_DATA_OFFSET(qinst->proxy_id, qinst->queue_id, | |
619 | d->data_first_reg); | |
620 | qinst->queue_buff_end = inst->queue_proxy_region + | |
621 | Q_DATA_OFFSET(qinst->proxy_id, qinst->queue_id, | |
622 | d->data_last_reg); | |
623 | qinst->queue_state = | |
624 | inst->queue_state_debug_region + | |
625 | Q_STATE_OFFSET(qinst->queue_id); | |
626 | qinst->is_tx = qd->is_tx; | |
627 | dir = qinst->is_tx ? "tx" : "rx"; | |
628 | snprintf(qinst->name, sizeof(qinst->name), "%s %s_%03d_%03d", | |
629 | dev_name(dev), dir, qinst->queue_id, qinst->proxy_id); | |
630 | } | |
631 | ||
aace66b1 NM |
632 | qinst->chan = chan; |
633 | ||
5ab935e1 NM |
634 | /* Setup an error value for IRQ - Lazy allocation */ |
635 | qinst->irq = -EINVAL; | |
636 | ||
aace66b1 NM |
637 | chan->con_priv = qinst; |
638 | ||
639 | dev_dbg(dev, "[%d] qidx=%d pidx=%d irq=%d q_s=%p q_e = %p\n", | |
640 | idx, qinst->queue_id, qinst->proxy_id, qinst->irq, | |
641 | qinst->queue_buff_start, qinst->queue_buff_end); | |
642 | return 0; | |
643 | } | |
644 | ||
645 | /* Queue operations */ | |
646 | static const struct mbox_chan_ops ti_msgmgr_chan_ops = { | |
647 | .startup = ti_msgmgr_queue_startup, | |
648 | .shutdown = ti_msgmgr_queue_shutdown, | |
649 | .peek_data = ti_msgmgr_queue_peek_data, | |
650 | .last_tx_done = ti_msgmgr_last_tx_done, | |
651 | .send_data = ti_msgmgr_send_data, | |
652 | }; | |
653 | ||
654 | /* Keystone K2G SoC integration details */ | |
655 | static const struct ti_msgmgr_valid_queue_desc k2g_valid_queues[] = { | |
656 | {.queue_id = 0, .proxy_id = 0, .is_tx = true,}, | |
657 | {.queue_id = 1, .proxy_id = 0, .is_tx = true,}, | |
658 | {.queue_id = 2, .proxy_id = 0, .is_tx = true,}, | |
659 | {.queue_id = 3, .proxy_id = 0, .is_tx = true,}, | |
660 | {.queue_id = 5, .proxy_id = 2, .is_tx = false,}, | |
661 | {.queue_id = 56, .proxy_id = 1, .is_tx = true,}, | |
662 | {.queue_id = 57, .proxy_id = 2, .is_tx = false,}, | |
663 | {.queue_id = 58, .proxy_id = 3, .is_tx = true,}, | |
664 | {.queue_id = 59, .proxy_id = 4, .is_tx = true,}, | |
665 | {.queue_id = 60, .proxy_id = 5, .is_tx = true,}, | |
666 | {.queue_id = 61, .proxy_id = 6, .is_tx = true,}, | |
667 | }; | |
668 | ||
669 | static const struct ti_msgmgr_desc k2g_desc = { | |
670 | .queue_count = 64, | |
671 | .max_message_size = 64, | |
672 | .max_messages = 128, | |
89c976c2 NM |
673 | .data_region_name = "queue_proxy_region", |
674 | .status_region_name = "queue_state_debug_region", | |
aace66b1 NM |
675 | .data_first_reg = 16, |
676 | .data_last_reg = 31, | |
8e560862 | 677 | .status_cnt_mask = Q_STATE_ENTRY_COUNT_MASK, |
aace66b1 NM |
678 | .tx_polled = false, |
679 | .valid_queues = k2g_valid_queues, | |
680 | .num_valid_queues = ARRAY_SIZE(k2g_valid_queues), | |
a2b79838 NM |
681 | .is_sproxy = false, |
682 | }; | |
683 | ||
684 | static const struct ti_msgmgr_desc am654_desc = { | |
685 | .queue_count = 190, | |
686 | .num_valid_queues = 190, | |
687 | .max_message_size = 60, | |
688 | .data_region_name = "target_data", | |
689 | .status_region_name = "rt", | |
690 | .ctrl_region_name = "scfg", | |
691 | .data_first_reg = 0, | |
692 | .data_last_reg = 14, | |
693 | .status_cnt_mask = SPROXY_THREAD_STATUS_COUNT_MASK, | |
694 | .tx_polled = false, | |
695 | .is_sproxy = true, | |
aace66b1 NM |
696 | }; |
697 | ||
698 | static const struct of_device_id ti_msgmgr_of_match[] = { | |
699 | {.compatible = "ti,k2g-message-manager", .data = &k2g_desc}, | |
a2b79838 | 700 | {.compatible = "ti,am654-secure-proxy", .data = &am654_desc}, |
aace66b1 NM |
701 | { /* Sentinel */ } |
702 | }; | |
a2b79838 | 703 | |
aace66b1 NM |
704 | MODULE_DEVICE_TABLE(of, ti_msgmgr_of_match); |
705 | ||
706 | static int ti_msgmgr_probe(struct platform_device *pdev) | |
707 | { | |
708 | struct device *dev = &pdev->dev; | |
709 | const struct of_device_id *of_id; | |
710 | struct device_node *np; | |
711 | struct resource *res; | |
712 | const struct ti_msgmgr_desc *desc; | |
713 | struct ti_msgmgr_inst *inst; | |
714 | struct ti_queue_inst *qinst; | |
715 | struct mbox_controller *mbox; | |
716 | struct mbox_chan *chans; | |
717 | int queue_count; | |
718 | int i; | |
719 | int ret = -EINVAL; | |
720 | const struct ti_msgmgr_valid_queue_desc *queue_desc; | |
721 | ||
722 | if (!dev->of_node) { | |
723 | dev_err(dev, "no OF information\n"); | |
724 | return -EINVAL; | |
725 | } | |
726 | np = dev->of_node; | |
727 | ||
728 | of_id = of_match_device(ti_msgmgr_of_match, dev); | |
729 | if (!of_id) { | |
730 | dev_err(dev, "OF data missing\n"); | |
731 | return -EINVAL; | |
732 | } | |
733 | desc = of_id->data; | |
734 | ||
735 | inst = devm_kzalloc(dev, sizeof(*inst), GFP_KERNEL); | |
736 | if (!inst) | |
737 | return -ENOMEM; | |
738 | ||
739 | inst->dev = dev; | |
740 | inst->desc = desc; | |
741 | ||
742 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, | |
89c976c2 | 743 | desc->data_region_name); |
aace66b1 NM |
744 | inst->queue_proxy_region = devm_ioremap_resource(dev, res); |
745 | if (IS_ERR(inst->queue_proxy_region)) | |
746 | return PTR_ERR(inst->queue_proxy_region); | |
747 | ||
748 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, | |
89c976c2 | 749 | desc->status_region_name); |
aace66b1 NM |
750 | inst->queue_state_debug_region = devm_ioremap_resource(dev, res); |
751 | if (IS_ERR(inst->queue_state_debug_region)) | |
752 | return PTR_ERR(inst->queue_state_debug_region); | |
753 | ||
a2b79838 NM |
754 | if (desc->is_sproxy) { |
755 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, | |
756 | desc->ctrl_region_name); | |
757 | inst->queue_ctrl_region = devm_ioremap_resource(dev, res); | |
758 | if (IS_ERR(inst->queue_ctrl_region)) | |
759 | return PTR_ERR(inst->queue_ctrl_region); | |
760 | } | |
761 | ||
aace66b1 NM |
762 | dev_dbg(dev, "proxy region=%p, queue_state=%p\n", |
763 | inst->queue_proxy_region, inst->queue_state_debug_region); | |
764 | ||
765 | queue_count = desc->num_valid_queues; | |
766 | if (!queue_count || queue_count > desc->queue_count) { | |
767 | dev_crit(dev, "Invalid Number of queues %d. Max %d\n", | |
768 | queue_count, desc->queue_count); | |
769 | return -ERANGE; | |
770 | } | |
771 | inst->num_valid_queues = queue_count; | |
772 | ||
a86854d0 | 773 | qinst = devm_kcalloc(dev, queue_count, sizeof(*qinst), GFP_KERNEL); |
aace66b1 NM |
774 | if (!qinst) |
775 | return -ENOMEM; | |
776 | inst->qinsts = qinst; | |
777 | ||
a86854d0 | 778 | chans = devm_kcalloc(dev, queue_count, sizeof(*chans), GFP_KERNEL); |
aace66b1 NM |
779 | if (!chans) |
780 | return -ENOMEM; | |
781 | inst->chans = chans; | |
782 | ||
a2b79838 NM |
783 | if (desc->is_sproxy) { |
784 | struct ti_msgmgr_valid_queue_desc sproxy_desc; | |
785 | ||
786 | /* All proxies may be valid in Secure Proxy instance */ | |
787 | for (i = 0; i < queue_count; i++, qinst++, chans++) { | |
788 | sproxy_desc.queue_id = 0; | |
789 | sproxy_desc.proxy_id = i; | |
790 | ret = ti_msgmgr_queue_setup(i, dev, np, inst, | |
791 | desc, &sproxy_desc, qinst, | |
792 | chans); | |
793 | if (ret) | |
794 | return ret; | |
795 | } | |
796 | } else { | |
797 | /* Only Some proxies are valid in Message Manager */ | |
798 | for (i = 0, queue_desc = desc->valid_queues; | |
799 | i < queue_count; i++, qinst++, chans++, queue_desc++) { | |
800 | ret = ti_msgmgr_queue_setup(i, dev, np, inst, | |
801 | desc, queue_desc, qinst, | |
802 | chans); | |
803 | if (ret) | |
804 | return ret; | |
805 | } | |
aace66b1 NM |
806 | } |
807 | ||
808 | mbox = &inst->mbox; | |
809 | mbox->dev = dev; | |
810 | mbox->ops = &ti_msgmgr_chan_ops; | |
811 | mbox->chans = inst->chans; | |
812 | mbox->num_chans = inst->num_valid_queues; | |
813 | mbox->txdone_irq = false; | |
814 | mbox->txdone_poll = desc->tx_polled; | |
815 | if (desc->tx_polled) | |
816 | mbox->txpoll_period = desc->tx_poll_timeout_ms; | |
817 | mbox->of_xlate = ti_msgmgr_of_xlate; | |
818 | ||
819 | platform_set_drvdata(pdev, inst); | |
2298a6f0 | 820 | ret = devm_mbox_controller_register(dev, mbox); |
aace66b1 NM |
821 | if (ret) |
822 | dev_err(dev, "Failed to register mbox_controller(%d)\n", ret); | |
823 | ||
824 | return ret; | |
825 | } | |
826 | ||
aace66b1 NM |
827 | static struct platform_driver ti_msgmgr_driver = { |
828 | .probe = ti_msgmgr_probe, | |
aace66b1 NM |
829 | .driver = { |
830 | .name = "ti-msgmgr", | |
831 | .of_match_table = of_match_ptr(ti_msgmgr_of_match), | |
832 | }, | |
833 | }; | |
834 | module_platform_driver(ti_msgmgr_driver); | |
835 | ||
836 | MODULE_LICENSE("GPL v2"); | |
837 | MODULE_DESCRIPTION("TI message manager driver"); | |
838 | MODULE_AUTHOR("Nishanth Menon"); | |
839 | MODULE_ALIAS("platform:ti-msgmgr"); |