[linux-block.git] / drivers / mailbox / stm32-ipcc.c

// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (C) STMicroelectronics 2018 - All Rights Reserved
 * Authors: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
 *          Fabien Dessenne <fabien.dessenne@st.com> for STMicroelectronics.
 */

#include <linux/bitfield.h>
#include <linux/clk.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/mailbox_controller.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/pm_wakeirq.h>

#define IPCC_XCR		0x000
#define XCR_RXOIE		BIT(0)
#define XCR_TXOIE		BIT(16)

#define IPCC_XMR		0x004
#define IPCC_XSCR		0x008
#define IPCC_XTOYSR		0x00c

#define IPCC_PROC_OFFST		0x010

#define IPCC_HWCFGR		0x3f0
#define IPCFGR_CHAN_MASK	GENMASK(7, 0)

#define IPCC_VER		0x3f4
#define VER_MINREV_MASK		GENMASK(3, 0)
#define VER_MAJREV_MASK		GENMASK(7, 4)

#define RX_BIT_MASK		GENMASK(15, 0)
#define RX_BIT_CHAN(chan)	BIT(chan)
#define TX_BIT_SHIFT		16
#define TX_BIT_MASK		GENMASK(31, 16)
#define TX_BIT_CHAN(chan)	BIT(TX_BIT_SHIFT + (chan))

#define STM32_MAX_PROCS		2

enum {
	IPCC_IRQ_RX,
	IPCC_IRQ_TX,
	IPCC_IRQ_NUM,
};

struct stm32_ipcc {
	struct mbox_controller controller;
	void __iomem *reg_base;
	void __iomem *reg_proc;
	struct clk *clk;
	spinlock_t lock; /* protect access to IPCC registers */
	int irqs[IPCC_IRQ_NUM];
	u32 proc_id;
	u32 n_chans;
	u32 xcr;
	u32 xmr;
};

static inline void stm32_ipcc_set_bits(spinlock_t *lock, void __iomem *reg,
				       u32 mask)
{
	unsigned long flags;

	spin_lock_irqsave(lock, flags);
	writel_relaxed(readl_relaxed(reg) | mask, reg);
	spin_unlock_irqrestore(lock, flags);
}

static inline void stm32_ipcc_clr_bits(spinlock_t *lock, void __iomem *reg,
				       u32 mask)
{
	unsigned long flags;

	spin_lock_irqsave(lock, flags);
	writel_relaxed(readl_relaxed(reg) & ~mask, reg);
	spin_unlock_irqrestore(lock, flags);
}

static irqreturn_t stm32_ipcc_rx_irq(int irq, void *data)
{
	struct stm32_ipcc *ipcc = data;
	struct device *dev = ipcc->controller.dev;
	u32 status, mr, tosr, chan;
	irqreturn_t ret = IRQ_NONE;
	int proc_offset;

	/* read 'channel occupied' status from other proc */
	proc_offset = ipcc->proc_id ? -IPCC_PROC_OFFST : IPCC_PROC_OFFST;
	tosr = readl_relaxed(ipcc->reg_proc + proc_offset + IPCC_XTOYSR);
	mr = readl_relaxed(ipcc->reg_proc + IPCC_XMR);

	/* search for unmasked 'channel occupied' */
	status = tosr & FIELD_GET(RX_BIT_MASK, ~mr);

	for (chan = 0; chan < ipcc->n_chans; chan++) {
		if (!(status & (1 << chan)))
			continue;

		dev_dbg(dev, "%s: chan:%d rx\n", __func__, chan);

		mbox_chan_received_data(&ipcc->controller.chans[chan], NULL);

		stm32_ipcc_set_bits(&ipcc->lock, ipcc->reg_proc + IPCC_XSCR,
				    RX_BIT_CHAN(chan));

		ret = IRQ_HANDLED;
	}

	return ret;
}

static irqreturn_t stm32_ipcc_tx_irq(int irq, void *data)
{
	struct stm32_ipcc *ipcc = data;
	struct device *dev = ipcc->controller.dev;
	u32 status, mr, tosr, chan;
	irqreturn_t ret = IRQ_NONE;

	tosr = readl_relaxed(ipcc->reg_proc + IPCC_XTOYSR);
	mr = readl_relaxed(ipcc->reg_proc + IPCC_XMR);

	/* search for unmasked 'channel free' */
	status = ~tosr & FIELD_GET(TX_BIT_MASK, ~mr);

	for (chan = 0; chan < ipcc->n_chans ; chan++) {
		if (!(status & (1 << chan)))
			continue;

		dev_dbg(dev, "%s: chan:%d tx\n", __func__, chan);

		/* mask 'tx channel free' interrupt */
		stm32_ipcc_set_bits(&ipcc->lock, ipcc->reg_proc + IPCC_XMR,
				    TX_BIT_CHAN(chan));

		mbox_chan_txdone(&ipcc->controller.chans[chan], 0);

		ret = IRQ_HANDLED;
	}

	return ret;
}

static int stm32_ipcc_send_data(struct mbox_chan *link, void *data)
{
	unsigned long chan = (unsigned long)link->con_priv;
	struct stm32_ipcc *ipcc = container_of(link->mbox, struct stm32_ipcc,
					       controller);

	dev_dbg(ipcc->controller.dev, "%s: chan:%lu\n", __func__, chan);

	/* set channel n occupied */
	stm32_ipcc_set_bits(&ipcc->lock, ipcc->reg_proc + IPCC_XSCR,
			    TX_BIT_CHAN(chan));

	/* unmask 'tx channel free' interrupt */
	stm32_ipcc_clr_bits(&ipcc->lock, ipcc->reg_proc + IPCC_XMR,
			    TX_BIT_CHAN(chan));

	return 0;
}

static int stm32_ipcc_startup(struct mbox_chan *link)
{
	unsigned long chan = (unsigned long)link->con_priv;
	struct stm32_ipcc *ipcc = container_of(link->mbox, struct stm32_ipcc,
					       controller);
	int ret;

	ret = clk_prepare_enable(ipcc->clk);
	if (ret) {
		dev_err(ipcc->controller.dev, "can not enable the clock\n");
		return ret;
	}

	/* unmask 'rx channel occupied' interrupt */
	stm32_ipcc_clr_bits(&ipcc->lock, ipcc->reg_proc + IPCC_XMR,
			    RX_BIT_CHAN(chan));

	return 0;
}

static void stm32_ipcc_shutdown(struct mbox_chan *link)
{
	unsigned long chan = (unsigned long)link->con_priv;
	struct stm32_ipcc *ipcc = container_of(link->mbox, struct stm32_ipcc,
					       controller);

	/* mask rx/tx interrupt */
	stm32_ipcc_set_bits(&ipcc->lock, ipcc->reg_proc + IPCC_XMR,
			    RX_BIT_CHAN(chan) | TX_BIT_CHAN(chan));

	clk_disable_unprepare(ipcc->clk);
}

static const struct mbox_chan_ops stm32_ipcc_ops = {
	.send_data	= stm32_ipcc_send_data,
	.startup	= stm32_ipcc_startup,
	.shutdown	= stm32_ipcc_shutdown,
};

static int stm32_ipcc_probe(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
	struct device_node *np = dev->of_node;
	struct stm32_ipcc *ipcc;
	unsigned long i;
	int ret;
	u32 ip_ver;
	static const char * const irq_name[] = {"rx", "tx"};
	irq_handler_t irq_thread[] = {stm32_ipcc_rx_irq, stm32_ipcc_tx_irq};

	if (!np) {
		dev_err(dev, "No DT found\n");
		return -ENODEV;
	}

	ipcc = devm_kzalloc(dev, sizeof(*ipcc), GFP_KERNEL);
	if (!ipcc)
		return -ENOMEM;

	spin_lock_init(&ipcc->lock);

	/* proc_id */
	if (of_property_read_u32(np, "st,proc-id", &ipcc->proc_id)) {
		dev_err(dev, "Missing st,proc-id\n");
		return -ENODEV;
	}

	if (ipcc->proc_id >= STM32_MAX_PROCS) {
		dev_err(dev, "Invalid proc_id (%d)\n", ipcc->proc_id);
		return -EINVAL;
	}

	/* regs */
	ipcc->reg_base = devm_platform_ioremap_resource(pdev, 0);
	if (IS_ERR(ipcc->reg_base))
		return PTR_ERR(ipcc->reg_base);

	ipcc->reg_proc = ipcc->reg_base + ipcc->proc_id * IPCC_PROC_OFFST;

	/* clock */
	ipcc->clk = devm_clk_get(dev, NULL);
	if (IS_ERR(ipcc->clk))
		return PTR_ERR(ipcc->clk);

	ret = clk_prepare_enable(ipcc->clk);
	if (ret) {
		dev_err(dev, "can not enable the clock\n");
		return ret;
	}

	/* irq */
	for (i = 0; i < IPCC_IRQ_NUM; i++) {
		ipcc->irqs[i] = platform_get_irq_byname(pdev, irq_name[i]);
		if (ipcc->irqs[i] < 0) {
			ret = ipcc->irqs[i];
			goto err_clk;
		}

		ret = devm_request_threaded_irq(dev, ipcc->irqs[i], NULL,
						irq_thread[i], IRQF_ONESHOT,
						dev_name(dev), ipcc);
		if (ret) {
			dev_err(dev, "failed to request irq %lu (%d)\n", i, ret);
			goto err_clk;
		}
	}

	/* mask and enable rx/tx irq */
	stm32_ipcc_set_bits(&ipcc->lock, ipcc->reg_proc + IPCC_XMR,
			    RX_BIT_MASK | TX_BIT_MASK);
	stm32_ipcc_set_bits(&ipcc->lock, ipcc->reg_proc + IPCC_XCR,
			    XCR_RXOIE | XCR_TXOIE);

	/* wakeup */
	if (of_property_read_bool(np, "wakeup-source")) {
		device_set_wakeup_capable(dev, true);

		ret = dev_pm_set_wake_irq(dev, ipcc->irqs[IPCC_IRQ_RX]);
		if (ret) {
			dev_err(dev, "Failed to set wake up irq\n");
			goto err_init_wkp;
		}
	}

	/* mailbox controller */
	ipcc->n_chans = readl_relaxed(ipcc->reg_base + IPCC_HWCFGR);
	ipcc->n_chans &= IPCFGR_CHAN_MASK;

	ipcc->controller.dev = dev;
	ipcc->controller.txdone_irq = true;
	ipcc->controller.ops = &stm32_ipcc_ops;
	ipcc->controller.num_chans = ipcc->n_chans;
	ipcc->controller.chans = devm_kcalloc(dev, ipcc->controller.num_chans,
					      sizeof(*ipcc->controller.chans),
					      GFP_KERNEL);
	if (!ipcc->controller.chans) {
		ret = -ENOMEM;
		goto err_irq_wkp;
	}

	for (i = 0; i < ipcc->controller.num_chans; i++)
		ipcc->controller.chans[i].con_priv = (void *)i;

	ret = devm_mbox_controller_register(dev, &ipcc->controller);
	if (ret)
		goto err_irq_wkp;

	platform_set_drvdata(pdev, ipcc);

	ip_ver = readl_relaxed(ipcc->reg_base + IPCC_VER);

	dev_info(dev, "ipcc rev:%ld.%ld enabled, %d chans, proc %d\n",
		 FIELD_GET(VER_MAJREV_MASK, ip_ver),
		 FIELD_GET(VER_MINREV_MASK, ip_ver),
		 ipcc->controller.num_chans, ipcc->proc_id);

	clk_disable_unprepare(ipcc->clk);
	return 0;

err_irq_wkp:
	if (of_property_read_bool(np, "wakeup-source"))
		dev_pm_clear_wake_irq(dev);
err_init_wkp:
	device_set_wakeup_capable(dev, false);
err_clk:
	clk_disable_unprepare(ipcc->clk);
	return ret;
}

static int stm32_ipcc_remove(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;

	if (of_property_read_bool(dev->of_node, "wakeup-source"))
		dev_pm_clear_wake_irq(&pdev->dev);

	device_set_wakeup_capable(dev, false);

	return 0;
}

#ifdef CONFIG_PM_SLEEP
static int stm32_ipcc_suspend(struct device *dev)
{
	struct stm32_ipcc *ipcc = dev_get_drvdata(dev);

	ipcc->xmr = readl_relaxed(ipcc->reg_proc + IPCC_XMR);
	ipcc->xcr = readl_relaxed(ipcc->reg_proc + IPCC_XCR);

	return 0;
}

static int stm32_ipcc_resume(struct device *dev)
{
	struct stm32_ipcc *ipcc = dev_get_drvdata(dev);

	writel_relaxed(ipcc->xmr, ipcc->reg_proc + IPCC_XMR);
	writel_relaxed(ipcc->xcr, ipcc->reg_proc + IPCC_XCR);

	return 0;
}
#endif

static SIMPLE_DEV_PM_OPS(stm32_ipcc_pm_ops,
			 stm32_ipcc_suspend, stm32_ipcc_resume);

static const struct of_device_id stm32_ipcc_of_match[] = {
	{ .compatible = "st,stm32mp1-ipcc" },
	{},
};
MODULE_DEVICE_TABLE(of, stm32_ipcc_of_match);

static struct platform_driver stm32_ipcc_driver = {
	.driver = {
		.name = "stm32-ipcc",
		.pm = &stm32_ipcc_pm_ops,
		.of_match_table = stm32_ipcc_of_match,
	},
	.probe		= stm32_ipcc_probe,
	.remove		= stm32_ipcc_remove,
};

module_platform_driver(stm32_ipcc_driver);

MODULE_AUTHOR("Ludovic Barre <ludovic.barre@st.com>");
MODULE_AUTHOR("Fabien Dessenne <fabien.dessenne@st.com>");
MODULE_DESCRIPTION("STM32 IPCC driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
ffbded7d FD	1	// SPDX-License-Identifier: GPL-2.0
	2	/*
	3	* Copyright (C) STMicroelectronics 2018 - All Rights Reserved
	4	* Authors: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
	5	* Fabien Dessenne <fabien.dessenne@st.com> for STMicroelectronics.
	6	*/
	7
	8	#include <linux/bitfield.h>
	9	#include <linux/clk.h>
	10	#include <linux/interrupt.h>
68a1c848	11	#include <linux/io.h>
ffbded7d FD	12	#include <linux/mailbox_controller.h>
ffbded7d FD	13	#include <linux/module.h>
ffbded7d FD	14	#include <linux/platform_device.h>
	15	#include <linux/pm_wakeirq.h>
	16
	17	#define IPCC_XCR 0x000
	18	#define XCR_RXOIE BIT(0)
	19	#define XCR_TXOIE BIT(16)
	20
	21	#define IPCC_XMR 0x004
	22	#define IPCC_XSCR 0x008
	23	#define IPCC_XTOYSR 0x00c
	24
	25	#define IPCC_PROC_OFFST 0x010
	26
	27	#define IPCC_HWCFGR 0x3f0
	28	#define IPCFGR_CHAN_MASK GENMASK(7, 0)
	29
	30	#define IPCC_VER 0x3f4
	31	#define VER_MINREV_MASK GENMASK(3, 0)
	32	#define VER_MAJREV_MASK GENMASK(7, 4)
	33
	34	#define RX_BIT_MASK GENMASK(15, 0)
	35	#define RX_BIT_CHAN(chan) BIT(chan)
	36	#define TX_BIT_SHIFT 16
	37	#define TX_BIT_MASK GENMASK(31, 16)
	38	#define TX_BIT_CHAN(chan) BIT(TX_BIT_SHIFT + (chan))
	39
	40	#define STM32_MAX_PROCS 2
	41
	42	enum {
	43	IPCC_IRQ_RX,
	44	IPCC_IRQ_TX,
	45	IPCC_IRQ_NUM,
	46	};
	47
	48	struct stm32_ipcc {
	49	struct mbox_controller controller;
	50	void __iomem *reg_base;
	51	void __iomem *reg_proc;
	52	struct clk *clk;
dba9a3df	53	spinlock_t lock; /* protect access to IPCC registers */
ffbded7d	54	int irqs[IPCC_IRQ_NUM];
ffbded7d FD	55	u32 proc_id;
	56	u32 n_chans;
	57	u32 xcr;
	58	u32 xmr;
	59	};
	60
dba9a3df AP	61	static inline void stm32_ipcc_set_bits(spinlock_t lock, void __iomem reg,
dba9a3df AP	62	u32 mask)
ffbded7d	63	{
dba9a3df AP	64	unsigned long flags;
	65
	66	spin_lock_irqsave(lock, flags);
ffbded7d	67	writel_relaxed(readl_relaxed(reg) \| mask, reg);
dba9a3df	68	spin_unlock_irqrestore(lock, flags);
ffbded7d FD	69	}
ffbded7d FD	70
dba9a3df AP	71	static inline void stm32_ipcc_clr_bits(spinlock_t lock, void __iomem reg,
dba9a3df AP	72	u32 mask)
ffbded7d	73	{
dba9a3df AP	74	unsigned long flags;
	75
	76	spin_lock_irqsave(lock, flags);
ffbded7d	77	writel_relaxed(readl_relaxed(reg) & ~mask, reg);
dba9a3df	78	spin_unlock_irqrestore(lock, flags);
ffbded7d FD	79	}
	80
	81	static irqreturn_t stm32_ipcc_rx_irq(int irq, void *data)
	82	{
	83	struct stm32_ipcc *ipcc = data;
	84	struct device *dev = ipcc->controller.dev;
	85	u32 status, mr, tosr, chan;
	86	irqreturn_t ret = IRQ_NONE;
	87	int proc_offset;
	88
	89	/* read 'channel occupied' status from other proc */
	90	proc_offset = ipcc->proc_id ? -IPCC_PROC_OFFST : IPCC_PROC_OFFST;
	91	tosr = readl_relaxed(ipcc->reg_proc + proc_offset + IPCC_XTOYSR);
	92	mr = readl_relaxed(ipcc->reg_proc + IPCC_XMR);
	93
	94	/* search for unmasked 'channel occupied' */
	95	status = tosr & FIELD_GET(RX_BIT_MASK, ~mr);
	96
	97	for (chan = 0; chan < ipcc->n_chans; chan++) {
	98	if (!(status & (1 << chan)))
	99	continue;
	100
	101	dev_dbg(dev, "%s: chan:%d rx\n", __func__, chan);
	102
	103	mbox_chan_received_data(&ipcc->controller.chans[chan], NULL);
	104
dba9a3df	105	stm32_ipcc_set_bits(&ipcc->lock, ipcc->reg_proc + IPCC_XSCR,
ffbded7d FD	106	RX_BIT_CHAN(chan));
	107
	108	ret = IRQ_HANDLED;
	109	}
	110
	111	return ret;
	112	}
	113
	114	static irqreturn_t stm32_ipcc_tx_irq(int irq, void *data)
	115	{
	116	struct stm32_ipcc *ipcc = data;
	117	struct device *dev = ipcc->controller.dev;
	118	u32 status, mr, tosr, chan;
	119	irqreturn_t ret = IRQ_NONE;
	120
	121	tosr = readl_relaxed(ipcc->reg_proc + IPCC_XTOYSR);
	122	mr = readl_relaxed(ipcc->reg_proc + IPCC_XMR);
	123
	124	/* search for unmasked 'channel free' */
	125	status = ~tosr & FIELD_GET(TX_BIT_MASK, ~mr);
	126
	127	for (chan = 0; chan < ipcc->n_chans ; chan++) {
	128	if (!(status & (1 << chan)))
	129	continue;
	130
	131	dev_dbg(dev, "%s: chan:%d tx\n", __func__, chan);
	132
	133	/* mask 'tx channel free' interrupt */
dba9a3df	134	stm32_ipcc_set_bits(&ipcc->lock, ipcc->reg_proc + IPCC_XMR,
ffbded7d FD	135	TX_BIT_CHAN(chan));
	136
	137	mbox_chan_txdone(&ipcc->controller.chans[chan], 0);
	138
	139	ret = IRQ_HANDLED;
	140	}
	141
	142	return ret;
	143	}
	144
	145	static int stm32_ipcc_send_data(struct mbox_chan link, void data)
	146	{
01790928	147	unsigned long chan = (unsigned long)link->con_priv;
ffbded7d FD	148	struct stm32_ipcc *ipcc = container_of(link->mbox, struct stm32_ipcc,
	149	controller);
	150
01790928	151	dev_dbg(ipcc->controller.dev, "%s: chan:%lu\n", __func__, chan);
ffbded7d FD	152
ffbded7d FD	153	/* set channel n occupied */
dba9a3df AP	154	stm32_ipcc_set_bits(&ipcc->lock, ipcc->reg_proc + IPCC_XSCR,
dba9a3df AP	155	TX_BIT_CHAN(chan));
ffbded7d FD	156
ffbded7d FD	157	/* unmask 'tx channel free' interrupt */
dba9a3df AP	158	stm32_ipcc_clr_bits(&ipcc->lock, ipcc->reg_proc + IPCC_XMR,
dba9a3df AP	159	TX_BIT_CHAN(chan));
ffbded7d FD	160
	161	return 0;
	162	}
	163
	164	static int stm32_ipcc_startup(struct mbox_chan *link)
	165	{
01790928	166	unsigned long chan = (unsigned long)link->con_priv;
ffbded7d FD	167	struct stm32_ipcc *ipcc = container_of(link->mbox, struct stm32_ipcc,
	168	controller);
	169	int ret;
	170
	171	ret = clk_prepare_enable(ipcc->clk);
	172	if (ret) {
	173	dev_err(ipcc->controller.dev, "can not enable the clock\n");
	174	return ret;
	175	}
	176
	177	/* unmask 'rx channel occupied' interrupt */
dba9a3df AP	178	stm32_ipcc_clr_bits(&ipcc->lock, ipcc->reg_proc + IPCC_XMR,
dba9a3df AP	179	RX_BIT_CHAN(chan));
ffbded7d FD	180
	181	return 0;
	182	}
	183
	184	static void stm32_ipcc_shutdown(struct mbox_chan *link)
	185	{
01790928	186	unsigned long chan = (unsigned long)link->con_priv;
ffbded7d FD	187	struct stm32_ipcc *ipcc = container_of(link->mbox, struct stm32_ipcc,
	188	controller);
	189
	190	/* mask rx/tx interrupt */
dba9a3df	191	stm32_ipcc_set_bits(&ipcc->lock, ipcc->reg_proc + IPCC_XMR,
ffbded7d FD	192	RX_BIT_CHAN(chan) \| TX_BIT_CHAN(chan));
	193
	194	clk_disable_unprepare(ipcc->clk);
	195	}
	196
	197	static const struct mbox_chan_ops stm32_ipcc_ops = {
	198	.send_data = stm32_ipcc_send_data,
	199	.startup = stm32_ipcc_startup,
	200	.shutdown = stm32_ipcc_shutdown,
	201	};
	202
	203	static int stm32_ipcc_probe(struct platform_device *pdev)
	204	{
	205	struct device *dev = &pdev->dev;
	206	struct device_node *np = dev->of_node;
	207	struct stm32_ipcc *ipcc;
01790928	208	unsigned long i;
ffbded7d FD	209	int ret;
	210	u32 ip_ver;
	211	static const char * const irq_name[] = {"rx", "tx"};
	212	irq_handler_t irq_thread[] = {stm32_ipcc_rx_irq, stm32_ipcc_tx_irq};
	213
	214	if (!np) {
	215	dev_err(dev, "No DT found\n");
	216	return -ENODEV;
	217	}
	218
	219	ipcc = devm_kzalloc(dev, sizeof(*ipcc), GFP_KERNEL);
	220	if (!ipcc)
	221	return -ENOMEM;
	222
dba9a3df AP	223	spin_lock_init(&ipcc->lock);
dba9a3df AP	224
ffbded7d FD	225	/* proc_id */
	226	if (of_property_read_u32(np, "st,proc-id", &ipcc->proc_id)) {
	227	dev_err(dev, "Missing st,proc-id\n");
	228	return -ENODEV;
	229	}
	230
	231	if (ipcc->proc_id >= STM32_MAX_PROCS) {
	232	dev_err(dev, "Invalid proc_id (%d)\n", ipcc->proc_id);
	233	return -EINVAL;
	234	}
	235
	236	/* regs */
f3908ccc	237	ipcc->reg_base = devm_platform_ioremap_resource(pdev, 0);
ffbded7d FD	238	if (IS_ERR(ipcc->reg_base))
	239	return PTR_ERR(ipcc->reg_base);
	240
	241	ipcc->reg_proc = ipcc->reg_base + ipcc->proc_id * IPCC_PROC_OFFST;
	242
	243	/* clock */
	244	ipcc->clk = devm_clk_get(dev, NULL);
	245	if (IS_ERR(ipcc->clk))
	246	return PTR_ERR(ipcc->clk);
	247
	248	ret = clk_prepare_enable(ipcc->clk);
	249	if (ret) {
	250	dev_err(dev, "can not enable the clock\n");
	251	return ret;
	252	}
	253
	254	/* irq */
	255	for (i = 0; i < IPCC_IRQ_NUM; i++) {
68a1c848	256	ipcc->irqs[i] = platform_get_irq_byname(pdev, irq_name[i]);
ffbded7d	257	if (ipcc->irqs[i] < 0) {
ffbded7d FD	258	ret = ipcc->irqs[i];
	259	goto err_clk;
	260	}
	261
	262	ret = devm_request_threaded_irq(dev, ipcc->irqs[i], NULL,
	263	irq_thread[i], IRQF_ONESHOT,
	264	dev_name(dev), ipcc);
	265	if (ret) {
01790928	266	dev_err(dev, "failed to request irq %lu (%d)\n", i, ret);
ffbded7d FD	267	goto err_clk;
	268	}
	269	}
	270
	271	/* mask and enable rx/tx irq */
dba9a3df	272	stm32_ipcc_set_bits(&ipcc->lock, ipcc->reg_proc + IPCC_XMR,
ffbded7d	273	RX_BIT_MASK \| TX_BIT_MASK);
dba9a3df AP	274	stm32_ipcc_set_bits(&ipcc->lock, ipcc->reg_proc + IPCC_XCR,
dba9a3df AP	275	XCR_RXOIE \| XCR_TXOIE);
ffbded7d FD	276
	277	/* wakeup */
	278	if (of_property_read_bool(np, "wakeup-source")) {
eac36c86	279	device_set_wakeup_capable(dev, true);
69269446 FD	280
69269446 FD	281	ret = dev_pm_set_wake_irq(dev, ipcc->irqs[IPCC_IRQ_RX]);
ffbded7d FD	282	if (ret) {
	283	dev_err(dev, "Failed to set wake up irq\n");
	284	goto err_init_wkp;
	285	}
ffbded7d FD	286	}
	287
	288	/* mailbox controller */
	289	ipcc->n_chans = readl_relaxed(ipcc->reg_base + IPCC_HWCFGR);
	290	ipcc->n_chans &= IPCFGR_CHAN_MASK;
	291
	292	ipcc->controller.dev = dev;
	293	ipcc->controller.txdone_irq = true;
	294	ipcc->controller.ops = &stm32_ipcc_ops;
	295	ipcc->controller.num_chans = ipcc->n_chans;
	296	ipcc->controller.chans = devm_kcalloc(dev, ipcc->controller.num_chans,
	297	sizeof(*ipcc->controller.chans),
	298	GFP_KERNEL);
	299	if (!ipcc->controller.chans) {
	300	ret = -ENOMEM;
	301	goto err_irq_wkp;
	302	}
	303
	304	for (i = 0; i < ipcc->controller.num_chans; i++)
	305	ipcc->controller.chans[i].con_priv = (void *)i;
	306
368d7767	307	ret = devm_mbox_controller_register(dev, &ipcc->controller);
ffbded7d FD	308	if (ret)
	309	goto err_irq_wkp;
	310
	311	platform_set_drvdata(pdev, ipcc);
	312
	313	ip_ver = readl_relaxed(ipcc->reg_base + IPCC_VER);
	314
	315	dev_info(dev, "ipcc rev:%ld.%ld enabled, %d chans, proc %d\n",
	316	FIELD_GET(VER_MAJREV_MASK, ip_ver),
	317	FIELD_GET(VER_MINREV_MASK, ip_ver),
	318	ipcc->controller.num_chans, ipcc->proc_id);
	319
	320	clk_disable_unprepare(ipcc->clk);
	321	return 0;
	322
	323	err_irq_wkp:
69269446	324	if (of_property_read_bool(np, "wakeup-source"))
ffbded7d FD	325	dev_pm_clear_wake_irq(dev);
ffbded7d FD	326	err_init_wkp:
69269446	327	device_set_wakeup_capable(dev, false);
ffbded7d FD	328	err_clk:
	329	clk_disable_unprepare(ipcc->clk);
	330	return ret;
	331	}
	332
	333	static int stm32_ipcc_remove(struct platform_device *pdev)
	334	{
69269446	335	struct device *dev = &pdev->dev;
ffbded7d	336
69269446	337	if (of_property_read_bool(dev->of_node, "wakeup-source"))
ffbded7d FD	338	dev_pm_clear_wake_irq(&pdev->dev);
ffbded7d FD	339
69269446	340	device_set_wakeup_capable(dev, false);
ffbded7d FD	341
	342	return 0;
	343	}
	344
	345	#ifdef CONFIG_PM_SLEEP
ffbded7d FD	346	static int stm32_ipcc_suspend(struct device *dev)
	347	{
	348	struct stm32_ipcc *ipcc = dev_get_drvdata(dev);
	349
	350	ipcc->xmr = readl_relaxed(ipcc->reg_proc + IPCC_XMR);
	351	ipcc->xcr = readl_relaxed(ipcc->reg_proc + IPCC_XCR);
	352
ffbded7d FD	353	return 0;
	354	}
	355
	356	static int stm32_ipcc_resume(struct device *dev)
	357	{
	358	struct stm32_ipcc *ipcc = dev_get_drvdata(dev);
	359
ffbded7d FD	360	writel_relaxed(ipcc->xmr, ipcc->reg_proc + IPCC_XMR);
	361	writel_relaxed(ipcc->xcr, ipcc->reg_proc + IPCC_XCR);
	362
	363	return 0;
	364	}
	365	#endif
	366
	367	static SIMPLE_DEV_PM_OPS(stm32_ipcc_pm_ops,
	368	stm32_ipcc_suspend, stm32_ipcc_resume);
	369
	370	static const struct of_device_id stm32_ipcc_of_match[] = {
	371	{ .compatible = "st,stm32mp1-ipcc" },
	372	{},
	373	};
	374	MODULE_DEVICE_TABLE(of, stm32_ipcc_of_match);
	375
	376	static struct platform_driver stm32_ipcc_driver = {
	377	.driver = {
	378	.name = "stm32-ipcc",
	379	.pm = &stm32_ipcc_pm_ops,
	380	.of_match_table = stm32_ipcc_of_match,
	381	},
	382	.probe = stm32_ipcc_probe,
	383	.remove = stm32_ipcc_remove,
	384	};
	385
	386	module_platform_driver(stm32_ipcc_driver);
	387
	388	MODULE_AUTHOR("Ludovic Barre <ludovic.barre@st.com>");
	389	MODULE_AUTHOR("Fabien Dessenne <fabien.dessenne@st.com>");
	390	MODULE_DESCRIPTION("STM32 IPCC driver");
	391	MODULE_LICENSE("GPL v2");