Commit | Line | Data |
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340a614a HD |
1 | /* |
2 | * OMAP mailbox driver | |
3 | * | |
f48cca87 | 4 | * Copyright (C) 2006-2009 Nokia Corporation. All rights reserved. |
5040f534 | 5 | * Copyright (C) 2013-2014 Texas Instruments Inc. |
340a614a | 6 | * |
f48cca87 | 7 | * Contact: Hiroshi DOYU <Hiroshi.DOYU@nokia.com> |
5040f534 | 8 | * Suman Anna <s-anna@ti.com> |
340a614a HD |
9 | * |
10 | * This program is free software; you can redistribute it and/or | |
11 | * modify it under the terms of the GNU General Public License | |
12 | * version 2 as published by the Free Software Foundation. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, but | |
15 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
17 | * General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA | |
22 | * 02110-1301 USA | |
23 | * | |
24 | */ | |
25 | ||
340a614a | 26 | #include <linux/interrupt.h> |
b3e69146 FC |
27 | #include <linux/spinlock.h> |
28 | #include <linux/mutex.h> | |
5a0e3ad6 | 29 | #include <linux/slab.h> |
b5bebe41 OBC |
30 | #include <linux/kfifo.h> |
31 | #include <linux/err.h> | |
73017a54 | 32 | #include <linux/module.h> |
75288cc6 | 33 | #include <linux/of_device.h> |
5040f534 SA |
34 | #include <linux/platform_device.h> |
35 | #include <linux/pm_runtime.h> | |
36 | #include <linux/platform_data/mailbox-omap.h> | |
37 | #include <linux/omap-mailbox.h> | |
8841a66a SA |
38 | #include <linux/mailbox_controller.h> |
39 | #include <linux/mailbox_client.h> | |
5040f534 | 40 | |
8e3c5952 DG |
41 | #include "mailbox.h" |
42 | ||
5040f534 SA |
43 | #define MAILBOX_REVISION 0x000 |
44 | #define MAILBOX_MESSAGE(m) (0x040 + 4 * (m)) | |
45 | #define MAILBOX_FIFOSTATUS(m) (0x080 + 4 * (m)) | |
46 | #define MAILBOX_MSGSTATUS(m) (0x0c0 + 4 * (m)) | |
47 | ||
48 | #define OMAP2_MAILBOX_IRQSTATUS(u) (0x100 + 8 * (u)) | |
49 | #define OMAP2_MAILBOX_IRQENABLE(u) (0x104 + 8 * (u)) | |
50 | ||
51 | #define OMAP4_MAILBOX_IRQSTATUS(u) (0x104 + 0x10 * (u)) | |
52 | #define OMAP4_MAILBOX_IRQENABLE(u) (0x108 + 0x10 * (u)) | |
53 | #define OMAP4_MAILBOX_IRQENABLE_CLR(u) (0x10c + 0x10 * (u)) | |
54 | ||
55 | #define MAILBOX_IRQSTATUS(type, u) (type ? OMAP4_MAILBOX_IRQSTATUS(u) : \ | |
56 | OMAP2_MAILBOX_IRQSTATUS(u)) | |
57 | #define MAILBOX_IRQENABLE(type, u) (type ? OMAP4_MAILBOX_IRQENABLE(u) : \ | |
58 | OMAP2_MAILBOX_IRQENABLE(u)) | |
59 | #define MAILBOX_IRQDISABLE(type, u) (type ? OMAP4_MAILBOX_IRQENABLE_CLR(u) \ | |
60 | : OMAP2_MAILBOX_IRQENABLE(u)) | |
61 | ||
62 | #define MAILBOX_IRQ_NEWMSG(m) (1 << (2 * (m))) | |
63 | #define MAILBOX_IRQ_NOTFULL(m) (1 << (2 * (m) + 1)) | |
64 | ||
65 | #define MBOX_REG_SIZE 0x120 | |
66 | ||
67 | #define OMAP4_MBOX_REG_SIZE 0x130 | |
68 | ||
69 | #define MBOX_NR_REGS (MBOX_REG_SIZE / sizeof(u32)) | |
70 | #define OMAP4_MBOX_NR_REGS (OMAP4_MBOX_REG_SIZE / sizeof(u32)) | |
71 | ||
72 | struct omap_mbox_fifo { | |
73 | unsigned long msg; | |
74 | unsigned long fifo_stat; | |
75 | unsigned long msg_stat; | |
5040f534 SA |
76 | unsigned long irqenable; |
77 | unsigned long irqstatus; | |
5040f534 | 78 | unsigned long irqdisable; |
be3322eb | 79 | u32 intr_bit; |
5040f534 SA |
80 | }; |
81 | ||
82 | struct omap_mbox_queue { | |
83 | spinlock_t lock; | |
84 | struct kfifo fifo; | |
85 | struct work_struct work; | |
5040f534 SA |
86 | struct omap_mbox *mbox; |
87 | bool full; | |
88 | }; | |
89 | ||
72c1c817 SA |
90 | struct omap_mbox_device { |
91 | struct device *dev; | |
92 | struct mutex cfg_lock; | |
93 | void __iomem *mbox_base; | |
94 | u32 num_users; | |
95 | u32 num_fifos; | |
96 | struct omap_mbox **mboxes; | |
8841a66a | 97 | struct mbox_controller controller; |
72c1c817 SA |
98 | struct list_head elem; |
99 | }; | |
100 | ||
75288cc6 SA |
101 | struct omap_mbox_fifo_info { |
102 | int tx_id; | |
103 | int tx_usr; | |
104 | int tx_irq; | |
105 | ||
106 | int rx_id; | |
107 | int rx_usr; | |
108 | int rx_irq; | |
109 | ||
110 | const char *name; | |
8e3c5952 | 111 | bool send_no_irq; |
75288cc6 SA |
112 | }; |
113 | ||
5040f534 SA |
114 | struct omap_mbox { |
115 | const char *name; | |
116 | int irq; | |
8841a66a | 117 | struct omap_mbox_queue *rxq; |
5040f534 | 118 | struct device *dev; |
72c1c817 | 119 | struct omap_mbox_device *parent; |
be3322eb SA |
120 | struct omap_mbox_fifo tx_fifo; |
121 | struct omap_mbox_fifo rx_fifo; | |
122 | u32 ctx[OMAP4_MBOX_NR_REGS]; | |
123 | u32 intr_type; | |
8841a66a | 124 | struct mbox_chan *chan; |
8e3c5952 | 125 | bool send_no_irq; |
5040f534 SA |
126 | }; |
127 | ||
72c1c817 SA |
128 | /* global variables for the mailbox devices */ |
129 | static DEFINE_MUTEX(omap_mbox_devices_lock); | |
130 | static LIST_HEAD(omap_mbox_devices); | |
5f00ec64 | 131 | |
b5bebe41 OBC |
132 | static unsigned int mbox_kfifo_size = CONFIG_OMAP_MBOX_KFIFO_SIZE; |
133 | module_param(mbox_kfifo_size, uint, S_IRUGO); | |
134 | MODULE_PARM_DESC(mbox_kfifo_size, "Size of omap's mailbox kfifo (bytes)"); | |
135 | ||
8841a66a SA |
136 | static struct omap_mbox *mbox_chan_to_omap_mbox(struct mbox_chan *chan) |
137 | { | |
138 | if (!chan || !chan->con_priv) | |
139 | return NULL; | |
140 | ||
141 | return (struct omap_mbox *)chan->con_priv; | |
142 | } | |
143 | ||
72c1c817 SA |
144 | static inline |
145 | unsigned int mbox_read_reg(struct omap_mbox_device *mdev, size_t ofs) | |
5040f534 | 146 | { |
72c1c817 | 147 | return __raw_readl(mdev->mbox_base + ofs); |
5040f534 SA |
148 | } |
149 | ||
72c1c817 SA |
150 | static inline |
151 | void mbox_write_reg(struct omap_mbox_device *mdev, u32 val, size_t ofs) | |
5040f534 | 152 | { |
72c1c817 | 153 | __raw_writel(val, mdev->mbox_base + ofs); |
5040f534 SA |
154 | } |
155 | ||
9ae0ee00 | 156 | /* Mailbox FIFO handle functions */ |
5040f534 | 157 | static mbox_msg_t mbox_fifo_read(struct omap_mbox *mbox) |
9ae0ee00 | 158 | { |
be3322eb | 159 | struct omap_mbox_fifo *fifo = &mbox->rx_fifo; |
72c1c817 | 160 | return (mbox_msg_t) mbox_read_reg(mbox->parent, fifo->msg); |
9ae0ee00 | 161 | } |
5040f534 SA |
162 | |
163 | static void mbox_fifo_write(struct omap_mbox *mbox, mbox_msg_t msg) | |
9ae0ee00 | 164 | { |
be3322eb | 165 | struct omap_mbox_fifo *fifo = &mbox->tx_fifo; |
72c1c817 | 166 | mbox_write_reg(mbox->parent, msg, fifo->msg); |
9ae0ee00 | 167 | } |
5040f534 SA |
168 | |
169 | static int mbox_fifo_empty(struct omap_mbox *mbox) | |
9ae0ee00 | 170 | { |
be3322eb | 171 | struct omap_mbox_fifo *fifo = &mbox->rx_fifo; |
72c1c817 | 172 | return (mbox_read_reg(mbox->parent, fifo->msg_stat) == 0); |
9ae0ee00 | 173 | } |
5040f534 SA |
174 | |
175 | static int mbox_fifo_full(struct omap_mbox *mbox) | |
9ae0ee00 | 176 | { |
be3322eb | 177 | struct omap_mbox_fifo *fifo = &mbox->tx_fifo; |
72c1c817 | 178 | return mbox_read_reg(mbox->parent, fifo->fifo_stat); |
9ae0ee00 HD |
179 | } |
180 | ||
181 | /* Mailbox IRQ handle functions */ | |
5040f534 | 182 | static void ack_mbox_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq) |
9ae0ee00 | 183 | { |
be3322eb SA |
184 | struct omap_mbox_fifo *fifo = (irq == IRQ_TX) ? |
185 | &mbox->tx_fifo : &mbox->rx_fifo; | |
186 | u32 bit = fifo->intr_bit; | |
187 | u32 irqstatus = fifo->irqstatus; | |
5040f534 | 188 | |
72c1c817 | 189 | mbox_write_reg(mbox->parent, bit, irqstatus); |
5040f534 SA |
190 | |
191 | /* Flush posted write for irq status to avoid spurious interrupts */ | |
72c1c817 | 192 | mbox_read_reg(mbox->parent, irqstatus); |
9ae0ee00 | 193 | } |
5040f534 SA |
194 | |
195 | static int is_mbox_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq) | |
9ae0ee00 | 196 | { |
be3322eb SA |
197 | struct omap_mbox_fifo *fifo = (irq == IRQ_TX) ? |
198 | &mbox->tx_fifo : &mbox->rx_fifo; | |
199 | u32 bit = fifo->intr_bit; | |
200 | u32 irqenable = fifo->irqenable; | |
201 | u32 irqstatus = fifo->irqstatus; | |
202 | ||
72c1c817 SA |
203 | u32 enable = mbox_read_reg(mbox->parent, irqenable); |
204 | u32 status = mbox_read_reg(mbox->parent, irqstatus); | |
5040f534 SA |
205 | |
206 | return (int)(enable & status & bit); | |
9ae0ee00 HD |
207 | } |
208 | ||
8841a66a | 209 | void omap_mbox_save_ctx(struct mbox_chan *chan) |
c869c75c | 210 | { |
5040f534 | 211 | int i; |
5040f534 | 212 | int nr_regs; |
8841a66a SA |
213 | struct omap_mbox *mbox = mbox_chan_to_omap_mbox(chan); |
214 | ||
215 | if (WARN_ON(!mbox)) | |
216 | return; | |
5040f534 | 217 | |
be3322eb | 218 | if (mbox->intr_type) |
5040f534 SA |
219 | nr_regs = OMAP4_MBOX_NR_REGS; |
220 | else | |
221 | nr_regs = MBOX_NR_REGS; | |
222 | for (i = 0; i < nr_regs; i++) { | |
72c1c817 | 223 | mbox->ctx[i] = mbox_read_reg(mbox->parent, i * sizeof(u32)); |
5040f534 SA |
224 | |
225 | dev_dbg(mbox->dev, "%s: [%02x] %08x\n", __func__, | |
be3322eb | 226 | i, mbox->ctx[i]); |
c869c75c | 227 | } |
c869c75c SA |
228 | } |
229 | EXPORT_SYMBOL(omap_mbox_save_ctx); | |
230 | ||
8841a66a | 231 | void omap_mbox_restore_ctx(struct mbox_chan *chan) |
c869c75c | 232 | { |
5040f534 | 233 | int i; |
5040f534 | 234 | int nr_regs; |
8841a66a SA |
235 | struct omap_mbox *mbox = mbox_chan_to_omap_mbox(chan); |
236 | ||
237 | if (WARN_ON(!mbox)) | |
238 | return; | |
5040f534 | 239 | |
be3322eb | 240 | if (mbox->intr_type) |
5040f534 SA |
241 | nr_regs = OMAP4_MBOX_NR_REGS; |
242 | else | |
243 | nr_regs = MBOX_NR_REGS; | |
244 | for (i = 0; i < nr_regs; i++) { | |
72c1c817 | 245 | mbox_write_reg(mbox->parent, mbox->ctx[i], i * sizeof(u32)); |
5040f534 | 246 | dev_dbg(mbox->dev, "%s: [%02x] %08x\n", __func__, |
be3322eb | 247 | i, mbox->ctx[i]); |
c869c75c | 248 | } |
c869c75c SA |
249 | } |
250 | EXPORT_SYMBOL(omap_mbox_restore_ctx); | |
251 | ||
8841a66a | 252 | static void _omap_mbox_enable_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq) |
c869c75c | 253 | { |
be3322eb SA |
254 | u32 l; |
255 | struct omap_mbox_fifo *fifo = (irq == IRQ_TX) ? | |
256 | &mbox->tx_fifo : &mbox->rx_fifo; | |
257 | u32 bit = fifo->intr_bit; | |
258 | u32 irqenable = fifo->irqenable; | |
5040f534 | 259 | |
72c1c817 | 260 | l = mbox_read_reg(mbox->parent, irqenable); |
5040f534 | 261 | l |= bit; |
72c1c817 | 262 | mbox_write_reg(mbox->parent, l, irqenable); |
c869c75c | 263 | } |
c869c75c | 264 | |
8841a66a | 265 | static void _omap_mbox_disable_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq) |
c869c75c | 266 | { |
be3322eb SA |
267 | struct omap_mbox_fifo *fifo = (irq == IRQ_TX) ? |
268 | &mbox->tx_fifo : &mbox->rx_fifo; | |
269 | u32 bit = fifo->intr_bit; | |
270 | u32 irqdisable = fifo->irqdisable; | |
5040f534 SA |
271 | |
272 | /* | |
273 | * Read and update the interrupt configuration register for pre-OMAP4. | |
274 | * OMAP4 and later SoCs have a dedicated interrupt disabling register. | |
275 | */ | |
be3322eb | 276 | if (!mbox->intr_type) |
72c1c817 | 277 | bit = mbox_read_reg(mbox->parent, irqdisable) & ~bit; |
5040f534 | 278 | |
72c1c817 | 279 | mbox_write_reg(mbox->parent, bit, irqdisable); |
c869c75c | 280 | } |
c869c75c | 281 | |
8841a66a | 282 | void omap_mbox_enable_irq(struct mbox_chan *chan, omap_mbox_irq_t irq) |
340a614a | 283 | { |
8841a66a | 284 | struct omap_mbox *mbox = mbox_chan_to_omap_mbox(chan); |
340a614a | 285 | |
8841a66a SA |
286 | if (WARN_ON(!mbox)) |
287 | return; | |
b5bebe41 | 288 | |
8841a66a SA |
289 | _omap_mbox_enable_irq(mbox, irq); |
290 | } | |
291 | EXPORT_SYMBOL(omap_mbox_enable_irq); | |
b5bebe41 | 292 | |
8841a66a SA |
293 | void omap_mbox_disable_irq(struct mbox_chan *chan, omap_mbox_irq_t irq) |
294 | { | |
295 | struct omap_mbox *mbox = mbox_chan_to_omap_mbox(chan); | |
296 | ||
297 | if (WARN_ON(!mbox)) | |
298 | return; | |
299 | ||
300 | _omap_mbox_disable_irq(mbox, irq); | |
340a614a | 301 | } |
8841a66a | 302 | EXPORT_SYMBOL(omap_mbox_disable_irq); |
340a614a HD |
303 | |
304 | /* | |
305 | * Message receiver(workqueue) | |
306 | */ | |
307 | static void mbox_rx_work(struct work_struct *work) | |
308 | { | |
309 | struct omap_mbox_queue *mq = | |
310 | container_of(work, struct omap_mbox_queue, work); | |
340a614a | 311 | mbox_msg_t msg; |
b5bebe41 OBC |
312 | int len; |
313 | ||
314 | while (kfifo_len(&mq->fifo) >= sizeof(msg)) { | |
315 | len = kfifo_out(&mq->fifo, (unsigned char *)&msg, sizeof(msg)); | |
316 | WARN_ON(len != sizeof(msg)); | |
340a614a | 317 | |
8841a66a | 318 | mbox_chan_received_data(mq->mbox->chan, (void *)msg); |
d2295042 FGL |
319 | spin_lock_irq(&mq->lock); |
320 | if (mq->full) { | |
321 | mq->full = false; | |
8841a66a | 322 | _omap_mbox_enable_irq(mq->mbox, IRQ_RX); |
d2295042 FGL |
323 | } |
324 | spin_unlock_irq(&mq->lock); | |
340a614a HD |
325 | } |
326 | } | |
327 | ||
328 | /* | |
329 | * Mailbox interrupt handler | |
330 | */ | |
340a614a HD |
331 | static void __mbox_tx_interrupt(struct omap_mbox *mbox) |
332 | { | |
8841a66a | 333 | _omap_mbox_disable_irq(mbox, IRQ_TX); |
340a614a | 334 | ack_mbox_irq(mbox, IRQ_TX); |
8841a66a | 335 | mbox_chan_txdone(mbox->chan, 0); |
340a614a HD |
336 | } |
337 | ||
338 | static void __mbox_rx_interrupt(struct omap_mbox *mbox) | |
339 | { | |
b5bebe41 | 340 | struct omap_mbox_queue *mq = mbox->rxq; |
340a614a | 341 | mbox_msg_t msg; |
b5bebe41 | 342 | int len; |
340a614a | 343 | |
340a614a | 344 | while (!mbox_fifo_empty(mbox)) { |
b5bebe41 | 345 | if (unlikely(kfifo_avail(&mq->fifo) < sizeof(msg))) { |
8841a66a | 346 | _omap_mbox_disable_irq(mbox, IRQ_RX); |
d2295042 | 347 | mq->full = true; |
340a614a | 348 | goto nomem; |
1ea5d6d1 | 349 | } |
340a614a HD |
350 | |
351 | msg = mbox_fifo_read(mbox); | |
340a614a | 352 | |
b5bebe41 OBC |
353 | len = kfifo_in(&mq->fifo, (unsigned char *)&msg, sizeof(msg)); |
354 | WARN_ON(len != sizeof(msg)); | |
340a614a HD |
355 | } |
356 | ||
357 | /* no more messages in the fifo. clear IRQ source. */ | |
358 | ack_mbox_irq(mbox, IRQ_RX); | |
f48cca87 | 359 | nomem: |
c4873005 | 360 | schedule_work(&mbox->rxq->work); |
340a614a HD |
361 | } |
362 | ||
363 | static irqreturn_t mbox_interrupt(int irq, void *p) | |
364 | { | |
2a7057e3 | 365 | struct omap_mbox *mbox = p; |
340a614a HD |
366 | |
367 | if (is_mbox_irq(mbox, IRQ_TX)) | |
368 | __mbox_tx_interrupt(mbox); | |
369 | ||
370 | if (is_mbox_irq(mbox, IRQ_RX)) | |
371 | __mbox_rx_interrupt(mbox); | |
372 | ||
373 | return IRQ_HANDLED; | |
374 | } | |
375 | ||
340a614a | 376 | static struct omap_mbox_queue *mbox_queue_alloc(struct omap_mbox *mbox, |
8841a66a | 377 | void (*work)(struct work_struct *)) |
340a614a | 378 | { |
340a614a HD |
379 | struct omap_mbox_queue *mq; |
380 | ||
8841a66a SA |
381 | if (!work) |
382 | return NULL; | |
383 | ||
340a614a HD |
384 | mq = kzalloc(sizeof(struct omap_mbox_queue), GFP_KERNEL); |
385 | if (!mq) | |
386 | return NULL; | |
387 | ||
388 | spin_lock_init(&mq->lock); | |
389 | ||
b5bebe41 | 390 | if (kfifo_alloc(&mq->fifo, mbox_kfifo_size, GFP_KERNEL)) |
340a614a | 391 | goto error; |
340a614a | 392 | |
8841a66a | 393 | INIT_WORK(&mq->work, work); |
340a614a | 394 | return mq; |
8841a66a | 395 | |
340a614a HD |
396 | error: |
397 | kfree(mq); | |
398 | return NULL; | |
399 | } | |
400 | ||
401 | static void mbox_queue_free(struct omap_mbox_queue *q) | |
402 | { | |
b5bebe41 | 403 | kfifo_free(&q->fifo); |
340a614a HD |
404 | kfree(q); |
405 | } | |
406 | ||
c7c158e5 | 407 | static int omap_mbox_startup(struct omap_mbox *mbox) |
340a614a | 408 | { |
5f00ec64 | 409 | int ret = 0; |
340a614a HD |
410 | struct omap_mbox_queue *mq; |
411 | ||
8841a66a SA |
412 | mq = mbox_queue_alloc(mbox, mbox_rx_work); |
413 | if (!mq) | |
414 | return -ENOMEM; | |
415 | mbox->rxq = mq; | |
416 | mq->mbox = mbox; | |
417 | ||
418 | ret = request_irq(mbox->irq, mbox_interrupt, IRQF_SHARED, | |
419 | mbox->name, mbox); | |
420 | if (unlikely(ret)) { | |
421 | pr_err("failed to register mailbox interrupt:%d\n", ret); | |
422 | goto fail_request_irq; | |
423 | } | |
340a614a | 424 | |
8e3c5952 DG |
425 | if (mbox->send_no_irq) |
426 | mbox->chan->txdone_method = TXDONE_BY_ACK; | |
427 | ||
8841a66a | 428 | _omap_mbox_enable_irq(mbox, IRQ_RX); |
1d8a0e96 | 429 | |
340a614a HD |
430 | return 0; |
431 | ||
ecf305cf SA |
432 | fail_request_irq: |
433 | mbox_queue_free(mbox->rxq); | |
340a614a HD |
434 | return ret; |
435 | } | |
436 | ||
437 | static void omap_mbox_fini(struct omap_mbox *mbox) | |
438 | { | |
8841a66a SA |
439 | _omap_mbox_disable_irq(mbox, IRQ_RX); |
440 | free_irq(mbox->irq, mbox); | |
441 | flush_work(&mbox->rxq->work); | |
442 | mbox_queue_free(mbox->rxq); | |
340a614a HD |
443 | } |
444 | ||
72c1c817 SA |
445 | static struct omap_mbox *omap_mbox_device_find(struct omap_mbox_device *mdev, |
446 | const char *mbox_name) | |
340a614a | 447 | { |
c0377320 | 448 | struct omap_mbox *_mbox, *mbox = NULL; |
72c1c817 SA |
449 | struct omap_mbox **mboxes = mdev->mboxes; |
450 | int i; | |
340a614a | 451 | |
9c80c8cd | 452 | if (!mboxes) |
72c1c817 | 453 | return NULL; |
340a614a | 454 | |
c0377320 | 455 | for (i = 0; (_mbox = mboxes[i]); i++) { |
72c1c817 | 456 | if (!strcmp(_mbox->name, mbox_name)) { |
c0377320 | 457 | mbox = _mbox; |
9c80c8cd | 458 | break; |
c0377320 KH |
459 | } |
460 | } | |
72c1c817 SA |
461 | return mbox; |
462 | } | |
463 | ||
8841a66a SA |
464 | struct mbox_chan *omap_mbox_request_channel(struct mbox_client *cl, |
465 | const char *chan_name) | |
72c1c817 | 466 | { |
8841a66a | 467 | struct device *dev = cl->dev; |
72c1c817 SA |
468 | struct omap_mbox *mbox = NULL; |
469 | struct omap_mbox_device *mdev; | |
8841a66a SA |
470 | struct mbox_chan *chan; |
471 | unsigned long flags; | |
72c1c817 SA |
472 | int ret; |
473 | ||
8841a66a SA |
474 | if (!dev) |
475 | return ERR_PTR(-ENODEV); | |
476 | ||
477 | if (dev->of_node) { | |
478 | pr_err("%s: please use mbox_request_channel(), this API is supported only for OMAP non-DT usage\n", | |
479 | __func__); | |
480 | return ERR_PTR(-ENODEV); | |
481 | } | |
482 | ||
72c1c817 SA |
483 | mutex_lock(&omap_mbox_devices_lock); |
484 | list_for_each_entry(mdev, &omap_mbox_devices, elem) { | |
8841a66a | 485 | mbox = omap_mbox_device_find(mdev, chan_name); |
72c1c817 SA |
486 | if (mbox) |
487 | break; | |
488 | } | |
489 | mutex_unlock(&omap_mbox_devices_lock); | |
9c80c8cd | 490 | |
8841a66a | 491 | if (!mbox || !mbox->chan) |
9c80c8cd | 492 | return ERR_PTR(-ENOENT); |
340a614a | 493 | |
8841a66a SA |
494 | chan = mbox->chan; |
495 | spin_lock_irqsave(&chan->lock, flags); | |
496 | chan->msg_free = 0; | |
497 | chan->msg_count = 0; | |
498 | chan->active_req = NULL; | |
499 | chan->cl = cl; | |
500 | init_completion(&chan->tx_complete); | |
501 | spin_unlock_irqrestore(&chan->lock, flags); | |
58256307 | 502 | |
8841a66a | 503 | ret = chan->mbox->ops->startup(chan); |
1d8a0e96 | 504 | if (ret) { |
8841a66a SA |
505 | pr_err("Unable to startup the chan (%d)\n", ret); |
506 | mbox_free_channel(chan); | |
507 | chan = ERR_PTR(ret); | |
1d8a0e96 JG |
508 | } |
509 | ||
8841a66a | 510 | return chan; |
340a614a | 511 | } |
8841a66a | 512 | EXPORT_SYMBOL(omap_mbox_request_channel); |
340a614a | 513 | |
6b233985 HD |
514 | static struct class omap_mbox_class = { .name = "mbox", }; |
515 | ||
72c1c817 | 516 | static int omap_mbox_register(struct omap_mbox_device *mdev) |
340a614a | 517 | { |
9c80c8cd FC |
518 | int ret; |
519 | int i; | |
72c1c817 | 520 | struct omap_mbox **mboxes; |
340a614a | 521 | |
72c1c817 | 522 | if (!mdev || !mdev->mboxes) |
340a614a | 523 | return -EINVAL; |
340a614a | 524 | |
72c1c817 | 525 | mboxes = mdev->mboxes; |
9c80c8cd FC |
526 | for (i = 0; mboxes[i]; i++) { |
527 | struct omap_mbox *mbox = mboxes[i]; | |
8841a66a SA |
528 | mbox->dev = device_create(&omap_mbox_class, mdev->dev, |
529 | 0, mbox, "%s", mbox->name); | |
9c80c8cd FC |
530 | if (IS_ERR(mbox->dev)) { |
531 | ret = PTR_ERR(mbox->dev); | |
532 | goto err_out; | |
533 | } | |
534 | } | |
72c1c817 SA |
535 | |
536 | mutex_lock(&omap_mbox_devices_lock); | |
537 | list_add(&mdev->elem, &omap_mbox_devices); | |
538 | mutex_unlock(&omap_mbox_devices_lock); | |
539 | ||
8841a66a | 540 | ret = mbox_controller_register(&mdev->controller); |
f48cca87 | 541 | |
9c80c8cd | 542 | err_out: |
8841a66a SA |
543 | if (ret) { |
544 | while (i--) | |
545 | device_unregister(mboxes[i]->dev); | |
546 | } | |
340a614a HD |
547 | return ret; |
548 | } | |
340a614a | 549 | |
72c1c817 | 550 | static int omap_mbox_unregister(struct omap_mbox_device *mdev) |
340a614a | 551 | { |
9c80c8cd | 552 | int i; |
72c1c817 | 553 | struct omap_mbox **mboxes; |
340a614a | 554 | |
72c1c817 | 555 | if (!mdev || !mdev->mboxes) |
9c80c8cd FC |
556 | return -EINVAL; |
557 | ||
72c1c817 SA |
558 | mutex_lock(&omap_mbox_devices_lock); |
559 | list_del(&mdev->elem); | |
560 | mutex_unlock(&omap_mbox_devices_lock); | |
561 | ||
8841a66a SA |
562 | mbox_controller_unregister(&mdev->controller); |
563 | ||
72c1c817 | 564 | mboxes = mdev->mboxes; |
9c80c8cd FC |
565 | for (i = 0; mboxes[i]; i++) |
566 | device_unregister(mboxes[i]->dev); | |
9c80c8cd | 567 | return 0; |
340a614a | 568 | } |
5040f534 | 569 | |
8841a66a SA |
570 | static int omap_mbox_chan_startup(struct mbox_chan *chan) |
571 | { | |
572 | struct omap_mbox *mbox = mbox_chan_to_omap_mbox(chan); | |
573 | struct omap_mbox_device *mdev = mbox->parent; | |
574 | int ret = 0; | |
575 | ||
576 | mutex_lock(&mdev->cfg_lock); | |
577 | pm_runtime_get_sync(mdev->dev); | |
578 | ret = omap_mbox_startup(mbox); | |
579 | if (ret) | |
580 | pm_runtime_put_sync(mdev->dev); | |
581 | mutex_unlock(&mdev->cfg_lock); | |
582 | return ret; | |
583 | } | |
584 | ||
585 | static void omap_mbox_chan_shutdown(struct mbox_chan *chan) | |
586 | { | |
587 | struct omap_mbox *mbox = mbox_chan_to_omap_mbox(chan); | |
588 | struct omap_mbox_device *mdev = mbox->parent; | |
589 | ||
590 | mutex_lock(&mdev->cfg_lock); | |
591 | omap_mbox_fini(mbox); | |
592 | pm_runtime_put_sync(mdev->dev); | |
593 | mutex_unlock(&mdev->cfg_lock); | |
594 | } | |
595 | ||
8e3c5952 | 596 | static int omap_mbox_chan_send_noirq(struct omap_mbox *mbox, void *data) |
8841a66a | 597 | { |
8841a66a SA |
598 | int ret = -EBUSY; |
599 | ||
8e3c5952 DG |
600 | if (!mbox_fifo_full(mbox)) { |
601 | _omap_mbox_enable_irq(mbox, IRQ_RX); | |
602 | mbox_fifo_write(mbox, (mbox_msg_t)data); | |
603 | ret = 0; | |
604 | _omap_mbox_disable_irq(mbox, IRQ_RX); | |
605 | ||
606 | /* we must read and ack the interrupt directly from here */ | |
607 | mbox_fifo_read(mbox); | |
608 | ack_mbox_irq(mbox, IRQ_RX); | |
609 | } | |
610 | ||
611 | return ret; | |
612 | } | |
613 | ||
614 | static int omap_mbox_chan_send(struct omap_mbox *mbox, void *data) | |
615 | { | |
616 | int ret = -EBUSY; | |
8841a66a SA |
617 | |
618 | if (!mbox_fifo_full(mbox)) { | |
619 | mbox_fifo_write(mbox, (mbox_msg_t)data); | |
620 | ret = 0; | |
621 | } | |
622 | ||
623 | /* always enable the interrupt */ | |
624 | _omap_mbox_enable_irq(mbox, IRQ_TX); | |
625 | return ret; | |
626 | } | |
627 | ||
8e3c5952 DG |
628 | static int omap_mbox_chan_send_data(struct mbox_chan *chan, void *data) |
629 | { | |
630 | struct omap_mbox *mbox = mbox_chan_to_omap_mbox(chan); | |
631 | int ret; | |
632 | ||
633 | if (!mbox) | |
634 | return -EINVAL; | |
635 | ||
636 | if (mbox->send_no_irq) | |
637 | ret = omap_mbox_chan_send_noirq(mbox, data); | |
638 | else | |
639 | ret = omap_mbox_chan_send(mbox, data); | |
640 | ||
641 | return ret; | |
642 | } | |
643 | ||
05ae7975 | 644 | static const struct mbox_chan_ops omap_mbox_chan_ops = { |
8841a66a SA |
645 | .startup = omap_mbox_chan_startup, |
646 | .send_data = omap_mbox_chan_send_data, | |
647 | .shutdown = omap_mbox_chan_shutdown, | |
648 | }; | |
649 | ||
75288cc6 SA |
650 | static const struct of_device_id omap_mailbox_of_match[] = { |
651 | { | |
652 | .compatible = "ti,omap2-mailbox", | |
653 | .data = (void *)MBOX_INTR_CFG_TYPE1, | |
654 | }, | |
655 | { | |
656 | .compatible = "ti,omap3-mailbox", | |
657 | .data = (void *)MBOX_INTR_CFG_TYPE1, | |
658 | }, | |
659 | { | |
660 | .compatible = "ti,omap4-mailbox", | |
661 | .data = (void *)MBOX_INTR_CFG_TYPE2, | |
662 | }, | |
663 | { | |
664 | /* end */ | |
665 | }, | |
666 | }; | |
667 | MODULE_DEVICE_TABLE(of, omap_mailbox_of_match); | |
668 | ||
8841a66a SA |
669 | static struct mbox_chan *omap_mbox_of_xlate(struct mbox_controller *controller, |
670 | const struct of_phandle_args *sp) | |
671 | { | |
672 | phandle phandle = sp->args[0]; | |
673 | struct device_node *node; | |
674 | struct omap_mbox_device *mdev; | |
675 | struct omap_mbox *mbox; | |
676 | ||
677 | mdev = container_of(controller, struct omap_mbox_device, controller); | |
678 | if (WARN_ON(!mdev)) | |
2d805fc1 | 679 | return ERR_PTR(-EINVAL); |
8841a66a SA |
680 | |
681 | node = of_find_node_by_phandle(phandle); | |
682 | if (!node) { | |
683 | pr_err("%s: could not find node phandle 0x%x\n", | |
684 | __func__, phandle); | |
2d805fc1 | 685 | return ERR_PTR(-ENODEV); |
8841a66a SA |
686 | } |
687 | ||
688 | mbox = omap_mbox_device_find(mdev, node->name); | |
689 | of_node_put(node); | |
2d805fc1 | 690 | return mbox ? mbox->chan : ERR_PTR(-ENOENT); |
8841a66a SA |
691 | } |
692 | ||
5040f534 SA |
693 | static int omap_mbox_probe(struct platform_device *pdev) |
694 | { | |
695 | struct resource *mem; | |
696 | int ret; | |
8841a66a | 697 | struct mbox_chan *chnls; |
5040f534 | 698 | struct omap_mbox **list, *mbox, *mboxblk; |
5040f534 | 699 | struct omap_mbox_pdata *pdata = pdev->dev.platform_data; |
75288cc6 SA |
700 | struct omap_mbox_dev_info *info = NULL; |
701 | struct omap_mbox_fifo_info *finfo, *finfoblk; | |
72c1c817 | 702 | struct omap_mbox_device *mdev; |
be3322eb | 703 | struct omap_mbox_fifo *fifo; |
75288cc6 SA |
704 | struct device_node *node = pdev->dev.of_node; |
705 | struct device_node *child; | |
706 | const struct of_device_id *match; | |
707 | u32 intr_type, info_count; | |
708 | u32 num_users, num_fifos; | |
709 | u32 tmp[3]; | |
5040f534 SA |
710 | u32 l; |
711 | int i; | |
712 | ||
75288cc6 | 713 | if (!node && (!pdata || !pdata->info_cnt || !pdata->info)) { |
5040f534 SA |
714 | pr_err("%s: platform not supported\n", __func__); |
715 | return -ENODEV; | |
716 | } | |
717 | ||
75288cc6 SA |
718 | if (node) { |
719 | match = of_match_device(omap_mailbox_of_match, &pdev->dev); | |
720 | if (!match) | |
721 | return -ENODEV; | |
722 | intr_type = (u32)match->data; | |
723 | ||
724 | if (of_property_read_u32(node, "ti,mbox-num-users", | |
725 | &num_users)) | |
726 | return -ENODEV; | |
727 | ||
728 | if (of_property_read_u32(node, "ti,mbox-num-fifos", | |
729 | &num_fifos)) | |
730 | return -ENODEV; | |
731 | ||
732 | info_count = of_get_available_child_count(node); | |
733 | if (!info_count) { | |
734 | dev_err(&pdev->dev, "no available mbox devices found\n"); | |
735 | return -ENODEV; | |
736 | } | |
737 | } else { /* non-DT device creation */ | |
738 | info_count = pdata->info_cnt; | |
739 | info = pdata->info; | |
740 | intr_type = pdata->intr_type; | |
741 | num_users = pdata->num_users; | |
742 | num_fifos = pdata->num_fifos; | |
743 | } | |
744 | ||
745 | finfoblk = devm_kzalloc(&pdev->dev, info_count * sizeof(*finfoblk), | |
746 | GFP_KERNEL); | |
747 | if (!finfoblk) | |
748 | return -ENOMEM; | |
749 | ||
750 | finfo = finfoblk; | |
751 | child = NULL; | |
752 | for (i = 0; i < info_count; i++, finfo++) { | |
753 | if (node) { | |
754 | child = of_get_next_available_child(node, child); | |
755 | ret = of_property_read_u32_array(child, "ti,mbox-tx", | |
756 | tmp, ARRAY_SIZE(tmp)); | |
757 | if (ret) | |
758 | return ret; | |
759 | finfo->tx_id = tmp[0]; | |
760 | finfo->tx_irq = tmp[1]; | |
761 | finfo->tx_usr = tmp[2]; | |
762 | ||
763 | ret = of_property_read_u32_array(child, "ti,mbox-rx", | |
764 | tmp, ARRAY_SIZE(tmp)); | |
765 | if (ret) | |
766 | return ret; | |
767 | finfo->rx_id = tmp[0]; | |
768 | finfo->rx_irq = tmp[1]; | |
769 | finfo->rx_usr = tmp[2]; | |
770 | ||
771 | finfo->name = child->name; | |
8e3c5952 DG |
772 | |
773 | if (of_find_property(child, "ti,mbox-send-noirq", NULL)) | |
774 | finfo->send_no_irq = true; | |
75288cc6 SA |
775 | } else { |
776 | finfo->tx_id = info->tx_id; | |
777 | finfo->rx_id = info->rx_id; | |
778 | finfo->tx_usr = info->usr_id; | |
779 | finfo->tx_irq = info->irq_id; | |
780 | finfo->rx_usr = info->usr_id; | |
781 | finfo->rx_irq = info->irq_id; | |
782 | finfo->name = info->name; | |
783 | info++; | |
784 | } | |
785 | if (finfo->tx_id >= num_fifos || finfo->rx_id >= num_fifos || | |
786 | finfo->tx_usr >= num_users || finfo->rx_usr >= num_users) | |
787 | return -EINVAL; | |
788 | } | |
789 | ||
72c1c817 SA |
790 | mdev = devm_kzalloc(&pdev->dev, sizeof(*mdev), GFP_KERNEL); |
791 | if (!mdev) | |
792 | return -ENOMEM; | |
793 | ||
794 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
795 | mdev->mbox_base = devm_ioremap_resource(&pdev->dev, mem); | |
796 | if (IS_ERR(mdev->mbox_base)) | |
797 | return PTR_ERR(mdev->mbox_base); | |
798 | ||
5040f534 | 799 | /* allocate one extra for marking end of list */ |
75288cc6 | 800 | list = devm_kzalloc(&pdev->dev, (info_count + 1) * sizeof(*list), |
5040f534 SA |
801 | GFP_KERNEL); |
802 | if (!list) | |
803 | return -ENOMEM; | |
804 | ||
8841a66a SA |
805 | chnls = devm_kzalloc(&pdev->dev, (info_count + 1) * sizeof(*chnls), |
806 | GFP_KERNEL); | |
807 | if (!chnls) | |
808 | return -ENOMEM; | |
809 | ||
75288cc6 | 810 | mboxblk = devm_kzalloc(&pdev->dev, info_count * sizeof(*mbox), |
5040f534 SA |
811 | GFP_KERNEL); |
812 | if (!mboxblk) | |
813 | return -ENOMEM; | |
814 | ||
5040f534 | 815 | mbox = mboxblk; |
75288cc6 SA |
816 | finfo = finfoblk; |
817 | for (i = 0; i < info_count; i++, finfo++) { | |
be3322eb | 818 | fifo = &mbox->tx_fifo; |
75288cc6 SA |
819 | fifo->msg = MAILBOX_MESSAGE(finfo->tx_id); |
820 | fifo->fifo_stat = MAILBOX_FIFOSTATUS(finfo->tx_id); | |
821 | fifo->intr_bit = MAILBOX_IRQ_NOTFULL(finfo->tx_id); | |
822 | fifo->irqenable = MAILBOX_IRQENABLE(intr_type, finfo->tx_usr); | |
823 | fifo->irqstatus = MAILBOX_IRQSTATUS(intr_type, finfo->tx_usr); | |
824 | fifo->irqdisable = MAILBOX_IRQDISABLE(intr_type, finfo->tx_usr); | |
be3322eb SA |
825 | |
826 | fifo = &mbox->rx_fifo; | |
75288cc6 SA |
827 | fifo->msg = MAILBOX_MESSAGE(finfo->rx_id); |
828 | fifo->msg_stat = MAILBOX_MSGSTATUS(finfo->rx_id); | |
829 | fifo->intr_bit = MAILBOX_IRQ_NEWMSG(finfo->rx_id); | |
830 | fifo->irqenable = MAILBOX_IRQENABLE(intr_type, finfo->rx_usr); | |
831 | fifo->irqstatus = MAILBOX_IRQSTATUS(intr_type, finfo->rx_usr); | |
832 | fifo->irqdisable = MAILBOX_IRQDISABLE(intr_type, finfo->rx_usr); | |
be3322eb | 833 | |
8e3c5952 | 834 | mbox->send_no_irq = finfo->send_no_irq; |
be3322eb SA |
835 | mbox->intr_type = intr_type; |
836 | ||
72c1c817 | 837 | mbox->parent = mdev; |
75288cc6 SA |
838 | mbox->name = finfo->name; |
839 | mbox->irq = platform_get_irq(pdev, finfo->tx_irq); | |
5040f534 SA |
840 | if (mbox->irq < 0) |
841 | return mbox->irq; | |
8841a66a SA |
842 | mbox->chan = &chnls[i]; |
843 | chnls[i].con_priv = mbox; | |
5040f534 SA |
844 | list[i] = mbox++; |
845 | } | |
846 | ||
72c1c817 SA |
847 | mutex_init(&mdev->cfg_lock); |
848 | mdev->dev = &pdev->dev; | |
75288cc6 SA |
849 | mdev->num_users = num_users; |
850 | mdev->num_fifos = num_fifos; | |
72c1c817 | 851 | mdev->mboxes = list; |
8841a66a SA |
852 | |
853 | /* OMAP does not have a Tx-Done IRQ, but rather a Tx-Ready IRQ */ | |
854 | mdev->controller.txdone_irq = true; | |
855 | mdev->controller.dev = mdev->dev; | |
856 | mdev->controller.ops = &omap_mbox_chan_ops; | |
857 | mdev->controller.chans = chnls; | |
858 | mdev->controller.num_chans = info_count; | |
859 | mdev->controller.of_xlate = omap_mbox_of_xlate; | |
72c1c817 | 860 | ret = omap_mbox_register(mdev); |
5040f534 SA |
861 | if (ret) |
862 | return ret; | |
863 | ||
72c1c817 SA |
864 | platform_set_drvdata(pdev, mdev); |
865 | pm_runtime_enable(mdev->dev); | |
5040f534 | 866 | |
72c1c817 | 867 | ret = pm_runtime_get_sync(mdev->dev); |
5040f534 | 868 | if (ret < 0) { |
72c1c817 | 869 | pm_runtime_put_noidle(mdev->dev); |
5040f534 SA |
870 | goto unregister; |
871 | } | |
872 | ||
873 | /* | |
874 | * just print the raw revision register, the format is not | |
875 | * uniform across all SoCs | |
876 | */ | |
72c1c817 SA |
877 | l = mbox_read_reg(mdev, MAILBOX_REVISION); |
878 | dev_info(mdev->dev, "omap mailbox rev 0x%x\n", l); | |
5040f534 | 879 | |
72c1c817 | 880 | ret = pm_runtime_put_sync(mdev->dev); |
5040f534 SA |
881 | if (ret < 0) |
882 | goto unregister; | |
883 | ||
75288cc6 | 884 | devm_kfree(&pdev->dev, finfoblk); |
5040f534 SA |
885 | return 0; |
886 | ||
887 | unregister: | |
72c1c817 SA |
888 | pm_runtime_disable(mdev->dev); |
889 | omap_mbox_unregister(mdev); | |
5040f534 SA |
890 | return ret; |
891 | } | |
892 | ||
893 | static int omap_mbox_remove(struct platform_device *pdev) | |
894 | { | |
72c1c817 SA |
895 | struct omap_mbox_device *mdev = platform_get_drvdata(pdev); |
896 | ||
897 | pm_runtime_disable(mdev->dev); | |
898 | omap_mbox_unregister(mdev); | |
5040f534 SA |
899 | |
900 | return 0; | |
901 | } | |
902 | ||
903 | static struct platform_driver omap_mbox_driver = { | |
904 | .probe = omap_mbox_probe, | |
905 | .remove = omap_mbox_remove, | |
906 | .driver = { | |
907 | .name = "omap-mailbox", | |
75288cc6 | 908 | .of_match_table = of_match_ptr(omap_mailbox_of_match), |
5040f534 SA |
909 | }, |
910 | }; | |
340a614a | 911 | |
c7c158e5 | 912 | static int __init omap_mbox_init(void) |
340a614a | 913 | { |
6b233985 HD |
914 | int err; |
915 | ||
916 | err = class_register(&omap_mbox_class); | |
917 | if (err) | |
918 | return err; | |
919 | ||
b5bebe41 OBC |
920 | /* kfifo size sanity check: alignment and minimal size */ |
921 | mbox_kfifo_size = ALIGN(mbox_kfifo_size, sizeof(mbox_msg_t)); | |
ab66ac30 KH |
922 | mbox_kfifo_size = max_t(unsigned int, mbox_kfifo_size, |
923 | sizeof(mbox_msg_t)); | |
b5bebe41 | 924 | |
5040f534 | 925 | return platform_driver_register(&omap_mbox_driver); |
340a614a | 926 | } |
6b233985 | 927 | subsys_initcall(omap_mbox_init); |
340a614a | 928 | |
c7c158e5 | 929 | static void __exit omap_mbox_exit(void) |
340a614a | 930 | { |
5040f534 | 931 | platform_driver_unregister(&omap_mbox_driver); |
6b233985 | 932 | class_unregister(&omap_mbox_class); |
340a614a | 933 | } |
c7c158e5 | 934 | module_exit(omap_mbox_exit); |
340a614a | 935 | |
f48cca87 HD |
936 | MODULE_LICENSE("GPL v2"); |
937 | MODULE_DESCRIPTION("omap mailbox: interrupt driven messaging"); | |
f375325a OBC |
938 | MODULE_AUTHOR("Toshihiro Kobayashi"); |
939 | MODULE_AUTHOR("Hiroshi DOYU"); |