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drm/client: fix circular reference counting issue
[linux-block.git] / drivers / mailbox / mtk-cmdq-mailbox.c
CommitLineData
623a6143
HW		 1// SPDX-License-Identifier: GPL-2.0
2//
3// Copyright (c) 2018 MediaTek Inc.
4
5#include <linux/bitops.h>
6#include <linux/clk.h>
7#include <linux/clk-provider.h>
8#include <linux/dma-mapping.h>
9#include <linux/errno.h>
10#include <linux/interrupt.h>
62e59c4e 11#include <linux/io.h>
623a6143
HW		 12#include <linux/iopoll.h>
13#include <linux/kernel.h>
14#include <linux/module.h>
15#include <linux/platform_device.h>
16#include <linux/mailbox_controller.h>
17#include <linux/mailbox/mtk-cmdq-mailbox.h>
18#include <linux/of_device.h>
19
20#define CMDQ_OP_CODE_MASK (0xff << CMDQ_OP_CODE_SHIFT)
623a6143 21#define CMDQ_NUM_CMD(t) (t->cmd_buf_size / CMDQ_INST_SIZE)
85dfdbfc 22#define CMDQ_GCE_NUM_MAX (2)
623a6143
HW		 23
24#define CMDQ_CURR_IRQ_STATUS 0x10
6058f118 25#define CMDQ_SYNC_TOKEN_UPDATE 0x68
623a6143
HW		 26#define CMDQ_THR_SLOT_CYCLES 0x30
27#define CMDQ_THR_BASE 0x100
28#define CMDQ_THR_SIZE 0x80
29#define CMDQ_THR_WARM_RESET 0x00
30#define CMDQ_THR_ENABLE_TASK 0x04
31#define CMDQ_THR_SUSPEND_TASK 0x08
32#define CMDQ_THR_CURR_STATUS 0x0c
33#define CMDQ_THR_IRQ_STATUS 0x10
34#define CMDQ_THR_IRQ_ENABLE 0x14
35#define CMDQ_THR_CURR_ADDR 0x20
36#define CMDQ_THR_END_ADDR 0x24
37#define CMDQ_THR_WAIT_TOKEN 0x30
38#define CMDQ_THR_PRIORITY 0x40
39
84fd4201 40#define GCE_GCTL_VALUE 0x48
23ba2e7f 41#define GCE_CTRL_BY_SW GENMASK(2, 0)
63f40a7f 42#define GCE_DDR_EN GENMASK(18, 16)
84fd4201 43
623a6143
HW		 44#define CMDQ_THR_ACTIVE_SLOT_CYCLES 0x3200
45#define CMDQ_THR_ENABLED 0x1
46#define CMDQ_THR_DISABLED 0x0
47#define CMDQ_THR_SUSPEND 0x1
48#define CMDQ_THR_RESUME 0x0
49#define CMDQ_THR_STATUS_SUSPENDED BIT(1)
50#define CMDQ_THR_DO_WARM_RESET BIT(0)
51#define CMDQ_THR_IRQ_DONE 0x1
52#define CMDQ_THR_IRQ_ERROR 0x12
53#define CMDQ_THR_IRQ_EN (CMDQ_THR_IRQ_ERROR | CMDQ_THR_IRQ_DONE)
54#define CMDQ_THR_IS_WAITING BIT(31)
55
56#define CMDQ_JUMP_BY_OFFSET 0x10000000
57#define CMDQ_JUMP_BY_PA 0x10000001
58
59struct cmdq_thread {
60 struct mbox_chan *chan;
61 void __iomem *base;
62 struct list_head task_busy_list;
63 u32 priority;
623a6143
HW		 64};
65
66struct cmdq_task {
67 struct cmdq *cmdq;
68 struct list_head list_entry;
69 dma_addr_t pa_base;
70 struct cmdq_thread *thread;
71 struct cmdq_pkt *pkt; /* the packet sent from mailbox client */
72};
73
74struct cmdq {
75 struct mbox_controller mbox;
76 void __iomem *base;
558e4c36 77 int irq;
2c49e4e8 78 u32 irq_mask;
acabe12c 79 const struct gce_plat *pdata;
623a6143 80 struct cmdq_thread *thread;
85dfdbfc 81 struct clk_bulk_data clocks[CMDQ_GCE_NUM_MAX];
623a6143
HW		 82 bool suspended;
83};
84
0858fde4
DYH		 85struct gce_plat {
86 u32 thread_nr;
87 u8 shift;
84fd4201 88 bool control_by_sw;
63f40a7f 89 bool sw_ddr_en;
85dfdbfc 90 u32 gce_num;
0858fde4
DYH		 91};
92
7abd037a
YN		 93static void cmdq_sw_ddr_enable(struct cmdq *cmdq, bool enable)
94{
acabe12c 95 WARN_ON(clk_bulk_enable(cmdq->pdata->gce_num, cmdq->clocks));
7abd037a
YN		 96
97 if (enable)
98 writel(GCE_DDR_EN | GCE_CTRL_BY_SW, cmdq->base + GCE_GCTL_VALUE);
99 else
100 writel(GCE_CTRL_BY_SW, cmdq->base + GCE_GCTL_VALUE);
101
acabe12c 102 clk_bulk_disable(cmdq->pdata->gce_num, cmdq->clocks);
7abd037a
YN		 103}
104
0858fde4
DYH		 105u8 cmdq_get_shift_pa(struct mbox_chan *chan)
106{
107 struct cmdq *cmdq = container_of(chan->mbox, struct cmdq, mbox);
108
acabe12c 109 return cmdq->pdata->shift;
0858fde4
DYH		 110}
111EXPORT_SYMBOL(cmdq_get_shift_pa);
112
623a6143
HW		 113static int cmdq_thread_suspend(struct cmdq *cmdq, struct cmdq_thread *thread)
114{
115 u32 status;
116
117 writel(CMDQ_THR_SUSPEND, thread->base + CMDQ_THR_SUSPEND_TASK);
118
119 /* If already disabled, treat as suspended successful. */
120 if (!(readl(thread->base + CMDQ_THR_ENABLE_TASK) & CMDQ_THR_ENABLED))
121 return 0;
122
123 if (readl_poll_timeout_atomic(thread->base + CMDQ_THR_CURR_STATUS,
124 status, status & CMDQ_THR_STATUS_SUSPENDED, 0, 10)) {
125 dev_err(cmdq->mbox.dev, "suspend GCE thread 0x%x failed\n",
126 (u32)(thread->base - cmdq->base));
127 return -EFAULT;
128 }
129
130 return 0;
131}
132
133static void cmdq_thread_resume(struct cmdq_thread *thread)
134{
135 writel(CMDQ_THR_RESUME, thread->base + CMDQ_THR_SUSPEND_TASK);
136}
137
138static void cmdq_init(struct cmdq *cmdq)
139{
6058f118 140 int i;
63f40a7f 141 u32 gctl_regval = 0;
6058f118 142
acabe12c
ADR		 143 WARN_ON(clk_bulk_enable(cmdq->pdata->gce_num, cmdq->clocks));
144 if (cmdq->pdata->control_by_sw)
63f40a7f 145 gctl_regval = GCE_CTRL_BY_SW;
acabe12c 146 if (cmdq->pdata->sw_ddr_en)
63f40a7f
YN		 147 gctl_regval |= GCE_DDR_EN;
148
149 if (gctl_regval)
150 writel(gctl_regval, cmdq->base + GCE_GCTL_VALUE);
23ba2e7f 151
623a6143 152 writel(CMDQ_THR_ACTIVE_SLOT_CYCLES, cmdq->base + CMDQ_THR_SLOT_CYCLES);
6058f118
BH		 153 for (i = 0; i <= CMDQ_MAX_EVENT; i++)
154 writel(i, cmdq->base + CMDQ_SYNC_TOKEN_UPDATE);
acabe12c 155 clk_bulk_disable(cmdq->pdata->gce_num, cmdq->clocks);
623a6143
HW		 156}
157
158static int cmdq_thread_reset(struct cmdq *cmdq, struct cmdq_thread *thread)
159{
160 u32 warm_reset;
161
162 writel(CMDQ_THR_DO_WARM_RESET, thread->base + CMDQ_THR_WARM_RESET);
163 if (readl_poll_timeout_atomic(thread->base + CMDQ_THR_WARM_RESET,
164 warm_reset, !(warm_reset & CMDQ_THR_DO_WARM_RESET),
165 0, 10)) {
166 dev_err(cmdq->mbox.dev, "reset GCE thread 0x%x failed\n",
167 (u32)(thread->base - cmdq->base));
168 return -EFAULT;
169 }
170
171 return 0;
172}
173
174static void cmdq_thread_disable(struct cmdq *cmdq, struct cmdq_thread *thread)
175{
176 cmdq_thread_reset(cmdq, thread);
177 writel(CMDQ_THR_DISABLED, thread->base + CMDQ_THR_ENABLE_TASK);
178}
179
180/* notify GCE to re-fetch commands by setting GCE thread PC */
181static void cmdq_thread_invalidate_fetched_data(struct cmdq_thread *thread)
182{
183 writel(readl(thread->base + CMDQ_THR_CURR_ADDR),
184 thread->base + CMDQ_THR_CURR_ADDR);
185}
186
187static void cmdq_task_insert_into_thread(struct cmdq_task *task)
188{
189 struct device *dev = task->cmdq->mbox.dev;
190 struct cmdq_thread *thread = task->thread;
191 struct cmdq_task *prev_task = list_last_entry(
192 &thread->task_busy_list, typeof(*task), list_entry);
193 u64 *prev_task_base = prev_task->pkt->va_base;
194
195 /* let previous task jump to this task */
196 dma_sync_single_for_cpu(dev, prev_task->pa_base,
197 prev_task->pkt->cmd_buf_size, DMA_TO_DEVICE);
198 prev_task_base[CMDQ_NUM_CMD(prev_task->pkt) - 1] =
8b60ed2b 199 (u64)CMDQ_JUMP_BY_PA << 32 |
acabe12c 200 (task->pa_base >> task->cmdq->pdata->shift);
623a6143
HW		 201 dma_sync_single_for_device(dev, prev_task->pa_base,
202 prev_task->pkt->cmd_buf_size, DMA_TO_DEVICE);
203
204 cmdq_thread_invalidate_fetched_data(thread);
205}
206
623a6143
HW		 207static bool cmdq_thread_is_in_wfe(struct cmdq_thread *thread)
208{
209 return readl(thread->base + CMDQ_THR_WAIT_TOKEN) & CMDQ_THR_IS_WAITING;
210}
211
b3c0d72b 212static void cmdq_task_exec_done(struct cmdq_task *task, int sta)
623a6143 213{
623a6143
HW		 214 struct cmdq_cb_data data;
215
623a6143 216 data.sta = sta;
8ebc3b5a 217 data.pkt = task->pkt;
1b6b0ce2 218 mbox_chan_received_data(task->thread->chan, &data);
623a6143
HW		 219
220 list_del(&task->list_entry);
221}
222
223static void cmdq_task_handle_error(struct cmdq_task *task)
224{
225 struct cmdq_thread *thread = task->thread;
226 struct cmdq_task *next_task;
0858fde4 227 struct cmdq *cmdq = task->cmdq;
623a6143 228
0858fde4
DYH		 229 dev_err(cmdq->mbox.dev, "task 0x%p error\n", task);
230 WARN_ON(cmdq_thread_suspend(cmdq, thread) < 0);
623a6143
HW		 231 next_task = list_first_entry_or_null(&thread->task_busy_list,
232 struct cmdq_task, list_entry);
233 if (next_task)
acabe12c 234 writel(next_task->pa_base >> cmdq->pdata->shift,
0858fde4 235 thread->base + CMDQ_THR_CURR_ADDR);
623a6143
HW		 236 cmdq_thread_resume(thread);
237}
238
239static void cmdq_thread_irq_handler(struct cmdq *cmdq,
240 struct cmdq_thread *thread)
241{
242 struct cmdq_task *task, *tmp, *curr_task = NULL;
243 u32 curr_pa, irq_flag, task_end_pa;
244 bool err;
245
246 irq_flag = readl(thread->base + CMDQ_THR_IRQ_STATUS);
247 writel(~irq_flag, thread->base + CMDQ_THR_IRQ_STATUS);
248
249 /*
250 * When ISR call this function, another CPU core could run
251 * "release task" right before we acquire the spin lock, and thus
252 * reset / disable this GCE thread, so we need to check the enable
253 * bit of this GCE thread.
254 */
255 if (!(readl(thread->base + CMDQ_THR_ENABLE_TASK) & CMDQ_THR_ENABLED))
256 return;
257
258 if (irq_flag & CMDQ_THR_IRQ_ERROR)
259 err = true;
260 else if (irq_flag & CMDQ_THR_IRQ_DONE)
261 err = false;
262 else
263 return;
264
acabe12c 265 curr_pa = readl(thread->base + CMDQ_THR_CURR_ADDR) << cmdq->pdata->shift;
623a6143
HW		 266
267 list_for_each_entry_safe(task, tmp, &thread->task_busy_list,
268 list_entry) {
269 task_end_pa = task->pa_base + task->pkt->cmd_buf_size;
270 if (curr_pa >= task->pa_base && curr_pa < task_end_pa)
271 curr_task = task;
272
273 if (!curr_task || curr_pa == task_end_pa - CMDQ_INST_SIZE) {
b3c0d72b 274 cmdq_task_exec_done(task, 0);
623a6143
HW		 275 kfree(task);
276 } else if (err) {
b3c0d72b 277 cmdq_task_exec_done(task, -ENOEXEC);
623a6143
HW		 278 cmdq_task_handle_error(curr_task);
279 kfree(task);
280 }
281
282 if (curr_task)
283 break;
284 }
285
286 if (list_empty(&thread->task_busy_list)) {
287 cmdq_thread_disable(cmdq, thread);
acabe12c 288 clk_bulk_disable(cmdq->pdata->gce_num, cmdq->clocks);
623a6143
HW		 289 }
290}
291
292static irqreturn_t cmdq_irq_handler(int irq, void *dev)
293{
294 struct cmdq *cmdq = dev;
295 unsigned long irq_status, flags = 0L;
296 int bit;
297
2c49e4e8
BH		 298 irq_status = readl(cmdq->base + CMDQ_CURR_IRQ_STATUS) & cmdq->irq_mask;
299 if (!(irq_status ^ cmdq->irq_mask))
623a6143
HW		 300 return IRQ_NONE;
301
acabe12c 302 for_each_clear_bit(bit, &irq_status, cmdq->pdata->thread_nr) {
623a6143
HW		 303 struct cmdq_thread *thread = &cmdq->thread[bit];
304
305 spin_lock_irqsave(&thread->chan->lock, flags);
306 cmdq_thread_irq_handler(cmdq, thread);
307 spin_unlock_irqrestore(&thread->chan->lock, flags);
308 }
309
310 return IRQ_HANDLED;
311}
312
313static int cmdq_suspend(struct device *dev)
314{
315 struct cmdq *cmdq = dev_get_drvdata(dev);
316 struct cmdq_thread *thread;
317 int i;
318 bool task_running = false;
319
320 cmdq->suspended = true;
321
acabe12c 322 for (i = 0; i < cmdq->pdata->thread_nr; i++) {
623a6143
HW		 323 thread = &cmdq->thread[i];
324 if (!list_empty(&thread->task_busy_list)) {
325 task_running = true;
326 break;
327 }
328 }
329
330 if (task_running)
331 dev_warn(dev, "exist running task(s) in suspend\n");
332
acabe12c 333 if (cmdq->pdata->sw_ddr_en)
7abd037a
YN		 334 cmdq_sw_ddr_enable(cmdq, false);
335
acabe12c 336 clk_bulk_unprepare(cmdq->pdata->gce_num, cmdq->clocks);
623a6143
HW		 337
338 return 0;
339}
340
341static int cmdq_resume(struct device *dev)
342{
343 struct cmdq *cmdq = dev_get_drvdata(dev);
344
acabe12c 345 WARN_ON(clk_bulk_prepare(cmdq->pdata->gce_num, cmdq->clocks));
623a6143 346 cmdq->suspended = false;
7abd037a 347
acabe12c 348 if (cmdq->pdata->sw_ddr_en)
7abd037a
YN		 349 cmdq_sw_ddr_enable(cmdq, true);
350
623a6143
HW		 351 return 0;
352}
353
354static int cmdq_remove(struct platform_device *pdev)
355{
356 struct cmdq *cmdq = platform_get_drvdata(pdev);
357
acabe12c 358 if (cmdq->pdata->sw_ddr_en)
7abd037a
YN		 359 cmdq_sw_ddr_enable(cmdq, false);
360
acabe12c 361 clk_bulk_unprepare(cmdq->pdata->gce_num, cmdq->clocks);
623a6143
HW		 362 return 0;
363}
364
365static int cmdq_mbox_send_data(struct mbox_chan *chan, void *data)
366{
367 struct cmdq_pkt *pkt = (struct cmdq_pkt *)data;
368 struct cmdq_thread *thread = (struct cmdq_thread *)chan->con_priv;
369 struct cmdq *cmdq = dev_get_drvdata(chan->mbox->dev);
370 struct cmdq_task *task;
371 unsigned long curr_pa, end_pa;
372
373 /* Client should not flush new tasks if suspended. */
374 WARN_ON(cmdq->suspended);
375
376 task = kzalloc(sizeof(*task), GFP_ATOMIC);
9f0a0a38
HW		 377 if (!task)
378 return -ENOMEM;
379
623a6143
HW		 380 task->cmdq = cmdq;
381 INIT_LIST_HEAD(&task->list_entry);
382 task->pa_base = pkt->pa_base;
383 task->thread = thread;
384 task->pkt = pkt;
385
386 if (list_empty(&thread->task_busy_list)) {
acabe12c 387 WARN_ON(clk_bulk_enable(cmdq->pdata->gce_num, cmdq->clocks));
85dfdbfc 388
88499698
DYH		 389 /*
390 * The thread reset will clear thread related register to 0,
391 * including pc, end, priority, irq, suspend and enable. Thus
392 * set CMDQ_THR_ENABLED to CMDQ_THR_ENABLE_TASK will enable
393 * thread and make it running.
394 */
623a6143
HW		 395 WARN_ON(cmdq_thread_reset(cmdq, thread) < 0);
396
acabe12c 397 writel(task->pa_base >> cmdq->pdata->shift,
0858fde4 398 thread->base + CMDQ_THR_CURR_ADDR);
acabe12c 399 writel((task->pa_base + pkt->cmd_buf_size) >> cmdq->pdata->shift,
623a6143 400 thread->base + CMDQ_THR_END_ADDR);
0858fde4 401
623a6143
HW		 402 writel(thread->priority, thread->base + CMDQ_THR_PRIORITY);
403 writel(CMDQ_THR_IRQ_EN, thread->base + CMDQ_THR_IRQ_ENABLE);
404 writel(CMDQ_THR_ENABLED, thread->base + CMDQ_THR_ENABLE_TASK);
405 } else {
406 WARN_ON(cmdq_thread_suspend(cmdq, thread) < 0);
0858fde4 407 curr_pa = readl(thread->base + CMDQ_THR_CURR_ADDR) <<
acabe12c 408 cmdq->pdata->shift;
0858fde4 409 end_pa = readl(thread->base + CMDQ_THR_END_ADDR) <<
acabe12c 410 cmdq->pdata->shift;
c9ea564f
BH		 411 /* check boundary */
412 if (curr_pa == end_pa - CMDQ_INST_SIZE ||
413 curr_pa == end_pa) {
414 /* set to this task directly */
acabe12c 415 writel(task->pa_base >> cmdq->pdata->shift,
c9ea564f 416 thread->base + CMDQ_THR_CURR_ADDR);
623a6143 417 } else {
c9ea564f
BH		 418 cmdq_task_insert_into_thread(task);
419 smp_mb(); /* modify jump before enable thread */
623a6143 420 }
acabe12c 421 writel((task->pa_base + pkt->cmd_buf_size) >> cmdq->pdata->shift,
623a6143
HW		 422 thread->base + CMDQ_THR_END_ADDR);
423 cmdq_thread_resume(thread);
424 }
425 list_move_tail(&task->list_entry, &thread->task_busy_list);
426
427 return 0;
428}
429
430static int cmdq_mbox_startup(struct mbox_chan *chan)
431{
432 return 0;
433}
434
435static void cmdq_mbox_shutdown(struct mbox_chan *chan)
436{
88499698
DYH		 437 struct cmdq_thread *thread = (struct cmdq_thread *)chan->con_priv;
438 struct cmdq *cmdq = dev_get_drvdata(chan->mbox->dev);
439 struct cmdq_task *task, *tmp;
440 unsigned long flags;
441
442 spin_lock_irqsave(&thread->chan->lock, flags);
443 if (list_empty(&thread->task_busy_list))
444 goto done;
445
446 WARN_ON(cmdq_thread_suspend(cmdq, thread) < 0);
447
448 /* make sure executed tasks have success callback */
449 cmdq_thread_irq_handler(cmdq, thread);
450 if (list_empty(&thread->task_busy_list))
451 goto done;
452
453 list_for_each_entry_safe(task, tmp, &thread->task_busy_list,
454 list_entry) {
b3c0d72b 455 cmdq_task_exec_done(task, -ECONNABORTED);
88499698
DYH		 456 kfree(task);
457 }
458
459 cmdq_thread_disable(cmdq, thread);
acabe12c 460 clk_bulk_disable(cmdq->pdata->gce_num, cmdq->clocks);
85dfdbfc 461
88499698
DYH		 462done:
463 /*
464 * The thread->task_busy_list empty means thread already disable. The
465 * cmdq_mbox_send_data() always reset thread which clear disable and
466 * suspend statue when first pkt send to channel, so there is no need
467 * to do any operation here, only unlock and leave.
468 */
469 spin_unlock_irqrestore(&thread->chan->lock, flags);
623a6143
HW		 470}
471
b0524f7c
BH		 472static int cmdq_mbox_flush(struct mbox_chan *chan, unsigned long timeout)
473{
474 struct cmdq_thread *thread = (struct cmdq_thread *)chan->con_priv;
b0524f7c
BH		 475 struct cmdq_cb_data data;
476 struct cmdq *cmdq = dev_get_drvdata(chan->mbox->dev);
477 struct cmdq_task *task, *tmp;
478 unsigned long flags;
479 u32 enable;
480
481 spin_lock_irqsave(&thread->chan->lock, flags);
482 if (list_empty(&thread->task_busy_list))
483 goto out;
484
485 WARN_ON(cmdq_thread_suspend(cmdq, thread) < 0);
486 if (!cmdq_thread_is_in_wfe(thread))
487 goto wait;
488
489 list_for_each_entry_safe(task, tmp, &thread->task_busy_list,
490 list_entry) {
1b6b0ce2 491 data.sta = -ECONNABORTED;
8ebc3b5a 492 data.pkt = task->pkt;
1b6b0ce2 493 mbox_chan_received_data(task->thread->chan, &data);
b0524f7c
BH		 494 list_del(&task->list_entry);
495 kfree(task);
496 }
497
498 cmdq_thread_resume(thread);
499 cmdq_thread_disable(cmdq, thread);
acabe12c 500 clk_bulk_disable(cmdq->pdata->gce_num, cmdq->clocks);
b0524f7c
BH		 501
502out:
503 spin_unlock_irqrestore(&thread->chan->lock, flags);
504 return 0;
505
506wait:
507 cmdq_thread_resume(thread);
508 spin_unlock_irqrestore(&thread->chan->lock, flags);
509 if (readl_poll_timeout_atomic(thread->base + CMDQ_THR_ENABLE_TASK,
510 enable, enable == 0, 1, timeout)) {
511 dev_err(cmdq->mbox.dev, "Fail to wait GCE thread 0x%x done\n",
512 (u32)(thread->base - cmdq->base));
513
514 return -EFAULT;
515 }
516 return 0;
517}
518
623a6143
HW		 519static const struct mbox_chan_ops cmdq_mbox_chan_ops = {
520 .send_data = cmdq_mbox_send_data,
521 .startup = cmdq_mbox_startup,
522 .shutdown = cmdq_mbox_shutdown,
b0524f7c 523 .flush = cmdq_mbox_flush,
623a6143
HW		 524};
525
526static struct mbox_chan *cmdq_xlate(struct mbox_controller *mbox,
527 const struct of_phandle_args *sp)
528{
529 int ind = sp->args[0];
530 struct cmdq_thread *thread;
531
532 if (ind >= mbox->num_chans)
533 return ERR_PTR(-EINVAL);
534
535 thread = (struct cmdq_thread *)mbox->chans[ind].con_priv;
536 thread->priority = sp->args[1];
623a6143
HW		 537 thread->chan = &mbox->chans[ind];
538
539 return &mbox->chans[ind];
540}
541
542static int cmdq_probe(struct platform_device *pdev)
543{
544 struct device *dev = &pdev->dev;
623a6143
HW		 545 struct cmdq *cmdq;
546 int err, i;
85dfdbfc 547 struct device_node *phandle = dev->of_node;
548 struct device_node *node;
549 int alias_id = 0;
0a5ad432
FS		 550 static const char * const clk_name = "gce";
551 static const char * const clk_names[] = { "gce0", "gce1" };
623a6143
HW		 552
553 cmdq = devm_kzalloc(dev, sizeof(*cmdq), GFP_KERNEL);
554 if (!cmdq)
555 return -ENOMEM;
556
a04f3035 557 cmdq->base = devm_platform_ioremap_resource(pdev, 0);
ff16cae3 558 if (IS_ERR(cmdq->base))
623a6143 559 return PTR_ERR(cmdq->base);
623a6143
HW		 560
561 cmdq->irq = platform_get_irq(pdev, 0);
558e4c36
KK		 562 if (cmdq->irq < 0)
563 return cmdq->irq;
2c49e4e8 564
acabe12c
ADR		 565 cmdq->pdata = device_get_match_data(dev);
566 if (!cmdq->pdata) {
0858fde4
DYH		 567 dev_err(dev, "failed to get match data\n");
568 return -EINVAL;
569 }
570
acabe12c 571 cmdq->irq_mask = GENMASK(cmdq->pdata->thread_nr - 1, 0);
623a6143
HW		 572
573 dev_dbg(dev, "cmdq device: addr:0x%p, va:0x%p, irq:%d\n",
574 dev, cmdq->base, cmdq->irq);
575
acabe12c 576 if (cmdq->pdata->gce_num > 1) {
85dfdbfc 577 for_each_child_of_node(phandle->parent, node) {
85dfdbfc 578 alias_id = of_alias_get_id(node, clk_name);
acabe12c 579 if (alias_id >= 0 && alias_id < cmdq->pdata->gce_num) {
0a5ad432 580 cmdq->clocks[alias_id].id = clk_names[alias_id];
85dfdbfc 581 cmdq->clocks[alias_id].clk = of_clk_get(node, 0);
582 if (IS_ERR(cmdq->clocks[alias_id].clk)) {
af8d0f6d 583 of_node_put(node);
99867e5a
HYW		 584 return dev_err_probe(dev,
585 PTR_ERR(cmdq->clocks[alias_id].clk),
586 "failed to get gce clk: %d\n",
587 alias_id);
85dfdbfc 588 }
589 }
590 }
591 } else {
592 cmdq->clocks[alias_id].id = clk_name;
593 cmdq->clocks[alias_id].clk = devm_clk_get(&pdev->dev, clk_name);
594 if (IS_ERR(cmdq->clocks[alias_id].clk)) {
99867e5a
HYW		 595 return dev_err_probe(dev, PTR_ERR(cmdq->clocks[alias_id].clk),
596 "failed to get gce clk\n");
85dfdbfc 597 }
623a6143
HW		 598 }
599
623a6143 600 cmdq->mbox.dev = dev;
acabe12c 601 cmdq->mbox.chans = devm_kcalloc(dev, cmdq->pdata->thread_nr,
623a6143
HW		 602 sizeof(*cmdq->mbox.chans), GFP_KERNEL);
603 if (!cmdq->mbox.chans)
604 return -ENOMEM;
605
acabe12c 606 cmdq->mbox.num_chans = cmdq->pdata->thread_nr;
623a6143
HW		 607 cmdq->mbox.ops = &cmdq_mbox_chan_ops;
608 cmdq->mbox.of_xlate = cmdq_xlate;
609
610 /* make use of TXDONE_BY_ACK */
611 cmdq->mbox.txdone_irq = false;
612 cmdq->mbox.txdone_poll = false;
613
acabe12c 614 cmdq->thread = devm_kcalloc(dev, cmdq->pdata->thread_nr,
623a6143
HW		 615 sizeof(*cmdq->thread), GFP_KERNEL);
616 if (!cmdq->thread)
617 return -ENOMEM;
618
acabe12c 619 for (i = 0; i < cmdq->pdata->thread_nr; i++) {
623a6143
HW		 620 cmdq->thread[i].base = cmdq->base + CMDQ_THR_BASE +
621 CMDQ_THR_SIZE * i;
622 INIT_LIST_HEAD(&cmdq->thread[i].task_busy_list);
623 cmdq->mbox.chans[i].con_priv = (void *)&cmdq->thread[i];
624 }
625
8aed5719 626 err = devm_mbox_controller_register(dev, &cmdq->mbox);
623a6143
HW		 627 if (err < 0) {
628 dev_err(dev, "failed to register mailbox: %d\n", err);
629 return err;
630 }
631
632 platform_set_drvdata(pdev, cmdq);
85dfdbfc 633
acabe12c 634 WARN_ON(clk_bulk_prepare(cmdq->pdata->gce_num, cmdq->clocks));
623a6143
HW		 635
636 cmdq_init(cmdq);
637
16edcfef
RR		 638 err = devm_request_irq(dev, cmdq->irq, cmdq_irq_handler, IRQF_SHARED,
639 "mtk_cmdq", cmdq);
640 if (err < 0) {
641 dev_err(dev, "failed to register ISR (%d)\n", err);
642 return err;
643 }
644
623a6143
HW		 645 return 0;
646}
647
648static const struct dev_pm_ops cmdq_pm_ops = {
649 .suspend = cmdq_suspend,
650 .resume = cmdq_resume,
651};
652
85dfdbfc 653static const struct gce_plat gce_plat_v2 = {
654 .thread_nr = 16,
655 .shift = 0,
656 .control_by_sw = false,
657 .gce_num = 1
658};
659
660static const struct gce_plat gce_plat_v3 = {
661 .thread_nr = 24,
662 .shift = 0,
663 .control_by_sw = false,
664 .gce_num = 1
665};
666
667static const struct gce_plat gce_plat_v4 = {
668 .thread_nr = 24,
669 .shift = 3,
670 .control_by_sw = false,
671 .gce_num = 1
672};
673
674static const struct gce_plat gce_plat_v5 = {
675 .thread_nr = 24,
676 .shift = 3,
677 .control_by_sw = true,
35ca4371 678 .gce_num = 1
85dfdbfc 679};
680
681static const struct gce_plat gce_plat_v6 = {
682 .thread_nr = 24,
683 .shift = 3,
9388501f 684 .control_by_sw = true,
85dfdbfc 685 .gce_num = 2
686};
0858fde4 687
926d6214
YN		 688static const struct gce_plat gce_plat_v7 = {
689 .thread_nr = 24,
690 .shift = 3,
691 .control_by_sw = true,
692 .sw_ddr_en = true,
693 .gce_num = 1
694};
695
623a6143 696static const struct of_device_id cmdq_of_ids[] = {
0858fde4
DYH		 697 {.compatible = "mediatek,mt8173-gce", .data = (void *)&gce_plat_v2},
698 {.compatible = "mediatek,mt8183-gce", .data = (void *)&gce_plat_v3},
926d6214 699 {.compatible = "mediatek,mt8186-gce", .data = (void *)&gce_plat_v7},
bb2b06e0 700 {.compatible = "mediatek,mt6779-gce", .data = (void *)&gce_plat_v4},
84fd4201 701 {.compatible = "mediatek,mt8192-gce", .data = (void *)&gce_plat_v5},
85dfdbfc 702 {.compatible = "mediatek,mt8195-gce", .data = (void *)&gce_plat_v6},
623a6143
HW		 703 {}
704};
705
706static struct platform_driver cmdq_drv = {
707 .probe = cmdq_probe,
708 .remove = cmdq_remove,
709 .driver = {
710 .name = "mtk_cmdq",
711 .pm = &cmdq_pm_ops,
712 .of_match_table = cmdq_of_ids,
713 }
714};
715
716static int __init cmdq_drv_init(void)
717{
718 return platform_driver_register(&cmdq_drv);
719}
720
721static void __exit cmdq_drv_exit(void)
722{
723 platform_driver_unregister(&cmdq_drv);
724}
725
726subsys_initcall(cmdq_drv_init);
727module_exit(cmdq_drv_exit);
c5f45fbb
RD		 728
729MODULE_LICENSE("GPL v2");
Linux 6.x block layer and io_uring tree(s)