[linux-block.git] / drivers / mailbox / mtk-cmdq-mailbox.c

// SPDX-License-Identifier: GPL-2.0
//
// Copyright (c) 2018 MediaTek Inc.

#include <linux/bitops.h>
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/dma-mapping.h>
#include <linux/errno.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/iopoll.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/mailbox_controller.h>
#include <linux/mailbox/mtk-cmdq-mailbox.h>
#include <linux/of_device.h>

#define CMDQ_OP_CODE_MASK		(0xff << CMDQ_OP_CODE_SHIFT)
#define CMDQ_NUM_CMD(t)			(t->cmd_buf_size / CMDQ_INST_SIZE)

#define CMDQ_CURR_IRQ_STATUS		0x10
#define CMDQ_SYNC_TOKEN_UPDATE		0x68
#define CMDQ_THR_SLOT_CYCLES		0x30
#define CMDQ_THR_BASE			0x100
#define CMDQ_THR_SIZE			0x80
#define CMDQ_THR_WARM_RESET		0x00
#define CMDQ_THR_ENABLE_TASK		0x04
#define CMDQ_THR_SUSPEND_TASK		0x08
#define CMDQ_THR_CURR_STATUS		0x0c
#define CMDQ_THR_IRQ_STATUS		0x10
#define CMDQ_THR_IRQ_ENABLE		0x14
#define CMDQ_THR_CURR_ADDR		0x20
#define CMDQ_THR_END_ADDR		0x24
#define CMDQ_THR_WAIT_TOKEN		0x30
#define CMDQ_THR_PRIORITY		0x40

#define CMDQ_THR_ACTIVE_SLOT_CYCLES	0x3200
#define CMDQ_THR_ENABLED		0x1
#define CMDQ_THR_DISABLED		0x0
#define CMDQ_THR_SUSPEND		0x1
#define CMDQ_THR_RESUME			0x0
#define CMDQ_THR_STATUS_SUSPENDED	BIT(1)
#define CMDQ_THR_DO_WARM_RESET		BIT(0)
#define CMDQ_THR_IRQ_DONE		0x1
#define CMDQ_THR_IRQ_ERROR		0x12
#define CMDQ_THR_IRQ_EN			(CMDQ_THR_IRQ_ERROR | CMDQ_THR_IRQ_DONE)
#define CMDQ_THR_IS_WAITING		BIT(31)

#define CMDQ_JUMP_BY_OFFSET		0x10000000
#define CMDQ_JUMP_BY_PA			0x10000001

struct cmdq_thread {
	struct mbox_chan	*chan;
	void __iomem		*base;
	struct list_head	task_busy_list;
	u32			priority;
};

struct cmdq_task {
	struct cmdq		*cmdq;
	struct list_head	list_entry;
	dma_addr_t		pa_base;
	struct cmdq_thread	*thread;
	struct cmdq_pkt		*pkt; /* the packet sent from mailbox client */
};

struct cmdq {
	struct mbox_controller	mbox;
	void __iomem		*base;
	int			irq;
	u32			thread_nr;
	u32			irq_mask;
	struct cmdq_thread	*thread;
	struct clk		*clock;
	bool			suspended;
	u8			shift_pa;
};

struct gce_plat {
	u32 thread_nr;
	u8 shift;
};

u8 cmdq_get_shift_pa(struct mbox_chan *chan)
{
	struct cmdq *cmdq = container_of(chan->mbox, struct cmdq, mbox);

	return cmdq->shift_pa;
}
EXPORT_SYMBOL(cmdq_get_shift_pa);

static int cmdq_thread_suspend(struct cmdq *cmdq, struct cmdq_thread *thread)
{
	u32 status;

	writel(CMDQ_THR_SUSPEND, thread->base + CMDQ_THR_SUSPEND_TASK);

	/* If already disabled, treat as suspended successful. */
	if (!(readl(thread->base + CMDQ_THR_ENABLE_TASK) & CMDQ_THR_ENABLED))
		return 0;

	if (readl_poll_timeout_atomic(thread->base + CMDQ_THR_CURR_STATUS,
			status, status & CMDQ_THR_STATUS_SUSPENDED, 0, 10)) {
		dev_err(cmdq->mbox.dev, "suspend GCE thread 0x%x failed\n",
			(u32)(thread->base - cmdq->base));
		return -EFAULT;
	}

	return 0;
}

static void cmdq_thread_resume(struct cmdq_thread *thread)
{
	writel(CMDQ_THR_RESUME, thread->base + CMDQ_THR_SUSPEND_TASK);
}

static void cmdq_init(struct cmdq *cmdq)
{
	int i;

	WARN_ON(clk_enable(cmdq->clock) < 0);
	writel(CMDQ_THR_ACTIVE_SLOT_CYCLES, cmdq->base + CMDQ_THR_SLOT_CYCLES);
	for (i = 0; i <= CMDQ_MAX_EVENT; i++)
		writel(i, cmdq->base + CMDQ_SYNC_TOKEN_UPDATE);
	clk_disable(cmdq->clock);
}

static int cmdq_thread_reset(struct cmdq *cmdq, struct cmdq_thread *thread)
{
	u32 warm_reset;

	writel(CMDQ_THR_DO_WARM_RESET, thread->base + CMDQ_THR_WARM_RESET);
	if (readl_poll_timeout_atomic(thread->base + CMDQ_THR_WARM_RESET,
			warm_reset, !(warm_reset & CMDQ_THR_DO_WARM_RESET),
			0, 10)) {
		dev_err(cmdq->mbox.dev, "reset GCE thread 0x%x failed\n",
			(u32)(thread->base - cmdq->base));
		return -EFAULT;
	}

	return 0;
}

static void cmdq_thread_disable(struct cmdq *cmdq, struct cmdq_thread *thread)
{
	cmdq_thread_reset(cmdq, thread);
	writel(CMDQ_THR_DISABLED, thread->base + CMDQ_THR_ENABLE_TASK);
}

/* notify GCE to re-fetch commands by setting GCE thread PC */
static void cmdq_thread_invalidate_fetched_data(struct cmdq_thread *thread)
{
	writel(readl(thread->base + CMDQ_THR_CURR_ADDR),
	       thread->base + CMDQ_THR_CURR_ADDR);
}

static void cmdq_task_insert_into_thread(struct cmdq_task *task)
{
	struct device *dev = task->cmdq->mbox.dev;
	struct cmdq_thread *thread = task->thread;
	struct cmdq_task *prev_task = list_last_entry(
			&thread->task_busy_list, typeof(*task), list_entry);
	u64 *prev_task_base = prev_task->pkt->va_base;

	/* let previous task jump to this task */
	dma_sync_single_for_cpu(dev, prev_task->pa_base,
				prev_task->pkt->cmd_buf_size, DMA_TO_DEVICE);
	prev_task_base[CMDQ_NUM_CMD(prev_task->pkt) - 1] =
		(u64)CMDQ_JUMP_BY_PA << 32 | task->pa_base;
	dma_sync_single_for_device(dev, prev_task->pa_base,
				   prev_task->pkt->cmd_buf_size, DMA_TO_DEVICE);

	cmdq_thread_invalidate_fetched_data(thread);
}

static bool cmdq_thread_is_in_wfe(struct cmdq_thread *thread)
{
	return readl(thread->base + CMDQ_THR_WAIT_TOKEN) & CMDQ_THR_IS_WAITING;
}

static void cmdq_task_exec_done(struct cmdq_task *task, int sta)
{
	struct cmdq_task_cb *cb = &task->pkt->async_cb;
	struct cmdq_cb_data data;

	WARN_ON(cb->cb == (cmdq_async_flush_cb)NULL);
	data.sta = sta;
	data.data = cb->data;
	data.pkt = task->pkt;
	if (cb->cb)
		cb->cb(data);

	mbox_chan_received_data(task->thread->chan, &data);

	list_del(&task->list_entry);
}

static void cmdq_task_handle_error(struct cmdq_task *task)
{
	struct cmdq_thread *thread = task->thread;
	struct cmdq_task *next_task;
	struct cmdq *cmdq = task->cmdq;

	dev_err(cmdq->mbox.dev, "task 0x%p error\n", task);
	WARN_ON(cmdq_thread_suspend(cmdq, thread) < 0);
	next_task = list_first_entry_or_null(&thread->task_busy_list,
			struct cmdq_task, list_entry);
	if (next_task)
		writel(next_task->pa_base >> cmdq->shift_pa,
		       thread->base + CMDQ_THR_CURR_ADDR);
	cmdq_thread_resume(thread);
}

static void cmdq_thread_irq_handler(struct cmdq *cmdq,
				    struct cmdq_thread *thread)
{
	struct cmdq_task *task, *tmp, *curr_task = NULL;
	u32 curr_pa, irq_flag, task_end_pa;
	bool err;

	irq_flag = readl(thread->base + CMDQ_THR_IRQ_STATUS);
	writel(~irq_flag, thread->base + CMDQ_THR_IRQ_STATUS);

	/*
	 * When ISR call this function, another CPU core could run
	 * "release task" right before we acquire the spin lock, and thus
	 * reset / disable this GCE thread, so we need to check the enable
	 * bit of this GCE thread.
	 */
	if (!(readl(thread->base + CMDQ_THR_ENABLE_TASK) & CMDQ_THR_ENABLED))
		return;

	if (irq_flag & CMDQ_THR_IRQ_ERROR)
		err = true;
	else if (irq_flag & CMDQ_THR_IRQ_DONE)
		err = false;
	else
		return;

	curr_pa = readl(thread->base + CMDQ_THR_CURR_ADDR) << cmdq->shift_pa;

	list_for_each_entry_safe(task, tmp, &thread->task_busy_list,
				 list_entry) {
		task_end_pa = task->pa_base + task->pkt->cmd_buf_size;
		if (curr_pa >= task->pa_base && curr_pa < task_end_pa)
			curr_task = task;

		if (!curr_task || curr_pa == task_end_pa - CMDQ_INST_SIZE) {
			cmdq_task_exec_done(task, 0);
			kfree(task);
		} else if (err) {
			cmdq_task_exec_done(task, -ENOEXEC);
			cmdq_task_handle_error(curr_task);
			kfree(task);
		}

		if (curr_task)
			break;
	}

	if (list_empty(&thread->task_busy_list)) {
		cmdq_thread_disable(cmdq, thread);
		clk_disable(cmdq->clock);
	}
}

static irqreturn_t cmdq_irq_handler(int irq, void *dev)
{
	struct cmdq *cmdq = dev;
	unsigned long irq_status, flags = 0L;
	int bit;

	irq_status = readl(cmdq->base + CMDQ_CURR_IRQ_STATUS) & cmdq->irq_mask;
	if (!(irq_status ^ cmdq->irq_mask))
		return IRQ_NONE;

	for_each_clear_bit(bit, &irq_status, cmdq->thread_nr) {
		struct cmdq_thread *thread = &cmdq->thread[bit];

		spin_lock_irqsave(&thread->chan->lock, flags);
		cmdq_thread_irq_handler(cmdq, thread);
		spin_unlock_irqrestore(&thread->chan->lock, flags);
	}

	return IRQ_HANDLED;
}

static int cmdq_suspend(struct device *dev)
{
	struct cmdq *cmdq = dev_get_drvdata(dev);
	struct cmdq_thread *thread;
	int i;
	bool task_running = false;

	cmdq->suspended = true;

	for (i = 0; i < cmdq->thread_nr; i++) {
		thread = &cmdq->thread[i];
		if (!list_empty(&thread->task_busy_list)) {
			task_running = true;
			break;
		}
	}

	if (task_running)
		dev_warn(dev, "exist running task(s) in suspend\n");

	clk_unprepare(cmdq->clock);

	return 0;
}

static int cmdq_resume(struct device *dev)
{
	struct cmdq *cmdq = dev_get_drvdata(dev);

	WARN_ON(clk_prepare(cmdq->clock) < 0);
	cmdq->suspended = false;
	return 0;
}

static int cmdq_remove(struct platform_device *pdev)
{
	struct cmdq *cmdq = platform_get_drvdata(pdev);

	clk_unprepare(cmdq->clock);

	return 0;
}

static int cmdq_mbox_send_data(struct mbox_chan *chan, void *data)
{
	struct cmdq_pkt *pkt = (struct cmdq_pkt *)data;
	struct cmdq_thread *thread = (struct cmdq_thread *)chan->con_priv;
	struct cmdq *cmdq = dev_get_drvdata(chan->mbox->dev);
	struct cmdq_task *task;
	unsigned long curr_pa, end_pa;

	/* Client should not flush new tasks if suspended. */
	WARN_ON(cmdq->suspended);

	task = kzalloc(sizeof(*task), GFP_ATOMIC);
	if (!task)
		return -ENOMEM;

	task->cmdq = cmdq;
	INIT_LIST_HEAD(&task->list_entry);
	task->pa_base = pkt->pa_base;
	task->thread = thread;
	task->pkt = pkt;

	if (list_empty(&thread->task_busy_list)) {
		WARN_ON(clk_enable(cmdq->clock) < 0);
		/*
		 * The thread reset will clear thread related register to 0,
		 * including pc, end, priority, irq, suspend and enable. Thus
		 * set CMDQ_THR_ENABLED to CMDQ_THR_ENABLE_TASK will enable
		 * thread and make it running.
		 */
		WARN_ON(cmdq_thread_reset(cmdq, thread) < 0);

		writel(task->pa_base >> cmdq->shift_pa,
		       thread->base + CMDQ_THR_CURR_ADDR);
		writel((task->pa_base + pkt->cmd_buf_size) >> cmdq->shift_pa,
		       thread->base + CMDQ_THR_END_ADDR);

		writel(thread->priority, thread->base + CMDQ_THR_PRIORITY);
		writel(CMDQ_THR_IRQ_EN, thread->base + CMDQ_THR_IRQ_ENABLE);
		writel(CMDQ_THR_ENABLED, thread->base + CMDQ_THR_ENABLE_TASK);
	} else {
		WARN_ON(cmdq_thread_suspend(cmdq, thread) < 0);
		curr_pa = readl(thread->base + CMDQ_THR_CURR_ADDR) <<
			cmdq->shift_pa;
		end_pa = readl(thread->base + CMDQ_THR_END_ADDR) <<
			cmdq->shift_pa;
		/* check boundary */
		if (curr_pa == end_pa - CMDQ_INST_SIZE ||
		    curr_pa == end_pa) {
			/* set to this task directly */
			writel(task->pa_base >> cmdq->shift_pa,
			       thread->base + CMDQ_THR_CURR_ADDR);
		} else {
			cmdq_task_insert_into_thread(task);
			smp_mb(); /* modify jump before enable thread */
		}
		writel((task->pa_base + pkt->cmd_buf_size) >> cmdq->shift_pa,
		       thread->base + CMDQ_THR_END_ADDR);
		cmdq_thread_resume(thread);
	}
	list_move_tail(&task->list_entry, &thread->task_busy_list);

	return 0;
}

static int cmdq_mbox_startup(struct mbox_chan *chan)
{
	return 0;
}

static void cmdq_mbox_shutdown(struct mbox_chan *chan)
{
	struct cmdq_thread *thread = (struct cmdq_thread *)chan->con_priv;
	struct cmdq *cmdq = dev_get_drvdata(chan->mbox->dev);
	struct cmdq_task *task, *tmp;
	unsigned long flags;

	spin_lock_irqsave(&thread->chan->lock, flags);
	if (list_empty(&thread->task_busy_list))
		goto done;

	WARN_ON(cmdq_thread_suspend(cmdq, thread) < 0);

	/* make sure executed tasks have success callback */
	cmdq_thread_irq_handler(cmdq, thread);
	if (list_empty(&thread->task_busy_list))
		goto done;

	list_for_each_entry_safe(task, tmp, &thread->task_busy_list,
				 list_entry) {
		cmdq_task_exec_done(task, -ECONNABORTED);
		kfree(task);
	}

	cmdq_thread_disable(cmdq, thread);
	clk_disable(cmdq->clock);
done:
	/*
	 * The thread->task_busy_list empty means thread already disable. The
	 * cmdq_mbox_send_data() always reset thread which clear disable and
	 * suspend statue when first pkt send to channel, so there is no need
	 * to do any operation here, only unlock and leave.
	 */
	spin_unlock_irqrestore(&thread->chan->lock, flags);
}

static int cmdq_mbox_flush(struct mbox_chan *chan, unsigned long timeout)
{
	struct cmdq_thread *thread = (struct cmdq_thread *)chan->con_priv;
	struct cmdq_task_cb *cb;
	struct cmdq_cb_data data;
	struct cmdq *cmdq = dev_get_drvdata(chan->mbox->dev);
	struct cmdq_task *task, *tmp;
	unsigned long flags;
	u32 enable;

	spin_lock_irqsave(&thread->chan->lock, flags);
	if (list_empty(&thread->task_busy_list))
		goto out;

	WARN_ON(cmdq_thread_suspend(cmdq, thread) < 0);
	if (!cmdq_thread_is_in_wfe(thread))
		goto wait;

	list_for_each_entry_safe(task, tmp, &thread->task_busy_list,
				 list_entry) {
		cb = &task->pkt->async_cb;
		data.sta = -ECONNABORTED;
		data.data = cb->data;
		data.pkt = task->pkt;
		if (cb->cb)
			cb->cb(data);

		mbox_chan_received_data(task->thread->chan, &data);
		list_del(&task->list_entry);
		kfree(task);
	}

	cmdq_thread_resume(thread);
	cmdq_thread_disable(cmdq, thread);
	clk_disable(cmdq->clock);

out:
	spin_unlock_irqrestore(&thread->chan->lock, flags);
	return 0;

wait:
	cmdq_thread_resume(thread);
	spin_unlock_irqrestore(&thread->chan->lock, flags);
	if (readl_poll_timeout_atomic(thread->base + CMDQ_THR_ENABLE_TASK,
				      enable, enable == 0, 1, timeout)) {
		dev_err(cmdq->mbox.dev, "Fail to wait GCE thread 0x%x done\n",
			(u32)(thread->base - cmdq->base));

		return -EFAULT;
	}
	return 0;
}

static const struct mbox_chan_ops cmdq_mbox_chan_ops = {
	.send_data = cmdq_mbox_send_data,
	.startup = cmdq_mbox_startup,
	.shutdown = cmdq_mbox_shutdown,
	.flush = cmdq_mbox_flush,
};

static struct mbox_chan *cmdq_xlate(struct mbox_controller *mbox,
		const struct of_phandle_args *sp)
{
	int ind = sp->args[0];
	struct cmdq_thread *thread;

	if (ind >= mbox->num_chans)
		return ERR_PTR(-EINVAL);

	thread = (struct cmdq_thread *)mbox->chans[ind].con_priv;
	thread->priority = sp->args[1];
	thread->chan = &mbox->chans[ind];

	return &mbox->chans[ind];
}

static int cmdq_probe(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
	struct resource *res;
	struct cmdq *cmdq;
	int err, i;
	struct gce_plat *plat_data;

	cmdq = devm_kzalloc(dev, sizeof(*cmdq), GFP_KERNEL);
	if (!cmdq)
		return -ENOMEM;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	cmdq->base = devm_ioremap_resource(dev, res);
	if (IS_ERR(cmdq->base))
		return PTR_ERR(cmdq->base);

	cmdq->irq = platform_get_irq(pdev, 0);
	if (cmdq->irq < 0)
		return cmdq->irq;

	plat_data = (struct gce_plat *)of_device_get_match_data(dev);
	if (!plat_data) {
		dev_err(dev, "failed to get match data\n");
		return -EINVAL;
	}

	cmdq->thread_nr = plat_data->thread_nr;
	cmdq->shift_pa = plat_data->shift;
	cmdq->irq_mask = GENMASK(cmdq->thread_nr - 1, 0);
	err = devm_request_irq(dev, cmdq->irq, cmdq_irq_handler, IRQF_SHARED,
			       "mtk_cmdq", cmdq);
	if (err < 0) {
		dev_err(dev, "failed to register ISR (%d)\n", err);
		return err;
	}

	dev_dbg(dev, "cmdq device: addr:0x%p, va:0x%p, irq:%d\n",
		dev, cmdq->base, cmdq->irq);

	cmdq->clock = devm_clk_get(dev, "gce");
	if (IS_ERR(cmdq->clock)) {
		dev_err(dev, "failed to get gce clk\n");
		return PTR_ERR(cmdq->clock);
	}

	cmdq->mbox.dev = dev;
	cmdq->mbox.chans = devm_kcalloc(dev, cmdq->thread_nr,
					sizeof(*cmdq->mbox.chans), GFP_KERNEL);
	if (!cmdq->mbox.chans)
		return -ENOMEM;

	cmdq->mbox.num_chans = cmdq->thread_nr;
	cmdq->mbox.ops = &cmdq_mbox_chan_ops;
	cmdq->mbox.of_xlate = cmdq_xlate;

	/* make use of TXDONE_BY_ACK */
	cmdq->mbox.txdone_irq = false;
	cmdq->mbox.txdone_poll = false;

	cmdq->thread = devm_kcalloc(dev, cmdq->thread_nr,
					sizeof(*cmdq->thread), GFP_KERNEL);
	if (!cmdq->thread)
		return -ENOMEM;

	for (i = 0; i < cmdq->thread_nr; i++) {
		cmdq->thread[i].base = cmdq->base + CMDQ_THR_BASE +
				CMDQ_THR_SIZE * i;
		INIT_LIST_HEAD(&cmdq->thread[i].task_busy_list);
		cmdq->mbox.chans[i].con_priv = (void *)&cmdq->thread[i];
	}

	err = devm_mbox_controller_register(dev, &cmdq->mbox);
	if (err < 0) {
		dev_err(dev, "failed to register mailbox: %d\n", err);
		return err;
	}

	platform_set_drvdata(pdev, cmdq);
	WARN_ON(clk_prepare(cmdq->clock) < 0);

	cmdq_init(cmdq);

	return 0;
}

static const struct dev_pm_ops cmdq_pm_ops = {
	.suspend = cmdq_suspend,
	.resume = cmdq_resume,
};

static const struct gce_plat gce_plat_v2 = {.thread_nr = 16};
static const struct gce_plat gce_plat_v3 = {.thread_nr = 24};
static const struct gce_plat gce_plat_v4 = {.thread_nr = 24, .shift = 3};

static const struct of_device_id cmdq_of_ids[] = {
	{.compatible = "mediatek,mt8173-gce", .data = (void *)&gce_plat_v2},
	{.compatible = "mediatek,mt8183-gce", .data = (void *)&gce_plat_v3},
	{.compatible = "mediatek,mt6779-gce", .data = (void *)&gce_plat_v4},
	{}
};

static struct platform_driver cmdq_drv = {
	.probe = cmdq_probe,
	.remove = cmdq_remove,
	.driver = {
		.name = "mtk_cmdq",
		.pm = &cmdq_pm_ops,
		.of_match_table = cmdq_of_ids,
	}
};

static int __init cmdq_drv_init(void)
{
	return platform_driver_register(&cmdq_drv);
}

static void __exit cmdq_drv_exit(void)
{
	platform_driver_unregister(&cmdq_drv);
}

subsys_initcall(cmdq_drv_init);
module_exit(cmdq_drv_exit);

MODULE_LICENSE("GPL v2");
Commit	Line	Data
623a6143 HW	1	// SPDX-License-Identifier: GPL-2.0
	2	//
	3	// Copyright (c) 2018 MediaTek Inc.
	4
	5	#include <linux/bitops.h>
	6	#include <linux/clk.h>
	7	#include <linux/clk-provider.h>
	8	#include <linux/dma-mapping.h>
	9	#include <linux/errno.h>
	10	#include <linux/interrupt.h>
62e59c4e	11	#include <linux/io.h>
623a6143 HW	12	#include <linux/iopoll.h>
	13	#include <linux/kernel.h>
	14	#include <linux/module.h>
	15	#include <linux/platform_device.h>
	16	#include <linux/mailbox_controller.h>
	17	#include <linux/mailbox/mtk-cmdq-mailbox.h>
	18	#include <linux/of_device.h>
	19
	20	#define CMDQ_OP_CODE_MASK (0xff << CMDQ_OP_CODE_SHIFT)
623a6143 HW	21	#define CMDQ_NUM_CMD(t) (t->cmd_buf_size / CMDQ_INST_SIZE)
	22
	23	#define CMDQ_CURR_IRQ_STATUS 0x10
6058f118	24	#define CMDQ_SYNC_TOKEN_UPDATE 0x68
623a6143 HW	25	#define CMDQ_THR_SLOT_CYCLES 0x30
	26	#define CMDQ_THR_BASE 0x100
	27	#define CMDQ_THR_SIZE 0x80
	28	#define CMDQ_THR_WARM_RESET 0x00
	29	#define CMDQ_THR_ENABLE_TASK 0x04
	30	#define CMDQ_THR_SUSPEND_TASK 0x08
	31	#define CMDQ_THR_CURR_STATUS 0x0c
	32	#define CMDQ_THR_IRQ_STATUS 0x10
	33	#define CMDQ_THR_IRQ_ENABLE 0x14
	34	#define CMDQ_THR_CURR_ADDR 0x20
	35	#define CMDQ_THR_END_ADDR 0x24
	36	#define CMDQ_THR_WAIT_TOKEN 0x30
	37	#define CMDQ_THR_PRIORITY 0x40
	38
	39	#define CMDQ_THR_ACTIVE_SLOT_CYCLES 0x3200
	40	#define CMDQ_THR_ENABLED 0x1
	41	#define CMDQ_THR_DISABLED 0x0
	42	#define CMDQ_THR_SUSPEND 0x1
	43	#define CMDQ_THR_RESUME 0x0
	44	#define CMDQ_THR_STATUS_SUSPENDED BIT(1)
	45	#define CMDQ_THR_DO_WARM_RESET BIT(0)
	46	#define CMDQ_THR_IRQ_DONE 0x1
	47	#define CMDQ_THR_IRQ_ERROR 0x12
	48	#define CMDQ_THR_IRQ_EN (CMDQ_THR_IRQ_ERROR \| CMDQ_THR_IRQ_DONE)
	49	#define CMDQ_THR_IS_WAITING BIT(31)
	50
	51	#define CMDQ_JUMP_BY_OFFSET 0x10000000
	52	#define CMDQ_JUMP_BY_PA 0x10000001
	53
	54	struct cmdq_thread {
	55	struct mbox_chan *chan;
	56	void __iomem *base;
	57	struct list_head task_busy_list;
	58	u32 priority;
623a6143 HW	59	};
	60
	61	struct cmdq_task {
	62	struct cmdq *cmdq;
	63	struct list_head list_entry;
	64	dma_addr_t pa_base;
	65	struct cmdq_thread *thread;
	66	struct cmdq_pkt pkt; / the packet sent from mailbox client */
	67	};
	68
	69	struct cmdq {
	70	struct mbox_controller mbox;
	71	void __iomem *base;
558e4c36	72	int irq;
623a6143	73	u32 thread_nr;
2c49e4e8	74	u32 irq_mask;
623a6143 HW	75	struct cmdq_thread *thread;
	76	struct clk *clock;
	77	bool suspended;
0858fde4	78	u8 shift_pa;
623a6143 HW	79	};
623a6143 HW	80
0858fde4 DYH	81	struct gce_plat {
	82	u32 thread_nr;
	83	u8 shift;
	84	};
	85
	86	u8 cmdq_get_shift_pa(struct mbox_chan *chan)
	87	{
	88	struct cmdq *cmdq = container_of(chan->mbox, struct cmdq, mbox);
	89
	90	return cmdq->shift_pa;
	91	}
	92	EXPORT_SYMBOL(cmdq_get_shift_pa);
	93
623a6143 HW	94	static int cmdq_thread_suspend(struct cmdq cmdq, struct cmdq_thread thread)
	95	{
	96	u32 status;
	97
	98	writel(CMDQ_THR_SUSPEND, thread->base + CMDQ_THR_SUSPEND_TASK);
	99
	100	/* If already disabled, treat as suspended successful. */
	101	if (!(readl(thread->base + CMDQ_THR_ENABLE_TASK) & CMDQ_THR_ENABLED))
	102	return 0;
	103
	104	if (readl_poll_timeout_atomic(thread->base + CMDQ_THR_CURR_STATUS,
	105	status, status & CMDQ_THR_STATUS_SUSPENDED, 0, 10)) {
	106	dev_err(cmdq->mbox.dev, "suspend GCE thread 0x%x failed\n",
	107	(u32)(thread->base - cmdq->base));
	108	return -EFAULT;
	109	}
	110
	111	return 0;
	112	}
	113
	114	static void cmdq_thread_resume(struct cmdq_thread *thread)
	115	{
	116	writel(CMDQ_THR_RESUME, thread->base + CMDQ_THR_SUSPEND_TASK);
	117	}
	118
	119	static void cmdq_init(struct cmdq *cmdq)
	120	{
6058f118 BH	121	int i;
6058f118 BH	122
623a6143 HW	123	WARN_ON(clk_enable(cmdq->clock) < 0);
623a6143 HW	124	writel(CMDQ_THR_ACTIVE_SLOT_CYCLES, cmdq->base + CMDQ_THR_SLOT_CYCLES);
6058f118 BH	125	for (i = 0; i <= CMDQ_MAX_EVENT; i++)
6058f118 BH	126	writel(i, cmdq->base + CMDQ_SYNC_TOKEN_UPDATE);
623a6143 HW	127	clk_disable(cmdq->clock);
	128	}
	129
	130	static int cmdq_thread_reset(struct cmdq cmdq, struct cmdq_thread thread)
	131	{
	132	u32 warm_reset;
	133
	134	writel(CMDQ_THR_DO_WARM_RESET, thread->base + CMDQ_THR_WARM_RESET);
	135	if (readl_poll_timeout_atomic(thread->base + CMDQ_THR_WARM_RESET,
	136	warm_reset, !(warm_reset & CMDQ_THR_DO_WARM_RESET),
	137	0, 10)) {
	138	dev_err(cmdq->mbox.dev, "reset GCE thread 0x%x failed\n",
	139	(u32)(thread->base - cmdq->base));
	140	return -EFAULT;
	141	}
	142
	143	return 0;
	144	}
	145
	146	static void cmdq_thread_disable(struct cmdq cmdq, struct cmdq_thread thread)
	147	{
	148	cmdq_thread_reset(cmdq, thread);
	149	writel(CMDQ_THR_DISABLED, thread->base + CMDQ_THR_ENABLE_TASK);
	150	}
	151
	152	/* notify GCE to re-fetch commands by setting GCE thread PC */
	153	static void cmdq_thread_invalidate_fetched_data(struct cmdq_thread *thread)
	154	{
	155	writel(readl(thread->base + CMDQ_THR_CURR_ADDR),
	156	thread->base + CMDQ_THR_CURR_ADDR);
	157	}
	158
	159	static void cmdq_task_insert_into_thread(struct cmdq_task *task)
	160	{
	161	struct device *dev = task->cmdq->mbox.dev;
	162	struct cmdq_thread *thread = task->thread;
	163	struct cmdq_task *prev_task = list_last_entry(
	164	&thread->task_busy_list, typeof(*task), list_entry);
	165	u64 *prev_task_base = prev_task->pkt->va_base;
	166
	167	/* let previous task jump to this task */
	168	dma_sync_single_for_cpu(dev, prev_task->pa_base,
	169	prev_task->pkt->cmd_buf_size, DMA_TO_DEVICE);
	170	prev_task_base[CMDQ_NUM_CMD(prev_task->pkt) - 1] =
	171	(u64)CMDQ_JUMP_BY_PA << 32 \| task->pa_base;
	172	dma_sync_single_for_device(dev, prev_task->pa_base,
	173	prev_task->pkt->cmd_buf_size, DMA_TO_DEVICE);
	174
	175	cmdq_thread_invalidate_fetched_data(thread);
	176	}
	177
623a6143 HW	178	static bool cmdq_thread_is_in_wfe(struct cmdq_thread *thread)
	179	{
	180	return readl(thread->base + CMDQ_THR_WAIT_TOKEN) & CMDQ_THR_IS_WAITING;
	181	}
	182
b3c0d72b	183	static void cmdq_task_exec_done(struct cmdq_task *task, int sta)
623a6143 HW	184	{
	185	struct cmdq_task_cb *cb = &task->pkt->async_cb;
	186	struct cmdq_cb_data data;
	187
	188	WARN_ON(cb->cb == (cmdq_async_flush_cb)NULL);
	189	data.sta = sta;
	190	data.data = cb->data;
8ebc3b5a	191	data.pkt = task->pkt;
1b6b0ce2 CKH	192	if (cb->cb)
	193	cb->cb(data);
	194
	195	mbox_chan_received_data(task->thread->chan, &data);
623a6143 HW	196
	197	list_del(&task->list_entry);
	198	}
	199
	200	static void cmdq_task_handle_error(struct cmdq_task *task)
	201	{
	202	struct cmdq_thread *thread = task->thread;
	203	struct cmdq_task *next_task;
0858fde4	204	struct cmdq *cmdq = task->cmdq;
623a6143	205
0858fde4 DYH	206	dev_err(cmdq->mbox.dev, "task 0x%p error\n", task);
0858fde4 DYH	207	WARN_ON(cmdq_thread_suspend(cmdq, thread) < 0);
623a6143 HW	208	next_task = list_first_entry_or_null(&thread->task_busy_list,
	209	struct cmdq_task, list_entry);
	210	if (next_task)
0858fde4 DYH	211	writel(next_task->pa_base >> cmdq->shift_pa,
0858fde4 DYH	212	thread->base + CMDQ_THR_CURR_ADDR);
623a6143 HW	213	cmdq_thread_resume(thread);
	214	}
	215
	216	static void cmdq_thread_irq_handler(struct cmdq *cmdq,
	217	struct cmdq_thread *thread)
	218	{
	219	struct cmdq_task task, tmp, *curr_task = NULL;
	220	u32 curr_pa, irq_flag, task_end_pa;
	221	bool err;
	222
	223	irq_flag = readl(thread->base + CMDQ_THR_IRQ_STATUS);
	224	writel(~irq_flag, thread->base + CMDQ_THR_IRQ_STATUS);
	225
	226	/*
	227	* When ISR call this function, another CPU core could run
	228	* "release task" right before we acquire the spin lock, and thus
	229	* reset / disable this GCE thread, so we need to check the enable
	230	* bit of this GCE thread.
	231	*/
	232	if (!(readl(thread->base + CMDQ_THR_ENABLE_TASK) & CMDQ_THR_ENABLED))
	233	return;
	234
	235	if (irq_flag & CMDQ_THR_IRQ_ERROR)
	236	err = true;
	237	else if (irq_flag & CMDQ_THR_IRQ_DONE)
	238	err = false;
	239	else
	240	return;
	241
0858fde4	242	curr_pa = readl(thread->base + CMDQ_THR_CURR_ADDR) << cmdq->shift_pa;
623a6143 HW	243
	244	list_for_each_entry_safe(task, tmp, &thread->task_busy_list,
	245	list_entry) {
	246	task_end_pa = task->pa_base + task->pkt->cmd_buf_size;
	247	if (curr_pa >= task->pa_base && curr_pa < task_end_pa)
	248	curr_task = task;
	249
	250	if (!curr_task \|\| curr_pa == task_end_pa - CMDQ_INST_SIZE) {
b3c0d72b	251	cmdq_task_exec_done(task, 0);
623a6143 HW	252	kfree(task);
623a6143 HW	253	} else if (err) {
b3c0d72b	254	cmdq_task_exec_done(task, -ENOEXEC);
623a6143 HW	255	cmdq_task_handle_error(curr_task);
	256	kfree(task);
	257	}
	258
	259	if (curr_task)
	260	break;
	261	}
	262
	263	if (list_empty(&thread->task_busy_list)) {
	264	cmdq_thread_disable(cmdq, thread);
	265	clk_disable(cmdq->clock);
	266	}
	267	}
	268
	269	static irqreturn_t cmdq_irq_handler(int irq, void *dev)
	270	{
	271	struct cmdq *cmdq = dev;
	272	unsigned long irq_status, flags = 0L;
	273	int bit;
	274
2c49e4e8 BH	275	irq_status = readl(cmdq->base + CMDQ_CURR_IRQ_STATUS) & cmdq->irq_mask;
2c49e4e8 BH	276	if (!(irq_status ^ cmdq->irq_mask))
623a6143 HW	277	return IRQ_NONE;
623a6143 HW	278
2c49e4e8	279	for_each_clear_bit(bit, &irq_status, cmdq->thread_nr) {
623a6143 HW	280	struct cmdq_thread *thread = &cmdq->thread[bit];
	281
	282	spin_lock_irqsave(&thread->chan->lock, flags);
	283	cmdq_thread_irq_handler(cmdq, thread);
	284	spin_unlock_irqrestore(&thread->chan->lock, flags);
	285	}
	286
	287	return IRQ_HANDLED;
	288	}
	289
	290	static int cmdq_suspend(struct device *dev)
	291	{
	292	struct cmdq *cmdq = dev_get_drvdata(dev);
	293	struct cmdq_thread *thread;
	294	int i;
	295	bool task_running = false;
	296
	297	cmdq->suspended = true;
	298
	299	for (i = 0; i < cmdq->thread_nr; i++) {
	300	thread = &cmdq->thread[i];
	301	if (!list_empty(&thread->task_busy_list)) {
	302	task_running = true;
	303	break;
	304	}
	305	}
	306
	307	if (task_running)
	308	dev_warn(dev, "exist running task(s) in suspend\n");
	309
	310	clk_unprepare(cmdq->clock);
	311
	312	return 0;
	313	}
	314
	315	static int cmdq_resume(struct device *dev)
	316	{
	317	struct cmdq *cmdq = dev_get_drvdata(dev);
	318
	319	WARN_ON(clk_prepare(cmdq->clock) < 0);
	320	cmdq->suspended = false;
	321	return 0;
	322	}
	323
	324	static int cmdq_remove(struct platform_device *pdev)
	325	{
	326	struct cmdq *cmdq = platform_get_drvdata(pdev);
	327
623a6143 HW	328	clk_unprepare(cmdq->clock);
623a6143 HW	329
623a6143 HW	330	return 0;
	331	}
	332
	333	static int cmdq_mbox_send_data(struct mbox_chan chan, void data)
	334	{
	335	struct cmdq_pkt pkt = (struct cmdq_pkt )data;
	336	struct cmdq_thread thread = (struct cmdq_thread )chan->con_priv;
	337	struct cmdq *cmdq = dev_get_drvdata(chan->mbox->dev);
	338	struct cmdq_task *task;
	339	unsigned long curr_pa, end_pa;
	340
	341	/* Client should not flush new tasks if suspended. */
	342	WARN_ON(cmdq->suspended);
	343
	344	task = kzalloc(sizeof(*task), GFP_ATOMIC);
9f0a0a38 HW	345	if (!task)
	346	return -ENOMEM;
	347
623a6143 HW	348	task->cmdq = cmdq;
	349	INIT_LIST_HEAD(&task->list_entry);
	350	task->pa_base = pkt->pa_base;
	351	task->thread = thread;
	352	task->pkt = pkt;
	353
	354	if (list_empty(&thread->task_busy_list)) {
	355	WARN_ON(clk_enable(cmdq->clock) < 0);
88499698 DYH	356	/*
	357	* The thread reset will clear thread related register to 0,
	358	* including pc, end, priority, irq, suspend and enable. Thus
	359	* set CMDQ_THR_ENABLED to CMDQ_THR_ENABLE_TASK will enable
	360	* thread and make it running.
	361	*/
623a6143 HW	362	WARN_ON(cmdq_thread_reset(cmdq, thread) < 0);
623a6143 HW	363
0858fde4 DYH	364	writel(task->pa_base >> cmdq->shift_pa,
	365	thread->base + CMDQ_THR_CURR_ADDR);
	366	writel((task->pa_base + pkt->cmd_buf_size) >> cmdq->shift_pa,
623a6143	367	thread->base + CMDQ_THR_END_ADDR);
0858fde4	368
623a6143 HW	369	writel(thread->priority, thread->base + CMDQ_THR_PRIORITY);
	370	writel(CMDQ_THR_IRQ_EN, thread->base + CMDQ_THR_IRQ_ENABLE);
	371	writel(CMDQ_THR_ENABLED, thread->base + CMDQ_THR_ENABLE_TASK);
	372	} else {
	373	WARN_ON(cmdq_thread_suspend(cmdq, thread) < 0);
0858fde4 DYH	374	curr_pa = readl(thread->base + CMDQ_THR_CURR_ADDR) <<
	375	cmdq->shift_pa;
	376	end_pa = readl(thread->base + CMDQ_THR_END_ADDR) <<
	377	cmdq->shift_pa;
c9ea564f BH	378	/* check boundary */
	379	if (curr_pa == end_pa - CMDQ_INST_SIZE \|\|
	380	curr_pa == end_pa) {
	381	/* set to this task directly */
0858fde4	382	writel(task->pa_base >> cmdq->shift_pa,
c9ea564f	383	thread->base + CMDQ_THR_CURR_ADDR);
623a6143	384	} else {
c9ea564f BH	385	cmdq_task_insert_into_thread(task);
c9ea564f BH	386	smp_mb(); /* modify jump before enable thread */
623a6143	387	}
0858fde4	388	writel((task->pa_base + pkt->cmd_buf_size) >> cmdq->shift_pa,
623a6143 HW	389	thread->base + CMDQ_THR_END_ADDR);
	390	cmdq_thread_resume(thread);
	391	}
	392	list_move_tail(&task->list_entry, &thread->task_busy_list);
	393
	394	return 0;
	395	}
	396
	397	static int cmdq_mbox_startup(struct mbox_chan *chan)
	398	{
	399	return 0;
	400	}
	401
	402	static void cmdq_mbox_shutdown(struct mbox_chan *chan)
	403	{
88499698 DYH	404	struct cmdq_thread thread = (struct cmdq_thread )chan->con_priv;
	405	struct cmdq *cmdq = dev_get_drvdata(chan->mbox->dev);
	406	struct cmdq_task task, tmp;
	407	unsigned long flags;
	408
	409	spin_lock_irqsave(&thread->chan->lock, flags);
	410	if (list_empty(&thread->task_busy_list))
	411	goto done;
	412
	413	WARN_ON(cmdq_thread_suspend(cmdq, thread) < 0);
	414
	415	/* make sure executed tasks have success callback */
	416	cmdq_thread_irq_handler(cmdq, thread);
	417	if (list_empty(&thread->task_busy_list))
	418	goto done;
	419
	420	list_for_each_entry_safe(task, tmp, &thread->task_busy_list,
	421	list_entry) {
b3c0d72b	422	cmdq_task_exec_done(task, -ECONNABORTED);
88499698 DYH	423	kfree(task);
	424	}
	425
	426	cmdq_thread_disable(cmdq, thread);
	427	clk_disable(cmdq->clock);
	428	done:
	429	/*
	430	* The thread->task_busy_list empty means thread already disable. The
	431	* cmdq_mbox_send_data() always reset thread which clear disable and
	432	* suspend statue when first pkt send to channel, so there is no need
	433	* to do any operation here, only unlock and leave.
	434	*/
	435	spin_unlock_irqrestore(&thread->chan->lock, flags);
623a6143 HW	436	}
623a6143 HW	437
b0524f7c BH	438	static int cmdq_mbox_flush(struct mbox_chan *chan, unsigned long timeout)
	439	{
	440	struct cmdq_thread thread = (struct cmdq_thread )chan->con_priv;
	441	struct cmdq_task_cb *cb;
	442	struct cmdq_cb_data data;
	443	struct cmdq *cmdq = dev_get_drvdata(chan->mbox->dev);
	444	struct cmdq_task task, tmp;
	445	unsigned long flags;
	446	u32 enable;
	447
	448	spin_lock_irqsave(&thread->chan->lock, flags);
	449	if (list_empty(&thread->task_busy_list))
	450	goto out;
	451
	452	WARN_ON(cmdq_thread_suspend(cmdq, thread) < 0);
	453	if (!cmdq_thread_is_in_wfe(thread))
	454	goto wait;
	455
	456	list_for_each_entry_safe(task, tmp, &thread->task_busy_list,
	457	list_entry) {
cc3eb518	458	cb = &task->pkt->async_cb;
1b6b0ce2 CKH	459	data.sta = -ECONNABORTED;
1b6b0ce2 CKH	460	data.data = cb->data;
8ebc3b5a	461	data.pkt = task->pkt;
1b6b0ce2	462	if (cb->cb)
b0524f7c	463	cb->cb(data);
1b6b0ce2 CKH	464
1b6b0ce2 CKH	465	mbox_chan_received_data(task->thread->chan, &data);
b0524f7c BH	466	list_del(&task->list_entry);
	467	kfree(task);
	468	}
	469
	470	cmdq_thread_resume(thread);
	471	cmdq_thread_disable(cmdq, thread);
	472	clk_disable(cmdq->clock);
	473
	474	out:
	475	spin_unlock_irqrestore(&thread->chan->lock, flags);
	476	return 0;
	477
	478	wait:
	479	cmdq_thread_resume(thread);
	480	spin_unlock_irqrestore(&thread->chan->lock, flags);
	481	if (readl_poll_timeout_atomic(thread->base + CMDQ_THR_ENABLE_TASK,
	482	enable, enable == 0, 1, timeout)) {
	483	dev_err(cmdq->mbox.dev, "Fail to wait GCE thread 0x%x done\n",
	484	(u32)(thread->base - cmdq->base));
	485
	486	return -EFAULT;
	487	}
	488	return 0;
	489	}
	490
623a6143 HW	491	static const struct mbox_chan_ops cmdq_mbox_chan_ops = {
	492	.send_data = cmdq_mbox_send_data,
	493	.startup = cmdq_mbox_startup,
	494	.shutdown = cmdq_mbox_shutdown,
b0524f7c	495	.flush = cmdq_mbox_flush,
623a6143 HW	496	};
	497
	498	static struct mbox_chan cmdq_xlate(struct mbox_controller mbox,
	499	const struct of_phandle_args *sp)
	500	{
	501	int ind = sp->args[0];
	502	struct cmdq_thread *thread;
	503
	504	if (ind >= mbox->num_chans)
	505	return ERR_PTR(-EINVAL);
	506
	507	thread = (struct cmdq_thread *)mbox->chans[ind].con_priv;
	508	thread->priority = sp->args[1];
623a6143 HW	509	thread->chan = &mbox->chans[ind];
	510
	511	return &mbox->chans[ind];
	512	}
	513
	514	static int cmdq_probe(struct platform_device *pdev)
	515	{
	516	struct device *dev = &pdev->dev;
	517	struct resource *res;
	518	struct cmdq *cmdq;
	519	int err, i;
0858fde4	520	struct gce_plat *plat_data;
623a6143 HW	521
	522	cmdq = devm_kzalloc(dev, sizeof(*cmdq), GFP_KERNEL);
	523	if (!cmdq)
	524	return -ENOMEM;
	525
	526	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	527	cmdq->base = devm_ioremap_resource(dev, res);
ff16cae3	528	if (IS_ERR(cmdq->base))
623a6143	529	return PTR_ERR(cmdq->base);
623a6143 HW	530
623a6143 HW	531	cmdq->irq = platform_get_irq(pdev, 0);
558e4c36 KK	532	if (cmdq->irq < 0)
558e4c36 KK	533	return cmdq->irq;
2c49e4e8	534
0858fde4 DYH	535	plat_data = (struct gce_plat *)of_device_get_match_data(dev);
	536	if (!plat_data) {
	537	dev_err(dev, "failed to get match data\n");
	538	return -EINVAL;
	539	}
	540
	541	cmdq->thread_nr = plat_data->thread_nr;
	542	cmdq->shift_pa = plat_data->shift;
2c49e4e8	543	cmdq->irq_mask = GENMASK(cmdq->thread_nr - 1, 0);
623a6143 HW	544	err = devm_request_irq(dev, cmdq->irq, cmdq_irq_handler, IRQF_SHARED,
	545	"mtk_cmdq", cmdq);
	546	if (err < 0) {
	547	dev_err(dev, "failed to register ISR (%d)\n", err);
	548	return err;
	549	}
	550
	551	dev_dbg(dev, "cmdq device: addr:0x%p, va:0x%p, irq:%d\n",
	552	dev, cmdq->base, cmdq->irq);
	553
	554	cmdq->clock = devm_clk_get(dev, "gce");
	555	if (IS_ERR(cmdq->clock)) {
	556	dev_err(dev, "failed to get gce clk\n");
	557	return PTR_ERR(cmdq->clock);
	558	}
	559
623a6143 HW	560	cmdq->mbox.dev = dev;
	561	cmdq->mbox.chans = devm_kcalloc(dev, cmdq->thread_nr,
	562	sizeof(*cmdq->mbox.chans), GFP_KERNEL);
	563	if (!cmdq->mbox.chans)
	564	return -ENOMEM;
	565
	566	cmdq->mbox.num_chans = cmdq->thread_nr;
	567	cmdq->mbox.ops = &cmdq_mbox_chan_ops;
	568	cmdq->mbox.of_xlate = cmdq_xlate;
	569
	570	/* make use of TXDONE_BY_ACK */
	571	cmdq->mbox.txdone_irq = false;
	572	cmdq->mbox.txdone_poll = false;
	573
	574	cmdq->thread = devm_kcalloc(dev, cmdq->thread_nr,
	575	sizeof(*cmdq->thread), GFP_KERNEL);
	576	if (!cmdq->thread)
	577	return -ENOMEM;
	578
	579	for (i = 0; i < cmdq->thread_nr; i++) {
	580	cmdq->thread[i].base = cmdq->base + CMDQ_THR_BASE +
	581	CMDQ_THR_SIZE * i;
	582	INIT_LIST_HEAD(&cmdq->thread[i].task_busy_list);
	583	cmdq->mbox.chans[i].con_priv = (void *)&cmdq->thread[i];
	584	}
	585
8aed5719	586	err = devm_mbox_controller_register(dev, &cmdq->mbox);
623a6143 HW	587	if (err < 0) {
	588	dev_err(dev, "failed to register mailbox: %d\n", err);
	589	return err;
	590	}
	591
	592	platform_set_drvdata(pdev, cmdq);
	593	WARN_ON(clk_prepare(cmdq->clock) < 0);
	594
	595	cmdq_init(cmdq);
	596
	597	return 0;
	598	}
	599
	600	static const struct dev_pm_ops cmdq_pm_ops = {
	601	.suspend = cmdq_suspend,
	602	.resume = cmdq_resume,
	603	};
	604
0858fde4 DYH	605	static const struct gce_plat gce_plat_v2 = {.thread_nr = 16};
0858fde4 DYH	606	static const struct gce_plat gce_plat_v3 = {.thread_nr = 24};
bb2b06e0	607	static const struct gce_plat gce_plat_v4 = {.thread_nr = 24, .shift = 3};
0858fde4	608
623a6143	609	static const struct of_device_id cmdq_of_ids[] = {
0858fde4 DYH	610	{.compatible = "mediatek,mt8173-gce", .data = (void *)&gce_plat_v2},
0858fde4 DYH	611	{.compatible = "mediatek,mt8183-gce", .data = (void *)&gce_plat_v3},
bb2b06e0	612	{.compatible = "mediatek,mt6779-gce", .data = (void *)&gce_plat_v4},
623a6143 HW	613	{}
	614	};
	615
	616	static struct platform_driver cmdq_drv = {
	617	.probe = cmdq_probe,
	618	.remove = cmdq_remove,
	619	.driver = {
	620	.name = "mtk_cmdq",
	621	.pm = &cmdq_pm_ops,
	622	.of_match_table = cmdq_of_ids,
	623	}
	624	};
	625
	626	static int __init cmdq_drv_init(void)
	627	{
	628	return platform_driver_register(&cmdq_drv);
	629	}
	630
	631	static void __exit cmdq_drv_exit(void)
	632	{
	633	platform_driver_unregister(&cmdq_drv);
	634	}
	635
	636	subsys_initcall(cmdq_drv_init);
	637	module_exit(cmdq_drv_exit);
c5f45fbb RD	638
c5f45fbb RD	639	MODULE_LICENSE("GPL v2");