[linux-block.git] / drivers / mailbox / mailbox-mpfs.c

// SPDX-License-Identifier: GPL-2.0
/*
 * Microchip PolarFire SoC (MPFS) system controller/mailbox controller driver
 *
 * Copyright (c) 2020 Microchip Corporation. All rights reserved.
 *
 * Author: Conor Dooley <conor.dooley@microchip.com>
 *
 */

#include <linux/io.h>
#include <linux/err.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/interrupt.h>
#include <linux/platform_device.h>
#include <linux/mailbox_controller.h>
#include <soc/microchip/mpfs.h>

#define SERVICES_CR_OFFSET		0x50u
#define SERVICES_SR_OFFSET		0x54u
#define MAILBOX_REG_OFFSET		0x800u
#define MSS_SYS_MAILBOX_DATA_OFFSET	0u
#define SCB_MASK_WIDTH			16u

/* SCBCTRL service control register */

#define SCB_CTRL_REQ (0)
#define SCB_CTRL_REQ_MASK BIT(SCB_CTRL_REQ)

#define SCB_CTRL_BUSY (1)
#define SCB_CTRL_BUSY_MASK BIT(SCB_CTRL_BUSY)

#define SCB_CTRL_ABORT (2)
#define SCB_CTRL_ABORT_MASK BIT(SCB_CTRL_ABORT)

#define SCB_CTRL_NOTIFY (3)
#define SCB_CTRL_NOTIFY_MASK BIT(SCB_CTRL_NOTIFY)

#define SCB_CTRL_POS (16)
#define SCB_CTRL_MASK GENMASK_ULL(SCB_CTRL_POS + SCB_MASK_WIDTH, SCB_CTRL_POS)

/* SCBCTRL service status register */

#define SCB_STATUS_REQ (0)
#define SCB_STATUS_REQ_MASK BIT(SCB_STATUS_REQ)

#define SCB_STATUS_BUSY (1)
#define SCB_STATUS_BUSY_MASK BIT(SCB_STATUS_BUSY)

#define SCB_STATUS_ABORT (2)
#define SCB_STATUS_ABORT_MASK BIT(SCB_STATUS_ABORT)

#define SCB_STATUS_NOTIFY (3)
#define SCB_STATUS_NOTIFY_MASK BIT(SCB_STATUS_NOTIFY)

#define SCB_STATUS_POS (16)
#define SCB_STATUS_MASK GENMASK_ULL(SCB_STATUS_POS + SCB_MASK_WIDTH, SCB_STATUS_POS)

struct mpfs_mbox {
	struct mbox_controller controller;
	struct device *dev;
	int irq;
	void __iomem *ctrl_base;
	void __iomem *mbox_base;
	void __iomem *int_reg;
	struct mbox_chan chans[1];
	struct mpfs_mss_response *response;
	u16 resp_offset;
};

static bool mpfs_mbox_busy(struct mpfs_mbox *mbox)
{
	u32 status;

	status = readl_relaxed(mbox->ctrl_base + SERVICES_SR_OFFSET);

	return status & SCB_STATUS_BUSY_MASK;
}

static int mpfs_mbox_send_data(struct mbox_chan *chan, void *data)
{
	struct mpfs_mbox *mbox = (struct mpfs_mbox *)chan->con_priv;
	struct mpfs_mss_msg *msg = data;
	u32 tx_trigger;
	u16 opt_sel;
	u32 val = 0u;

	mbox->response = msg->response;
	mbox->resp_offset = msg->resp_offset;

	if (mpfs_mbox_busy(mbox))
		return -EBUSY;

	if (msg->cmd_data_size) {
		u32 index;
		u8 extra_bits = msg->cmd_data_size & 3;
		u32 *word_buf = (u32 *)msg->cmd_data;

		for (index = 0; index < (msg->cmd_data_size / 4); index++)
			writel_relaxed(word_buf[index],
				       mbox->mbox_base + msg->mbox_offset + index * 0x4);
		if (extra_bits) {
			u8 i;
			u8 byte_off = ALIGN_DOWN(msg->cmd_data_size, 4);
			u8 *byte_buf = msg->cmd_data + byte_off;

			val = readl_relaxed(mbox->mbox_base + msg->mbox_offset + index * 0x4);

			for (i = 0u; i < extra_bits; i++) {
				val &= ~(0xffu << (i * 8u));
				val |= (byte_buf[i] << (i * 8u));
			}

			writel_relaxed(val, mbox->mbox_base + msg->mbox_offset + index * 0x4);
		}
	}

	opt_sel = ((msg->mbox_offset << 7u) | (msg->cmd_opcode & 0x7fu));
	tx_trigger = (opt_sel << SCB_CTRL_POS) & SCB_CTRL_MASK;
	tx_trigger |= SCB_CTRL_REQ_MASK | SCB_STATUS_NOTIFY_MASK;
	writel_relaxed(tx_trigger, mbox->ctrl_base + SERVICES_CR_OFFSET);

	return 0;
}

static void mpfs_mbox_rx_data(struct mbox_chan *chan)
{
	struct mpfs_mbox *mbox = (struct mpfs_mbox *)chan->con_priv;
	struct mpfs_mss_response *response = mbox->response;
	u16 num_words = ALIGN((response->resp_size), (4)) / 4U;
	u32 i;

	if (!response->resp_msg) {
		dev_err(mbox->dev, "failed to assign memory for response %d\n", -ENOMEM);
		return;
	}

	if (!mpfs_mbox_busy(mbox)) {
		for (i = 0; i < num_words; i++) {
			response->resp_msg[i] =
				readl_relaxed(mbox->mbox_base
					      + mbox->resp_offset + i * 0x4);
		}
	}

	mbox_chan_received_data(chan, response);
}

static irqreturn_t mpfs_mbox_inbox_isr(int irq, void *data)
{
	struct mbox_chan *chan = data;
	struct mpfs_mbox *mbox = (struct mpfs_mbox *)chan->con_priv;

	writel_relaxed(0, mbox->int_reg);

	mpfs_mbox_rx_data(chan);

	mbox_chan_txdone(chan, 0);
	return IRQ_HANDLED;
}

static int mpfs_mbox_startup(struct mbox_chan *chan)
{
	struct mpfs_mbox *mbox = (struct mpfs_mbox *)chan->con_priv;
	int ret = 0;

	if (!mbox)
		return -EINVAL;

	ret = devm_request_irq(mbox->dev, mbox->irq, mpfs_mbox_inbox_isr, 0, "mpfs-mailbox", chan);
	if (ret)
		dev_err(mbox->dev, "failed to register mailbox interrupt:%d\n", ret);

	return ret;
}

static void mpfs_mbox_shutdown(struct mbox_chan *chan)
{
	struct mpfs_mbox *mbox = (struct mpfs_mbox *)chan->con_priv;

	devm_free_irq(mbox->dev, mbox->irq, chan);
}

static const struct mbox_chan_ops mpfs_mbox_ops = {
	.send_data = mpfs_mbox_send_data,
	.startup = mpfs_mbox_startup,
	.shutdown = mpfs_mbox_shutdown,
};

static int mpfs_mbox_probe(struct platform_device *pdev)
{
	struct mpfs_mbox *mbox;
	struct resource *regs;
	int ret;

	mbox = devm_kzalloc(&pdev->dev, sizeof(*mbox), GFP_KERNEL);
	if (!mbox)
		return -ENOMEM;

	mbox->ctrl_base = devm_platform_get_and_ioremap_resource(pdev, 0, &regs);
	if (IS_ERR(mbox->ctrl_base))
		return PTR_ERR(mbox->ctrl_base);

	mbox->int_reg = devm_platform_get_and_ioremap_resource(pdev, 1, &regs);
	if (IS_ERR(mbox->int_reg))
		return PTR_ERR(mbox->int_reg);

	mbox->mbox_base = devm_platform_get_and_ioremap_resource(pdev, 2, &regs);
	if (IS_ERR(mbox->mbox_base)) // account for the old dt-binding w/ 2 regs
		mbox->mbox_base = mbox->ctrl_base + MAILBOX_REG_OFFSET;

	mbox->irq = platform_get_irq(pdev, 0);
	if (mbox->irq < 0)
		return mbox->irq;

	mbox->dev = &pdev->dev;

	mbox->chans[0].con_priv = mbox;
	mbox->controller.dev = mbox->dev;
	mbox->controller.num_chans = 1;
	mbox->controller.chans = mbox->chans;
	mbox->controller.ops = &mpfs_mbox_ops;
	mbox->controller.txdone_irq = true;

	ret = devm_mbox_controller_register(&pdev->dev, &mbox->controller);
	if (ret) {
		dev_err(&pdev->dev, "Registering MPFS mailbox controller failed\n");
		return ret;
	}
	dev_info(&pdev->dev, "Registered MPFS mailbox controller driver\n");

	return 0;
}

static const struct of_device_id mpfs_mbox_of_match[] = {
	{.compatible = "microchip,mpfs-mailbox", },
	{},
};
MODULE_DEVICE_TABLE(of, mpfs_mbox_of_match);

static struct platform_driver mpfs_mbox_driver = {
	.driver = {
		.name = "mpfs-mailbox",
		.of_match_table = mpfs_mbox_of_match,
	},
	.probe = mpfs_mbox_probe,
};
module_platform_driver(mpfs_mbox_driver);

MODULE_LICENSE("GPL v2");
MODULE_AUTHOR("Conor Dooley <conor.dooley@microchip.com>");
MODULE_DESCRIPTION("MPFS mailbox controller driver");
Commit	Line	Data
83d7b156 CD	1	// SPDX-License-Identifier: GPL-2.0
	2	/*
	3	* Microchip PolarFire SoC (MPFS) system controller/mailbox controller driver
	4	*
	5	* Copyright (c) 2020 Microchip Corporation. All rights reserved.
	6	*
	7	* Author: Conor Dooley <conor.dooley@microchip.com>
	8	*
	9	*/
	10
	11	#include <linux/io.h>
	12	#include <linux/err.h>
	13	#include <linux/init.h>
	14	#include <linux/module.h>
	15	#include <linux/kernel.h>
	16	#include <linux/interrupt.h>
	17	#include <linux/platform_device.h>
	18	#include <linux/mailbox_controller.h>
	19	#include <soc/microchip/mpfs.h>
	20
	21	#define SERVICES_CR_OFFSET 0x50u
	22	#define SERVICES_SR_OFFSET 0x54u
	23	#define MAILBOX_REG_OFFSET 0x800u
	24	#define MSS_SYS_MAILBOX_DATA_OFFSET 0u
	25	#define SCB_MASK_WIDTH 16u
	26
	27	/* SCBCTRL service control register */
	28
	29	#define SCB_CTRL_REQ (0)
	30	#define SCB_CTRL_REQ_MASK BIT(SCB_CTRL_REQ)
	31
	32	#define SCB_CTRL_BUSY (1)
	33	#define SCB_CTRL_BUSY_MASK BIT(SCB_CTRL_BUSY)
	34
	35	#define SCB_CTRL_ABORT (2)
	36	#define SCB_CTRL_ABORT_MASK BIT(SCB_CTRL_ABORT)
	37
	38	#define SCB_CTRL_NOTIFY (3)
	39	#define SCB_CTRL_NOTIFY_MASK BIT(SCB_CTRL_NOTIFY)
	40
	41	#define SCB_CTRL_POS (16)
	42	#define SCB_CTRL_MASK GENMASK_ULL(SCB_CTRL_POS + SCB_MASK_WIDTH, SCB_CTRL_POS)
	43
	44	/* SCBCTRL service status register */
	45
	46	#define SCB_STATUS_REQ (0)
	47	#define SCB_STATUS_REQ_MASK BIT(SCB_STATUS_REQ)
	48
	49	#define SCB_STATUS_BUSY (1)
	50	#define SCB_STATUS_BUSY_MASK BIT(SCB_STATUS_BUSY)
	51
	52	#define SCB_STATUS_ABORT (2)
	53	#define SCB_STATUS_ABORT_MASK BIT(SCB_STATUS_ABORT)
	54
	55	#define SCB_STATUS_NOTIFY (3)
	56	#define SCB_STATUS_NOTIFY_MASK BIT(SCB_STATUS_NOTIFY)
	57
	58	#define SCB_STATUS_POS (16)
	59	#define SCB_STATUS_MASK GENMASK_ULL(SCB_STATUS_POS + SCB_MASK_WIDTH, SCB_STATUS_POS)
	60
	61	struct mpfs_mbox {
	62	struct mbox_controller controller;
	63	struct device *dev;
	64	int irq;
2e10289d	65	void __iomem *ctrl_base;
83d7b156 CD	66	void __iomem *mbox_base;
	67	void __iomem *int_reg;
	68	struct mbox_chan chans[1];
	69	struct mpfs_mss_response *response;
	70	u16 resp_offset;
	71	};
	72
	73	static bool mpfs_mbox_busy(struct mpfs_mbox *mbox)
	74	{
	75	u32 status;
	76
2e10289d	77	status = readl_relaxed(mbox->ctrl_base + SERVICES_SR_OFFSET);
83d7b156 CD	78
	79	return status & SCB_STATUS_BUSY_MASK;
	80	}
	81
	82	static int mpfs_mbox_send_data(struct mbox_chan chan, void data)
	83	{
	84	struct mpfs_mbox mbox = (struct mpfs_mbox )chan->con_priv;
	85	struct mpfs_mss_msg *msg = data;
	86	u32 tx_trigger;
	87	u16 opt_sel;
	88	u32 val = 0u;
	89
	90	mbox->response = msg->response;
	91	mbox->resp_offset = msg->resp_offset;
	92
	93	if (mpfs_mbox_busy(mbox))
	94	return -EBUSY;
	95
	96	if (msg->cmd_data_size) {
	97	u32 index;
	98	u8 extra_bits = msg->cmd_data_size & 3;
	99	u32 word_buf = (u32 )msg->cmd_data;
	100
	101	for (index = 0; index < (msg->cmd_data_size / 4); index++)
	102	writel_relaxed(word_buf[index],
0d1aadfe	103	mbox->mbox_base + msg->mbox_offset + index * 0x4);
83d7b156 CD	104	if (extra_bits) {
	105	u8 i;
	106	u8 byte_off = ALIGN_DOWN(msg->cmd_data_size, 4);
	107	u8 *byte_buf = msg->cmd_data + byte_off;
	108
0d1aadfe	109	val = readl_relaxed(mbox->mbox_base + msg->mbox_offset + index * 0x4);
83d7b156 CD	110
	111	for (i = 0u; i < extra_bits; i++) {
	112	val &= ~(0xffu << (i * 8u));
	113	val \|= (byte_buf[i] << (i * 8u));
	114	}
	115
0d1aadfe	116	writel_relaxed(val, mbox->mbox_base + msg->mbox_offset + index * 0x4);
83d7b156 CD	117	}
	118	}
	119
	120	opt_sel = ((msg->mbox_offset << 7u) \| (msg->cmd_opcode & 0x7fu));
	121	tx_trigger = (opt_sel << SCB_CTRL_POS) & SCB_CTRL_MASK;
	122	tx_trigger \|= SCB_CTRL_REQ_MASK \| SCB_STATUS_NOTIFY_MASK;
2e10289d	123	writel_relaxed(tx_trigger, mbox->ctrl_base + SERVICES_CR_OFFSET);
83d7b156 CD	124
	125	return 0;
	126	}
	127
	128	static void mpfs_mbox_rx_data(struct mbox_chan *chan)
	129	{
	130	struct mpfs_mbox mbox = (struct mpfs_mbox )chan->con_priv;
	131	struct mpfs_mss_response *response = mbox->response;
	132	u16 num_words = ALIGN((response->resp_size), (4)) / 4U;
	133	u32 i;
	134
	135	if (!response->resp_msg) {
	136	dev_err(mbox->dev, "failed to assign memory for response %d\n", -ENOMEM);
	137	return;
	138	}
	139
	140	if (!mpfs_mbox_busy(mbox)) {
	141	for (i = 0; i < num_words; i++) {
	142	response->resp_msg[i] =
2e10289d	143	readl_relaxed(mbox->mbox_base
83d7b156 CD	144	+ mbox->resp_offset + i * 0x4);
	145	}
	146	}
	147
	148	mbox_chan_received_data(chan, response);
	149	}
	150
	151	static irqreturn_t mpfs_mbox_inbox_isr(int irq, void *data)
	152	{
	153	struct mbox_chan *chan = data;
	154	struct mpfs_mbox mbox = (struct mpfs_mbox )chan->con_priv;
	155
	156	writel_relaxed(0, mbox->int_reg);
	157
	158	mpfs_mbox_rx_data(chan);
	159
	160	mbox_chan_txdone(chan, 0);
	161	return IRQ_HANDLED;
	162	}
	163
	164	static int mpfs_mbox_startup(struct mbox_chan *chan)
	165	{
	166	struct mpfs_mbox mbox = (struct mpfs_mbox )chan->con_priv;
	167	int ret = 0;
	168
	169	if (!mbox)
	170	return -EINVAL;
	171
	172	ret = devm_request_irq(mbox->dev, mbox->irq, mpfs_mbox_inbox_isr, 0, "mpfs-mailbox", chan);
	173	if (ret)
	174	dev_err(mbox->dev, "failed to register mailbox interrupt:%d\n", ret);
	175
	176	return ret;
	177	}
	178
	179	static void mpfs_mbox_shutdown(struct mbox_chan *chan)
	180	{
	181	struct mpfs_mbox mbox = (struct mpfs_mbox )chan->con_priv;
	182
	183	devm_free_irq(mbox->dev, mbox->irq, chan);
	184	}
	185
	186	static const struct mbox_chan_ops mpfs_mbox_ops = {
	187	.send_data = mpfs_mbox_send_data,
	188	.startup = mpfs_mbox_startup,
	189	.shutdown = mpfs_mbox_shutdown,
	190	};
	191
	192	static int mpfs_mbox_probe(struct platform_device *pdev)
	193	{
	194	struct mpfs_mbox *mbox;
	195	struct resource *regs;
	196	int ret;
	197
	198	mbox = devm_kzalloc(&pdev->dev, sizeof(*mbox), GFP_KERNEL);
	199	if (!mbox)
	200	return -ENOMEM;
	201
2e10289d CD	202	mbox->ctrl_base = devm_platform_get_and_ioremap_resource(pdev, 0, &regs);
	203	if (IS_ERR(mbox->ctrl_base))
	204	return PTR_ERR(mbox->ctrl_base);
83d7b156 CD	205
	206	mbox->int_reg = devm_platform_get_and_ioremap_resource(pdev, 1, &regs);
	207	if (IS_ERR(mbox->int_reg))
	208	return PTR_ERR(mbox->int_reg);
	209
2e10289d CD	210	mbox->mbox_base = devm_platform_get_and_ioremap_resource(pdev, 2, &regs);
	211	if (IS_ERR(mbox->mbox_base)) // account for the old dt-binding w/ 2 regs
	212	mbox->mbox_base = mbox->ctrl_base + MAILBOX_REG_OFFSET;
	213
83d7b156 CD	214	mbox->irq = platform_get_irq(pdev, 0);
	215	if (mbox->irq < 0)
	216	return mbox->irq;
	217
	218	mbox->dev = &pdev->dev;
	219
	220	mbox->chans[0].con_priv = mbox;
	221	mbox->controller.dev = mbox->dev;
	222	mbox->controller.num_chans = 1;
	223	mbox->controller.chans = mbox->chans;
	224	mbox->controller.ops = &mpfs_mbox_ops;
	225	mbox->controller.txdone_irq = true;
	226
	227	ret = devm_mbox_controller_register(&pdev->dev, &mbox->controller);
	228	if (ret) {
	229	dev_err(&pdev->dev, "Registering MPFS mailbox controller failed\n");
	230	return ret;
	231	}
	232	dev_info(&pdev->dev, "Registered MPFS mailbox controller driver\n");
	233
	234	return 0;
	235	}
	236
	237	static const struct of_device_id mpfs_mbox_of_match[] = {
f10b1fc0	238	{.compatible = "microchip,mpfs-mailbox", },
83d7b156 CD	239	{},
	240	};
	241	MODULE_DEVICE_TABLE(of, mpfs_mbox_of_match);
	242
	243	static struct platform_driver mpfs_mbox_driver = {
	244	.driver = {
	245	.name = "mpfs-mailbox",
	246	.of_match_table = mpfs_mbox_of_match,
	247	},
	248	.probe = mpfs_mbox_probe,
	249	};
	250	module_platform_driver(mpfs_mbox_driver);
	251
	252	MODULE_LICENSE("GPL v2");
	253	MODULE_AUTHOR("Conor Dooley <conor.dooley@microchip.com>");
	254	MODULE_DESCRIPTION("MPFS mailbox controller driver");