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Merge tag 'tegra-for-5.17-arm64-dt-fixes' of git://git.kernel.org/pub/scm/linux/kerne...
[linux-block.git] / drivers / mailbox / imx-mailbox.c
CommitLineData
2bb70056
OR		 1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2018 Pengutronix, Oleksij Rempel <o.rempel@pengutronix.de>
4 */
5
6#include <linux/clk.h>
0a67003b 7#include <linux/firmware/imx/ipc.h>
97961f78 8#include <linux/firmware/imx/s4.h>
2bb70056
OR		 9#include <linux/interrupt.h>
10#include <linux/io.h>
0a67003b 11#include <linux/iopoll.h>
2bb70056
OR		 12#include <linux/kernel.h>
13#include <linux/mailbox_controller.h>
14#include <linux/module.h>
15#include <linux/of_device.h>
676f23ea 16#include <linux/pm_runtime.h>
2bb70056
OR		 17#include <linux/slab.h>
18
2bb70056 19#define IMX_MU_CHANS 16
0a67003b
PF		 20/* TX0/RX0/RXDB[0-3] */
21#define IMX_MU_SCU_CHANS 6
97961f78
PF		 22/* TX0/RX0 */
23#define IMX_MU_S4_CHANS 2
2bb70056
OR		 24#define IMX_MU_CHAN_NAME_SIZE 20
25
26enum imx_mu_chan_type {
27 IMX_MU_TYPE_TX, /* Tx */
28 IMX_MU_TYPE_RX, /* Rx */
29 IMX_MU_TYPE_TXDB, /* Tx doorbell */
30 IMX_MU_TYPE_RXDB, /* Rx doorbell */
31};
32
f689a7cf 33enum imx_mu_xcr {
4f0b776e 34 IMX_MU_GIER,
f689a7cf
PF		 35 IMX_MU_GCR,
36 IMX_MU_TCR,
37 IMX_MU_RCR,
38 IMX_MU_xCR_MAX,
39};
40
41enum imx_mu_xsr {
42 IMX_MU_SR,
43 IMX_MU_GSR,
44 IMX_MU_TSR,
45 IMX_MU_RSR,
46};
47
0a67003b
PF		 48struct imx_sc_rpc_msg_max {
49 struct imx_sc_rpc_msg hdr;
50 u32 data[7];
51};
52
97961f78
PF		 53struct imx_s4_rpc_msg_max {
54 struct imx_s4_rpc_msg hdr;
55 u32 data[254];
56};
57
2bb70056
OR		 58struct imx_mu_con_priv {
59 unsigned int idx;
60 char irq_desc[IMX_MU_CHAN_NAME_SIZE];
61 enum imx_mu_chan_type type;
62 struct mbox_chan *chan;
63 struct tasklet_struct txdb_tasklet;
64};
65
66struct imx_mu_priv {
67 struct device *dev;
68 void __iomem *base;
97961f78 69 void *msg;
2bb70056
OR		 70 spinlock_t xcr_lock; /* control register lock */
71
72 struct mbox_controller mbox;
73 struct mbox_chan mbox_chans[IMX_MU_CHANS];
74
75 struct imx_mu_con_priv con_priv[IMX_MU_CHANS];
c6c6bc6e 76 const struct imx_mu_dcfg *dcfg;
2bb70056
OR		 77 struct clk *clk;
78 int irq;
79
f689a7cf 80 u32 xcr[4];
ba5f9fa0 81
2bb70056
OR		 82 bool side_b;
83};
84
4f0b776e
PF		 85enum imx_mu_type {
86 IMX_MU_V1,
97961f78
PF		 87 IMX_MU_V2 = BIT(1),
88 IMX_MU_V2_S4 = BIT(15),
4f0b776e
PF		 89};
90
63b38357
PF		 91struct imx_mu_dcfg {
92 int (*tx)(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp, void *data);
93 int (*rx)(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp);
94 void (*init)(struct imx_mu_priv *priv);
4f0b776e 95 enum imx_mu_type type;
32f7443d
PF		 96 u32 xTR; /* Transmit Register0 */
97 u32 xRR; /* Receive Register0 */
f689a7cf
PF		 98 u32 xSR[4]; /* Status Registers */
99 u32 xCR[4]; /* Control Registers */
c6c6bc6e
RZ		 100};
101
97961f78
PF		 102#define IMX_MU_xSR_GIPn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(28 + (3 - (x))))
103#define IMX_MU_xSR_RFn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(24 + (3 - (x))))
104#define IMX_MU_xSR_TEn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(20 + (3 - (x))))
4f0b776e
PF		 105
106/* General Purpose Interrupt Enable */
97961f78 107#define IMX_MU_xCR_GIEn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(28 + (3 - (x))))
4f0b776e 108/* Receive Interrupt Enable */
97961f78 109#define IMX_MU_xCR_RIEn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(24 + (3 - (x))))
4f0b776e 110/* Transmit Interrupt Enable */
97961f78 111#define IMX_MU_xCR_TIEn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(20 + (3 - (x))))
4f0b776e 112/* General Purpose Interrupt Request */
97961f78 113#define IMX_MU_xCR_GIRn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(16 + (3 - (x))))
4f0b776e
PF		 114
115
2bb70056
OR		 116static struct imx_mu_priv *to_imx_mu_priv(struct mbox_controller *mbox)
117{
118 return container_of(mbox, struct imx_mu_priv, mbox);
119}
120
121static void imx_mu_write(struct imx_mu_priv *priv, u32 val, u32 offs)
122{
123 iowrite32(val, priv->base + offs);
124}
125
126static u32 imx_mu_read(struct imx_mu_priv *priv, u32 offs)
127{
128 return ioread32(priv->base + offs);
129}
130
f689a7cf 131static u32 imx_mu_xcr_rmw(struct imx_mu_priv *priv, enum imx_mu_xcr type, u32 set, u32 clr)
2bb70056
OR		 132{
133 unsigned long flags;
134 u32 val;
135
136 spin_lock_irqsave(&priv->xcr_lock, flags);
f689a7cf 137 val = imx_mu_read(priv, priv->dcfg->xCR[type]);
2bb70056
OR		 138 val &= ~clr;
139 val |= set;
f689a7cf 140 imx_mu_write(priv, val, priv->dcfg->xCR[type]);
2bb70056
OR		 141 spin_unlock_irqrestore(&priv->xcr_lock, flags);
142
143 return val;
144}
145
63b38357
PF		 146static int imx_mu_generic_tx(struct imx_mu_priv *priv,
147 struct imx_mu_con_priv *cp,
148 void *data)
149{
150 u32 *arg = data;
151
152 switch (cp->type) {
153 case IMX_MU_TYPE_TX:
32f7443d 154 imx_mu_write(priv, *arg, priv->dcfg->xTR + cp->idx * 4);
4f0b776e 155 imx_mu_xcr_rmw(priv, IMX_MU_TCR, IMX_MU_xCR_TIEn(priv->dcfg->type, cp->idx), 0);
63b38357
PF		 156 break;
157 case IMX_MU_TYPE_TXDB:
4f0b776e 158 imx_mu_xcr_rmw(priv, IMX_MU_GCR, IMX_MU_xCR_GIRn(priv->dcfg->type, cp->idx), 0);
63b38357
PF		 159 tasklet_schedule(&cp->txdb_tasklet);
160 break;
161 default:
162 dev_warn_ratelimited(priv->dev, "Send data on wrong channel type: %d\n", cp->type);
163 return -EINVAL;
164 }
165
166 return 0;
167}
168
169static int imx_mu_generic_rx(struct imx_mu_priv *priv,
170 struct imx_mu_con_priv *cp)
171{
172 u32 dat;
173
32f7443d 174 dat = imx_mu_read(priv, priv->dcfg->xRR + (cp->idx) * 4);
63b38357
PF		 175 mbox_chan_received_data(cp->chan, (void *)&dat);
176
177 return 0;
178}
179
97961f78 180static int imx_mu_specific_tx(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp, void *data)
0a67003b 181{
0a67003b
PF		 182 u32 *arg = data;
183 int i, ret;
184 u32 xsr;
97961f78
PF		 185 u32 size, max_size, num_tr;
186
187 if (priv->dcfg->type & IMX_MU_V2_S4) {
188 size = ((struct imx_s4_rpc_msg_max *)data)->hdr.size;
189 max_size = sizeof(struct imx_s4_rpc_msg_max);
190 num_tr = 8;
191 } else {
192 size = ((struct imx_sc_rpc_msg_max *)data)->hdr.size;
193 max_size = sizeof(struct imx_sc_rpc_msg_max);
194 num_tr = 4;
195 }
0a67003b
PF		 196
197 switch (cp->type) {
198 case IMX_MU_TYPE_TX:
9d8ca628
PF		 199 /*
200 * msg->hdr.size specifies the number of u32 words while
201 * sizeof yields bytes.
202 */
203
97961f78 204 if (size > max_size / 4) {
0a67003b
PF		 205 /*
206 * The real message size can be different to
97961f78 207 * struct imx_sc_rpc_msg_max/imx_s4_rpc_msg_max size
0a67003b 208 */
97961f78 209 dev_err(priv->dev, "Maximal message size (%u bytes) exceeded on TX; got: %i bytes\n", max_size, size << 2);
0a67003b
PF		 210 return -EINVAL;
211 }
212
97961f78
PF		 213 for (i = 0; i < num_tr && i < size; i++)
214 imx_mu_write(priv, *arg++, priv->dcfg->xTR + (i % num_tr) * 4);
215 for (; i < size; i++) {
f689a7cf 216 ret = readl_poll_timeout(priv->base + priv->dcfg->xSR[IMX_MU_TSR],
0a67003b 217 xsr,
97961f78 218 xsr & IMX_MU_xSR_TEn(priv->dcfg->type, i % num_tr),
0a67003b
PF		 219 0, 100);
220 if (ret) {
221 dev_err(priv->dev, "Send data index: %d timeout\n", i);
222 return ret;
223 }
97961f78 224 imx_mu_write(priv, *arg++, priv->dcfg->xTR + (i % num_tr) * 4);
0a67003b
PF		 225 }
226
4f0b776e 227 imx_mu_xcr_rmw(priv, IMX_MU_TCR, IMX_MU_xCR_TIEn(priv->dcfg->type, cp->idx), 0);
0a67003b
PF		 228 break;
229 default:
230 dev_warn_ratelimited(priv->dev, "Send data on wrong channel type: %d\n", cp->type);
231 return -EINVAL;
232 }
233
234 return 0;
235}
236
97961f78 237static int imx_mu_specific_rx(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp)
0a67003b 238{
97961f78 239 u32 *data;
0a67003b
PF		 240 int i, ret;
241 u32 xsr;
97961f78
PF		 242 u32 size, max_size;
243
244 data = (u32 *)priv->msg;
0a67003b 245
4f0b776e 246 imx_mu_xcr_rmw(priv, IMX_MU_RCR, 0, IMX_MU_xCR_RIEn(priv->dcfg->type, 0));
32f7443d 247 *data++ = imx_mu_read(priv, priv->dcfg->xRR);
0a67003b 248
97961f78
PF		 249 if (priv->dcfg->type & IMX_MU_V2_S4) {
250 size = ((struct imx_s4_rpc_msg_max *)priv->msg)->hdr.size;
251 max_size = sizeof(struct imx_s4_rpc_msg_max);
252 } else {
253 size = ((struct imx_sc_rpc_msg_max *)priv->msg)->hdr.size;
254 max_size = sizeof(struct imx_sc_rpc_msg_max);
255 }
256
257 if (size > max_size / 4) {
258 dev_err(priv->dev, "Maximal message size (%u bytes) exceeded on RX; got: %i bytes\n", max_size, size << 2);
0a67003b
PF		 259 return -EINVAL;
260 }
261
97961f78 262 for (i = 1; i < size; i++) {
f689a7cf 263 ret = readl_poll_timeout(priv->base + priv->dcfg->xSR[IMX_MU_RSR], xsr,
4f0b776e 264 xsr & IMX_MU_xSR_RFn(priv->dcfg->type, i % 4), 0, 100);
0a67003b
PF		 265 if (ret) {
266 dev_err(priv->dev, "timeout read idx %d\n", i);
267 return ret;
268 }
32f7443d 269 *data++ = imx_mu_read(priv, priv->dcfg->xRR + (i % 4) * 4);
0a67003b
PF		 270 }
271
4f0b776e 272 imx_mu_xcr_rmw(priv, IMX_MU_RCR, IMX_MU_xCR_RIEn(priv->dcfg->type, 0), 0);
97961f78 273 mbox_chan_received_data(cp->chan, (void *)priv->msg);
0a67003b
PF		 274
275 return 0;
276}
277
2bb70056
OR		 278static void imx_mu_txdb_tasklet(unsigned long data)
279{
280 struct imx_mu_con_priv *cp = (struct imx_mu_con_priv *)data;
281
282 mbox_chan_txdone(cp->chan, 0);
283}
284
285static irqreturn_t imx_mu_isr(int irq, void *p)
286{
287 struct mbox_chan *chan = p;
288 struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox);
289 struct imx_mu_con_priv *cp = chan->con_priv;
63b38357 290 u32 val, ctrl;
2bb70056 291
2bb70056
OR		 292 switch (cp->type) {
293 case IMX_MU_TYPE_TX:
f689a7cf
PF		 294 ctrl = imx_mu_read(priv, priv->dcfg->xCR[IMX_MU_TCR]);
295 val = imx_mu_read(priv, priv->dcfg->xSR[IMX_MU_TSR]);
4f0b776e
PF		 296 val &= IMX_MU_xSR_TEn(priv->dcfg->type, cp->idx) &
297 (ctrl & IMX_MU_xCR_TIEn(priv->dcfg->type, cp->idx));
2bb70056
OR		 298 break;
299 case IMX_MU_TYPE_RX:
f689a7cf
PF		 300 ctrl = imx_mu_read(priv, priv->dcfg->xCR[IMX_MU_RCR]);
301 val = imx_mu_read(priv, priv->dcfg->xSR[IMX_MU_RSR]);
4f0b776e
PF		 302 val &= IMX_MU_xSR_RFn(priv->dcfg->type, cp->idx) &
303 (ctrl & IMX_MU_xCR_RIEn(priv->dcfg->type, cp->idx));
2bb70056
OR		 304 break;
305 case IMX_MU_TYPE_RXDB:
4f0b776e 306 ctrl = imx_mu_read(priv, priv->dcfg->xCR[IMX_MU_GIER]);
f689a7cf 307 val = imx_mu_read(priv, priv->dcfg->xSR[IMX_MU_GSR]);
4f0b776e
PF		 308 val &= IMX_MU_xSR_GIPn(priv->dcfg->type, cp->idx) &
309 (ctrl & IMX_MU_xCR_GIEn(priv->dcfg->type, cp->idx));
2bb70056
OR		 310 break;
311 default:
e80a7e7e
NC		 312 dev_warn_ratelimited(priv->dev, "Unhandled channel type %d\n",
313 cp->type);
314 return IRQ_NONE;
2bb70056
OR		 315 }
316
317 if (!val)
318 return IRQ_NONE;
319
4f0b776e
PF		 320 if ((val == IMX_MU_xSR_TEn(priv->dcfg->type, cp->idx)) &&
321 (cp->type == IMX_MU_TYPE_TX)) {
322 imx_mu_xcr_rmw(priv, IMX_MU_TCR, 0, IMX_MU_xCR_TIEn(priv->dcfg->type, cp->idx));
2bb70056 323 mbox_chan_txdone(chan, 0);
4f0b776e
PF		 324 } else if ((val == IMX_MU_xSR_RFn(priv->dcfg->type, cp->idx)) &&
325 (cp->type == IMX_MU_TYPE_RX)) {
63b38357 326 priv->dcfg->rx(priv, cp);
4f0b776e
PF		 327 } else if ((val == IMX_MU_xSR_GIPn(priv->dcfg->type, cp->idx)) &&
328 (cp->type == IMX_MU_TYPE_RXDB)) {
329 imx_mu_write(priv, IMX_MU_xSR_GIPn(priv->dcfg->type, cp->idx),
330 priv->dcfg->xSR[IMX_MU_GSR]);
2bb70056
OR		 331 mbox_chan_received_data(chan, NULL);
332 } else {
333 dev_warn_ratelimited(priv->dev, "Not handled interrupt\n");
334 return IRQ_NONE;
335 }
336
337 return IRQ_HANDLED;
338}
339
340static int imx_mu_send_data(struct mbox_chan *chan, void *data)
341{
342 struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox);
343 struct imx_mu_con_priv *cp = chan->con_priv;
2bb70056 344
63b38357 345 return priv->dcfg->tx(priv, cp, data);
2bb70056
OR		 346}
347
348static int imx_mu_startup(struct mbox_chan *chan)
349{
350 struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox);
351 struct imx_mu_con_priv *cp = chan->con_priv;
b7b2796b 352 unsigned long irq_flag = IRQF_SHARED;
2bb70056
OR		 353 int ret;
354
676f23ea 355 pm_runtime_get_sync(priv->dev);
2bb70056
OR		 356 if (cp->type == IMX_MU_TYPE_TXDB) {
357 /* Tx doorbell don't have ACK support */
358 tasklet_init(&cp->txdb_tasklet, imx_mu_txdb_tasklet,
359 (unsigned long)cp);
360 return 0;
361 }
362
b7b2796b
AH		 363 /* IPC MU should be with IRQF_NO_SUSPEND set */
364 if (!priv->dev->pm_domain)
365 irq_flag |= IRQF_NO_SUSPEND;
366
367 ret = request_irq(priv->irq, imx_mu_isr, irq_flag,
368 cp->irq_desc, chan);
2bb70056
OR		 369 if (ret) {
370 dev_err(priv->dev,
371 "Unable to acquire IRQ %d\n", priv->irq);
372 return ret;
373 }
374
375 switch (cp->type) {
376 case IMX_MU_TYPE_RX:
4f0b776e 377 imx_mu_xcr_rmw(priv, IMX_MU_RCR, IMX_MU_xCR_RIEn(priv->dcfg->type, cp->idx), 0);
2bb70056
OR		 378 break;
379 case IMX_MU_TYPE_RXDB:
4f0b776e 380 imx_mu_xcr_rmw(priv, IMX_MU_GIER, IMX_MU_xCR_GIEn(priv->dcfg->type, cp->idx), 0);
2bb70056
OR		 381 break;
382 default:
383 break;
384 }
385
386 return 0;
387}
388
389static void imx_mu_shutdown(struct mbox_chan *chan)
390{
391 struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox);
392 struct imx_mu_con_priv *cp = chan->con_priv;
393
bf159d15 394 if (cp->type == IMX_MU_TYPE_TXDB) {
2bb70056 395 tasklet_kill(&cp->txdb_tasklet);
676f23ea 396 pm_runtime_put_sync(priv->dev);
bf159d15
DB		 397 return;
398 }
2bb70056 399
5f0af07e
DB		 400 switch (cp->type) {
401 case IMX_MU_TYPE_TX:
4f0b776e 402 imx_mu_xcr_rmw(priv, IMX_MU_TCR, 0, IMX_MU_xCR_TIEn(priv->dcfg->type, cp->idx));
5f0af07e
DB		 403 break;
404 case IMX_MU_TYPE_RX:
4f0b776e 405 imx_mu_xcr_rmw(priv, IMX_MU_RCR, 0, IMX_MU_xCR_RIEn(priv->dcfg->type, cp->idx));
5f0af07e
DB		 406 break;
407 case IMX_MU_TYPE_RXDB:
4f0b776e 408 imx_mu_xcr_rmw(priv, IMX_MU_GIER, 0, IMX_MU_xCR_GIEn(priv->dcfg->type, cp->idx));
5f0af07e
DB		 409 break;
410 default:
411 break;
412 }
2bb70056
OR		 413
414 free_irq(priv->irq, chan);
676f23ea 415 pm_runtime_put_sync(priv->dev);
2bb70056
OR		 416}
417
418static const struct mbox_chan_ops imx_mu_ops = {
419 .send_data = imx_mu_send_data,
420 .startup = imx_mu_startup,
421 .shutdown = imx_mu_shutdown,
422};
423
97961f78
PF		 424static struct mbox_chan *imx_mu_specific_xlate(struct mbox_controller *mbox,
425 const struct of_phandle_args *sp)
0a67003b
PF		 426{
427 u32 type, idx, chan;
428
429 if (sp->args_count != 2) {
430 dev_err(mbox->dev, "Invalid argument count %d\n", sp->args_count);
431 return ERR_PTR(-EINVAL);
432 }
433
434 type = sp->args[0]; /* channel type */
435 idx = sp->args[1]; /* index */
436
437 switch (type) {
438 case IMX_MU_TYPE_TX:
439 case IMX_MU_TYPE_RX:
440 if (idx != 0)
441 dev_err(mbox->dev, "Invalid chan idx: %d\n", idx);
442 chan = type;
443 break;
444 case IMX_MU_TYPE_RXDB:
445 chan = 2 + idx;
446 break;
447 default:
448 dev_err(mbox->dev, "Invalid chan type: %d\n", type);
1b3a347b 449 return ERR_PTR(-EINVAL);
0a67003b
PF		 450 }
451
452 if (chan >= mbox->num_chans) {
453 dev_err(mbox->dev, "Not supported channel number: %d. (type: %d, idx: %d)\n", chan, type, idx);
454 return ERR_PTR(-EINVAL);
455 }
456
457 return &mbox->chans[chan];
458}
459
2bb70056
OR		 460static struct mbox_chan * imx_mu_xlate(struct mbox_controller *mbox,
461 const struct of_phandle_args *sp)
462{
463 u32 type, idx, chan;
464
465 if (sp->args_count != 2) {
466 dev_err(mbox->dev, "Invalid argument count %d\n", sp->args_count);
467 return ERR_PTR(-EINVAL);
468 }
469
470 type = sp->args[0]; /* channel type */
471 idx = sp->args[1]; /* index */
472 chan = type * 4 + idx;
473
474 if (chan >= mbox->num_chans) {
475 dev_err(mbox->dev, "Not supported channel number: %d. (type: %d, idx: %d)\n", chan, type, idx);
476 return ERR_PTR(-EINVAL);
477 }
478
479 return &mbox->chans[chan];
480}
481
482static void imx_mu_init_generic(struct imx_mu_priv *priv)
483{
63b38357
PF		 484 unsigned int i;
485
486 for (i = 0; i < IMX_MU_CHANS; i++) {
487 struct imx_mu_con_priv *cp = &priv->con_priv[i];
488
489 cp->idx = i % 4;
490 cp->type = i >> 2;
491 cp->chan = &priv->mbox_chans[i];
492 priv->mbox_chans[i].con_priv = cp;
493 snprintf(cp->irq_desc, sizeof(cp->irq_desc),
494 "imx_mu_chan[%i-%i]", cp->type, cp->idx);
495 }
496
497 priv->mbox.num_chans = IMX_MU_CHANS;
498 priv->mbox.of_xlate = imx_mu_xlate;
499
2bb70056
OR		 500 if (priv->side_b)
501 return;
502
503 /* Set default MU configuration */
f689a7cf
PF		 504 for (i = 0; i < IMX_MU_xCR_MAX; i++)
505 imx_mu_write(priv, 0, priv->dcfg->xCR[i]);
2bb70056
OR		 506}
507
97961f78 508static void imx_mu_init_specific(struct imx_mu_priv *priv)
0a67003b
PF		 509{
510 unsigned int i;
97961f78 511 int num_chans = priv->dcfg->type & IMX_MU_V2_S4 ? IMX_MU_S4_CHANS : IMX_MU_SCU_CHANS;
0a67003b 512
97961f78 513 for (i = 0; i < num_chans; i++) {
0a67003b
PF		 514 struct imx_mu_con_priv *cp = &priv->con_priv[i];
515
516 cp->idx = i < 2 ? 0 : i - 2;
517 cp->type = i < 2 ? i : IMX_MU_TYPE_RXDB;
518 cp->chan = &priv->mbox_chans[i];
519 priv->mbox_chans[i].con_priv = cp;
520 snprintf(cp->irq_desc, sizeof(cp->irq_desc),
521 "imx_mu_chan[%i-%i]", cp->type, cp->idx);
522 }
523
97961f78
PF		 524 priv->mbox.num_chans = num_chans;
525 priv->mbox.of_xlate = imx_mu_specific_xlate;
0a67003b
PF		 526
527 /* Set default MU configuration */
f689a7cf
PF		 528 for (i = 0; i < IMX_MU_xCR_MAX; i++)
529 imx_mu_write(priv, 0, priv->dcfg->xCR[i]);
0a67003b
PF		 530}
531
2bb70056
OR		 532static int imx_mu_probe(struct platform_device *pdev)
533{
534 struct device *dev = &pdev->dev;
535 struct device_node *np = dev->of_node;
2bb70056 536 struct imx_mu_priv *priv;
c6c6bc6e 537 const struct imx_mu_dcfg *dcfg;
2bb70056 538 int ret;
97961f78 539 u32 size;
2bb70056
OR		 540
541 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
542 if (!priv)
543 return -ENOMEM;
544
545 priv->dev = dev;
546
0c40e631 547 priv->base = devm_platform_ioremap_resource(pdev, 0);
2bb70056
OR		 548 if (IS_ERR(priv->base))
549 return PTR_ERR(priv->base);
550
551 priv->irq = platform_get_irq(pdev, 0);
552 if (priv->irq < 0)
553 return priv->irq;
554
c6c6bc6e
RZ		 555 dcfg = of_device_get_match_data(dev);
556 if (!dcfg)
557 return -EINVAL;
558 priv->dcfg = dcfg;
559
97961f78
PF		 560 if (priv->dcfg->type & IMX_MU_V2_S4)
561 size = sizeof(struct imx_s4_rpc_msg_max);
562 else
563 size = sizeof(struct imx_sc_rpc_msg_max);
564
565 priv->msg = devm_kzalloc(dev, size, GFP_KERNEL);
05d06f37
DC		 566 if (!priv->msg)
567 return -ENOMEM;
97961f78 568
2bb70056
OR		 569 priv->clk = devm_clk_get(dev, NULL);
570 if (IS_ERR(priv->clk)) {
571 if (PTR_ERR(priv->clk) != -ENOENT)
572 return PTR_ERR(priv->clk);
573
574 priv->clk = NULL;
575 }
576
577 ret = clk_prepare_enable(priv->clk);
578 if (ret) {
579 dev_err(dev, "Failed to enable clock\n");
580 return ret;
581 }
582
2bb70056
OR		 583 priv->side_b = of_property_read_bool(np, "fsl,mu-side-b");
584
63b38357
PF		 585 priv->dcfg->init(priv);
586
2bb70056
OR		 587 spin_lock_init(&priv->xcr_lock);
588
589 priv->mbox.dev = dev;
590 priv->mbox.ops = &imx_mu_ops;
591 priv->mbox.chans = priv->mbox_chans;
2bb70056
OR		 592 priv->mbox.txdone_irq = true;
593
594 platform_set_drvdata(pdev, priv);
595
676f23ea 596 ret = devm_mbox_controller_register(dev, &priv->mbox);
47303f94
FE		 597 if (ret) {
598 clk_disable_unprepare(priv->clk);
676f23ea 599 return ret;
47303f94 600 }
676f23ea
AH		 601
602 pm_runtime_enable(dev);
603
604 ret = pm_runtime_get_sync(dev);
605 if (ret < 0) {
606 pm_runtime_put_noidle(dev);
607 goto disable_runtime_pm;
608 }
609
610 ret = pm_runtime_put_sync(dev);
611 if (ret < 0)
612 goto disable_runtime_pm;
613
bb2b2624
AH		 614 clk_disable_unprepare(priv->clk);
615
676f23ea
AH		 616 return 0;
617
618disable_runtime_pm:
619 pm_runtime_disable(dev);
bb2b2624 620 clk_disable_unprepare(priv->clk);
676f23ea 621 return ret;
2bb70056
OR		 622}
623
624static int imx_mu_remove(struct platform_device *pdev)
625{
626 struct imx_mu_priv *priv = platform_get_drvdata(pdev);
627
676f23ea 628 pm_runtime_disable(priv->dev);
2bb70056
OR		 629
630 return 0;
631}
632
63b38357
PF		 633static const struct imx_mu_dcfg imx_mu_cfg_imx6sx = {
634 .tx = imx_mu_generic_tx,
635 .rx = imx_mu_generic_rx,
636 .init = imx_mu_init_generic,
32f7443d
PF		 637 .xTR = 0x0,
638 .xRR = 0x10,
f689a7cf
PF		 639 .xSR = {0x20, 0x20, 0x20, 0x20},
640 .xCR = {0x24, 0x24, 0x24, 0x24},
63b38357
PF		 641};
642
643static const struct imx_mu_dcfg imx_mu_cfg_imx7ulp = {
644 .tx = imx_mu_generic_tx,
645 .rx = imx_mu_generic_rx,
646 .init = imx_mu_init_generic,
32f7443d
PF		 647 .xTR = 0x20,
648 .xRR = 0x40,
f689a7cf
PF		 649 .xSR = {0x60, 0x60, 0x60, 0x60},
650 .xCR = {0x64, 0x64, 0x64, 0x64},
63b38357
PF		 651};
652
4f0b776e
PF		 653static const struct imx_mu_dcfg imx_mu_cfg_imx8ulp = {
654 .tx = imx_mu_generic_tx,
655 .rx = imx_mu_generic_rx,
656 .init = imx_mu_init_generic,
657 .type = IMX_MU_V2,
658 .xTR = 0x200,
659 .xRR = 0x280,
660 .xSR = {0xC, 0x118, 0x124, 0x12C},
661 .xCR = {0x110, 0x114, 0x120, 0x128},
662};
663
97961f78
PF		 664static const struct imx_mu_dcfg imx_mu_cfg_imx8ulp_s4 = {
665 .tx = imx_mu_specific_tx,
666 .rx = imx_mu_specific_rx,
667 .init = imx_mu_init_specific,
668 .type = IMX_MU_V2 | IMX_MU_V2_S4,
669 .xTR = 0x200,
670 .xRR = 0x280,
671 .xSR = {0xC, 0x118, 0x124, 0x12C},
672 .xCR = {0x110, 0x114, 0x120, 0x128},
673};
674
0a67003b 675static const struct imx_mu_dcfg imx_mu_cfg_imx8_scu = {
97961f78
PF		 676 .tx = imx_mu_specific_tx,
677 .rx = imx_mu_specific_rx,
678 .init = imx_mu_init_specific,
4f0b776e
PF		 679 .xTR = 0x0,
680 .xRR = 0x10,
f689a7cf
PF		 681 .xSR = {0x20, 0x20, 0x20, 0x20},
682 .xCR = {0x24, 0x24, 0x24, 0x24},
0a67003b
PF		 683};
684
2bb70056 685static const struct of_device_id imx_mu_dt_ids[] = {
c6c6bc6e
RZ		 686 { .compatible = "fsl,imx7ulp-mu", .data = &imx_mu_cfg_imx7ulp },
687 { .compatible = "fsl,imx6sx-mu", .data = &imx_mu_cfg_imx6sx },
4f0b776e 688 { .compatible = "fsl,imx8ulp-mu", .data = &imx_mu_cfg_imx8ulp },
97961f78 689 { .compatible = "fsl,imx8ulp-mu-s4", .data = &imx_mu_cfg_imx8ulp_s4 },
0a67003b 690 { .compatible = "fsl,imx8-mu-scu", .data = &imx_mu_cfg_imx8_scu },
2bb70056
OR		 691 { },
692};
693MODULE_DEVICE_TABLE(of, imx_mu_dt_ids);
694
03b70130 695static int __maybe_unused imx_mu_suspend_noirq(struct device *dev)
ba5f9fa0
DA		 696{
697 struct imx_mu_priv *priv = dev_get_drvdata(dev);
f689a7cf 698 int i;
ba5f9fa0 699
f689a7cf
PF		 700 if (!priv->clk) {
701 for (i = 0; i < IMX_MU_xCR_MAX; i++)
702 priv->xcr[i] = imx_mu_read(priv, priv->dcfg->xCR[i]);
703 }
ba5f9fa0
DA		 704
705 return 0;
706}
707
03b70130 708static int __maybe_unused imx_mu_resume_noirq(struct device *dev)
ba5f9fa0
DA		 709{
710 struct imx_mu_priv *priv = dev_get_drvdata(dev);
f689a7cf 711 int i;
ba5f9fa0
DA		 712
713 /*
714 * ONLY restore MU when context lost, the TIE could
715 * be set during noirq resume as there is MU data
716 * communication going on, and restore the saved
717 * value will overwrite the TIE and cause MU data
718 * send failed, may lead to system freeze. This issue
719 * is observed by testing freeze mode suspend.
720 */
f689a7cf
PF		 721 if (!imx_mu_read(priv, priv->dcfg->xCR[0]) && !priv->clk) {
722 for (i = 0; i < IMX_MU_xCR_MAX; i++)
723 imx_mu_write(priv, priv->xcr[i], priv->dcfg->xCR[i]);
724 }
ba5f9fa0
DA		 725
726 return 0;
727}
728
03b70130 729static int __maybe_unused imx_mu_runtime_suspend(struct device *dev)
bb2b2624
AH		 730{
731 struct imx_mu_priv *priv = dev_get_drvdata(dev);
732
733 clk_disable_unprepare(priv->clk);
734
735 return 0;
736}
737
03b70130 738static int __maybe_unused imx_mu_runtime_resume(struct device *dev)
bb2b2624
AH		 739{
740 struct imx_mu_priv *priv = dev_get_drvdata(dev);
741 int ret;
742
743 ret = clk_prepare_enable(priv->clk);
744 if (ret)
745 dev_err(dev, "failed to enable clock\n");
746
747 return ret;
748}
749
ba5f9fa0
DA		 750static const struct dev_pm_ops imx_mu_pm_ops = {
751 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(imx_mu_suspend_noirq,
752 imx_mu_resume_noirq)
bb2b2624
AH		 753 SET_RUNTIME_PM_OPS(imx_mu_runtime_suspend,
754 imx_mu_runtime_resume, NULL)
ba5f9fa0
DA		 755};
756
2bb70056
OR		 757static struct platform_driver imx_mu_driver = {
758 .probe = imx_mu_probe,
759 .remove = imx_mu_remove,
760 .driver = {
761 .name = "imx_mu",
762 .of_match_table = imx_mu_dt_ids,
ba5f9fa0 763 .pm = &imx_mu_pm_ops,
2bb70056
OR		 764 },
765};
766module_platform_driver(imx_mu_driver);
767
768MODULE_AUTHOR("Oleksij Rempel <o.rempel@pengutronix.de>");
769MODULE_DESCRIPTION("Message Unit driver for i.MX");
770MODULE_LICENSE("GPL v2");
Linux 6.x block layer and io_uring tree(s)