[linux-2.6-block.git] / drivers / mailbox / imx-mailbox.c

// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (c) 2018 Pengutronix, Oleksij Rempel <o.rempel@pengutronix.de>
 */

#include <linux/clk.h>
#include <linux/firmware/imx/ipc.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/iopoll.h>
#include <linux/kernel.h>
#include <linux/mailbox_controller.h>
#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/pm_runtime.h>
#include <linux/slab.h>

#define IMX_MU_xSR_GIPn(x)	BIT(28 + (3 - (x)))
#define IMX_MU_xSR_RFn(x)	BIT(24 + (3 - (x)))
#define IMX_MU_xSR_TEn(x)	BIT(20 + (3 - (x)))
#define IMX_MU_xSR_BRDIP	BIT(9)

/* General Purpose Interrupt Enable */
#define IMX_MU_xCR_GIEn(x)	BIT(28 + (3 - (x)))
/* Receive Interrupt Enable */
#define IMX_MU_xCR_RIEn(x)	BIT(24 + (3 - (x)))
/* Transmit Interrupt Enable */
#define IMX_MU_xCR_TIEn(x)	BIT(20 + (3 - (x)))
/* General Purpose Interrupt Request */
#define IMX_MU_xCR_GIRn(x)	BIT(16 + (3 - (x)))

#define IMX_MU_CHANS		16
/* TX0/RX0/RXDB[0-3] */
#define IMX_MU_SCU_CHANS	6
#define IMX_MU_CHAN_NAME_SIZE	20

enum imx_mu_chan_type {
	IMX_MU_TYPE_TX,		/* Tx */
	IMX_MU_TYPE_RX,		/* Rx */
	IMX_MU_TYPE_TXDB,	/* Tx doorbell */
	IMX_MU_TYPE_RXDB,	/* Rx doorbell */
};

struct imx_sc_rpc_msg_max {
	struct imx_sc_rpc_msg hdr;
	u32 data[7];
};

struct imx_mu_con_priv {
	unsigned int		idx;
	char			irq_desc[IMX_MU_CHAN_NAME_SIZE];
	enum imx_mu_chan_type	type;
	struct mbox_chan	*chan;
	struct tasklet_struct	txdb_tasklet;
};

struct imx_mu_priv {
	struct device		*dev;
	void __iomem		*base;
	spinlock_t		xcr_lock; /* control register lock */

	struct mbox_controller	mbox;
	struct mbox_chan	mbox_chans[IMX_MU_CHANS];

	struct imx_mu_con_priv  con_priv[IMX_MU_CHANS];
	const struct imx_mu_dcfg	*dcfg;
	struct clk		*clk;
	int			irq;

	u32 xcr;

	bool			side_b;
};

struct imx_mu_dcfg {
	int (*tx)(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp, void *data);
	int (*rx)(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp);
	void (*init)(struct imx_mu_priv *priv);
	u32	xTR[4];		/* Transmit Registers */
	u32	xRR[4];		/* Receive Registers */
	u32	xSR;		/* Status Register */
	u32	xCR;		/* Control Register */
};

static struct imx_mu_priv *to_imx_mu_priv(struct mbox_controller *mbox)
{
	return container_of(mbox, struct imx_mu_priv, mbox);
}

static void imx_mu_write(struct imx_mu_priv *priv, u32 val, u32 offs)
{
	iowrite32(val, priv->base + offs);
}

static u32 imx_mu_read(struct imx_mu_priv *priv, u32 offs)
{
	return ioread32(priv->base + offs);
}

static u32 imx_mu_xcr_rmw(struct imx_mu_priv *priv, u32 set, u32 clr)
{
	unsigned long flags;
	u32 val;

	spin_lock_irqsave(&priv->xcr_lock, flags);
	val = imx_mu_read(priv, priv->dcfg->xCR);
	val &= ~clr;
	val |= set;
	imx_mu_write(priv, val, priv->dcfg->xCR);
	spin_unlock_irqrestore(&priv->xcr_lock, flags);

	return val;
}

static int imx_mu_generic_tx(struct imx_mu_priv *priv,
			     struct imx_mu_con_priv *cp,
			     void *data)
{
	u32 *arg = data;

	switch (cp->type) {
	case IMX_MU_TYPE_TX:
		imx_mu_write(priv, *arg, priv->dcfg->xTR[cp->idx]);
		imx_mu_xcr_rmw(priv, IMX_MU_xCR_TIEn(cp->idx), 0);
		break;
	case IMX_MU_TYPE_TXDB:
		imx_mu_xcr_rmw(priv, IMX_MU_xCR_GIRn(cp->idx), 0);
		tasklet_schedule(&cp->txdb_tasklet);
		break;
	default:
		dev_warn_ratelimited(priv->dev, "Send data on wrong channel type: %d\n", cp->type);
		return -EINVAL;
	}

	return 0;
}

static int imx_mu_generic_rx(struct imx_mu_priv *priv,
			     struct imx_mu_con_priv *cp)
{
	u32 dat;

	dat = imx_mu_read(priv, priv->dcfg->xRR[cp->idx]);
	mbox_chan_received_data(cp->chan, (void *)&dat);

	return 0;
}

static int imx_mu_scu_tx(struct imx_mu_priv *priv,
			 struct imx_mu_con_priv *cp,
			 void *data)
{
	struct imx_sc_rpc_msg_max *msg = data;
	u32 *arg = data;
	int i, ret;
	u32 xsr;

	switch (cp->type) {
	case IMX_MU_TYPE_TX:
		/*
		 * msg->hdr.size specifies the number of u32 words while
		 * sizeof yields bytes.
		 */

		if (msg->hdr.size > sizeof(*msg) / 4) {
			/*
			 * The real message size can be different to
			 * struct imx_sc_rpc_msg_max size
			 */
			dev_err(priv->dev, "Maximal message size (%zu bytes) exceeded on TX; got: %i bytes\n", sizeof(*msg), msg->hdr.size << 2);
			return -EINVAL;
		}

		for (i = 0; i < 4 && i < msg->hdr.size; i++)
			imx_mu_write(priv, *arg++, priv->dcfg->xTR[i % 4]);
		for (; i < msg->hdr.size; i++) {
			ret = readl_poll_timeout(priv->base + priv->dcfg->xSR,
						 xsr,
						 xsr & IMX_MU_xSR_TEn(i % 4),
						 0, 100);
			if (ret) {
				dev_err(priv->dev, "Send data index: %d timeout\n", i);
				return ret;
			}
			imx_mu_write(priv, *arg++, priv->dcfg->xTR[i % 4]);
		}

		imx_mu_xcr_rmw(priv, IMX_MU_xCR_TIEn(cp->idx), 0);
		break;
	default:
		dev_warn_ratelimited(priv->dev, "Send data on wrong channel type: %d\n", cp->type);
		return -EINVAL;
	}

	return 0;
}

static int imx_mu_scu_rx(struct imx_mu_priv *priv,
			 struct imx_mu_con_priv *cp)
{
	struct imx_sc_rpc_msg_max msg;
	u32 *data = (u32 *)&msg;
	int i, ret;
	u32 xsr;

	imx_mu_xcr_rmw(priv, 0, IMX_MU_xCR_RIEn(0));
	*data++ = imx_mu_read(priv, priv->dcfg->xRR[0]);

	if (msg.hdr.size > sizeof(msg) / 4) {
		dev_err(priv->dev, "Maximal message size (%zu bytes) exceeded on RX; got: %i bytes\n", sizeof(msg), msg.hdr.size << 2);
		return -EINVAL;
	}

	for (i = 1; i < msg.hdr.size; i++) {
		ret = readl_poll_timeout(priv->base + priv->dcfg->xSR, xsr,
					 xsr & IMX_MU_xSR_RFn(i % 4), 0, 100);
		if (ret) {
			dev_err(priv->dev, "timeout read idx %d\n", i);
			return ret;
		}
		*data++ = imx_mu_read(priv, priv->dcfg->xRR[i % 4]);
	}

	imx_mu_xcr_rmw(priv, IMX_MU_xCR_RIEn(0), 0);
	mbox_chan_received_data(cp->chan, (void *)&msg);

	return 0;
}

static void imx_mu_txdb_tasklet(unsigned long data)
{
	struct imx_mu_con_priv *cp = (struct imx_mu_con_priv *)data;

	mbox_chan_txdone(cp->chan, 0);
}

static irqreturn_t imx_mu_isr(int irq, void *p)
{
	struct mbox_chan *chan = p;
	struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox);
	struct imx_mu_con_priv *cp = chan->con_priv;
	u32 val, ctrl;

	ctrl = imx_mu_read(priv, priv->dcfg->xCR);
	val = imx_mu_read(priv, priv->dcfg->xSR);

	switch (cp->type) {
	case IMX_MU_TYPE_TX:
		val &= IMX_MU_xSR_TEn(cp->idx) &
			(ctrl & IMX_MU_xCR_TIEn(cp->idx));
		break;
	case IMX_MU_TYPE_RX:
		val &= IMX_MU_xSR_RFn(cp->idx) &
			(ctrl & IMX_MU_xCR_RIEn(cp->idx));
		break;
	case IMX_MU_TYPE_RXDB:
		val &= IMX_MU_xSR_GIPn(cp->idx) &
			(ctrl & IMX_MU_xCR_GIEn(cp->idx));
		break;
	default:
		break;
	}

	if (!val)
		return IRQ_NONE;

	if (val == IMX_MU_xSR_TEn(cp->idx)) {
		imx_mu_xcr_rmw(priv, 0, IMX_MU_xCR_TIEn(cp->idx));
		mbox_chan_txdone(chan, 0);
	} else if (val == IMX_MU_xSR_RFn(cp->idx)) {
		priv->dcfg->rx(priv, cp);
	} else if (val == IMX_MU_xSR_GIPn(cp->idx)) {
		imx_mu_write(priv, IMX_MU_xSR_GIPn(cp->idx), priv->dcfg->xSR);
		mbox_chan_received_data(chan, NULL);
	} else {
		dev_warn_ratelimited(priv->dev, "Not handled interrupt\n");
		return IRQ_NONE;
	}

	return IRQ_HANDLED;
}

static int imx_mu_send_data(struct mbox_chan *chan, void *data)
{
	struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox);
	struct imx_mu_con_priv *cp = chan->con_priv;

	return priv->dcfg->tx(priv, cp, data);
}

static int imx_mu_startup(struct mbox_chan *chan)
{
	struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox);
	struct imx_mu_con_priv *cp = chan->con_priv;
	unsigned long irq_flag = IRQF_SHARED;
	int ret;

	pm_runtime_get_sync(priv->dev);
	if (cp->type == IMX_MU_TYPE_TXDB) {
		/* Tx doorbell don't have ACK support */
		tasklet_init(&cp->txdb_tasklet, imx_mu_txdb_tasklet,
			     (unsigned long)cp);
		return 0;
	}

	/* IPC MU should be with IRQF_NO_SUSPEND set */
	if (!priv->dev->pm_domain)
		irq_flag |= IRQF_NO_SUSPEND;

	ret = request_irq(priv->irq, imx_mu_isr, irq_flag,
			  cp->irq_desc, chan);
	if (ret) {
		dev_err(priv->dev,
			"Unable to acquire IRQ %d\n", priv->irq);
		return ret;
	}

	switch (cp->type) {
	case IMX_MU_TYPE_RX:
		imx_mu_xcr_rmw(priv, IMX_MU_xCR_RIEn(cp->idx), 0);
		break;
	case IMX_MU_TYPE_RXDB:
		imx_mu_xcr_rmw(priv, IMX_MU_xCR_GIEn(cp->idx), 0);
		break;
	default:
		break;
	}

	return 0;
}

static void imx_mu_shutdown(struct mbox_chan *chan)
{
	struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox);
	struct imx_mu_con_priv *cp = chan->con_priv;

	if (cp->type == IMX_MU_TYPE_TXDB) {
		tasklet_kill(&cp->txdb_tasklet);
		pm_runtime_put_sync(priv->dev);
		return;
	}

	switch (cp->type) {
	case IMX_MU_TYPE_TX:
		imx_mu_xcr_rmw(priv, 0, IMX_MU_xCR_TIEn(cp->idx));
		break;
	case IMX_MU_TYPE_RX:
		imx_mu_xcr_rmw(priv, 0, IMX_MU_xCR_RIEn(cp->idx));
		break;
	case IMX_MU_TYPE_RXDB:
		imx_mu_xcr_rmw(priv, 0, IMX_MU_xCR_GIEn(cp->idx));
		break;
	default:
		break;
	}

	free_irq(priv->irq, chan);
	pm_runtime_put_sync(priv->dev);
}

static const struct mbox_chan_ops imx_mu_ops = {
	.send_data = imx_mu_send_data,
	.startup = imx_mu_startup,
	.shutdown = imx_mu_shutdown,
};

static struct mbox_chan *imx_mu_scu_xlate(struct mbox_controller *mbox,
					  const struct of_phandle_args *sp)
{
	u32 type, idx, chan;

	if (sp->args_count != 2) {
		dev_err(mbox->dev, "Invalid argument count %d\n", sp->args_count);
		return ERR_PTR(-EINVAL);
	}

	type = sp->args[0]; /* channel type */
	idx = sp->args[1]; /* index */

	switch (type) {
	case IMX_MU_TYPE_TX:
	case IMX_MU_TYPE_RX:
		if (idx != 0)
			dev_err(mbox->dev, "Invalid chan idx: %d\n", idx);
		chan = type;
		break;
	case IMX_MU_TYPE_RXDB:
		chan = 2 + idx;
		break;
	default:
		dev_err(mbox->dev, "Invalid chan type: %d\n", type);
		return ERR_PTR(-EINVAL);
	}

	if (chan >= mbox->num_chans) {
		dev_err(mbox->dev, "Not supported channel number: %d. (type: %d, idx: %d)\n", chan, type, idx);
		return ERR_PTR(-EINVAL);
	}

	return &mbox->chans[chan];
}

static struct mbox_chan * imx_mu_xlate(struct mbox_controller *mbox,
				       const struct of_phandle_args *sp)
{
	u32 type, idx, chan;

	if (sp->args_count != 2) {
		dev_err(mbox->dev, "Invalid argument count %d\n", sp->args_count);
		return ERR_PTR(-EINVAL);
	}

	type = sp->args[0]; /* channel type */
	idx = sp->args[1]; /* index */
	chan = type * 4 + idx;

	if (chan >= mbox->num_chans) {
		dev_err(mbox->dev, "Not supported channel number: %d. (type: %d, idx: %d)\n", chan, type, idx);
		return ERR_PTR(-EINVAL);
	}

	return &mbox->chans[chan];
}

static void imx_mu_init_generic(struct imx_mu_priv *priv)
{
	unsigned int i;

	for (i = 0; i < IMX_MU_CHANS; i++) {
		struct imx_mu_con_priv *cp = &priv->con_priv[i];

		cp->idx = i % 4;
		cp->type = i >> 2;
		cp->chan = &priv->mbox_chans[i];
		priv->mbox_chans[i].con_priv = cp;
		snprintf(cp->irq_desc, sizeof(cp->irq_desc),
			 "imx_mu_chan[%i-%i]", cp->type, cp->idx);
	}

	priv->mbox.num_chans = IMX_MU_CHANS;
	priv->mbox.of_xlate = imx_mu_xlate;

	if (priv->side_b)
		return;

	/* Set default MU configuration */
	imx_mu_write(priv, 0, priv->dcfg->xCR);
}

static void imx_mu_init_scu(struct imx_mu_priv *priv)
{
	unsigned int i;

	for (i = 0; i < IMX_MU_SCU_CHANS; i++) {
		struct imx_mu_con_priv *cp = &priv->con_priv[i];

		cp->idx = i < 2 ? 0 : i - 2;
		cp->type = i < 2 ? i : IMX_MU_TYPE_RXDB;
		cp->chan = &priv->mbox_chans[i];
		priv->mbox_chans[i].con_priv = cp;
		snprintf(cp->irq_desc, sizeof(cp->irq_desc),
			 "imx_mu_chan[%i-%i]", cp->type, cp->idx);
	}

	priv->mbox.num_chans = IMX_MU_SCU_CHANS;
	priv->mbox.of_xlate = imx_mu_scu_xlate;

	/* Set default MU configuration */
	imx_mu_write(priv, 0, priv->dcfg->xCR);
}

static int imx_mu_probe(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
	struct device_node *np = dev->of_node;
	struct imx_mu_priv *priv;
	const struct imx_mu_dcfg *dcfg;
	int ret;

	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
	if (!priv)
		return -ENOMEM;

	priv->dev = dev;

	priv->base = devm_platform_ioremap_resource(pdev, 0);
	if (IS_ERR(priv->base))
		return PTR_ERR(priv->base);

	priv->irq = platform_get_irq(pdev, 0);
	if (priv->irq < 0)
		return priv->irq;

	dcfg = of_device_get_match_data(dev);
	if (!dcfg)
		return -EINVAL;
	priv->dcfg = dcfg;

	priv->clk = devm_clk_get(dev, NULL);
	if (IS_ERR(priv->clk)) {
		if (PTR_ERR(priv->clk) != -ENOENT)
			return PTR_ERR(priv->clk);

		priv->clk = NULL;
	}

	ret = clk_prepare_enable(priv->clk);
	if (ret) {
		dev_err(dev, "Failed to enable clock\n");
		return ret;
	}

	priv->side_b = of_property_read_bool(np, "fsl,mu-side-b");

	priv->dcfg->init(priv);

	spin_lock_init(&priv->xcr_lock);

	priv->mbox.dev = dev;
	priv->mbox.ops = &imx_mu_ops;
	priv->mbox.chans = priv->mbox_chans;
	priv->mbox.txdone_irq = true;

	platform_set_drvdata(pdev, priv);

	ret = devm_mbox_controller_register(dev, &priv->mbox);
	if (ret) {
		clk_disable_unprepare(priv->clk);
		return ret;
	}

	pm_runtime_enable(dev);

	ret = pm_runtime_get_sync(dev);
	if (ret < 0) {
		pm_runtime_put_noidle(dev);
		goto disable_runtime_pm;
	}

	ret = pm_runtime_put_sync(dev);
	if (ret < 0)
		goto disable_runtime_pm;

	clk_disable_unprepare(priv->clk);

	return 0;

disable_runtime_pm:
	pm_runtime_disable(dev);
	clk_disable_unprepare(priv->clk);
	return ret;
}

static int imx_mu_remove(struct platform_device *pdev)
{
	struct imx_mu_priv *priv = platform_get_drvdata(pdev);

	pm_runtime_disable(priv->dev);

	return 0;
}

static const struct imx_mu_dcfg imx_mu_cfg_imx6sx = {
	.tx	= imx_mu_generic_tx,
	.rx	= imx_mu_generic_rx,
	.init	= imx_mu_init_generic,
	.xTR	= {0x0, 0x4, 0x8, 0xc},
	.xRR	= {0x10, 0x14, 0x18, 0x1c},
	.xSR	= 0x20,
	.xCR	= 0x24,
};

static const struct imx_mu_dcfg imx_mu_cfg_imx7ulp = {
	.tx	= imx_mu_generic_tx,
	.rx	= imx_mu_generic_rx,
	.init	= imx_mu_init_generic,
	.xTR	= {0x20, 0x24, 0x28, 0x2c},
	.xRR	= {0x40, 0x44, 0x48, 0x4c},
	.xSR	= 0x60,
	.xCR	= 0x64,
};

static const struct imx_mu_dcfg imx_mu_cfg_imx8_scu = {
	.tx	= imx_mu_scu_tx,
	.rx	= imx_mu_scu_rx,
	.init	= imx_mu_init_scu,
	.xTR	= {0x0, 0x4, 0x8, 0xc},
	.xRR	= {0x10, 0x14, 0x18, 0x1c},
	.xSR	= 0x20,
	.xCR	= 0x24,
};

static const struct of_device_id imx_mu_dt_ids[] = {
	{ .compatible = "fsl,imx7ulp-mu", .data = &imx_mu_cfg_imx7ulp },
	{ .compatible = "fsl,imx6sx-mu", .data = &imx_mu_cfg_imx6sx },
	{ .compatible = "fsl,imx8-mu-scu", .data = &imx_mu_cfg_imx8_scu },
	{ },
};
MODULE_DEVICE_TABLE(of, imx_mu_dt_ids);

static int __maybe_unused imx_mu_suspend_noirq(struct device *dev)
{
	struct imx_mu_priv *priv = dev_get_drvdata(dev);

	if (!priv->clk)
		priv->xcr = imx_mu_read(priv, priv->dcfg->xCR);

	return 0;
}

static int __maybe_unused imx_mu_resume_noirq(struct device *dev)
{
	struct imx_mu_priv *priv = dev_get_drvdata(dev);

	/*
	 * ONLY restore MU when context lost, the TIE could
	 * be set during noirq resume as there is MU data
	 * communication going on, and restore the saved
	 * value will overwrite the TIE and cause MU data
	 * send failed, may lead to system freeze. This issue
	 * is observed by testing freeze mode suspend.
	 */
	if (!imx_mu_read(priv, priv->dcfg->xCR) && !priv->clk)
		imx_mu_write(priv, priv->xcr, priv->dcfg->xCR);

	return 0;
}

static int __maybe_unused imx_mu_runtime_suspend(struct device *dev)
{
	struct imx_mu_priv *priv = dev_get_drvdata(dev);

	clk_disable_unprepare(priv->clk);

	return 0;
}

static int __maybe_unused imx_mu_runtime_resume(struct device *dev)
{
	struct imx_mu_priv *priv = dev_get_drvdata(dev);
	int ret;

	ret = clk_prepare_enable(priv->clk);
	if (ret)
		dev_err(dev, "failed to enable clock\n");

	return ret;
}

static const struct dev_pm_ops imx_mu_pm_ops = {
	SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(imx_mu_suspend_noirq,
				      imx_mu_resume_noirq)
	SET_RUNTIME_PM_OPS(imx_mu_runtime_suspend,
			   imx_mu_runtime_resume, NULL)
};

static struct platform_driver imx_mu_driver = {
	.probe		= imx_mu_probe,
	.remove		= imx_mu_remove,
	.driver = {
		.name	= "imx_mu",
		.of_match_table = imx_mu_dt_ids,
		.pm = &imx_mu_pm_ops,
	},
};
module_platform_driver(imx_mu_driver);

MODULE_AUTHOR("Oleksij Rempel <o.rempel@pengutronix.de>");
MODULE_DESCRIPTION("Message Unit driver for i.MX");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
2bb70056 OR	1	// SPDX-License-Identifier: GPL-2.0
	2	/*
	3	* Copyright (c) 2018 Pengutronix, Oleksij Rempel <o.rempel@pengutronix.de>
	4	*/
	5
	6	#include <linux/clk.h>
0a67003b	7	#include <linux/firmware/imx/ipc.h>
2bb70056 OR	8	#include <linux/interrupt.h>
2bb70056 OR	9	#include <linux/io.h>
0a67003b	10	#include <linux/iopoll.h>
2bb70056 OR	11	#include <linux/kernel.h>
	12	#include <linux/mailbox_controller.h>
	13	#include <linux/module.h>
	14	#include <linux/of_device.h>
676f23ea	15	#include <linux/pm_runtime.h>
2bb70056 OR	16	#include <linux/slab.h>
2bb70056 OR	17
2bb70056 OR	18	#define IMX_MU_xSR_GIPn(x) BIT(28 + (3 - (x)))
	19	#define IMX_MU_xSR_RFn(x) BIT(24 + (3 - (x)))
	20	#define IMX_MU_xSR_TEn(x) BIT(20 + (3 - (x)))
	21	#define IMX_MU_xSR_BRDIP BIT(9)
	22
2bb70056 OR	23	/* General Purpose Interrupt Enable */
	24	#define IMX_MU_xCR_GIEn(x) BIT(28 + (3 - (x)))
	25	/* Receive Interrupt Enable */
	26	#define IMX_MU_xCR_RIEn(x) BIT(24 + (3 - (x)))
	27	/* Transmit Interrupt Enable */
	28	#define IMX_MU_xCR_TIEn(x) BIT(20 + (3 - (x)))
	29	/* General Purpose Interrupt Request */
	30	#define IMX_MU_xCR_GIRn(x) BIT(16 + (3 - (x)))
	31
	32	#define IMX_MU_CHANS 16
0a67003b PF	33	/* TX0/RX0/RXDB[0-3] */
0a67003b PF	34	#define IMX_MU_SCU_CHANS 6
2bb70056 OR	35	#define IMX_MU_CHAN_NAME_SIZE 20
	36
	37	enum imx_mu_chan_type {
	38	IMX_MU_TYPE_TX, /* Tx */
	39	IMX_MU_TYPE_RX, /* Rx */
	40	IMX_MU_TYPE_TXDB, /* Tx doorbell */
	41	IMX_MU_TYPE_RXDB, /* Rx doorbell */
	42	};
	43
0a67003b PF	44	struct imx_sc_rpc_msg_max {
	45	struct imx_sc_rpc_msg hdr;
	46	u32 data[7];
	47	};
	48
2bb70056 OR	49	struct imx_mu_con_priv {
	50	unsigned int idx;
	51	char irq_desc[IMX_MU_CHAN_NAME_SIZE];
	52	enum imx_mu_chan_type type;
	53	struct mbox_chan *chan;
	54	struct tasklet_struct txdb_tasklet;
	55	};
	56
	57	struct imx_mu_priv {
	58	struct device *dev;
	59	void __iomem *base;
	60	spinlock_t xcr_lock; /* control register lock */
	61
	62	struct mbox_controller mbox;
	63	struct mbox_chan mbox_chans[IMX_MU_CHANS];
	64
	65	struct imx_mu_con_priv con_priv[IMX_MU_CHANS];
c6c6bc6e	66	const struct imx_mu_dcfg *dcfg;
2bb70056 OR	67	struct clk *clk;
	68	int irq;
	69
ba5f9fa0 DA	70	u32 xcr;
ba5f9fa0 DA	71
2bb70056 OR	72	bool side_b;
	73	};
	74
63b38357 PF	75	struct imx_mu_dcfg {
	76	int (tx)(struct imx_mu_priv priv, struct imx_mu_con_priv cp, void data);
	77	int (rx)(struct imx_mu_priv priv, struct imx_mu_con_priv *cp);
	78	void (init)(struct imx_mu_priv priv);
	79	u32 xTR[4]; /* Transmit Registers */
	80	u32 xRR[4]; /* Receive Registers */
	81	u32 xSR; /* Status Register */
	82	u32 xCR; /* Control Register */
c6c6bc6e RZ	83	};
c6c6bc6e RZ	84
2bb70056 OR	85	static struct imx_mu_priv to_imx_mu_priv(struct mbox_controller mbox)
	86	{
	87	return container_of(mbox, struct imx_mu_priv, mbox);
	88	}
	89
	90	static void imx_mu_write(struct imx_mu_priv *priv, u32 val, u32 offs)
	91	{
	92	iowrite32(val, priv->base + offs);
	93	}
	94
	95	static u32 imx_mu_read(struct imx_mu_priv *priv, u32 offs)
	96	{
	97	return ioread32(priv->base + offs);
	98	}
	99
	100	static u32 imx_mu_xcr_rmw(struct imx_mu_priv *priv, u32 set, u32 clr)
	101	{
	102	unsigned long flags;
	103	u32 val;
	104
	105	spin_lock_irqsave(&priv->xcr_lock, flags);
c6c6bc6e	106	val = imx_mu_read(priv, priv->dcfg->xCR);
2bb70056 OR	107	val &= ~clr;
2bb70056 OR	108	val \|= set;
c6c6bc6e	109	imx_mu_write(priv, val, priv->dcfg->xCR);
2bb70056 OR	110	spin_unlock_irqrestore(&priv->xcr_lock, flags);
	111
	112	return val;
	113	}
	114
63b38357 PF	115	static int imx_mu_generic_tx(struct imx_mu_priv *priv,
	116	struct imx_mu_con_priv *cp,
	117	void *data)
	118	{
	119	u32 *arg = data;
	120
	121	switch (cp->type) {
	122	case IMX_MU_TYPE_TX:
	123	imx_mu_write(priv, *arg, priv->dcfg->xTR[cp->idx]);
	124	imx_mu_xcr_rmw(priv, IMX_MU_xCR_TIEn(cp->idx), 0);
	125	break;
	126	case IMX_MU_TYPE_TXDB:
	127	imx_mu_xcr_rmw(priv, IMX_MU_xCR_GIRn(cp->idx), 0);
	128	tasklet_schedule(&cp->txdb_tasklet);
	129	break;
	130	default:
	131	dev_warn_ratelimited(priv->dev, "Send data on wrong channel type: %d\n", cp->type);
	132	return -EINVAL;
	133	}
	134
	135	return 0;
	136	}
	137
	138	static int imx_mu_generic_rx(struct imx_mu_priv *priv,
	139	struct imx_mu_con_priv *cp)
	140	{
	141	u32 dat;
	142
	143	dat = imx_mu_read(priv, priv->dcfg->xRR[cp->idx]);
	144	mbox_chan_received_data(cp->chan, (void *)&dat);
	145
	146	return 0;
	147	}
	148
0a67003b PF	149	static int imx_mu_scu_tx(struct imx_mu_priv *priv,
	150	struct imx_mu_con_priv *cp,
	151	void *data)
	152	{
	153	struct imx_sc_rpc_msg_max *msg = data;
	154	u32 *arg = data;
	155	int i, ret;
	156	u32 xsr;
	157
	158	switch (cp->type) {
	159	case IMX_MU_TYPE_TX:
9d8ca628 PF	160	/*
	161	* msg->hdr.size specifies the number of u32 words while
	162	* sizeof yields bytes.
	163	*/
	164
	165	if (msg->hdr.size > sizeof(*msg) / 4) {
0a67003b PF	166	/*
	167	* The real message size can be different to
	168	* struct imx_sc_rpc_msg_max size
	169	*/
9d8ca628	170	dev_err(priv->dev, "Maximal message size (%zu bytes) exceeded on TX; got: %i bytes\n", sizeof(*msg), msg->hdr.size << 2);
0a67003b PF	171	return -EINVAL;
	172	}
	173
	174	for (i = 0; i < 4 && i < msg->hdr.size; i++)
	175	imx_mu_write(priv, *arg++, priv->dcfg->xTR[i % 4]);
	176	for (; i < msg->hdr.size; i++) {
	177	ret = readl_poll_timeout(priv->base + priv->dcfg->xSR,
	178	xsr,
	179	xsr & IMX_MU_xSR_TEn(i % 4),
	180	0, 100);
	181	if (ret) {
	182	dev_err(priv->dev, "Send data index: %d timeout\n", i);
	183	return ret;
	184	}
	185	imx_mu_write(priv, *arg++, priv->dcfg->xTR[i % 4]);
	186	}
	187
	188	imx_mu_xcr_rmw(priv, IMX_MU_xCR_TIEn(cp->idx), 0);
	189	break;
	190	default:
	191	dev_warn_ratelimited(priv->dev, "Send data on wrong channel type: %d\n", cp->type);
	192	return -EINVAL;
	193	}
	194
	195	return 0;
	196	}
	197
	198	static int imx_mu_scu_rx(struct imx_mu_priv *priv,
	199	struct imx_mu_con_priv *cp)
	200	{
	201	struct imx_sc_rpc_msg_max msg;
	202	u32 data = (u32 )&msg;
	203	int i, ret;
	204	u32 xsr;
	205
	206	imx_mu_xcr_rmw(priv, 0, IMX_MU_xCR_RIEn(0));
	207	*data++ = imx_mu_read(priv, priv->dcfg->xRR[0]);
	208
9d8ca628 PF	209	if (msg.hdr.size > sizeof(msg) / 4) {
9d8ca628 PF	210	dev_err(priv->dev, "Maximal message size (%zu bytes) exceeded on RX; got: %i bytes\n", sizeof(msg), msg.hdr.size << 2);
0a67003b PF	211	return -EINVAL;
	212	}
	213
	214	for (i = 1; i < msg.hdr.size; i++) {
	215	ret = readl_poll_timeout(priv->base + priv->dcfg->xSR, xsr,
	216	xsr & IMX_MU_xSR_RFn(i % 4), 0, 100);
	217	if (ret) {
	218	dev_err(priv->dev, "timeout read idx %d\n", i);
	219	return ret;
	220	}
	221	*data++ = imx_mu_read(priv, priv->dcfg->xRR[i % 4]);
	222	}
	223
	224	imx_mu_xcr_rmw(priv, IMX_MU_xCR_RIEn(0), 0);
	225	mbox_chan_received_data(cp->chan, (void *)&msg);
	226
	227	return 0;
	228	}
	229
2bb70056 OR	230	static void imx_mu_txdb_tasklet(unsigned long data)
	231	{
	232	struct imx_mu_con_priv cp = (struct imx_mu_con_priv )data;
	233
	234	mbox_chan_txdone(cp->chan, 0);
	235	}
	236
	237	static irqreturn_t imx_mu_isr(int irq, void *p)
	238	{
	239	struct mbox_chan *chan = p;
	240	struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox);
	241	struct imx_mu_con_priv *cp = chan->con_priv;
63b38357	242	u32 val, ctrl;
2bb70056	243
c6c6bc6e RZ	244	ctrl = imx_mu_read(priv, priv->dcfg->xCR);
c6c6bc6e RZ	245	val = imx_mu_read(priv, priv->dcfg->xSR);
2bb70056 OR	246
	247	switch (cp->type) {
	248	case IMX_MU_TYPE_TX:
	249	val &= IMX_MU_xSR_TEn(cp->idx) &
	250	(ctrl & IMX_MU_xCR_TIEn(cp->idx));
	251	break;
	252	case IMX_MU_TYPE_RX:
	253	val &= IMX_MU_xSR_RFn(cp->idx) &
	254	(ctrl & IMX_MU_xCR_RIEn(cp->idx));
	255	break;
	256	case IMX_MU_TYPE_RXDB:
	257	val &= IMX_MU_xSR_GIPn(cp->idx) &
	258	(ctrl & IMX_MU_xCR_GIEn(cp->idx));
	259	break;
	260	default:
	261	break;
	262	}
	263
	264	if (!val)
	265	return IRQ_NONE;
	266
	267	if (val == IMX_MU_xSR_TEn(cp->idx)) {
	268	imx_mu_xcr_rmw(priv, 0, IMX_MU_xCR_TIEn(cp->idx));
	269	mbox_chan_txdone(chan, 0);
	270	} else if (val == IMX_MU_xSR_RFn(cp->idx)) {
63b38357	271	priv->dcfg->rx(priv, cp);
2bb70056	272	} else if (val == IMX_MU_xSR_GIPn(cp->idx)) {
c6c6bc6e	273	imx_mu_write(priv, IMX_MU_xSR_GIPn(cp->idx), priv->dcfg->xSR);
2bb70056 OR	274	mbox_chan_received_data(chan, NULL);
	275	} else {
	276	dev_warn_ratelimited(priv->dev, "Not handled interrupt\n");
	277	return IRQ_NONE;
	278	}
	279
	280	return IRQ_HANDLED;
	281	}
	282
	283	static int imx_mu_send_data(struct mbox_chan chan, void data)
	284	{
	285	struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox);
	286	struct imx_mu_con_priv *cp = chan->con_priv;
2bb70056	287
63b38357	288	return priv->dcfg->tx(priv, cp, data);
2bb70056 OR	289	}
	290
	291	static int imx_mu_startup(struct mbox_chan *chan)
	292	{
	293	struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox);
	294	struct imx_mu_con_priv *cp = chan->con_priv;
b7b2796b	295	unsigned long irq_flag = IRQF_SHARED;
2bb70056 OR	296	int ret;
2bb70056 OR	297
676f23ea	298	pm_runtime_get_sync(priv->dev);
2bb70056 OR	299	if (cp->type == IMX_MU_TYPE_TXDB) {
	300	/* Tx doorbell don't have ACK support */
	301	tasklet_init(&cp->txdb_tasklet, imx_mu_txdb_tasklet,
	302	(unsigned long)cp);
	303	return 0;
	304	}
	305
b7b2796b AH	306	/* IPC MU should be with IRQF_NO_SUSPEND set */
	307	if (!priv->dev->pm_domain)
	308	irq_flag \|= IRQF_NO_SUSPEND;
	309
	310	ret = request_irq(priv->irq, imx_mu_isr, irq_flag,
	311	cp->irq_desc, chan);
2bb70056 OR	312	if (ret) {
	313	dev_err(priv->dev,
	314	"Unable to acquire IRQ %d\n", priv->irq);
	315	return ret;
	316	}
	317
	318	switch (cp->type) {
	319	case IMX_MU_TYPE_RX:
	320	imx_mu_xcr_rmw(priv, IMX_MU_xCR_RIEn(cp->idx), 0);
	321	break;
	322	case IMX_MU_TYPE_RXDB:
	323	imx_mu_xcr_rmw(priv, IMX_MU_xCR_GIEn(cp->idx), 0);
	324	break;
	325	default:
	326	break;
	327	}
	328
	329	return 0;
	330	}
	331
	332	static void imx_mu_shutdown(struct mbox_chan *chan)
	333	{
	334	struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox);
	335	struct imx_mu_con_priv *cp = chan->con_priv;
	336
bf159d15	337	if (cp->type == IMX_MU_TYPE_TXDB) {
2bb70056	338	tasklet_kill(&cp->txdb_tasklet);
676f23ea	339	pm_runtime_put_sync(priv->dev);
bf159d15 DB	340	return;
bf159d15 DB	341	}
2bb70056	342
5f0af07e DB	343	switch (cp->type) {
	344	case IMX_MU_TYPE_TX:
	345	imx_mu_xcr_rmw(priv, 0, IMX_MU_xCR_TIEn(cp->idx));
	346	break;
	347	case IMX_MU_TYPE_RX:
	348	imx_mu_xcr_rmw(priv, 0, IMX_MU_xCR_RIEn(cp->idx));
	349	break;
	350	case IMX_MU_TYPE_RXDB:
	351	imx_mu_xcr_rmw(priv, 0, IMX_MU_xCR_GIEn(cp->idx));
	352	break;
	353	default:
	354	break;
	355	}
2bb70056 OR	356
2bb70056 OR	357	free_irq(priv->irq, chan);
676f23ea	358	pm_runtime_put_sync(priv->dev);
2bb70056 OR	359	}
	360
	361	static const struct mbox_chan_ops imx_mu_ops = {
	362	.send_data = imx_mu_send_data,
	363	.startup = imx_mu_startup,
	364	.shutdown = imx_mu_shutdown,
	365	};
	366
0a67003b PF	367	static struct mbox_chan imx_mu_scu_xlate(struct mbox_controller mbox,
	368	const struct of_phandle_args *sp)
	369	{
	370	u32 type, idx, chan;
	371
	372	if (sp->args_count != 2) {
	373	dev_err(mbox->dev, "Invalid argument count %d\n", sp->args_count);
	374	return ERR_PTR(-EINVAL);
	375	}
	376
	377	type = sp->args[0]; /* channel type */
	378	idx = sp->args[1]; /* index */
	379
	380	switch (type) {
	381	case IMX_MU_TYPE_TX:
	382	case IMX_MU_TYPE_RX:
	383	if (idx != 0)
	384	dev_err(mbox->dev, "Invalid chan idx: %d\n", idx);
	385	chan = type;
	386	break;
	387	case IMX_MU_TYPE_RXDB:
	388	chan = 2 + idx;
	389	break;
	390	default:
	391	dev_err(mbox->dev, "Invalid chan type: %d\n", type);
1b3a347b	392	return ERR_PTR(-EINVAL);
0a67003b PF	393	}
	394
	395	if (chan >= mbox->num_chans) {
	396	dev_err(mbox->dev, "Not supported channel number: %d. (type: %d, idx: %d)\n", chan, type, idx);
	397	return ERR_PTR(-EINVAL);
	398	}
	399
	400	return &mbox->chans[chan];
	401	}
	402
2bb70056 OR	403	static struct mbox_chan * imx_mu_xlate(struct mbox_controller *mbox,
	404	const struct of_phandle_args *sp)
	405	{
	406	u32 type, idx, chan;
	407
	408	if (sp->args_count != 2) {
	409	dev_err(mbox->dev, "Invalid argument count %d\n", sp->args_count);
	410	return ERR_PTR(-EINVAL);
	411	}
	412
	413	type = sp->args[0]; /* channel type */
	414	idx = sp->args[1]; /* index */
	415	chan = type * 4 + idx;
	416
	417	if (chan >= mbox->num_chans) {
	418	dev_err(mbox->dev, "Not supported channel number: %d. (type: %d, idx: %d)\n", chan, type, idx);
	419	return ERR_PTR(-EINVAL);
	420	}
	421
	422	return &mbox->chans[chan];
	423	}
	424
	425	static void imx_mu_init_generic(struct imx_mu_priv *priv)
	426	{
63b38357 PF	427	unsigned int i;
	428
	429	for (i = 0; i < IMX_MU_CHANS; i++) {
	430	struct imx_mu_con_priv *cp = &priv->con_priv[i];
	431
	432	cp->idx = i % 4;
	433	cp->type = i >> 2;
	434	cp->chan = &priv->mbox_chans[i];
	435	priv->mbox_chans[i].con_priv = cp;
	436	snprintf(cp->irq_desc, sizeof(cp->irq_desc),
	437	"imx_mu_chan[%i-%i]", cp->type, cp->idx);
	438	}
	439
	440	priv->mbox.num_chans = IMX_MU_CHANS;
	441	priv->mbox.of_xlate = imx_mu_xlate;
	442
2bb70056 OR	443	if (priv->side_b)
	444	return;
	445
	446	/* Set default MU configuration */
c6c6bc6e	447	imx_mu_write(priv, 0, priv->dcfg->xCR);
2bb70056 OR	448	}
2bb70056 OR	449
0a67003b PF	450	static void imx_mu_init_scu(struct imx_mu_priv *priv)
	451	{
	452	unsigned int i;
	453
	454	for (i = 0; i < IMX_MU_SCU_CHANS; i++) {
	455	struct imx_mu_con_priv *cp = &priv->con_priv[i];
	456
	457	cp->idx = i < 2 ? 0 : i - 2;
	458	cp->type = i < 2 ? i : IMX_MU_TYPE_RXDB;
	459	cp->chan = &priv->mbox_chans[i];
	460	priv->mbox_chans[i].con_priv = cp;
	461	snprintf(cp->irq_desc, sizeof(cp->irq_desc),
	462	"imx_mu_chan[%i-%i]", cp->type, cp->idx);
	463	}
	464
	465	priv->mbox.num_chans = IMX_MU_SCU_CHANS;
	466	priv->mbox.of_xlate = imx_mu_scu_xlate;
	467
	468	/* Set default MU configuration */
	469	imx_mu_write(priv, 0, priv->dcfg->xCR);
	470	}
	471
2bb70056 OR	472	static int imx_mu_probe(struct platform_device *pdev)
	473	{
	474	struct device *dev = &pdev->dev;
	475	struct device_node *np = dev->of_node;
2bb70056	476	struct imx_mu_priv *priv;
c6c6bc6e	477	const struct imx_mu_dcfg *dcfg;
2bb70056 OR	478	int ret;
	479
	480	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
	481	if (!priv)
	482	return -ENOMEM;
	483
	484	priv->dev = dev;
	485
0c40e631	486	priv->base = devm_platform_ioremap_resource(pdev, 0);
2bb70056 OR	487	if (IS_ERR(priv->base))
	488	return PTR_ERR(priv->base);
	489
	490	priv->irq = platform_get_irq(pdev, 0);
	491	if (priv->irq < 0)
	492	return priv->irq;
	493
c6c6bc6e RZ	494	dcfg = of_device_get_match_data(dev);
	495	if (!dcfg)
	496	return -EINVAL;
	497	priv->dcfg = dcfg;
	498
2bb70056 OR	499	priv->clk = devm_clk_get(dev, NULL);
	500	if (IS_ERR(priv->clk)) {
	501	if (PTR_ERR(priv->clk) != -ENOENT)
	502	return PTR_ERR(priv->clk);
	503
	504	priv->clk = NULL;
	505	}
	506
	507	ret = clk_prepare_enable(priv->clk);
	508	if (ret) {
	509	dev_err(dev, "Failed to enable clock\n");
	510	return ret;
	511	}
	512
2bb70056 OR	513	priv->side_b = of_property_read_bool(np, "fsl,mu-side-b");
2bb70056 OR	514
63b38357 PF	515	priv->dcfg->init(priv);
63b38357 PF	516
2bb70056 OR	517	spin_lock_init(&priv->xcr_lock);
	518
	519	priv->mbox.dev = dev;
	520	priv->mbox.ops = &imx_mu_ops;
	521	priv->mbox.chans = priv->mbox_chans;
2bb70056 OR	522	priv->mbox.txdone_irq = true;
	523
	524	platform_set_drvdata(pdev, priv);
	525
676f23ea	526	ret = devm_mbox_controller_register(dev, &priv->mbox);
47303f94 FE	527	if (ret) {
47303f94 FE	528	clk_disable_unprepare(priv->clk);
676f23ea	529	return ret;
47303f94	530	}
676f23ea AH	531
	532	pm_runtime_enable(dev);
	533
	534	ret = pm_runtime_get_sync(dev);
	535	if (ret < 0) {
	536	pm_runtime_put_noidle(dev);
	537	goto disable_runtime_pm;
	538	}
	539
	540	ret = pm_runtime_put_sync(dev);
	541	if (ret < 0)
	542	goto disable_runtime_pm;
	543
bb2b2624 AH	544	clk_disable_unprepare(priv->clk);
bb2b2624 AH	545
676f23ea AH	546	return 0;
	547
	548	disable_runtime_pm:
	549	pm_runtime_disable(dev);
bb2b2624	550	clk_disable_unprepare(priv->clk);
676f23ea	551	return ret;
2bb70056 OR	552	}
	553
	554	static int imx_mu_remove(struct platform_device *pdev)
	555	{
	556	struct imx_mu_priv *priv = platform_get_drvdata(pdev);
	557
676f23ea	558	pm_runtime_disable(priv->dev);
2bb70056 OR	559
	560	return 0;
	561	}
	562
63b38357 PF	563	static const struct imx_mu_dcfg imx_mu_cfg_imx6sx = {
	564	.tx = imx_mu_generic_tx,
	565	.rx = imx_mu_generic_rx,
	566	.init = imx_mu_init_generic,
	567	.xTR = {0x0, 0x4, 0x8, 0xc},
	568	.xRR = {0x10, 0x14, 0x18, 0x1c},
	569	.xSR = 0x20,
	570	.xCR = 0x24,
	571	};
	572
	573	static const struct imx_mu_dcfg imx_mu_cfg_imx7ulp = {
	574	.tx = imx_mu_generic_tx,
	575	.rx = imx_mu_generic_rx,
	576	.init = imx_mu_init_generic,
	577	.xTR = {0x20, 0x24, 0x28, 0x2c},
	578	.xRR = {0x40, 0x44, 0x48, 0x4c},
	579	.xSR = 0x60,
	580	.xCR = 0x64,
	581	};
	582
0a67003b PF	583	static const struct imx_mu_dcfg imx_mu_cfg_imx8_scu = {
	584	.tx = imx_mu_scu_tx,
	585	.rx = imx_mu_scu_rx,
	586	.init = imx_mu_init_scu,
	587	.xTR = {0x0, 0x4, 0x8, 0xc},
	588	.xRR = {0x10, 0x14, 0x18, 0x1c},
	589	.xSR = 0x20,
	590	.xCR = 0x24,
	591	};
	592
2bb70056	593	static const struct of_device_id imx_mu_dt_ids[] = {
c6c6bc6e RZ	594	{ .compatible = "fsl,imx7ulp-mu", .data = &imx_mu_cfg_imx7ulp },
c6c6bc6e RZ	595	{ .compatible = "fsl,imx6sx-mu", .data = &imx_mu_cfg_imx6sx },
0a67003b	596	{ .compatible = "fsl,imx8-mu-scu", .data = &imx_mu_cfg_imx8_scu },
2bb70056 OR	597	{ },
	598	};
	599	MODULE_DEVICE_TABLE(of, imx_mu_dt_ids);
	600
03b70130	601	static int __maybe_unused imx_mu_suspend_noirq(struct device *dev)
ba5f9fa0 DA	602	{
	603	struct imx_mu_priv *priv = dev_get_drvdata(dev);
	604
bb2b2624 AH	605	if (!priv->clk)
bb2b2624 AH	606	priv->xcr = imx_mu_read(priv, priv->dcfg->xCR);
ba5f9fa0 DA	607
	608	return 0;
	609	}
	610
03b70130	611	static int __maybe_unused imx_mu_resume_noirq(struct device *dev)
ba5f9fa0 DA	612	{
	613	struct imx_mu_priv *priv = dev_get_drvdata(dev);
	614
	615	/*
	616	* ONLY restore MU when context lost, the TIE could
	617	* be set during noirq resume as there is MU data
	618	* communication going on, and restore the saved
	619	* value will overwrite the TIE and cause MU data
	620	* send failed, may lead to system freeze. This issue
	621	* is observed by testing freeze mode suspend.
	622	*/
bb2b2624	623	if (!imx_mu_read(priv, priv->dcfg->xCR) && !priv->clk)
ba5f9fa0 DA	624	imx_mu_write(priv, priv->xcr, priv->dcfg->xCR);
	625
	626	return 0;
	627	}
	628
03b70130	629	static int __maybe_unused imx_mu_runtime_suspend(struct device *dev)
bb2b2624 AH	630	{
	631	struct imx_mu_priv *priv = dev_get_drvdata(dev);
	632
	633	clk_disable_unprepare(priv->clk);
	634
	635	return 0;
	636	}
	637
03b70130	638	static int __maybe_unused imx_mu_runtime_resume(struct device *dev)
bb2b2624 AH	639	{
	640	struct imx_mu_priv *priv = dev_get_drvdata(dev);
	641	int ret;
	642
	643	ret = clk_prepare_enable(priv->clk);
	644	if (ret)
	645	dev_err(dev, "failed to enable clock\n");
	646
	647	return ret;
	648	}
	649
ba5f9fa0 DA	650	static const struct dev_pm_ops imx_mu_pm_ops = {
	651	SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(imx_mu_suspend_noirq,
	652	imx_mu_resume_noirq)
bb2b2624 AH	653	SET_RUNTIME_PM_OPS(imx_mu_runtime_suspend,
bb2b2624 AH	654	imx_mu_runtime_resume, NULL)
ba5f9fa0 DA	655	};
ba5f9fa0 DA	656
2bb70056 OR	657	static struct platform_driver imx_mu_driver = {
	658	.probe = imx_mu_probe,
	659	.remove = imx_mu_remove,
	660	.driver = {
	661	.name = "imx_mu",
	662	.of_match_table = imx_mu_dt_ids,
ba5f9fa0	663	.pm = &imx_mu_pm_ops,
2bb70056 OR	664	},
	665	};
	666	module_platform_driver(imx_mu_driver);
	667
	668	MODULE_AUTHOR("Oleksij Rempel <o.rempel@pengutronix.de>");
	669	MODULE_DESCRIPTION("Message Unit driver for i.MX");
	670	MODULE_LICENSE("GPL v2");