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2bb70056 OR |
1 | // SPDX-License-Identifier: GPL-2.0 |
2 | /* | |
3 | * Copyright (c) 2018 Pengutronix, Oleksij Rempel <o.rempel@pengutronix.de> | |
4 | */ | |
5 | ||
6 | #include <linux/clk.h> | |
0a67003b | 7 | #include <linux/firmware/imx/ipc.h> |
2bb70056 OR |
8 | #include <linux/interrupt.h> |
9 | #include <linux/io.h> | |
0a67003b | 10 | #include <linux/iopoll.h> |
2bb70056 OR |
11 | #include <linux/kernel.h> |
12 | #include <linux/mailbox_controller.h> | |
13 | #include <linux/module.h> | |
14 | #include <linux/of_device.h> | |
676f23ea | 15 | #include <linux/pm_runtime.h> |
2bb70056 OR |
16 | #include <linux/slab.h> |
17 | ||
2bb70056 | 18 | #define IMX_MU_CHANS 16 |
0a67003b PF |
19 | /* TX0/RX0/RXDB[0-3] */ |
20 | #define IMX_MU_SCU_CHANS 6 | |
2bb70056 OR |
21 | #define IMX_MU_CHAN_NAME_SIZE 20 |
22 | ||
23 | enum imx_mu_chan_type { | |
24 | IMX_MU_TYPE_TX, /* Tx */ | |
25 | IMX_MU_TYPE_RX, /* Rx */ | |
26 | IMX_MU_TYPE_TXDB, /* Tx doorbell */ | |
27 | IMX_MU_TYPE_RXDB, /* Rx doorbell */ | |
28 | }; | |
29 | ||
f689a7cf | 30 | enum imx_mu_xcr { |
4f0b776e | 31 | IMX_MU_GIER, |
f689a7cf PF |
32 | IMX_MU_GCR, |
33 | IMX_MU_TCR, | |
34 | IMX_MU_RCR, | |
35 | IMX_MU_xCR_MAX, | |
36 | }; | |
37 | ||
38 | enum imx_mu_xsr { | |
39 | IMX_MU_SR, | |
40 | IMX_MU_GSR, | |
41 | IMX_MU_TSR, | |
42 | IMX_MU_RSR, | |
43 | }; | |
44 | ||
0a67003b PF |
45 | struct imx_sc_rpc_msg_max { |
46 | struct imx_sc_rpc_msg hdr; | |
47 | u32 data[7]; | |
48 | }; | |
49 | ||
2bb70056 OR |
50 | struct imx_mu_con_priv { |
51 | unsigned int idx; | |
52 | char irq_desc[IMX_MU_CHAN_NAME_SIZE]; | |
53 | enum imx_mu_chan_type type; | |
54 | struct mbox_chan *chan; | |
55 | struct tasklet_struct txdb_tasklet; | |
56 | }; | |
57 | ||
58 | struct imx_mu_priv { | |
59 | struct device *dev; | |
60 | void __iomem *base; | |
61 | spinlock_t xcr_lock; /* control register lock */ | |
62 | ||
63 | struct mbox_controller mbox; | |
64 | struct mbox_chan mbox_chans[IMX_MU_CHANS]; | |
65 | ||
66 | struct imx_mu_con_priv con_priv[IMX_MU_CHANS]; | |
c6c6bc6e | 67 | const struct imx_mu_dcfg *dcfg; |
2bb70056 OR |
68 | struct clk *clk; |
69 | int irq; | |
70 | ||
f689a7cf | 71 | u32 xcr[4]; |
ba5f9fa0 | 72 | |
2bb70056 OR |
73 | bool side_b; |
74 | }; | |
75 | ||
4f0b776e PF |
76 | enum imx_mu_type { |
77 | IMX_MU_V1, | |
78 | IMX_MU_V2, | |
79 | }; | |
80 | ||
63b38357 PF |
81 | struct imx_mu_dcfg { |
82 | int (*tx)(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp, void *data); | |
83 | int (*rx)(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp); | |
84 | void (*init)(struct imx_mu_priv *priv); | |
4f0b776e | 85 | enum imx_mu_type type; |
32f7443d PF |
86 | u32 xTR; /* Transmit Register0 */ |
87 | u32 xRR; /* Receive Register0 */ | |
f689a7cf PF |
88 | u32 xSR[4]; /* Status Registers */ |
89 | u32 xCR[4]; /* Control Registers */ | |
c6c6bc6e RZ |
90 | }; |
91 | ||
4f0b776e PF |
92 | #define IMX_MU_xSR_GIPn(type, x) (type == IMX_MU_V2 ? BIT(x) : BIT(28 + (3 - (x)))) |
93 | #define IMX_MU_xSR_RFn(type, x) (type == IMX_MU_V2 ? BIT(x) : BIT(24 + (3 - (x)))) | |
94 | #define IMX_MU_xSR_TEn(type, x) (type == IMX_MU_V2 ? BIT(x) : BIT(20 + (3 - (x)))) | |
95 | ||
96 | /* General Purpose Interrupt Enable */ | |
97 | #define IMX_MU_xCR_GIEn(type, x) (type == IMX_MU_V2 ? BIT(x) : BIT(28 + (3 - (x)))) | |
98 | /* Receive Interrupt Enable */ | |
99 | #define IMX_MU_xCR_RIEn(type, x) (type == IMX_MU_V2 ? BIT(x) : BIT(24 + (3 - (x)))) | |
100 | /* Transmit Interrupt Enable */ | |
101 | #define IMX_MU_xCR_TIEn(type, x) (type == IMX_MU_V2 ? BIT(x) : BIT(20 + (3 - (x)))) | |
102 | /* General Purpose Interrupt Request */ | |
103 | #define IMX_MU_xCR_GIRn(type, x) (type == IMX_MU_V2 ? BIT(x) : BIT(16 + (3 - (x)))) | |
104 | ||
105 | ||
2bb70056 OR |
106 | static struct imx_mu_priv *to_imx_mu_priv(struct mbox_controller *mbox) |
107 | { | |
108 | return container_of(mbox, struct imx_mu_priv, mbox); | |
109 | } | |
110 | ||
111 | static void imx_mu_write(struct imx_mu_priv *priv, u32 val, u32 offs) | |
112 | { | |
113 | iowrite32(val, priv->base + offs); | |
114 | } | |
115 | ||
116 | static u32 imx_mu_read(struct imx_mu_priv *priv, u32 offs) | |
117 | { | |
118 | return ioread32(priv->base + offs); | |
119 | } | |
120 | ||
f689a7cf | 121 | static u32 imx_mu_xcr_rmw(struct imx_mu_priv *priv, enum imx_mu_xcr type, u32 set, u32 clr) |
2bb70056 OR |
122 | { |
123 | unsigned long flags; | |
124 | u32 val; | |
125 | ||
126 | spin_lock_irqsave(&priv->xcr_lock, flags); | |
f689a7cf | 127 | val = imx_mu_read(priv, priv->dcfg->xCR[type]); |
2bb70056 OR |
128 | val &= ~clr; |
129 | val |= set; | |
f689a7cf | 130 | imx_mu_write(priv, val, priv->dcfg->xCR[type]); |
2bb70056 OR |
131 | spin_unlock_irqrestore(&priv->xcr_lock, flags); |
132 | ||
133 | return val; | |
134 | } | |
135 | ||
63b38357 PF |
136 | static int imx_mu_generic_tx(struct imx_mu_priv *priv, |
137 | struct imx_mu_con_priv *cp, | |
138 | void *data) | |
139 | { | |
140 | u32 *arg = data; | |
141 | ||
142 | switch (cp->type) { | |
143 | case IMX_MU_TYPE_TX: | |
32f7443d | 144 | imx_mu_write(priv, *arg, priv->dcfg->xTR + cp->idx * 4); |
4f0b776e | 145 | imx_mu_xcr_rmw(priv, IMX_MU_TCR, IMX_MU_xCR_TIEn(priv->dcfg->type, cp->idx), 0); |
63b38357 PF |
146 | break; |
147 | case IMX_MU_TYPE_TXDB: | |
4f0b776e | 148 | imx_mu_xcr_rmw(priv, IMX_MU_GCR, IMX_MU_xCR_GIRn(priv->dcfg->type, cp->idx), 0); |
63b38357 PF |
149 | tasklet_schedule(&cp->txdb_tasklet); |
150 | break; | |
151 | default: | |
152 | dev_warn_ratelimited(priv->dev, "Send data on wrong channel type: %d\n", cp->type); | |
153 | return -EINVAL; | |
154 | } | |
155 | ||
156 | return 0; | |
157 | } | |
158 | ||
159 | static int imx_mu_generic_rx(struct imx_mu_priv *priv, | |
160 | struct imx_mu_con_priv *cp) | |
161 | { | |
162 | u32 dat; | |
163 | ||
32f7443d | 164 | dat = imx_mu_read(priv, priv->dcfg->xRR + (cp->idx) * 4); |
63b38357 PF |
165 | mbox_chan_received_data(cp->chan, (void *)&dat); |
166 | ||
167 | return 0; | |
168 | } | |
169 | ||
0a67003b PF |
170 | static int imx_mu_scu_tx(struct imx_mu_priv *priv, |
171 | struct imx_mu_con_priv *cp, | |
172 | void *data) | |
173 | { | |
174 | struct imx_sc_rpc_msg_max *msg = data; | |
175 | u32 *arg = data; | |
176 | int i, ret; | |
177 | u32 xsr; | |
178 | ||
179 | switch (cp->type) { | |
180 | case IMX_MU_TYPE_TX: | |
9d8ca628 PF |
181 | /* |
182 | * msg->hdr.size specifies the number of u32 words while | |
183 | * sizeof yields bytes. | |
184 | */ | |
185 | ||
186 | if (msg->hdr.size > sizeof(*msg) / 4) { | |
0a67003b PF |
187 | /* |
188 | * The real message size can be different to | |
189 | * struct imx_sc_rpc_msg_max size | |
190 | */ | |
9d8ca628 | 191 | dev_err(priv->dev, "Maximal message size (%zu bytes) exceeded on TX; got: %i bytes\n", sizeof(*msg), msg->hdr.size << 2); |
0a67003b PF |
192 | return -EINVAL; |
193 | } | |
194 | ||
195 | for (i = 0; i < 4 && i < msg->hdr.size; i++) | |
32f7443d | 196 | imx_mu_write(priv, *arg++, priv->dcfg->xTR + (i % 4) * 4); |
0a67003b | 197 | for (; i < msg->hdr.size; i++) { |
f689a7cf | 198 | ret = readl_poll_timeout(priv->base + priv->dcfg->xSR[IMX_MU_TSR], |
0a67003b | 199 | xsr, |
4f0b776e | 200 | xsr & IMX_MU_xSR_TEn(priv->dcfg->type, i % 4), |
0a67003b PF |
201 | 0, 100); |
202 | if (ret) { | |
203 | dev_err(priv->dev, "Send data index: %d timeout\n", i); | |
204 | return ret; | |
205 | } | |
32f7443d | 206 | imx_mu_write(priv, *arg++, priv->dcfg->xTR + (i % 4) * 4); |
0a67003b PF |
207 | } |
208 | ||
4f0b776e | 209 | imx_mu_xcr_rmw(priv, IMX_MU_TCR, IMX_MU_xCR_TIEn(priv->dcfg->type, cp->idx), 0); |
0a67003b PF |
210 | break; |
211 | default: | |
212 | dev_warn_ratelimited(priv->dev, "Send data on wrong channel type: %d\n", cp->type); | |
213 | return -EINVAL; | |
214 | } | |
215 | ||
216 | return 0; | |
217 | } | |
218 | ||
219 | static int imx_mu_scu_rx(struct imx_mu_priv *priv, | |
220 | struct imx_mu_con_priv *cp) | |
221 | { | |
222 | struct imx_sc_rpc_msg_max msg; | |
223 | u32 *data = (u32 *)&msg; | |
224 | int i, ret; | |
225 | u32 xsr; | |
226 | ||
4f0b776e | 227 | imx_mu_xcr_rmw(priv, IMX_MU_RCR, 0, IMX_MU_xCR_RIEn(priv->dcfg->type, 0)); |
32f7443d | 228 | *data++ = imx_mu_read(priv, priv->dcfg->xRR); |
0a67003b | 229 | |
9d8ca628 PF |
230 | if (msg.hdr.size > sizeof(msg) / 4) { |
231 | dev_err(priv->dev, "Maximal message size (%zu bytes) exceeded on RX; got: %i bytes\n", sizeof(msg), msg.hdr.size << 2); | |
0a67003b PF |
232 | return -EINVAL; |
233 | } | |
234 | ||
235 | for (i = 1; i < msg.hdr.size; i++) { | |
f689a7cf | 236 | ret = readl_poll_timeout(priv->base + priv->dcfg->xSR[IMX_MU_RSR], xsr, |
4f0b776e | 237 | xsr & IMX_MU_xSR_RFn(priv->dcfg->type, i % 4), 0, 100); |
0a67003b PF |
238 | if (ret) { |
239 | dev_err(priv->dev, "timeout read idx %d\n", i); | |
240 | return ret; | |
241 | } | |
32f7443d | 242 | *data++ = imx_mu_read(priv, priv->dcfg->xRR + (i % 4) * 4); |
0a67003b PF |
243 | } |
244 | ||
4f0b776e | 245 | imx_mu_xcr_rmw(priv, IMX_MU_RCR, IMX_MU_xCR_RIEn(priv->dcfg->type, 0), 0); |
0a67003b PF |
246 | mbox_chan_received_data(cp->chan, (void *)&msg); |
247 | ||
248 | return 0; | |
249 | } | |
250 | ||
2bb70056 OR |
251 | static void imx_mu_txdb_tasklet(unsigned long data) |
252 | { | |
253 | struct imx_mu_con_priv *cp = (struct imx_mu_con_priv *)data; | |
254 | ||
255 | mbox_chan_txdone(cp->chan, 0); | |
256 | } | |
257 | ||
258 | static irqreturn_t imx_mu_isr(int irq, void *p) | |
259 | { | |
260 | struct mbox_chan *chan = p; | |
261 | struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox); | |
262 | struct imx_mu_con_priv *cp = chan->con_priv; | |
63b38357 | 263 | u32 val, ctrl; |
2bb70056 | 264 | |
2bb70056 OR |
265 | switch (cp->type) { |
266 | case IMX_MU_TYPE_TX: | |
f689a7cf PF |
267 | ctrl = imx_mu_read(priv, priv->dcfg->xCR[IMX_MU_TCR]); |
268 | val = imx_mu_read(priv, priv->dcfg->xSR[IMX_MU_TSR]); | |
4f0b776e PF |
269 | val &= IMX_MU_xSR_TEn(priv->dcfg->type, cp->idx) & |
270 | (ctrl & IMX_MU_xCR_TIEn(priv->dcfg->type, cp->idx)); | |
2bb70056 OR |
271 | break; |
272 | case IMX_MU_TYPE_RX: | |
f689a7cf PF |
273 | ctrl = imx_mu_read(priv, priv->dcfg->xCR[IMX_MU_RCR]); |
274 | val = imx_mu_read(priv, priv->dcfg->xSR[IMX_MU_RSR]); | |
4f0b776e PF |
275 | val &= IMX_MU_xSR_RFn(priv->dcfg->type, cp->idx) & |
276 | (ctrl & IMX_MU_xCR_RIEn(priv->dcfg->type, cp->idx)); | |
2bb70056 OR |
277 | break; |
278 | case IMX_MU_TYPE_RXDB: | |
4f0b776e | 279 | ctrl = imx_mu_read(priv, priv->dcfg->xCR[IMX_MU_GIER]); |
f689a7cf | 280 | val = imx_mu_read(priv, priv->dcfg->xSR[IMX_MU_GSR]); |
4f0b776e PF |
281 | val &= IMX_MU_xSR_GIPn(priv->dcfg->type, cp->idx) & |
282 | (ctrl & IMX_MU_xCR_GIEn(priv->dcfg->type, cp->idx)); | |
2bb70056 OR |
283 | break; |
284 | default: | |
e80a7e7e NC |
285 | dev_warn_ratelimited(priv->dev, "Unhandled channel type %d\n", |
286 | cp->type); | |
287 | return IRQ_NONE; | |
2bb70056 OR |
288 | } |
289 | ||
290 | if (!val) | |
291 | return IRQ_NONE; | |
292 | ||
4f0b776e PF |
293 | if ((val == IMX_MU_xSR_TEn(priv->dcfg->type, cp->idx)) && |
294 | (cp->type == IMX_MU_TYPE_TX)) { | |
295 | imx_mu_xcr_rmw(priv, IMX_MU_TCR, 0, IMX_MU_xCR_TIEn(priv->dcfg->type, cp->idx)); | |
2bb70056 | 296 | mbox_chan_txdone(chan, 0); |
4f0b776e PF |
297 | } else if ((val == IMX_MU_xSR_RFn(priv->dcfg->type, cp->idx)) && |
298 | (cp->type == IMX_MU_TYPE_RX)) { | |
63b38357 | 299 | priv->dcfg->rx(priv, cp); |
4f0b776e PF |
300 | } else if ((val == IMX_MU_xSR_GIPn(priv->dcfg->type, cp->idx)) && |
301 | (cp->type == IMX_MU_TYPE_RXDB)) { | |
302 | imx_mu_write(priv, IMX_MU_xSR_GIPn(priv->dcfg->type, cp->idx), | |
303 | priv->dcfg->xSR[IMX_MU_GSR]); | |
2bb70056 OR |
304 | mbox_chan_received_data(chan, NULL); |
305 | } else { | |
306 | dev_warn_ratelimited(priv->dev, "Not handled interrupt\n"); | |
307 | return IRQ_NONE; | |
308 | } | |
309 | ||
310 | return IRQ_HANDLED; | |
311 | } | |
312 | ||
313 | static int imx_mu_send_data(struct mbox_chan *chan, void *data) | |
314 | { | |
315 | struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox); | |
316 | struct imx_mu_con_priv *cp = chan->con_priv; | |
2bb70056 | 317 | |
63b38357 | 318 | return priv->dcfg->tx(priv, cp, data); |
2bb70056 OR |
319 | } |
320 | ||
321 | static int imx_mu_startup(struct mbox_chan *chan) | |
322 | { | |
323 | struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox); | |
324 | struct imx_mu_con_priv *cp = chan->con_priv; | |
b7b2796b | 325 | unsigned long irq_flag = IRQF_SHARED; |
2bb70056 OR |
326 | int ret; |
327 | ||
676f23ea | 328 | pm_runtime_get_sync(priv->dev); |
2bb70056 OR |
329 | if (cp->type == IMX_MU_TYPE_TXDB) { |
330 | /* Tx doorbell don't have ACK support */ | |
331 | tasklet_init(&cp->txdb_tasklet, imx_mu_txdb_tasklet, | |
332 | (unsigned long)cp); | |
333 | return 0; | |
334 | } | |
335 | ||
b7b2796b AH |
336 | /* IPC MU should be with IRQF_NO_SUSPEND set */ |
337 | if (!priv->dev->pm_domain) | |
338 | irq_flag |= IRQF_NO_SUSPEND; | |
339 | ||
340 | ret = request_irq(priv->irq, imx_mu_isr, irq_flag, | |
341 | cp->irq_desc, chan); | |
2bb70056 OR |
342 | if (ret) { |
343 | dev_err(priv->dev, | |
344 | "Unable to acquire IRQ %d\n", priv->irq); | |
345 | return ret; | |
346 | } | |
347 | ||
348 | switch (cp->type) { | |
349 | case IMX_MU_TYPE_RX: | |
4f0b776e | 350 | imx_mu_xcr_rmw(priv, IMX_MU_RCR, IMX_MU_xCR_RIEn(priv->dcfg->type, cp->idx), 0); |
2bb70056 OR |
351 | break; |
352 | case IMX_MU_TYPE_RXDB: | |
4f0b776e | 353 | imx_mu_xcr_rmw(priv, IMX_MU_GIER, IMX_MU_xCR_GIEn(priv->dcfg->type, cp->idx), 0); |
2bb70056 OR |
354 | break; |
355 | default: | |
356 | break; | |
357 | } | |
358 | ||
359 | return 0; | |
360 | } | |
361 | ||
362 | static void imx_mu_shutdown(struct mbox_chan *chan) | |
363 | { | |
364 | struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox); | |
365 | struct imx_mu_con_priv *cp = chan->con_priv; | |
366 | ||
bf159d15 | 367 | if (cp->type == IMX_MU_TYPE_TXDB) { |
2bb70056 | 368 | tasklet_kill(&cp->txdb_tasklet); |
676f23ea | 369 | pm_runtime_put_sync(priv->dev); |
bf159d15 DB |
370 | return; |
371 | } | |
2bb70056 | 372 | |
5f0af07e DB |
373 | switch (cp->type) { |
374 | case IMX_MU_TYPE_TX: | |
4f0b776e | 375 | imx_mu_xcr_rmw(priv, IMX_MU_TCR, 0, IMX_MU_xCR_TIEn(priv->dcfg->type, cp->idx)); |
5f0af07e DB |
376 | break; |
377 | case IMX_MU_TYPE_RX: | |
4f0b776e | 378 | imx_mu_xcr_rmw(priv, IMX_MU_RCR, 0, IMX_MU_xCR_RIEn(priv->dcfg->type, cp->idx)); |
5f0af07e DB |
379 | break; |
380 | case IMX_MU_TYPE_RXDB: | |
4f0b776e | 381 | imx_mu_xcr_rmw(priv, IMX_MU_GIER, 0, IMX_MU_xCR_GIEn(priv->dcfg->type, cp->idx)); |
5f0af07e DB |
382 | break; |
383 | default: | |
384 | break; | |
385 | } | |
2bb70056 OR |
386 | |
387 | free_irq(priv->irq, chan); | |
676f23ea | 388 | pm_runtime_put_sync(priv->dev); |
2bb70056 OR |
389 | } |
390 | ||
391 | static const struct mbox_chan_ops imx_mu_ops = { | |
392 | .send_data = imx_mu_send_data, | |
393 | .startup = imx_mu_startup, | |
394 | .shutdown = imx_mu_shutdown, | |
395 | }; | |
396 | ||
0a67003b PF |
397 | static struct mbox_chan *imx_mu_scu_xlate(struct mbox_controller *mbox, |
398 | const struct of_phandle_args *sp) | |
399 | { | |
400 | u32 type, idx, chan; | |
401 | ||
402 | if (sp->args_count != 2) { | |
403 | dev_err(mbox->dev, "Invalid argument count %d\n", sp->args_count); | |
404 | return ERR_PTR(-EINVAL); | |
405 | } | |
406 | ||
407 | type = sp->args[0]; /* channel type */ | |
408 | idx = sp->args[1]; /* index */ | |
409 | ||
410 | switch (type) { | |
411 | case IMX_MU_TYPE_TX: | |
412 | case IMX_MU_TYPE_RX: | |
413 | if (idx != 0) | |
414 | dev_err(mbox->dev, "Invalid chan idx: %d\n", idx); | |
415 | chan = type; | |
416 | break; | |
417 | case IMX_MU_TYPE_RXDB: | |
418 | chan = 2 + idx; | |
419 | break; | |
420 | default: | |
421 | dev_err(mbox->dev, "Invalid chan type: %d\n", type); | |
1b3a347b | 422 | return ERR_PTR(-EINVAL); |
0a67003b PF |
423 | } |
424 | ||
425 | if (chan >= mbox->num_chans) { | |
426 | dev_err(mbox->dev, "Not supported channel number: %d. (type: %d, idx: %d)\n", chan, type, idx); | |
427 | return ERR_PTR(-EINVAL); | |
428 | } | |
429 | ||
430 | return &mbox->chans[chan]; | |
431 | } | |
432 | ||
2bb70056 OR |
433 | static struct mbox_chan * imx_mu_xlate(struct mbox_controller *mbox, |
434 | const struct of_phandle_args *sp) | |
435 | { | |
436 | u32 type, idx, chan; | |
437 | ||
438 | if (sp->args_count != 2) { | |
439 | dev_err(mbox->dev, "Invalid argument count %d\n", sp->args_count); | |
440 | return ERR_PTR(-EINVAL); | |
441 | } | |
442 | ||
443 | type = sp->args[0]; /* channel type */ | |
444 | idx = sp->args[1]; /* index */ | |
445 | chan = type * 4 + idx; | |
446 | ||
447 | if (chan >= mbox->num_chans) { | |
448 | dev_err(mbox->dev, "Not supported channel number: %d. (type: %d, idx: %d)\n", chan, type, idx); | |
449 | return ERR_PTR(-EINVAL); | |
450 | } | |
451 | ||
452 | return &mbox->chans[chan]; | |
453 | } | |
454 | ||
455 | static void imx_mu_init_generic(struct imx_mu_priv *priv) | |
456 | { | |
63b38357 PF |
457 | unsigned int i; |
458 | ||
459 | for (i = 0; i < IMX_MU_CHANS; i++) { | |
460 | struct imx_mu_con_priv *cp = &priv->con_priv[i]; | |
461 | ||
462 | cp->idx = i % 4; | |
463 | cp->type = i >> 2; | |
464 | cp->chan = &priv->mbox_chans[i]; | |
465 | priv->mbox_chans[i].con_priv = cp; | |
466 | snprintf(cp->irq_desc, sizeof(cp->irq_desc), | |
467 | "imx_mu_chan[%i-%i]", cp->type, cp->idx); | |
468 | } | |
469 | ||
470 | priv->mbox.num_chans = IMX_MU_CHANS; | |
471 | priv->mbox.of_xlate = imx_mu_xlate; | |
472 | ||
2bb70056 OR |
473 | if (priv->side_b) |
474 | return; | |
475 | ||
476 | /* Set default MU configuration */ | |
f689a7cf PF |
477 | for (i = 0; i < IMX_MU_xCR_MAX; i++) |
478 | imx_mu_write(priv, 0, priv->dcfg->xCR[i]); | |
2bb70056 OR |
479 | } |
480 | ||
0a67003b PF |
481 | static void imx_mu_init_scu(struct imx_mu_priv *priv) |
482 | { | |
483 | unsigned int i; | |
484 | ||
485 | for (i = 0; i < IMX_MU_SCU_CHANS; i++) { | |
486 | struct imx_mu_con_priv *cp = &priv->con_priv[i]; | |
487 | ||
488 | cp->idx = i < 2 ? 0 : i - 2; | |
489 | cp->type = i < 2 ? i : IMX_MU_TYPE_RXDB; | |
490 | cp->chan = &priv->mbox_chans[i]; | |
491 | priv->mbox_chans[i].con_priv = cp; | |
492 | snprintf(cp->irq_desc, sizeof(cp->irq_desc), | |
493 | "imx_mu_chan[%i-%i]", cp->type, cp->idx); | |
494 | } | |
495 | ||
496 | priv->mbox.num_chans = IMX_MU_SCU_CHANS; | |
497 | priv->mbox.of_xlate = imx_mu_scu_xlate; | |
498 | ||
499 | /* Set default MU configuration */ | |
f689a7cf PF |
500 | for (i = 0; i < IMX_MU_xCR_MAX; i++) |
501 | imx_mu_write(priv, 0, priv->dcfg->xCR[i]); | |
0a67003b PF |
502 | } |
503 | ||
2bb70056 OR |
504 | static int imx_mu_probe(struct platform_device *pdev) |
505 | { | |
506 | struct device *dev = &pdev->dev; | |
507 | struct device_node *np = dev->of_node; | |
2bb70056 | 508 | struct imx_mu_priv *priv; |
c6c6bc6e | 509 | const struct imx_mu_dcfg *dcfg; |
2bb70056 OR |
510 | int ret; |
511 | ||
512 | priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); | |
513 | if (!priv) | |
514 | return -ENOMEM; | |
515 | ||
516 | priv->dev = dev; | |
517 | ||
0c40e631 | 518 | priv->base = devm_platform_ioremap_resource(pdev, 0); |
2bb70056 OR |
519 | if (IS_ERR(priv->base)) |
520 | return PTR_ERR(priv->base); | |
521 | ||
522 | priv->irq = platform_get_irq(pdev, 0); | |
523 | if (priv->irq < 0) | |
524 | return priv->irq; | |
525 | ||
c6c6bc6e RZ |
526 | dcfg = of_device_get_match_data(dev); |
527 | if (!dcfg) | |
528 | return -EINVAL; | |
529 | priv->dcfg = dcfg; | |
530 | ||
2bb70056 OR |
531 | priv->clk = devm_clk_get(dev, NULL); |
532 | if (IS_ERR(priv->clk)) { | |
533 | if (PTR_ERR(priv->clk) != -ENOENT) | |
534 | return PTR_ERR(priv->clk); | |
535 | ||
536 | priv->clk = NULL; | |
537 | } | |
538 | ||
539 | ret = clk_prepare_enable(priv->clk); | |
540 | if (ret) { | |
541 | dev_err(dev, "Failed to enable clock\n"); | |
542 | return ret; | |
543 | } | |
544 | ||
2bb70056 OR |
545 | priv->side_b = of_property_read_bool(np, "fsl,mu-side-b"); |
546 | ||
63b38357 PF |
547 | priv->dcfg->init(priv); |
548 | ||
2bb70056 OR |
549 | spin_lock_init(&priv->xcr_lock); |
550 | ||
551 | priv->mbox.dev = dev; | |
552 | priv->mbox.ops = &imx_mu_ops; | |
553 | priv->mbox.chans = priv->mbox_chans; | |
2bb70056 OR |
554 | priv->mbox.txdone_irq = true; |
555 | ||
556 | platform_set_drvdata(pdev, priv); | |
557 | ||
676f23ea | 558 | ret = devm_mbox_controller_register(dev, &priv->mbox); |
47303f94 FE |
559 | if (ret) { |
560 | clk_disable_unprepare(priv->clk); | |
676f23ea | 561 | return ret; |
47303f94 | 562 | } |
676f23ea AH |
563 | |
564 | pm_runtime_enable(dev); | |
565 | ||
566 | ret = pm_runtime_get_sync(dev); | |
567 | if (ret < 0) { | |
568 | pm_runtime_put_noidle(dev); | |
569 | goto disable_runtime_pm; | |
570 | } | |
571 | ||
572 | ret = pm_runtime_put_sync(dev); | |
573 | if (ret < 0) | |
574 | goto disable_runtime_pm; | |
575 | ||
bb2b2624 AH |
576 | clk_disable_unprepare(priv->clk); |
577 | ||
676f23ea AH |
578 | return 0; |
579 | ||
580 | disable_runtime_pm: | |
581 | pm_runtime_disable(dev); | |
bb2b2624 | 582 | clk_disable_unprepare(priv->clk); |
676f23ea | 583 | return ret; |
2bb70056 OR |
584 | } |
585 | ||
586 | static int imx_mu_remove(struct platform_device *pdev) | |
587 | { | |
588 | struct imx_mu_priv *priv = platform_get_drvdata(pdev); | |
589 | ||
676f23ea | 590 | pm_runtime_disable(priv->dev); |
2bb70056 OR |
591 | |
592 | return 0; | |
593 | } | |
594 | ||
63b38357 PF |
595 | static const struct imx_mu_dcfg imx_mu_cfg_imx6sx = { |
596 | .tx = imx_mu_generic_tx, | |
597 | .rx = imx_mu_generic_rx, | |
598 | .init = imx_mu_init_generic, | |
32f7443d PF |
599 | .xTR = 0x0, |
600 | .xRR = 0x10, | |
f689a7cf PF |
601 | .xSR = {0x20, 0x20, 0x20, 0x20}, |
602 | .xCR = {0x24, 0x24, 0x24, 0x24}, | |
63b38357 PF |
603 | }; |
604 | ||
605 | static const struct imx_mu_dcfg imx_mu_cfg_imx7ulp = { | |
606 | .tx = imx_mu_generic_tx, | |
607 | .rx = imx_mu_generic_rx, | |
608 | .init = imx_mu_init_generic, | |
32f7443d PF |
609 | .xTR = 0x20, |
610 | .xRR = 0x40, | |
f689a7cf PF |
611 | .xSR = {0x60, 0x60, 0x60, 0x60}, |
612 | .xCR = {0x64, 0x64, 0x64, 0x64}, | |
63b38357 PF |
613 | }; |
614 | ||
4f0b776e PF |
615 | static const struct imx_mu_dcfg imx_mu_cfg_imx8ulp = { |
616 | .tx = imx_mu_generic_tx, | |
617 | .rx = imx_mu_generic_rx, | |
618 | .init = imx_mu_init_generic, | |
619 | .type = IMX_MU_V2, | |
620 | .xTR = 0x200, | |
621 | .xRR = 0x280, | |
622 | .xSR = {0xC, 0x118, 0x124, 0x12C}, | |
623 | .xCR = {0x110, 0x114, 0x120, 0x128}, | |
624 | }; | |
625 | ||
0a67003b PF |
626 | static const struct imx_mu_dcfg imx_mu_cfg_imx8_scu = { |
627 | .tx = imx_mu_scu_tx, | |
628 | .rx = imx_mu_scu_rx, | |
629 | .init = imx_mu_init_scu, | |
4f0b776e PF |
630 | .xTR = 0x0, |
631 | .xRR = 0x10, | |
f689a7cf PF |
632 | .xSR = {0x20, 0x20, 0x20, 0x20}, |
633 | .xCR = {0x24, 0x24, 0x24, 0x24}, | |
0a67003b PF |
634 | }; |
635 | ||
2bb70056 | 636 | static const struct of_device_id imx_mu_dt_ids[] = { |
c6c6bc6e RZ |
637 | { .compatible = "fsl,imx7ulp-mu", .data = &imx_mu_cfg_imx7ulp }, |
638 | { .compatible = "fsl,imx6sx-mu", .data = &imx_mu_cfg_imx6sx }, | |
4f0b776e | 639 | { .compatible = "fsl,imx8ulp-mu", .data = &imx_mu_cfg_imx8ulp }, |
0a67003b | 640 | { .compatible = "fsl,imx8-mu-scu", .data = &imx_mu_cfg_imx8_scu }, |
2bb70056 OR |
641 | { }, |
642 | }; | |
643 | MODULE_DEVICE_TABLE(of, imx_mu_dt_ids); | |
644 | ||
03b70130 | 645 | static int __maybe_unused imx_mu_suspend_noirq(struct device *dev) |
ba5f9fa0 DA |
646 | { |
647 | struct imx_mu_priv *priv = dev_get_drvdata(dev); | |
f689a7cf | 648 | int i; |
ba5f9fa0 | 649 | |
f689a7cf PF |
650 | if (!priv->clk) { |
651 | for (i = 0; i < IMX_MU_xCR_MAX; i++) | |
652 | priv->xcr[i] = imx_mu_read(priv, priv->dcfg->xCR[i]); | |
653 | } | |
ba5f9fa0 DA |
654 | |
655 | return 0; | |
656 | } | |
657 | ||
03b70130 | 658 | static int __maybe_unused imx_mu_resume_noirq(struct device *dev) |
ba5f9fa0 DA |
659 | { |
660 | struct imx_mu_priv *priv = dev_get_drvdata(dev); | |
f689a7cf | 661 | int i; |
ba5f9fa0 DA |
662 | |
663 | /* | |
664 | * ONLY restore MU when context lost, the TIE could | |
665 | * be set during noirq resume as there is MU data | |
666 | * communication going on, and restore the saved | |
667 | * value will overwrite the TIE and cause MU data | |
668 | * send failed, may lead to system freeze. This issue | |
669 | * is observed by testing freeze mode suspend. | |
670 | */ | |
f689a7cf PF |
671 | if (!imx_mu_read(priv, priv->dcfg->xCR[0]) && !priv->clk) { |
672 | for (i = 0; i < IMX_MU_xCR_MAX; i++) | |
673 | imx_mu_write(priv, priv->xcr[i], priv->dcfg->xCR[i]); | |
674 | } | |
ba5f9fa0 DA |
675 | |
676 | return 0; | |
677 | } | |
678 | ||
03b70130 | 679 | static int __maybe_unused imx_mu_runtime_suspend(struct device *dev) |
bb2b2624 AH |
680 | { |
681 | struct imx_mu_priv *priv = dev_get_drvdata(dev); | |
682 | ||
683 | clk_disable_unprepare(priv->clk); | |
684 | ||
685 | return 0; | |
686 | } | |
687 | ||
03b70130 | 688 | static int __maybe_unused imx_mu_runtime_resume(struct device *dev) |
bb2b2624 AH |
689 | { |
690 | struct imx_mu_priv *priv = dev_get_drvdata(dev); | |
691 | int ret; | |
692 | ||
693 | ret = clk_prepare_enable(priv->clk); | |
694 | if (ret) | |
695 | dev_err(dev, "failed to enable clock\n"); | |
696 | ||
697 | return ret; | |
698 | } | |
699 | ||
ba5f9fa0 DA |
700 | static const struct dev_pm_ops imx_mu_pm_ops = { |
701 | SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(imx_mu_suspend_noirq, | |
702 | imx_mu_resume_noirq) | |
bb2b2624 AH |
703 | SET_RUNTIME_PM_OPS(imx_mu_runtime_suspend, |
704 | imx_mu_runtime_resume, NULL) | |
ba5f9fa0 DA |
705 | }; |
706 | ||
2bb70056 OR |
707 | static struct platform_driver imx_mu_driver = { |
708 | .probe = imx_mu_probe, | |
709 | .remove = imx_mu_remove, | |
710 | .driver = { | |
711 | .name = "imx_mu", | |
712 | .of_match_table = imx_mu_dt_ids, | |
ba5f9fa0 | 713 | .pm = &imx_mu_pm_ops, |
2bb70056 OR |
714 | }, |
715 | }; | |
716 | module_platform_driver(imx_mu_driver); | |
717 | ||
718 | MODULE_AUTHOR("Oleksij Rempel <o.rempel@pengutronix.de>"); | |
719 | MODULE_DESCRIPTION("Message Unit driver for i.MX"); | |
720 | MODULE_LICENSE("GPL v2"); |