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9c384189 LY |
1 | /* |
2 | * Hisilicon's Hi6220 mailbox driver | |
3 | * | |
4 | * Copyright (c) 2015 Hisilicon Limited. | |
5 | * Copyright (c) 2015 Linaro Limited. | |
6 | * | |
7 | * Author: Leo Yan <leo.yan@linaro.org> | |
8 | * | |
9 | * This program is free software: you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License as published by | |
11 | * the Free Software Foundation, version 2 of the License. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | */ | |
19 | ||
20 | #include <linux/device.h> | |
21 | #include <linux/err.h> | |
22 | #include <linux/interrupt.h> | |
23 | #include <linux/io.h> | |
24 | #include <linux/kfifo.h> | |
25 | #include <linux/mailbox_controller.h> | |
26 | #include <linux/module.h> | |
27 | #include <linux/platform_device.h> | |
28 | #include <linux/slab.h> | |
29 | ||
30 | #define MBOX_CHAN_MAX 32 | |
31 | ||
32 | #define MBOX_TX 0x1 | |
33 | ||
34 | /* Mailbox message length: 8 words */ | |
35 | #define MBOX_MSG_LEN 8 | |
36 | ||
37 | /* Mailbox Registers */ | |
38 | #define MBOX_OFF(m) (0x40 * (m)) | |
39 | #define MBOX_MODE_REG(m) (MBOX_OFF(m) + 0x0) | |
40 | #define MBOX_DATA_REG(m) (MBOX_OFF(m) + 0x4) | |
41 | ||
42 | #define MBOX_STATE_MASK (0xF << 4) | |
43 | #define MBOX_STATE_IDLE (0x1 << 4) | |
44 | #define MBOX_STATE_TX (0x2 << 4) | |
45 | #define MBOX_STATE_RX (0x4 << 4) | |
46 | #define MBOX_STATE_ACK (0x8 << 4) | |
47 | #define MBOX_ACK_CONFIG_MASK (0x1 << 0) | |
48 | #define MBOX_ACK_AUTOMATIC (0x1 << 0) | |
49 | #define MBOX_ACK_IRQ (0x0 << 0) | |
50 | ||
51 | /* IPC registers */ | |
52 | #define ACK_INT_RAW_REG(i) ((i) + 0x400) | |
53 | #define ACK_INT_MSK_REG(i) ((i) + 0x404) | |
54 | #define ACK_INT_STAT_REG(i) ((i) + 0x408) | |
55 | #define ACK_INT_CLR_REG(i) ((i) + 0x40c) | |
56 | #define ACK_INT_ENA_REG(i) ((i) + 0x500) | |
57 | #define ACK_INT_DIS_REG(i) ((i) + 0x504) | |
58 | #define DST_INT_RAW_REG(i) ((i) + 0x420) | |
59 | ||
60 | ||
61 | struct hi6220_mbox_chan { | |
62 | ||
63 | /* | |
64 | * Description for channel's hardware info: | |
65 | * - direction: tx or rx | |
66 | * - dst irq: peer core's irq number | |
67 | * - ack irq: local irq number | |
68 | * - slot number | |
69 | */ | |
70 | unsigned int dir, dst_irq, ack_irq; | |
71 | unsigned int slot; | |
72 | ||
73 | struct hi6220_mbox *parent; | |
74 | }; | |
75 | ||
76 | struct hi6220_mbox { | |
77 | struct device *dev; | |
78 | ||
79 | int irq; | |
80 | ||
81 | /* flag of enabling tx's irq mode */ | |
82 | bool tx_irq_mode; | |
83 | ||
84 | /* region for ipc event */ | |
85 | void __iomem *ipc; | |
86 | ||
87 | /* region for mailbox */ | |
88 | void __iomem *base; | |
89 | ||
90 | unsigned int chan_num; | |
91 | struct hi6220_mbox_chan *mchan; | |
92 | ||
93 | void *irq_map_chan[MBOX_CHAN_MAX]; | |
94 | struct mbox_chan *chan; | |
95 | struct mbox_controller controller; | |
96 | }; | |
97 | ||
98 | static void mbox_set_state(struct hi6220_mbox *mbox, | |
99 | unsigned int slot, u32 val) | |
100 | { | |
101 | u32 status; | |
102 | ||
103 | status = readl(mbox->base + MBOX_MODE_REG(slot)); | |
104 | status = (status & ~MBOX_STATE_MASK) | val; | |
105 | writel(status, mbox->base + MBOX_MODE_REG(slot)); | |
106 | } | |
107 | ||
108 | static void mbox_set_mode(struct hi6220_mbox *mbox, | |
109 | unsigned int slot, u32 val) | |
110 | { | |
111 | u32 mode; | |
112 | ||
113 | mode = readl(mbox->base + MBOX_MODE_REG(slot)); | |
114 | mode = (mode & ~MBOX_ACK_CONFIG_MASK) | val; | |
115 | writel(mode, mbox->base + MBOX_MODE_REG(slot)); | |
116 | } | |
117 | ||
118 | static bool hi6220_mbox_last_tx_done(struct mbox_chan *chan) | |
119 | { | |
120 | struct hi6220_mbox_chan *mchan = chan->con_priv; | |
121 | struct hi6220_mbox *mbox = mchan->parent; | |
122 | u32 state; | |
123 | ||
124 | /* Only set idle state for polling mode */ | |
125 | BUG_ON(mbox->tx_irq_mode); | |
126 | ||
127 | state = readl(mbox->base + MBOX_MODE_REG(mchan->slot)); | |
128 | return ((state & MBOX_STATE_MASK) == MBOX_STATE_IDLE); | |
129 | } | |
130 | ||
131 | static int hi6220_mbox_send_data(struct mbox_chan *chan, void *msg) | |
132 | { | |
133 | struct hi6220_mbox_chan *mchan = chan->con_priv; | |
134 | struct hi6220_mbox *mbox = mchan->parent; | |
135 | unsigned int slot = mchan->slot; | |
136 | u32 *buf = msg; | |
137 | int i; | |
138 | ||
139 | /* indicate as a TX channel */ | |
140 | mchan->dir = MBOX_TX; | |
141 | ||
142 | mbox_set_state(mbox, slot, MBOX_STATE_TX); | |
143 | ||
144 | if (mbox->tx_irq_mode) | |
145 | mbox_set_mode(mbox, slot, MBOX_ACK_IRQ); | |
146 | else | |
147 | mbox_set_mode(mbox, slot, MBOX_ACK_AUTOMATIC); | |
148 | ||
149 | for (i = 0; i < MBOX_MSG_LEN; i++) | |
150 | writel(buf[i], mbox->base + MBOX_DATA_REG(slot) + i * 4); | |
151 | ||
152 | /* trigger remote request */ | |
153 | writel(BIT(mchan->dst_irq), DST_INT_RAW_REG(mbox->ipc)); | |
154 | return 0; | |
155 | } | |
156 | ||
157 | static irqreturn_t hi6220_mbox_interrupt(int irq, void *p) | |
158 | { | |
159 | struct hi6220_mbox *mbox = p; | |
160 | struct hi6220_mbox_chan *mchan; | |
161 | struct mbox_chan *chan; | |
162 | unsigned int state, intr_bit, i; | |
163 | u32 msg[MBOX_MSG_LEN]; | |
164 | ||
165 | state = readl(ACK_INT_STAT_REG(mbox->ipc)); | |
166 | if (!state) { | |
167 | dev_warn(mbox->dev, "%s: spurious interrupt\n", | |
168 | __func__); | |
169 | return IRQ_HANDLED; | |
170 | } | |
171 | ||
172 | while (state) { | |
173 | intr_bit = __ffs(state); | |
174 | state &= (state - 1); | |
175 | ||
176 | chan = mbox->irq_map_chan[intr_bit]; | |
177 | if (!chan) { | |
178 | dev_warn(mbox->dev, "%s: unexpected irq vector %d\n", | |
179 | __func__, intr_bit); | |
180 | continue; | |
181 | } | |
182 | ||
183 | mchan = chan->con_priv; | |
184 | if (mchan->dir == MBOX_TX) | |
185 | mbox_chan_txdone(chan, 0); | |
186 | else { | |
187 | for (i = 0; i < MBOX_MSG_LEN; i++) | |
188 | msg[i] = readl(mbox->base + | |
189 | MBOX_DATA_REG(mchan->slot) + i * 4); | |
190 | ||
191 | mbox_chan_received_data(chan, (void *)msg); | |
192 | } | |
193 | ||
194 | /* clear IRQ source */ | |
195 | writel(BIT(mchan->ack_irq), ACK_INT_CLR_REG(mbox->ipc)); | |
196 | mbox_set_state(mbox, mchan->slot, MBOX_STATE_IDLE); | |
197 | } | |
198 | ||
199 | return IRQ_HANDLED; | |
200 | } | |
201 | ||
202 | static int hi6220_mbox_startup(struct mbox_chan *chan) | |
203 | { | |
204 | struct hi6220_mbox_chan *mchan = chan->con_priv; | |
205 | struct hi6220_mbox *mbox = mchan->parent; | |
206 | ||
207 | mchan->dir = 0; | |
208 | ||
209 | /* enable interrupt */ | |
210 | writel(BIT(mchan->ack_irq), ACK_INT_ENA_REG(mbox->ipc)); | |
211 | return 0; | |
212 | } | |
213 | ||
214 | static void hi6220_mbox_shutdown(struct mbox_chan *chan) | |
215 | { | |
216 | struct hi6220_mbox_chan *mchan = chan->con_priv; | |
217 | struct hi6220_mbox *mbox = mchan->parent; | |
218 | ||
219 | /* disable interrupt */ | |
220 | writel(BIT(mchan->ack_irq), ACK_INT_DIS_REG(mbox->ipc)); | |
221 | mbox->irq_map_chan[mchan->ack_irq] = NULL; | |
222 | } | |
223 | ||
8ce33c6f | 224 | static const struct mbox_chan_ops hi6220_mbox_ops = { |
9c384189 LY |
225 | .send_data = hi6220_mbox_send_data, |
226 | .startup = hi6220_mbox_startup, | |
227 | .shutdown = hi6220_mbox_shutdown, | |
228 | .last_tx_done = hi6220_mbox_last_tx_done, | |
229 | }; | |
230 | ||
231 | static struct mbox_chan *hi6220_mbox_xlate(struct mbox_controller *controller, | |
232 | const struct of_phandle_args *spec) | |
233 | { | |
234 | struct hi6220_mbox *mbox = dev_get_drvdata(controller->dev); | |
235 | struct hi6220_mbox_chan *mchan; | |
236 | struct mbox_chan *chan; | |
237 | unsigned int i = spec->args[0]; | |
238 | unsigned int dst_irq = spec->args[1]; | |
239 | unsigned int ack_irq = spec->args[2]; | |
240 | ||
241 | /* Bounds checking */ | |
242 | if (i >= mbox->chan_num || dst_irq >= mbox->chan_num || | |
243 | ack_irq >= mbox->chan_num) { | |
244 | dev_err(mbox->dev, | |
245 | "Invalid channel idx %d dst_irq %d ack_irq %d\n", | |
246 | i, dst_irq, ack_irq); | |
247 | return ERR_PTR(-EINVAL); | |
248 | } | |
249 | ||
250 | /* Is requested channel free? */ | |
251 | chan = &mbox->chan[i]; | |
252 | if (mbox->irq_map_chan[ack_irq] == (void *)chan) { | |
253 | dev_err(mbox->dev, "Channel in use\n"); | |
254 | return ERR_PTR(-EBUSY); | |
255 | } | |
256 | ||
257 | mchan = chan->con_priv; | |
258 | mchan->dst_irq = dst_irq; | |
259 | mchan->ack_irq = ack_irq; | |
260 | ||
261 | mbox->irq_map_chan[ack_irq] = (void *)chan; | |
262 | return chan; | |
263 | } | |
264 | ||
265 | static const struct of_device_id hi6220_mbox_of_match[] = { | |
266 | { .compatible = "hisilicon,hi6220-mbox", }, | |
267 | {}, | |
268 | }; | |
269 | MODULE_DEVICE_TABLE(of, hi6220_mbox_of_match); | |
270 | ||
271 | static int hi6220_mbox_probe(struct platform_device *pdev) | |
272 | { | |
273 | struct device_node *node = pdev->dev.of_node; | |
274 | struct device *dev = &pdev->dev; | |
275 | struct hi6220_mbox *mbox; | |
276 | struct resource *res; | |
277 | int i, err; | |
278 | ||
279 | mbox = devm_kzalloc(dev, sizeof(*mbox), GFP_KERNEL); | |
280 | if (!mbox) | |
281 | return -ENOMEM; | |
282 | ||
283 | mbox->dev = dev; | |
284 | mbox->chan_num = MBOX_CHAN_MAX; | |
285 | mbox->mchan = devm_kzalloc(dev, | |
286 | mbox->chan_num * sizeof(*mbox->mchan), GFP_KERNEL); | |
287 | if (!mbox->mchan) | |
288 | return -ENOMEM; | |
289 | ||
290 | mbox->chan = devm_kzalloc(dev, | |
291 | mbox->chan_num * sizeof(*mbox->chan), GFP_KERNEL); | |
292 | if (!mbox->chan) | |
293 | return -ENOMEM; | |
294 | ||
295 | mbox->irq = platform_get_irq(pdev, 0); | |
296 | if (mbox->irq < 0) | |
297 | return mbox->irq; | |
298 | ||
299 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
300 | mbox->ipc = devm_ioremap_resource(dev, res); | |
301 | if (IS_ERR(mbox->ipc)) { | |
302 | dev_err(dev, "ioremap ipc failed\n"); | |
303 | return PTR_ERR(mbox->ipc); | |
304 | } | |
305 | ||
306 | res = platform_get_resource(pdev, IORESOURCE_MEM, 1); | |
307 | mbox->base = devm_ioremap_resource(dev, res); | |
308 | if (IS_ERR(mbox->base)) { | |
309 | dev_err(dev, "ioremap buffer failed\n"); | |
310 | return PTR_ERR(mbox->base); | |
311 | } | |
312 | ||
313 | err = devm_request_irq(dev, mbox->irq, hi6220_mbox_interrupt, 0, | |
314 | dev_name(dev), mbox); | |
315 | if (err) { | |
316 | dev_err(dev, "Failed to register a mailbox IRQ handler: %d\n", | |
317 | err); | |
318 | return -ENODEV; | |
319 | } | |
320 | ||
321 | mbox->controller.dev = dev; | |
322 | mbox->controller.chans = &mbox->chan[0]; | |
323 | mbox->controller.num_chans = mbox->chan_num; | |
324 | mbox->controller.ops = &hi6220_mbox_ops; | |
325 | mbox->controller.of_xlate = hi6220_mbox_xlate; | |
326 | ||
327 | for (i = 0; i < mbox->chan_num; i++) { | |
328 | mbox->chan[i].con_priv = &mbox->mchan[i]; | |
329 | mbox->irq_map_chan[i] = NULL; | |
330 | ||
331 | mbox->mchan[i].parent = mbox; | |
332 | mbox->mchan[i].slot = i; | |
333 | } | |
334 | ||
335 | /* mask and clear all interrupt vectors */ | |
336 | writel(0x0, ACK_INT_MSK_REG(mbox->ipc)); | |
337 | writel(~0x0, ACK_INT_CLR_REG(mbox->ipc)); | |
338 | ||
339 | /* use interrupt for tx's ack */ | |
340 | if (of_find_property(node, "hi6220,mbox-tx-noirq", NULL)) | |
341 | mbox->tx_irq_mode = false; | |
342 | else | |
343 | mbox->tx_irq_mode = true; | |
344 | ||
345 | if (mbox->tx_irq_mode) | |
346 | mbox->controller.txdone_irq = true; | |
347 | else { | |
348 | mbox->controller.txdone_poll = true; | |
349 | mbox->controller.txpoll_period = 5; | |
350 | } | |
351 | ||
352 | err = mbox_controller_register(&mbox->controller); | |
353 | if (err) { | |
354 | dev_err(dev, "Failed to register mailbox %d\n", err); | |
355 | return err; | |
356 | } | |
357 | ||
358 | platform_set_drvdata(pdev, mbox); | |
359 | dev_info(dev, "Mailbox enabled\n"); | |
360 | return 0; | |
361 | } | |
362 | ||
363 | static int hi6220_mbox_remove(struct platform_device *pdev) | |
364 | { | |
365 | struct hi6220_mbox *mbox = platform_get_drvdata(pdev); | |
366 | ||
367 | mbox_controller_unregister(&mbox->controller); | |
368 | return 0; | |
369 | } | |
370 | ||
371 | static struct platform_driver hi6220_mbox_driver = { | |
372 | .driver = { | |
373 | .name = "hi6220-mbox", | |
374 | .owner = THIS_MODULE, | |
375 | .of_match_table = hi6220_mbox_of_match, | |
376 | }, | |
377 | .probe = hi6220_mbox_probe, | |
378 | .remove = hi6220_mbox_remove, | |
379 | }; | |
380 | ||
381 | static int __init hi6220_mbox_init(void) | |
382 | { | |
383 | return platform_driver_register(&hi6220_mbox_driver); | |
384 | } | |
385 | core_initcall(hi6220_mbox_init); | |
386 | ||
387 | static void __exit hi6220_mbox_exit(void) | |
388 | { | |
389 | platform_driver_unregister(&hi6220_mbox_driver); | |
390 | } | |
391 | module_exit(hi6220_mbox_exit); | |
392 | ||
393 | MODULE_AUTHOR("Leo Yan <leo.yan@linaro.org>"); | |
394 | MODULE_DESCRIPTION("Hi6220 mailbox driver"); | |
395 | MODULE_LICENSE("GPL v2"); |