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mailbox: bcm-pdc: Changes so mbox client can be removed / re-inserted
[linux-block.git] / drivers / mailbox / bcm-pdc-mailbox.c
CommitLineData
a24532f8
RR		 1/*
2 * Copyright 2016 Broadcom
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License, version 2, as
6 * published by the Free Software Foundation (the "GPL").
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
11 * General Public License version 2 (GPLv2) for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * version 2 (GPLv2) along with this source code.
15 */
16
17/*
18 * Broadcom PDC Mailbox Driver
19 * The PDC provides a ring based programming interface to one or more hardware
20 * offload engines. For example, the PDC driver works with both SPU-M and SPU2
21 * cryptographic offload hardware. In some chips the PDC is referred to as MDE.
22 *
23 * The PDC driver registers with the Linux mailbox framework as a mailbox
24 * controller, once for each PDC instance. Ring 0 for each PDC is registered as
25 * a mailbox channel. The PDC driver uses interrupts to determine when data
26 * transfers to and from an offload engine are complete. The PDC driver uses
27 * threaded IRQs so that response messages are handled outside of interrupt
28 * context.
29 *
30 * The PDC driver allows multiple messages to be pending in the descriptor
31 * rings. The tx_msg_start descriptor index indicates where the last message
32 * starts. The txin_numd value at this index indicates how many descriptor
33 * indexes make up the message. Similar state is kept on the receive side. When
34 * an rx interrupt indicates a response is ready, the PDC driver processes numd
35 * descriptors from the tx and rx ring, thus processing one response at a time.
36 */
37
38#include <linux/errno.h>
39#include <linux/module.h>
40#include <linux/init.h>
41#include <linux/slab.h>
42#include <linux/debugfs.h>
43#include <linux/interrupt.h>
44#include <linux/wait.h>
45#include <linux/platform_device.h>
46#include <linux/io.h>
47#include <linux/of.h>
48#include <linux/of_device.h>
49#include <linux/of_address.h>
50#include <linux/of_irq.h>
51#include <linux/mailbox_controller.h>
52#include <linux/mailbox/brcm-message.h>
53#include <linux/scatterlist.h>
54#include <linux/dma-direction.h>
55#include <linux/dma-mapping.h>
56#include <linux/dmapool.h>
57
58#define PDC_SUCCESS 0
59
60#define RING_ENTRY_SIZE sizeof(struct dma64dd)
61
62/* # entries in PDC dma ring */
63#define PDC_RING_ENTRIES 128
64#define PDC_RING_SIZE (PDC_RING_ENTRIES * RING_ENTRY_SIZE)
65/* Rings are 8k aligned */
66#define RING_ALIGN_ORDER 13
67#define RING_ALIGN BIT(RING_ALIGN_ORDER)
68
69#define RX_BUF_ALIGN_ORDER 5
70#define RX_BUF_ALIGN BIT(RX_BUF_ALIGN_ORDER)
71
72/* descriptor bumping macros */
73#define XXD(x, max_mask) ((x) & (max_mask))
74#define TXD(x, max_mask) XXD((x), (max_mask))
75#define RXD(x, max_mask) XXD((x), (max_mask))
76#define NEXTTXD(i, max_mask) TXD((i) + 1, (max_mask))
77#define PREVTXD(i, max_mask) TXD((i) - 1, (max_mask))
78#define NEXTRXD(i, max_mask) RXD((i) + 1, (max_mask))
79#define PREVRXD(i, max_mask) RXD((i) - 1, (max_mask))
80#define NTXDACTIVE(h, t, max_mask) TXD((t) - (h), (max_mask))
81#define NRXDACTIVE(h, t, max_mask) RXD((t) - (h), (max_mask))
82
83/* Length of BCM header at start of SPU msg, in bytes */
84#define BCM_HDR_LEN 8
85
86/*
87 * PDC driver reserves ringset 0 on each SPU for its own use. The driver does
88 * not currently support use of multiple ringsets on a single PDC engine.
89 */
90#define PDC_RINGSET 0
91
92/*
93 * Interrupt mask and status definitions. Enable interrupts for tx and rx on
94 * ring 0
95 */
96#define PDC_XMTINT_0 (24 + PDC_RINGSET)
97#define PDC_RCVINT_0 (16 + PDC_RINGSET)
98#define PDC_XMTINTEN_0 BIT(PDC_XMTINT_0)
99#define PDC_RCVINTEN_0 BIT(PDC_RCVINT_0)
100#define PDC_INTMASK (PDC_XMTINTEN_0 | PDC_RCVINTEN_0)
101#define PDC_LAZY_FRAMECOUNT 1
102#define PDC_LAZY_TIMEOUT 10000
103#define PDC_LAZY_INT (PDC_LAZY_TIMEOUT | (PDC_LAZY_FRAMECOUNT << 24))
104#define PDC_INTMASK_OFFSET 0x24
105#define PDC_INTSTATUS_OFFSET 0x20
106#define PDC_RCVLAZY0_OFFSET (0x30 + 4 * PDC_RINGSET)
107
108/*
109 * For SPU2, configure MDE_CKSUM_CONTROL to write 17 bytes of metadata
110 * before frame
111 */
112#define PDC_SPU2_RESP_HDR_LEN 17
113#define PDC_CKSUM_CTRL BIT(27)
114#define PDC_CKSUM_CTRL_OFFSET 0x400
115
116#define PDC_SPUM_RESP_HDR_LEN 32
117
118/*
119 * Sets the following bits for write to transmit control reg:
a24532f8
RR		 120 * 11 - PtyChkDisable - parity check is disabled
121 * 20:18 - BurstLen = 3 -> 2^7 = 128 byte data reads from memory
122 */
9fb0f9ac
SL		 123#define PDC_TX_CTL 0x000C0800
124
125/* Bit in tx control reg to enable tx channel */
126#define PDC_TX_ENABLE 0x1
a24532f8
RR		 127
128/*
129 * Sets the following bits for write to receive control reg:
a24532f8
RR		 130 * 7:1 - RcvOffset - size in bytes of status region at start of rx frame buf
131 * 9 - SepRxHdrDescEn - place start of new frames only in descriptors
132 * that have StartOfFrame set
133 * 10 - OflowContinue - on rx FIFO overflow, clear rx fifo, discard all
134 * remaining bytes in current frame, report error
135 * in rx frame status for current frame
136 * 11 - PtyChkDisable - parity check is disabled
137 * 20:18 - BurstLen = 3 -> 2^7 = 128 byte data reads from memory
138 */
9fb0f9ac
SL		 139#define PDC_RX_CTL 0x000C0E00
140
141/* Bit in rx control reg to enable rx channel */
142#define PDC_RX_ENABLE 0x1
a24532f8
RR		 143
144#define CRYPTO_D64_RS0_CD_MASK ((PDC_RING_ENTRIES * RING_ENTRY_SIZE) - 1)
145
146/* descriptor flags */
147#define D64_CTRL1_EOT BIT(28) /* end of descriptor table */
148#define D64_CTRL1_IOC BIT(29) /* interrupt on complete */
149#define D64_CTRL1_EOF BIT(30) /* end of frame */
150#define D64_CTRL1_SOF BIT(31) /* start of frame */
151
152#define RX_STATUS_OVERFLOW 0x00800000
153#define RX_STATUS_LEN 0x0000FFFF
154
155#define PDC_TXREGS_OFFSET 0x200
156#define PDC_RXREGS_OFFSET 0x220
157
158/* Maximum size buffer the DMA engine can handle */
159#define PDC_DMA_BUF_MAX 16384
160
161struct pdc_dma_map {
162 void *ctx; /* opaque context associated with frame */
163};
164
165/* dma descriptor */
166struct dma64dd {
167 u32 ctrl1; /* misc control bits */
168 u32 ctrl2; /* buffer count and address extension */
169 u32 addrlow; /* memory address of the date buffer, bits 31:0 */
170 u32 addrhigh; /* memory address of the date buffer, bits 63:32 */
171};
172
173/* dma registers per channel(xmt or rcv) */
174struct dma64_regs {
175 u32 control; /* enable, et al */
176 u32 ptr; /* last descriptor posted to chip */
177 u32 addrlow; /* descriptor ring base address low 32-bits */
178 u32 addrhigh; /* descriptor ring base address bits 63:32 */
179 u32 status0; /* last rx descriptor written by hw */
180 u32 status1; /* driver does not use */
181};
182
183/* cpp contortions to concatenate w/arg prescan */
184#ifndef PAD
185#define _PADLINE(line) pad ## line
186#define _XSTR(line) _PADLINE(line)
187#define PAD _XSTR(__LINE__)
188#endif /* PAD */
189
190/* dma registers. matches hw layout. */
191struct dma64 {
192 struct dma64_regs dmaxmt; /* dma tx */
193 u32 PAD[2];
194 struct dma64_regs dmarcv; /* dma rx */
195 u32 PAD[2];
196};
197
198/* PDC registers */
199struct pdc_regs {
200 u32 devcontrol; /* 0x000 */
201 u32 devstatus; /* 0x004 */
202 u32 PAD;
203 u32 biststatus; /* 0x00c */
204 u32 PAD[4];
205 u32 intstatus; /* 0x020 */
206 u32 intmask; /* 0x024 */
207 u32 gptimer; /* 0x028 */
208
209 u32 PAD;
210 u32 intrcvlazy_0; /* 0x030 */
211 u32 intrcvlazy_1; /* 0x034 */
212 u32 intrcvlazy_2; /* 0x038 */
213 u32 intrcvlazy_3; /* 0x03c */
214
215 u32 PAD[48];
216 u32 removed_intrecvlazy; /* 0x100 */
217 u32 flowctlthresh; /* 0x104 */
218 u32 wrrthresh; /* 0x108 */
219 u32 gmac_idle_cnt_thresh; /* 0x10c */
220
221 u32 PAD[4];
222 u32 ifioaccessaddr; /* 0x120 */
223 u32 ifioaccessbyte; /* 0x124 */
224 u32 ifioaccessdata; /* 0x128 */
225
226 u32 PAD[21];
227 u32 phyaccess; /* 0x180 */
228 u32 PAD;
229 u32 phycontrol; /* 0x188 */
230 u32 txqctl; /* 0x18c */
231 u32 rxqctl; /* 0x190 */
232 u32 gpioselect; /* 0x194 */
233 u32 gpio_output_en; /* 0x198 */
234 u32 PAD; /* 0x19c */
235 u32 txq_rxq_mem_ctl; /* 0x1a0 */
236 u32 memory_ecc_status; /* 0x1a4 */
237 u32 serdes_ctl; /* 0x1a8 */
238 u32 serdes_status0; /* 0x1ac */
239 u32 serdes_status1; /* 0x1b0 */
240 u32 PAD[11]; /* 0x1b4-1dc */
241 u32 clk_ctl_st; /* 0x1e0 */
242 u32 hw_war; /* 0x1e4 */
243 u32 pwrctl; /* 0x1e8 */
244 u32 PAD[5];
245
246#define PDC_NUM_DMA_RINGS 4
247 struct dma64 dmaregs[PDC_NUM_DMA_RINGS]; /* 0x0200 - 0x2fc */
248
249 /* more registers follow, but we don't use them */
250};
251
252/* structure for allocating/freeing DMA rings */
253struct pdc_ring_alloc {
254 dma_addr_t dmabase; /* DMA address of start of ring */
255 void *vbase; /* base kernel virtual address of ring */
256 u32 size; /* ring allocation size in bytes */
257};
258
259/* PDC state structure */
260struct pdc_state {
261 /* synchronize access to this PDC state structure */
262 spinlock_t pdc_lock;
263
264 /* Index of the PDC whose state is in this structure instance */
265 u8 pdc_idx;
266
267 /* Platform device for this PDC instance */
268 struct platform_device *pdev;
269
270 /*
271 * Each PDC instance has a mailbox controller. PDC receives request
272 * messages through mailboxes, and sends response messages through the
273 * mailbox framework.
274 */
275 struct mbox_controller mbc;
276
277 unsigned int pdc_irq;
278
279 /*
280 * Last interrupt status read from PDC device. Saved in interrupt
281 * handler so the handler can clear the interrupt in the device,
282 * and the interrupt thread called later can know which interrupt
283 * bits are active.
284 */
285 unsigned long intstatus;
286
287 /* Number of bytes of receive status prior to each rx frame */
288 u32 rx_status_len;
289 /* Whether a BCM header is prepended to each frame */
290 bool use_bcm_hdr;
291 /* Sum of length of BCM header and rx status header */
292 u32 pdc_resp_hdr_len;
293
294 /* The base virtual address of DMA hw registers */
295 void __iomem *pdc_reg_vbase;
296
297 /* Pool for allocation of DMA rings */
298 struct dma_pool *ring_pool;
299
300 /* Pool for allocation of metadata buffers for response messages */
301 struct dma_pool *rx_buf_pool;
302
303 /*
304 * The base virtual address of DMA tx/rx descriptor rings. Corresponding
305 * DMA address and size of ring allocation.
306 */
307 struct pdc_ring_alloc tx_ring_alloc;
308 struct pdc_ring_alloc rx_ring_alloc;
309
310 struct pdc_regs *regs; /* start of PDC registers */
311
312 struct dma64_regs *txregs_64; /* dma tx engine registers */
313 struct dma64_regs *rxregs_64; /* dma rx engine registers */
314
315 /*
316 * Arrays of PDC_RING_ENTRIES descriptors
317 * To use multiple ringsets, this needs to be extended
318 */
319 struct dma64dd *txd_64; /* tx descriptor ring */
320 struct dma64dd *rxd_64; /* rx descriptor ring */
321
322 /* descriptor ring sizes */
323 u32 ntxd; /* # tx descriptors */
324 u32 nrxd; /* # rx descriptors */
325 u32 nrxpost; /* # rx buffers to keep posted */
326 u32 ntxpost; /* max number of tx buffers that can be posted */
327
328 /*
329 * Index of next tx descriptor to reclaim. That is, the descriptor
330 * index of the oldest tx buffer for which the host has yet to process
331 * the corresponding response.
332 */
333 u32 txin;
334
335 /*
336 * Index of the first receive descriptor for the sequence of
337 * message fragments currently under construction. Used to build up
338 * the rxin_numd count for a message. Updated to rxout when the host
339 * starts a new sequence of rx buffers for a new message.
340 */
341 u32 tx_msg_start;
342
343 /* Index of next tx descriptor to post. */
344 u32 txout;
345
346 /*
347 * Number of tx descriptors associated with the message that starts
348 * at this tx descriptor index.
349 */
350 u32 txin_numd[PDC_RING_ENTRIES];
351
352 /*
353 * Index of next rx descriptor to reclaim. This is the index of
354 * the next descriptor whose data has yet to be processed by the host.
355 */
356 u32 rxin;
357
358 /*
359 * Index of the first receive descriptor for the sequence of
360 * message fragments currently under construction. Used to build up
361 * the rxin_numd count for a message. Updated to rxout when the host
362 * starts a new sequence of rx buffers for a new message.
363 */
364 u32 rx_msg_start;
365
366 /*
367 * Saved value of current hardware rx descriptor index.
368 * The last rx buffer written by the hw is the index previous to
369 * this one.
370 */
371 u32 last_rx_curr;
372
373 /* Index of next rx descriptor to post. */
374 u32 rxout;
375
376 /*
377 * opaque context associated with frame that starts at each
378 * rx ring index.
379 */
380 void *rxp_ctx[PDC_RING_ENTRIES];
381
382 /*
383 * Scatterlists used to form request and reply frames beginning at a
384 * given ring index. Retained in order to unmap each sg after reply
385 * is processed
386 */
387 struct scatterlist *src_sg[PDC_RING_ENTRIES];
388 struct scatterlist *dst_sg[PDC_RING_ENTRIES];
389
390 /*
391 * Number of rx descriptors associated with the message that starts
392 * at this descriptor index. Not set for every index. For example,
393 * if descriptor index i points to a scatterlist with 4 entries, then
394 * the next three descriptor indexes don't have a value set.
395 */
396 u32 rxin_numd[PDC_RING_ENTRIES];
397
398 void *resp_hdr[PDC_RING_ENTRIES];
399 dma_addr_t resp_hdr_daddr[PDC_RING_ENTRIES];
400
401 struct dentry *debugfs_stats; /* debug FS stats file for this PDC */
402
403 /* counters */
404 u32 pdc_requests; /* number of request messages submitted */
405 u32 pdc_replies; /* number of reply messages received */
406 u32 txnobuf; /* count of tx ring full */
407 u32 rxnobuf; /* count of rx ring full */
408 u32 rx_oflow; /* count of rx overflows */
409};
410
411/* Global variables */
412
413struct pdc_globals {
414 /* Actual number of SPUs in hardware, as reported by device tree */
415 u32 num_spu;
416};
417
418static struct pdc_globals pdcg;
419
420/* top level debug FS directory for PDC driver */
421static struct dentry *debugfs_dir;
422
423static ssize_t pdc_debugfs_read(struct file *filp, char __user *ubuf,
424 size_t count, loff_t *offp)
425{
426 struct pdc_state *pdcs;
427 char *buf;
428 ssize_t ret, out_offset, out_count;
429
430 out_count = 512;
431
432 buf = kmalloc(out_count, GFP_KERNEL);
433 if (!buf)
434 return -ENOMEM;
435
436 pdcs = filp->private_data;
437 out_offset = 0;
438 out_offset += snprintf(buf + out_offset, out_count - out_offset,
439 "SPU %u stats:\n", pdcs->pdc_idx);
440 out_offset += snprintf(buf + out_offset, out_count - out_offset,
441 "PDC requests............%u\n",
442 pdcs->pdc_requests);
443 out_offset += snprintf(buf + out_offset, out_count - out_offset,
444 "PDC responses...........%u\n",
445 pdcs->pdc_replies);
446 out_offset += snprintf(buf + out_offset, out_count - out_offset,
447 "Tx err ring full........%u\n",
448 pdcs->txnobuf);
449 out_offset += snprintf(buf + out_offset, out_count - out_offset,
450 "Rx err ring full........%u\n",
451 pdcs->rxnobuf);
452 out_offset += snprintf(buf + out_offset, out_count - out_offset,
453 "Receive overflow........%u\n",
454 pdcs->rx_oflow);
455
456 if (out_offset > out_count)
457 out_offset = out_count;
458
459 ret = simple_read_from_buffer(ubuf, count, offp, buf, out_offset);
460 kfree(buf);
461 return ret;
462}
463
464static const struct file_operations pdc_debugfs_stats = {
465 .owner = THIS_MODULE,
466 .open = simple_open,
467 .read = pdc_debugfs_read,
468};
469
470/**
471 * pdc_setup_debugfs() - Create the debug FS directories. If the top-level
472 * directory has not yet been created, create it now. Create a stats file in
473 * this directory for a SPU.
474 * @pdcs: PDC state structure
475 */
a75e4a85 476static void pdc_setup_debugfs(struct pdc_state *pdcs)
a24532f8
RR		 477{
478 char spu_stats_name[16];
479
480 if (!debugfs_initialized())
481 return;
482
483 snprintf(spu_stats_name, 16, "pdc%d_stats", pdcs->pdc_idx);
484 if (!debugfs_dir)
485 debugfs_dir = debugfs_create_dir(KBUILD_MODNAME, NULL);
486
9b1b2b3a
RR		 487 /* S_IRUSR == 0400 */
488 pdcs->debugfs_stats = debugfs_create_file(spu_stats_name, 0400,
a24532f8
RR		 489 debugfs_dir, pdcs,
490 &pdc_debugfs_stats);
491}
492
a75e4a85 493static void pdc_free_debugfs(void)
a24532f8
RR		 494{
495 if (debugfs_dir && simple_empty(debugfs_dir)) {
496 debugfs_remove_recursive(debugfs_dir);
497 debugfs_dir = NULL;
498 }
499}
500
501/**
502 * pdc_build_rxd() - Build DMA descriptor to receive SPU result.
503 * @pdcs: PDC state for SPU that will generate result
504 * @dma_addr: DMA address of buffer that descriptor is being built for
505 * @buf_len: Length of the receive buffer, in bytes
506 * @flags: Flags to be stored in descriptor
507 */
508static inline void
509pdc_build_rxd(struct pdc_state *pdcs, dma_addr_t dma_addr,
510 u32 buf_len, u32 flags)
511{
512 struct device *dev = &pdcs->pdev->dev;
513
514 dev_dbg(dev,
515 "Writing rx descriptor for PDC %u at index %u with length %u. flags %#x\n",
516 pdcs->pdc_idx, pdcs->rxout, buf_len, flags);
517
518 iowrite32(lower_32_bits(dma_addr),
519 (void *)&pdcs->rxd_64[pdcs->rxout].addrlow);
520 iowrite32(upper_32_bits(dma_addr),
521 (void *)&pdcs->rxd_64[pdcs->rxout].addrhigh);
522 iowrite32(flags, (void *)&pdcs->rxd_64[pdcs->rxout].ctrl1);
523 iowrite32(buf_len, (void *)&pdcs->rxd_64[pdcs->rxout].ctrl2);
524 /* bump ring index and return */
525 pdcs->rxout = NEXTRXD(pdcs->rxout, pdcs->nrxpost);
526}
527
528/**
529 * pdc_build_txd() - Build a DMA descriptor to transmit a SPU request to
530 * hardware.
531 * @pdcs: PDC state for the SPU that will process this request
532 * @dma_addr: DMA address of packet to be transmitted
533 * @buf_len: Length of tx buffer, in bytes
534 * @flags: Flags to be stored in descriptor
535 */
536static inline void
537pdc_build_txd(struct pdc_state *pdcs, dma_addr_t dma_addr, u32 buf_len,
538 u32 flags)
539{
540 struct device *dev = &pdcs->pdev->dev;
541
542 dev_dbg(dev,
543 "Writing tx descriptor for PDC %u at index %u with length %u, flags %#x\n",
544 pdcs->pdc_idx, pdcs->txout, buf_len, flags);
545
546 iowrite32(lower_32_bits(dma_addr),
547 (void *)&pdcs->txd_64[pdcs->txout].addrlow);
548 iowrite32(upper_32_bits(dma_addr),
549 (void *)&pdcs->txd_64[pdcs->txout].addrhigh);
550 iowrite32(flags, (void *)&pdcs->txd_64[pdcs->txout].ctrl1);
551 iowrite32(buf_len, (void *)&pdcs->txd_64[pdcs->txout].ctrl2);
552
553 /* bump ring index and return */
554 pdcs->txout = NEXTTXD(pdcs->txout, pdcs->ntxpost);
555}
556
557/**
558 * pdc_receive() - Receive a response message from a given SPU.
559 * @pdcs: PDC state for the SPU to receive from
560 * @mssg: mailbox message to be returned to client
561 *
562 * When the return code indicates success, the response message is available in
563 * the receive buffers provided prior to submission of the request.
564 *
565 * Input:
566 * pdcs - PDC state structure for the SPU to be polled
567 * mssg - mailbox message to be returned to client. This function sets the
568 * context pointer on the message to help the client associate the
569 * response with a request.
570 *
571 * Return: PDC_SUCCESS if one or more receive descriptors was processed
572 * -EAGAIN indicates that no response message is available
573 * -EIO an error occurred
574 */
575static int
576pdc_receive(struct pdc_state *pdcs, struct brcm_message *mssg)
577{
578 struct device *dev = &pdcs->pdev->dev;
579 u32 len, rx_status;
580 u32 num_frags;
581 int i;
582 u8 *resp_hdr; /* virtual addr of start of resp message DMA header */
583 u32 frags_rdy; /* number of fragments ready to read */
584 u32 rx_idx; /* ring index of start of receive frame */
585 dma_addr_t resp_hdr_daddr;
586
587 spin_lock(&pdcs->pdc_lock);
588
589 /*
590 * return if a complete response message is not yet ready.
591 * rxin_numd[rxin] is the number of fragments in the next msg
592 * to read.
593 */
594 frags_rdy = NRXDACTIVE(pdcs->rxin, pdcs->last_rx_curr, pdcs->nrxpost);
595 if ((frags_rdy == 0) || (frags_rdy < pdcs->rxin_numd[pdcs->rxin])) {
596 /* See if the hw has written more fragments than we know */
597 pdcs->last_rx_curr =
598 (ioread32((void *)&pdcs->rxregs_64->status0) &
599 CRYPTO_D64_RS0_CD_MASK) / RING_ENTRY_SIZE;
600 frags_rdy = NRXDACTIVE(pdcs->rxin, pdcs->last_rx_curr,
601 pdcs->nrxpost);
602 if ((frags_rdy == 0) ||
603 (frags_rdy < pdcs->rxin_numd[pdcs->rxin])) {
604 /* No response ready */
605 spin_unlock(&pdcs->pdc_lock);
606 return -EAGAIN;
607 }
608 /* can't read descriptors/data until write index is read */
609 rmb();
610 }
611
612 num_frags = pdcs->txin_numd[pdcs->txin];
613 dma_unmap_sg(dev, pdcs->src_sg[pdcs->txin],
614 sg_nents(pdcs->src_sg[pdcs->txin]), DMA_TO_DEVICE);
615
616 for (i = 0; i < num_frags; i++)
617 pdcs->txin = NEXTTXD(pdcs->txin, pdcs->ntxpost);
618
619 dev_dbg(dev, "PDC %u reclaimed %d tx descriptors",
620 pdcs->pdc_idx, num_frags);
621
622 rx_idx = pdcs->rxin;
623 num_frags = pdcs->rxin_numd[rx_idx];
624 /* Return opaque context with result */
625 mssg->ctx = pdcs->rxp_ctx[rx_idx];
626 pdcs->rxp_ctx[rx_idx] = NULL;
627 resp_hdr = pdcs->resp_hdr[rx_idx];
628 resp_hdr_daddr = pdcs->resp_hdr_daddr[rx_idx];
629 dma_unmap_sg(dev, pdcs->dst_sg[rx_idx],
630 sg_nents(pdcs->dst_sg[rx_idx]), DMA_FROM_DEVICE);
631
632 for (i = 0; i < num_frags; i++)
633 pdcs->rxin = NEXTRXD(pdcs->rxin, pdcs->nrxpost);
634
635 spin_unlock(&pdcs->pdc_lock);
636
637 dev_dbg(dev, "PDC %u reclaimed %d rx descriptors",
638 pdcs->pdc_idx, num_frags);
639
640 dev_dbg(dev,
641 "PDC %u txin %u, txout %u, rxin %u, rxout %u, last_rx_curr %u\n",
642 pdcs->pdc_idx, pdcs->txin, pdcs->txout, pdcs->rxin,
643 pdcs->rxout, pdcs->last_rx_curr);
644
645 if (pdcs->pdc_resp_hdr_len == PDC_SPUM_RESP_HDR_LEN) {
646 /*
647 * For SPU-M, get length of response msg and rx overflow status.
648 */
649 rx_status = *((u32 *)resp_hdr);
650 len = rx_status & RX_STATUS_LEN;
651 dev_dbg(dev,
652 "SPU response length %u bytes", len);
653 if (unlikely(((rx_status & RX_STATUS_OVERFLOW) || (!len)))) {
654 if (rx_status & RX_STATUS_OVERFLOW) {
655 dev_err_ratelimited(dev,
656 "crypto receive overflow");
657 pdcs->rx_oflow++;
658 } else {
659 dev_info_ratelimited(dev, "crypto rx len = 0");
660 }
661 return -EIO;
662 }
663 }
664
665 dma_pool_free(pdcs->rx_buf_pool, resp_hdr, resp_hdr_daddr);
666
667 pdcs->pdc_replies++;
668 /* if we read one or more rx descriptors, claim success */
669 if (num_frags > 0)
670 return PDC_SUCCESS;
671 else
672 return -EIO;
673}
674
675/**
676 * pdc_tx_list_sg_add() - Add the buffers in a scatterlist to the transmit
677 * descriptors for a given SPU. The scatterlist buffers contain the data for a
678 * SPU request message.
679 * @spu_idx: The index of the SPU to submit the request to, [0, max_spu)
680 * @sg: Scatterlist whose buffers contain part of the SPU request
681 *
682 * If a scatterlist buffer is larger than PDC_DMA_BUF_MAX, multiple descriptors
683 * are written for that buffer, each <= PDC_DMA_BUF_MAX byte in length.
684 *
685 * Return: PDC_SUCCESS if successful
686 * < 0 otherwise
687 */
688static int pdc_tx_list_sg_add(struct pdc_state *pdcs, struct scatterlist *sg)
689{
690 u32 flags = 0;
691 u32 eot;
692 u32 tx_avail;
693
694 /*
695 * Num descriptors needed. Conservatively assume we need a descriptor
696 * for every entry in sg.
697 */
698 u32 num_desc;
699 u32 desc_w = 0; /* Number of tx descriptors written */
700 u32 bufcnt; /* Number of bytes of buffer pointed to by descriptor */
701 dma_addr_t databufptr; /* DMA address to put in descriptor */
702
703 num_desc = (u32)sg_nents(sg);
704
705 /* check whether enough tx descriptors are available */
706 tx_avail = pdcs->ntxpost - NTXDACTIVE(pdcs->txin, pdcs->txout,
707 pdcs->ntxpost);
708 if (unlikely(num_desc > tx_avail)) {
709 pdcs->txnobuf++;
710 return -ENOSPC;
711 }
712
713 /* build tx descriptors */
714 if (pdcs->tx_msg_start == pdcs->txout) {
715 /* Start of frame */
716 pdcs->txin_numd[pdcs->tx_msg_start] = 0;
717 pdcs->src_sg[pdcs->txout] = sg;
718 flags = D64_CTRL1_SOF;
719 }
720
721 while (sg) {
722 if (unlikely(pdcs->txout == (pdcs->ntxd - 1)))
723 eot = D64_CTRL1_EOT;
724 else
725 eot = 0;
726
727 /*
728 * If sg buffer larger than PDC limit, split across
729 * multiple descriptors
730 */
731 bufcnt = sg_dma_len(sg);
732 databufptr = sg_dma_address(sg);
733 while (bufcnt > PDC_DMA_BUF_MAX) {
734 pdc_build_txd(pdcs, databufptr, PDC_DMA_BUF_MAX,
735 flags | eot);
736 desc_w++;
737 bufcnt -= PDC_DMA_BUF_MAX;
738 databufptr += PDC_DMA_BUF_MAX;
739 if (unlikely(pdcs->txout == (pdcs->ntxd - 1)))
740 eot = D64_CTRL1_EOT;
741 else
742 eot = 0;
743 }
744 sg = sg_next(sg);
745 if (!sg)
746 /* Writing last descriptor for frame */
747 flags |= (D64_CTRL1_EOF | D64_CTRL1_IOC);
748 pdc_build_txd(pdcs, databufptr, bufcnt, flags | eot);
749 desc_w++;
750 /* Clear start of frame after first descriptor */
751 flags &= ~D64_CTRL1_SOF;
752 }
753 pdcs->txin_numd[pdcs->tx_msg_start] += desc_w;
754
755 return PDC_SUCCESS;
756}
757
758/**
759 * pdc_tx_list_final() - Initiate DMA transfer of last frame written to tx
760 * ring.
761 * @pdcs: PDC state for SPU to process the request
762 *
763 * Sets the index of the last descriptor written in both the rx and tx ring.
764 *
765 * Return: PDC_SUCCESS
766 */
767static int pdc_tx_list_final(struct pdc_state *pdcs)
768{
769 /*
770 * write barrier to ensure all register writes are complete
771 * before chip starts to process new request
772 */
773 wmb();
774 iowrite32(pdcs->rxout << 4, (void *)&pdcs->rxregs_64->ptr);
775 iowrite32(pdcs->txout << 4, (void *)&pdcs->txregs_64->ptr);
776 pdcs->pdc_requests++;
777
778 return PDC_SUCCESS;
779}
780
781/**
782 * pdc_rx_list_init() - Start a new receive descriptor list for a given PDC.
783 * @pdcs: PDC state for SPU handling request
784 * @dst_sg: scatterlist providing rx buffers for response to be returned to
785 * mailbox client
786 * @ctx: Opaque context for this request
787 *
788 * Posts a single receive descriptor to hold the metadata that precedes a
789 * response. For example, with SPU-M, the metadata is a 32-byte DMA header and
790 * an 8-byte BCM header. Moves the msg_start descriptor indexes for both tx and
791 * rx to indicate the start of a new message.
792 *
793 * Return: PDC_SUCCESS if successful
794 * < 0 if an error (e.g., rx ring is full)
795 */
796static int pdc_rx_list_init(struct pdc_state *pdcs, struct scatterlist *dst_sg,
797 void *ctx)
798{
799 u32 flags = 0;
800 u32 rx_avail;
801 u32 rx_pkt_cnt = 1; /* Adding a single rx buffer */
802 dma_addr_t daddr;
803 void *vaddr;
804
805 rx_avail = pdcs->nrxpost - NRXDACTIVE(pdcs->rxin, pdcs->rxout,
806 pdcs->nrxpost);
807 if (unlikely(rx_pkt_cnt > rx_avail)) {
808 pdcs->rxnobuf++;
809 return -ENOSPC;
810 }
811
812 /* allocate a buffer for the dma rx status */
813 vaddr = dma_pool_zalloc(pdcs->rx_buf_pool, GFP_ATOMIC, &daddr);
814 if (!vaddr)
815 return -ENOMEM;
816
817 /*
818 * Update msg_start indexes for both tx and rx to indicate the start
819 * of a new sequence of descriptor indexes that contain the fragments
820 * of the same message.
821 */
822 pdcs->rx_msg_start = pdcs->rxout;
823 pdcs->tx_msg_start = pdcs->txout;
824
825 /* This is always the first descriptor in the receive sequence */
826 flags = D64_CTRL1_SOF;
827 pdcs->rxin_numd[pdcs->rx_msg_start] = 1;
828
829 if (unlikely(pdcs->rxout == (pdcs->nrxd - 1)))
830 flags |= D64_CTRL1_EOT;
831
832 pdcs->rxp_ctx[pdcs->rxout] = ctx;
833 pdcs->dst_sg[pdcs->rxout] = dst_sg;
834 pdcs->resp_hdr[pdcs->rxout] = vaddr;
835 pdcs->resp_hdr_daddr[pdcs->rxout] = daddr;
836 pdc_build_rxd(pdcs, daddr, pdcs->pdc_resp_hdr_len, flags);
837 return PDC_SUCCESS;
838}
839
840/**
841 * pdc_rx_list_sg_add() - Add the buffers in a scatterlist to the receive
842 * descriptors for a given SPU. The caller must have already DMA mapped the
843 * scatterlist.
844 * @spu_idx: Indicates which SPU the buffers are for
845 * @sg: Scatterlist whose buffers are added to the receive ring
846 *
847 * If a receive buffer in the scatterlist is larger than PDC_DMA_BUF_MAX,
848 * multiple receive descriptors are written, each with a buffer <=
849 * PDC_DMA_BUF_MAX.
850 *
851 * Return: PDC_SUCCESS if successful
852 * < 0 otherwise (e.g., receive ring is full)
853 */
854static int pdc_rx_list_sg_add(struct pdc_state *pdcs, struct scatterlist *sg)
855{
856 u32 flags = 0;
857 u32 rx_avail;
858
859 /*
860 * Num descriptors needed. Conservatively assume we need a descriptor
861 * for every entry from our starting point in the scatterlist.
862 */
863 u32 num_desc;
864 u32 desc_w = 0; /* Number of tx descriptors written */
865 u32 bufcnt; /* Number of bytes of buffer pointed to by descriptor */
866 dma_addr_t databufptr; /* DMA address to put in descriptor */
867
868 num_desc = (u32)sg_nents(sg);
869
870 rx_avail = pdcs->nrxpost - NRXDACTIVE(pdcs->rxin, pdcs->rxout,
871 pdcs->nrxpost);
872 if (unlikely(num_desc > rx_avail)) {
873 pdcs->rxnobuf++;
874 return -ENOSPC;
875 }
876
877 while (sg) {
878 if (unlikely(pdcs->rxout == (pdcs->nrxd - 1)))
879 flags = D64_CTRL1_EOT;
880 else
881 flags = 0;
882
883 /*
884 * If sg buffer larger than PDC limit, split across
885 * multiple descriptors
886 */
887 bufcnt = sg_dma_len(sg);
888 databufptr = sg_dma_address(sg);
889 while (bufcnt > PDC_DMA_BUF_MAX) {
890 pdc_build_rxd(pdcs, databufptr, PDC_DMA_BUF_MAX, flags);
891 desc_w++;
892 bufcnt -= PDC_DMA_BUF_MAX;
893 databufptr += PDC_DMA_BUF_MAX;
894 if (unlikely(pdcs->rxout == (pdcs->nrxd - 1)))
895 flags = D64_CTRL1_EOT;
896 else
897 flags = 0;
898 }
899 pdc_build_rxd(pdcs, databufptr, bufcnt, flags);
900 desc_w++;
901 sg = sg_next(sg);
902 }
903 pdcs->rxin_numd[pdcs->rx_msg_start] += desc_w;
904
905 return PDC_SUCCESS;
906}
907
908/**
909 * pdc_irq_handler() - Interrupt handler called in interrupt context.
910 * @irq: Interrupt number that has fired
911 * @cookie: PDC state for DMA engine that generated the interrupt
912 *
913 * We have to clear the device interrupt status flags here. So cache the
914 * status for later use in the thread function. Other than that, just return
915 * WAKE_THREAD to invoke the thread function.
916 *
917 * Return: IRQ_WAKE_THREAD if interrupt is ours
918 * IRQ_NONE otherwise
919 */
920static irqreturn_t pdc_irq_handler(int irq, void *cookie)
921{
922 struct pdc_state *pdcs = cookie;
923 u32 intstatus = ioread32(pdcs->pdc_reg_vbase + PDC_INTSTATUS_OFFSET);
924
925 if (intstatus & PDC_XMTINTEN_0)
926 set_bit(PDC_XMTINT_0, &pdcs->intstatus);
927 if (intstatus & PDC_RCVINTEN_0)
928 set_bit(PDC_RCVINT_0, &pdcs->intstatus);
929
930 /* Clear interrupt flags in device */
931 iowrite32(intstatus, pdcs->pdc_reg_vbase + PDC_INTSTATUS_OFFSET);
932
933 /* Wakeup IRQ thread */
934 if (pdcs && (irq == pdcs->pdc_irq) && (intstatus & PDC_INTMASK))
935 return IRQ_WAKE_THREAD;
936
937 return IRQ_NONE;
938}
939
940/**
941 * pdc_irq_thread() - Function invoked on deferred thread when a DMA tx has
942 * completed or data is available to receive.
943 * @irq: Interrupt number
944 * @cookie: PDC state for PDC that generated the interrupt
945 *
946 * On DMA tx complete, notify the mailbox client. On DMA rx complete, process
947 * as many SPU response messages as are available and send each to the mailbox
948 * client.
949 *
950 * Return: IRQ_HANDLED if we recognized and handled the interrupt
951 * IRQ_NONE otherwise
952 */
953static irqreturn_t pdc_irq_thread(int irq, void *cookie)
954{
955 struct pdc_state *pdcs = cookie;
956 struct mbox_controller *mbc;
957 struct mbox_chan *chan;
958 bool tx_int;
959 bool rx_int;
960 int rx_status;
961 struct brcm_message mssg;
962
963 tx_int = test_and_clear_bit(PDC_XMTINT_0, &pdcs->intstatus);
964 rx_int = test_and_clear_bit(PDC_RCVINT_0, &pdcs->intstatus);
965
966 if (pdcs && (tx_int || rx_int)) {
967 dev_dbg(&pdcs->pdev->dev,
968 "%s() got irq %d with tx_int %s, rx_int %s",
969 __func__, irq,
970 tx_int ? "set" : "clear", rx_int ? "set" : "clear");
971
972 mbc = &pdcs->mbc;
973 chan = &mbc->chans[0];
974
975 if (tx_int) {
976 dev_dbg(&pdcs->pdev->dev, "%s(): tx done", __func__);
977 /* only one frame in flight at a time */
978 mbox_chan_txdone(chan, PDC_SUCCESS);
979 }
980 if (rx_int) {
981 while (1) {
982 /* Could be many frames ready */
983 memset(&mssg, 0, sizeof(mssg));
984 mssg.type = BRCM_MESSAGE_SPU;
985 rx_status = pdc_receive(pdcs, &mssg);
986 if (rx_status >= 0) {
987 dev_dbg(&pdcs->pdev->dev,
988 "%s(): invoking client rx cb",
989 __func__);
990 mbox_chan_received_data(chan, &mssg);
991 } else {
992 dev_dbg(&pdcs->pdev->dev,
993 "%s(): no SPU response available",
994 __func__);
995 break;
996 }
997 }
998 }
999 return IRQ_HANDLED;
1000 }
1001 return IRQ_NONE;
1002}
1003
1004/**
1005 * pdc_ring_init() - Allocate DMA rings and initialize constant fields of
1006 * descriptors in one ringset.
1007 * @pdcs: PDC instance state
1008 * @ringset: index of ringset being used
1009 *
1010 * Return: PDC_SUCCESS if ring initialized
1011 * < 0 otherwise
1012 */
1013static int pdc_ring_init(struct pdc_state *pdcs, int ringset)
1014{
1015 int i;
1016 int err = PDC_SUCCESS;
1017 struct dma64 *dma_reg;
1018 struct device *dev = &pdcs->pdev->dev;
1019 struct pdc_ring_alloc tx;
1020 struct pdc_ring_alloc rx;
1021
1022 /* Allocate tx ring */
1023 tx.vbase = dma_pool_zalloc(pdcs->ring_pool, GFP_KERNEL, &tx.dmabase);
1024 if (!tx.vbase) {
1025 err = -ENOMEM;
1026 goto done;
1027 }
1028
1029 /* Allocate rx ring */
1030 rx.vbase = dma_pool_zalloc(pdcs->ring_pool, GFP_KERNEL, &rx.dmabase);
1031 if (!rx.vbase) {
1032 err = -ENOMEM;
1033 goto fail_dealloc;
1034 }
1035
a68b2166 1036 dev_dbg(dev, " - base DMA addr of tx ring %pad", &tx.dmabase);
a24532f8 1037 dev_dbg(dev, " - base virtual addr of tx ring %p", tx.vbase);
a68b2166 1038 dev_dbg(dev, " - base DMA addr of rx ring %pad", &rx.dmabase);
a24532f8
RR		 1039 dev_dbg(dev, " - base virtual addr of rx ring %p", rx.vbase);
1040
1041 /* lock after ring allocation to avoid scheduling while atomic */
1042 spin_lock(&pdcs->pdc_lock);
1043
1044 memcpy(&pdcs->tx_ring_alloc, &tx, sizeof(tx));
1045 memcpy(&pdcs->rx_ring_alloc, &rx, sizeof(rx));
1046
1047 pdcs->rxin = 0;
1048 pdcs->rx_msg_start = 0;
1049 pdcs->last_rx_curr = 0;
1050 pdcs->rxout = 0;
1051 pdcs->txin = 0;
1052 pdcs->tx_msg_start = 0;
1053 pdcs->txout = 0;
1054
1055 /* Set descriptor array base addresses */
1056 pdcs->txd_64 = (struct dma64dd *)pdcs->tx_ring_alloc.vbase;
1057 pdcs->rxd_64 = (struct dma64dd *)pdcs->rx_ring_alloc.vbase;
1058
1059 /* Tell device the base DMA address of each ring */
1060 dma_reg = &pdcs->regs->dmaregs[ringset];
9fb0f9ac
SL		 1061
1062 /* But first disable DMA and set curptr to 0 for both TX & RX */
1063 iowrite32(PDC_TX_CTL, &dma_reg->dmaxmt.control);
1064 iowrite32((PDC_RX_CTL + (pdcs->rx_status_len << 1)),
1065 (void *)&dma_reg->dmarcv.control);
1066 iowrite32(0, (void *)&dma_reg->dmaxmt.ptr);
1067 iowrite32(0, (void *)&dma_reg->dmarcv.ptr);
1068
1069 /* Set base DMA addresses */
a24532f8
RR		 1070 iowrite32(lower_32_bits(pdcs->tx_ring_alloc.dmabase),
1071 (void *)&dma_reg->dmaxmt.addrlow);
1072 iowrite32(upper_32_bits(pdcs->tx_ring_alloc.dmabase),
1073 (void *)&dma_reg->dmaxmt.addrhigh);
1074
1075 iowrite32(lower_32_bits(pdcs->rx_ring_alloc.dmabase),
1076 (void *)&dma_reg->dmarcv.addrlow);
1077 iowrite32(upper_32_bits(pdcs->rx_ring_alloc.dmabase),
1078 (void *)&dma_reg->dmarcv.addrhigh);
1079
9fb0f9ac
SL		 1080 /* Re-enable DMA */
1081 iowrite32(PDC_TX_CTL | PDC_TX_ENABLE, &dma_reg->dmaxmt.control);
1082 iowrite32((PDC_RX_CTL | PDC_RX_ENABLE | (pdcs->rx_status_len << 1)),
1083 (void *)&dma_reg->dmarcv.control);
1084
a24532f8
RR		 1085 /* Initialize descriptors */
1086 for (i = 0; i < PDC_RING_ENTRIES; i++) {
1087 /* Every tx descriptor can be used for start of frame. */
1088 if (i != pdcs->ntxpost) {
1089 iowrite32(D64_CTRL1_SOF | D64_CTRL1_EOF,
1090 (void *)&pdcs->txd_64[i].ctrl1);
1091 } else {
1092 /* Last descriptor in ringset. Set End of Table. */
1093 iowrite32(D64_CTRL1_SOF | D64_CTRL1_EOF |
1094 D64_CTRL1_EOT,
1095 (void *)&pdcs->txd_64[i].ctrl1);
1096 }
1097
1098 /* Every rx descriptor can be used for start of frame */
1099 if (i != pdcs->nrxpost) {
1100 iowrite32(D64_CTRL1_SOF,
1101 (void *)&pdcs->rxd_64[i].ctrl1);
1102 } else {
1103 /* Last descriptor in ringset. Set End of Table. */
1104 iowrite32(D64_CTRL1_SOF | D64_CTRL1_EOT,
1105 (void *)&pdcs->rxd_64[i].ctrl1);
1106 }
1107 }
1108 spin_unlock(&pdcs->pdc_lock);
1109 return PDC_SUCCESS;
1110
1111fail_dealloc:
1112 dma_pool_free(pdcs->ring_pool, tx.vbase, tx.dmabase);
1113done:
1114 return err;
1115}
1116
1117static void pdc_ring_free(struct pdc_state *pdcs)
1118{
1119 if (pdcs->tx_ring_alloc.vbase) {
1120 dma_pool_free(pdcs->ring_pool, pdcs->tx_ring_alloc.vbase,
1121 pdcs->tx_ring_alloc.dmabase);
1122 pdcs->tx_ring_alloc.vbase = NULL;
1123 }
1124
1125 if (pdcs->rx_ring_alloc.vbase) {
1126 dma_pool_free(pdcs->ring_pool, pdcs->rx_ring_alloc.vbase,
1127 pdcs->rx_ring_alloc.dmabase);
1128 pdcs->rx_ring_alloc.vbase = NULL;
1129 }
1130}
1131
1132/**
1133 * pdc_send_data() - mailbox send_data function
1134 * @chan: The mailbox channel on which the data is sent. The channel
1135 * corresponds to a DMA ringset.
1136 * @data: The mailbox message to be sent. The message must be a
1137 * brcm_message structure.
1138 *
1139 * This function is registered as the send_data function for the mailbox
1140 * controller. From the destination scatterlist in the mailbox message, it
1141 * creates a sequence of receive descriptors in the rx ring. From the source
1142 * scatterlist, it creates a sequence of transmit descriptors in the tx ring.
1143 * After creating the descriptors, it writes the rx ptr and tx ptr registers to
1144 * initiate the DMA transfer.
1145 *
1146 * This function does the DMA map and unmap of the src and dst scatterlists in
1147 * the mailbox message.
1148 *
1149 * Return: 0 if successful
1150 * -ENOTSUPP if the mailbox message is a type this driver does not
1151 * support
1152 * < 0 if an error
1153 */
1154static int pdc_send_data(struct mbox_chan *chan, void *data)
1155{
1156 struct pdc_state *pdcs = chan->con_priv;
1157 struct device *dev = &pdcs->pdev->dev;
1158 struct brcm_message *mssg = data;
1159 int err = PDC_SUCCESS;
1160 int src_nent;
1161 int dst_nent;
1162 int nent;
1163
1164 if (mssg->type != BRCM_MESSAGE_SPU)
1165 return -ENOTSUPP;
1166
1167 src_nent = sg_nents(mssg->spu.src);
1168 if (src_nent) {
1169 nent = dma_map_sg(dev, mssg->spu.src, src_nent, DMA_TO_DEVICE);
1170 if (nent == 0)
1171 return -EIO;
1172 }
1173
1174 dst_nent = sg_nents(mssg->spu.dst);
1175 if (dst_nent) {
1176 nent = dma_map_sg(dev, mssg->spu.dst, dst_nent,
1177 DMA_FROM_DEVICE);
1178 if (nent == 0) {
1179 dma_unmap_sg(dev, mssg->spu.src, src_nent,
1180 DMA_TO_DEVICE);
1181 return -EIO;
1182 }
1183 }
1184
1185 spin_lock(&pdcs->pdc_lock);
1186
1187 /* Create rx descriptors to SPU catch response */
1188 err = pdc_rx_list_init(pdcs, mssg->spu.dst, mssg->ctx);
1189 err |= pdc_rx_list_sg_add(pdcs, mssg->spu.dst);
1190
1191 /* Create tx descriptors to submit SPU request */
1192 err |= pdc_tx_list_sg_add(pdcs, mssg->spu.src);
1193 err |= pdc_tx_list_final(pdcs); /* initiate transfer */
1194
1195 spin_unlock(&pdcs->pdc_lock);
1196
1197 if (err)
1198 dev_err(&pdcs->pdev->dev,
1199 "%s failed with error %d", __func__, err);
1200
1201 return err;
1202}
1203
1204static int pdc_startup(struct mbox_chan *chan)
1205{
1206 return pdc_ring_init(chan->con_priv, PDC_RINGSET);
1207}
1208
1209static void pdc_shutdown(struct mbox_chan *chan)
1210{
1211 struct pdc_state *pdcs = chan->con_priv;
1212
068cf29e
DC		 1213 if (!pdcs)
1214 return;
a24532f8 1215
068cf29e
DC		 1216 dev_dbg(&pdcs->pdev->dev,
1217 "Shutdown mailbox channel for PDC %u", pdcs->pdc_idx);
a24532f8
RR		 1218 pdc_ring_free(pdcs);
1219}
1220
1221/**
1222 * pdc_hw_init() - Use the given initialization parameters to initialize the
1223 * state for one of the PDCs.
1224 * @pdcs: state of the PDC
1225 */
1226static
1227void pdc_hw_init(struct pdc_state *pdcs)
1228{
1229 struct platform_device *pdev;
1230 struct device *dev;
1231 struct dma64 *dma_reg;
1232 int ringset = PDC_RINGSET;
1233
1234 pdev = pdcs->pdev;
1235 dev = &pdev->dev;
1236
1237 dev_dbg(dev, "PDC %u initial values:", pdcs->pdc_idx);
1238 dev_dbg(dev, "state structure: %p",
1239 pdcs);
1240 dev_dbg(dev, " - base virtual addr of hw regs %p",
1241 pdcs->pdc_reg_vbase);
1242
1243 /* initialize data structures */
1244 pdcs->regs = (struct pdc_regs *)pdcs->pdc_reg_vbase;
1245 pdcs->txregs_64 = (struct dma64_regs *)
1246 (void *)(((u8 *)pdcs->pdc_reg_vbase) +
1247 PDC_TXREGS_OFFSET + (sizeof(struct dma64) * ringset));
1248 pdcs->rxregs_64 = (struct dma64_regs *)
1249 (void *)(((u8 *)pdcs->pdc_reg_vbase) +
1250 PDC_RXREGS_OFFSET + (sizeof(struct dma64) * ringset));
1251
1252 pdcs->ntxd = PDC_RING_ENTRIES;
1253 pdcs->nrxd = PDC_RING_ENTRIES;
1254 pdcs->ntxpost = PDC_RING_ENTRIES - 1;
1255 pdcs->nrxpost = PDC_RING_ENTRIES - 1;
9fb0f9ac 1256 iowrite32(0, &pdcs->regs->intmask);
a24532f8
RR		 1257
1258 dma_reg = &pdcs->regs->dmaregs[ringset];
a24532f8 1259
9fb0f9ac
SL		 1260 /* Configure DMA but will enable later in pdc_ring_init() */
1261 iowrite32(PDC_TX_CTL, &dma_reg->dmaxmt.control);
a24532f8
RR		 1262
1263 iowrite32(PDC_RX_CTL + (pdcs->rx_status_len << 1),
1264 (void *)&dma_reg->dmarcv.control);
1265
9fb0f9ac
SL		 1266 /* Reset current index pointers after making sure DMA is disabled */
1267 iowrite32(0, &dma_reg->dmaxmt.ptr);
1268 iowrite32(0, &dma_reg->dmarcv.ptr);
1269
a24532f8
RR		 1270 if (pdcs->pdc_resp_hdr_len == PDC_SPU2_RESP_HDR_LEN)
1271 iowrite32(PDC_CKSUM_CTRL,
1272 pdcs->pdc_reg_vbase + PDC_CKSUM_CTRL_OFFSET);
1273}
1274
9fb0f9ac
SL		 1275/**
1276 * pdc_hw_disable() - Disable the tx and rx control in the hw.
1277 * @pdcs: PDC state structure
1278 *
1279 */
1280static void pdc_hw_disable(struct pdc_state *pdcs)
1281{
1282 struct dma64 *dma_reg;
1283
1284 dma_reg = &pdcs->regs->dmaregs[PDC_RINGSET];
1285 iowrite32(PDC_TX_CTL, &dma_reg->dmaxmt.control);
1286 iowrite32(PDC_RX_CTL + (pdcs->rx_status_len << 1),
1287 &dma_reg->dmarcv.control);
1288}
1289
a24532f8
RR		 1290/**
1291 * pdc_rx_buf_pool_create() - Pool of receive buffers used to catch the metadata
1292 * header returned with each response message.
1293 * @pdcs: PDC state structure
1294 *
1295 * The metadata is not returned to the mailbox client. So the PDC driver
1296 * manages these buffers.
1297 *
1298 * Return: PDC_SUCCESS
1299 * -ENOMEM if pool creation fails
1300 */
1301static int pdc_rx_buf_pool_create(struct pdc_state *pdcs)
1302{
1303 struct platform_device *pdev;
1304 struct device *dev;
1305
1306 pdev = pdcs->pdev;
1307 dev = &pdev->dev;
1308
1309 pdcs->pdc_resp_hdr_len = pdcs->rx_status_len;
1310 if (pdcs->use_bcm_hdr)
1311 pdcs->pdc_resp_hdr_len += BCM_HDR_LEN;
1312
1313 pdcs->rx_buf_pool = dma_pool_create("pdc rx bufs", dev,
1314 pdcs->pdc_resp_hdr_len,
1315 RX_BUF_ALIGN, 0);
1316 if (!pdcs->rx_buf_pool)
1317 return -ENOMEM;
1318
1319 return PDC_SUCCESS;
1320}
1321
1322/**
1323 * pdc_interrupts_init() - Initialize the interrupt configuration for a PDC and
1324 * specify a threaded IRQ handler for deferred handling of interrupts outside of
1325 * interrupt context.
1326 * @pdcs: PDC state
1327 *
1328 * Set the interrupt mask for transmit and receive done.
1329 * Set the lazy interrupt frame count to generate an interrupt for just one pkt.
1330 *
1331 * Return: PDC_SUCCESS
1332 * <0 if threaded irq request fails
1333 */
1334static int pdc_interrupts_init(struct pdc_state *pdcs)
1335{
1336 struct platform_device *pdev = pdcs->pdev;
1337 struct device *dev = &pdev->dev;
1338 struct device_node *dn = pdev->dev.of_node;
1339 int err;
1340
1341 pdcs->intstatus = 0;
1342
1343 /* interrupt configuration */
1344 iowrite32(PDC_INTMASK, pdcs->pdc_reg_vbase + PDC_INTMASK_OFFSET);
1345 iowrite32(PDC_LAZY_INT, pdcs->pdc_reg_vbase + PDC_RCVLAZY0_OFFSET);
1346
1347 /* read irq from device tree */
1348 pdcs->pdc_irq = irq_of_parse_and_map(dn, 0);
1349 dev_dbg(dev, "pdc device %s irq %u for pdcs %p",
1350 dev_name(dev), pdcs->pdc_irq, pdcs);
1351 err = devm_request_threaded_irq(dev, pdcs->pdc_irq,
1352 pdc_irq_handler,
1353 pdc_irq_thread, 0, dev_name(dev), pdcs);
1354 if (err) {
1355 dev_err(dev, "threaded tx IRQ %u request failed with err %d\n",
1356 pdcs->pdc_irq, err);
1357 return err;
1358 }
1359 return PDC_SUCCESS;
1360}
1361
1362static const struct mbox_chan_ops pdc_mbox_chan_ops = {
1363 .send_data = pdc_send_data,
1364 .startup = pdc_startup,
1365 .shutdown = pdc_shutdown
1366};
1367
1368/**
1369 * pdc_mb_init() - Initialize the mailbox controller.
1370 * @pdcs: PDC state
1371 *
1372 * Each PDC is a mailbox controller. Each ringset is a mailbox channel. Kernel
1373 * driver only uses one ringset and thus one mb channel. PDC uses the transmit
1374 * complete interrupt to determine when a mailbox message has successfully been
1375 * transmitted.
1376 *
1377 * Return: 0 on success
1378 * < 0 if there is an allocation or registration failure
1379 */
1380static int pdc_mb_init(struct pdc_state *pdcs)
1381{
1382 struct device *dev = &pdcs->pdev->dev;
1383 struct mbox_controller *mbc;
1384 int chan_index;
1385 int err;
1386
1387 mbc = &pdcs->mbc;
1388 mbc->dev = dev;
1389 mbc->ops = &pdc_mbox_chan_ops;
1390 mbc->num_chans = 1;
1391 mbc->chans = devm_kcalloc(dev, mbc->num_chans, sizeof(*mbc->chans),
1392 GFP_KERNEL);
1393 if (!mbc->chans)
1394 return -ENOMEM;
1395
1396 mbc->txdone_irq = true;
1397 mbc->txdone_poll = false;
1398 for (chan_index = 0; chan_index < mbc->num_chans; chan_index++)
1399 mbc->chans[chan_index].con_priv = pdcs;
1400
1401 /* Register mailbox controller */
1402 err = mbox_controller_register(mbc);
1403 if (err) {
1404 dev_crit(dev,
1405 "Failed to register PDC mailbox controller. Error %d.",
1406 err);
1407 return err;
1408 }
1409 return 0;
1410}
1411
1412/**
1413 * pdc_dt_read() - Read application-specific data from device tree.
1414 * @pdev: Platform device
1415 * @pdcs: PDC state
1416 *
1417 * Reads the number of bytes of receive status that precede each received frame.
1418 * Reads whether transmit and received frames should be preceded by an 8-byte
1419 * BCM header.
1420 *
1421 * Return: 0 if successful
1422 * -ENODEV if device not available
1423 */
1424static int pdc_dt_read(struct platform_device *pdev, struct pdc_state *pdcs)
1425{
1426 struct device *dev = &pdev->dev;
1427 struct device_node *dn = pdev->dev.of_node;
1428 int err;
1429
1430 err = of_property_read_u32(dn, "brcm,rx-status-len",
1431 &pdcs->rx_status_len);
1432 if (err < 0)
1433 dev_err(dev,
1434 "%s failed to get DMA receive status length from device tree",
1435 __func__);
1436
1437 pdcs->use_bcm_hdr = of_property_read_bool(dn, "brcm,use-bcm-hdr");
1438
1439 return 0;
1440}
1441
1442/**
1443 * pdc_probe() - Probe function for PDC driver.
1444 * @pdev: PDC platform device
1445 *
1446 * Reserve and map register regions defined in device tree.
1447 * Allocate and initialize tx and rx DMA rings.
1448 * Initialize a mailbox controller for each PDC.
1449 *
1450 * Return: 0 if successful
1451 * < 0 if an error
1452 */
1453static int pdc_probe(struct platform_device *pdev)
1454{
1455 int err = 0;
1456 struct device *dev = &pdev->dev;
1457 struct resource *pdc_regs;
1458 struct pdc_state *pdcs;
1459
1460 /* PDC state for one SPU */
1461 pdcs = devm_kzalloc(dev, sizeof(*pdcs), GFP_KERNEL);
1462 if (!pdcs) {
1463 err = -ENOMEM;
1464 goto cleanup;
1465 }
1466
1467 spin_lock_init(&pdcs->pdc_lock);
1468 pdcs->pdev = pdev;
1469 platform_set_drvdata(pdev, pdcs);
1470 pdcs->pdc_idx = pdcg.num_spu;
1471 pdcg.num_spu++;
1472
1473 err = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
1474 if (err) {
1475 dev_warn(dev, "PDC device cannot perform DMA. Error %d.", err);
1476 goto cleanup;
1477 }
1478
1479 /* Create DMA pool for tx ring */
1480 pdcs->ring_pool = dma_pool_create("pdc rings", dev, PDC_RING_SIZE,
1481 RING_ALIGN, 0);
1482 if (!pdcs->ring_pool) {
1483 err = -ENOMEM;
1484 goto cleanup;
1485 }
1486
1487 err = pdc_dt_read(pdev, pdcs);
1488 if (err)
1489 goto cleanup_ring_pool;
1490
1491 pdc_regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1492 if (!pdc_regs) {
1493 err = -ENODEV;
1494 goto cleanup_ring_pool;
1495 }
a68b2166
RR		 1496 dev_dbg(dev, "PDC register region res.start = %pa, res.end = %pa",
1497 &pdc_regs->start, &pdc_regs->end);
a24532f8
RR		 1498
1499 pdcs->pdc_reg_vbase = devm_ioremap_resource(&pdev->dev, pdc_regs);
1500 if (IS_ERR(pdcs->pdc_reg_vbase)) {
1501 err = PTR_ERR(pdcs->pdc_reg_vbase);
1502 dev_err(&pdev->dev, "Failed to map registers: %d\n", err);
1503 goto cleanup_ring_pool;
1504 }
1505
1506 /* create rx buffer pool after dt read to know how big buffers are */
1507 err = pdc_rx_buf_pool_create(pdcs);
1508 if (err)
1509 goto cleanup_ring_pool;
1510
1511 pdc_hw_init(pdcs);
1512
1513 err = pdc_interrupts_init(pdcs);
1514 if (err)
1515 goto cleanup_buf_pool;
1516
1517 /* Initialize mailbox controller */
1518 err = pdc_mb_init(pdcs);
1519 if (err)
1520 goto cleanup_buf_pool;
1521
1522 pdcs->debugfs_stats = NULL;
1523 pdc_setup_debugfs(pdcs);
1524
1525 dev_dbg(dev, "pdc_probe() successful");
1526 return PDC_SUCCESS;
1527
1528cleanup_buf_pool:
1529 dma_pool_destroy(pdcs->rx_buf_pool);
1530
1531cleanup_ring_pool:
1532 dma_pool_destroy(pdcs->ring_pool);
1533
1534cleanup:
1535 return err;
1536}
1537
1538static int pdc_remove(struct platform_device *pdev)
1539{
1540 struct pdc_state *pdcs = platform_get_drvdata(pdev);
1541
1542 pdc_free_debugfs();
1543
9fb0f9ac
SL		 1544 pdc_hw_disable(pdcs);
1545
a24532f8
RR		 1546 mbox_controller_unregister(&pdcs->mbc);
1547
1548 dma_pool_destroy(pdcs->rx_buf_pool);
1549 dma_pool_destroy(pdcs->ring_pool);
1550 return 0;
1551}
1552
1553static const struct of_device_id pdc_mbox_of_match[] = {
1554 {.compatible = "brcm,iproc-pdc-mbox"},
1555 { /* sentinel */ }
1556};
1557MODULE_DEVICE_TABLE(of, pdc_mbox_of_match);
1558
1559static struct platform_driver pdc_mbox_driver = {
1560 .probe = pdc_probe,
1561 .remove = pdc_remove,
1562 .driver = {
1563 .name = "brcm-iproc-pdc-mbox",
1564 .of_match_table = of_match_ptr(pdc_mbox_of_match),
1565 },
1566};
1567module_platform_driver(pdc_mbox_driver);
1568
1569MODULE_AUTHOR("Rob Rice <rob.rice@broadcom.com>");
1570MODULE_DESCRIPTION("Broadcom PDC mailbox driver");
1571MODULE_LICENSE("GPL v2");
Linux 6.x block layer and io_uring tree(s)