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8e8e69d6 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
ee23d66a JB |
2 | /* |
3 | * Copyright (C) 2013-2015 Fujitsu Semiconductor Ltd. | |
4 | * Copyright (C) 2015 Linaro Ltd. | |
5 | * Author: Jassi Brar <jaswinder.singh@linaro.org> | |
ee23d66a JB |
6 | */ |
7 | ||
8 | #include <linux/interrupt.h> | |
9 | #include <linux/spinlock.h> | |
10 | #include <linux/mutex.h> | |
11 | #include <linux/delay.h> | |
12 | #include <linux/slab.h> | |
13 | #include <linux/err.h> | |
14 | #include <linux/io.h> | |
15 | #include <linux/module.h> | |
16 | #include <linux/amba/bus.h> | |
17 | #include <linux/mailbox_controller.h> | |
18 | ||
19 | #define INTR_STAT_OFS 0x0 | |
20 | #define INTR_SET_OFS 0x8 | |
21 | #define INTR_CLR_OFS 0x10 | |
22 | ||
23 | #define MHU_LP_OFFSET 0x0 | |
24 | #define MHU_HP_OFFSET 0x20 | |
25 | #define MHU_SEC_OFFSET 0x200 | |
26 | #define TX_REG_OFFSET 0x100 | |
27 | ||
28 | #define MHU_CHANS 3 | |
29 | ||
30 | struct mhu_link { | |
31 | unsigned irq; | |
32 | void __iomem *tx_reg; | |
33 | void __iomem *rx_reg; | |
34 | }; | |
35 | ||
36 | struct arm_mhu { | |
37 | void __iomem *base; | |
38 | struct mhu_link mlink[MHU_CHANS]; | |
39 | struct mbox_chan chan[MHU_CHANS]; | |
40 | struct mbox_controller mbox; | |
41 | }; | |
42 | ||
43 | static irqreturn_t mhu_rx_interrupt(int irq, void *p) | |
44 | { | |
45 | struct mbox_chan *chan = p; | |
46 | struct mhu_link *mlink = chan->con_priv; | |
47 | u32 val; | |
48 | ||
49 | val = readl_relaxed(mlink->rx_reg + INTR_STAT_OFS); | |
50 | if (!val) | |
51 | return IRQ_NONE; | |
52 | ||
53 | mbox_chan_received_data(chan, (void *)&val); | |
54 | ||
55 | writel_relaxed(val, mlink->rx_reg + INTR_CLR_OFS); | |
56 | ||
57 | return IRQ_HANDLED; | |
58 | } | |
59 | ||
60 | static bool mhu_last_tx_done(struct mbox_chan *chan) | |
61 | { | |
62 | struct mhu_link *mlink = chan->con_priv; | |
63 | u32 val = readl_relaxed(mlink->tx_reg + INTR_STAT_OFS); | |
64 | ||
65 | return (val == 0); | |
66 | } | |
67 | ||
68 | static int mhu_send_data(struct mbox_chan *chan, void *data) | |
69 | { | |
70 | struct mhu_link *mlink = chan->con_priv; | |
71 | u32 *arg = data; | |
72 | ||
73 | writel_relaxed(*arg, mlink->tx_reg + INTR_SET_OFS); | |
74 | ||
75 | return 0; | |
76 | } | |
77 | ||
78 | static int mhu_startup(struct mbox_chan *chan) | |
79 | { | |
80 | struct mhu_link *mlink = chan->con_priv; | |
81 | u32 val; | |
82 | int ret; | |
83 | ||
84 | val = readl_relaxed(mlink->tx_reg + INTR_STAT_OFS); | |
85 | writel_relaxed(val, mlink->tx_reg + INTR_CLR_OFS); | |
86 | ||
87 | ret = request_irq(mlink->irq, mhu_rx_interrupt, | |
88 | IRQF_SHARED, "mhu_link", chan); | |
89 | if (ret) { | |
90 | dev_err(chan->mbox->dev, | |
971bd8fa | 91 | "Unable to acquire IRQ %d\n", mlink->irq); |
ee23d66a JB |
92 | return ret; |
93 | } | |
94 | ||
95 | return 0; | |
96 | } | |
97 | ||
98 | static void mhu_shutdown(struct mbox_chan *chan) | |
99 | { | |
100 | struct mhu_link *mlink = chan->con_priv; | |
101 | ||
102 | free_irq(mlink->irq, chan); | |
103 | } | |
104 | ||
05ae7975 | 105 | static const struct mbox_chan_ops mhu_ops = { |
ee23d66a JB |
106 | .send_data = mhu_send_data, |
107 | .startup = mhu_startup, | |
108 | .shutdown = mhu_shutdown, | |
109 | .last_tx_done = mhu_last_tx_done, | |
110 | }; | |
111 | ||
112 | static int mhu_probe(struct amba_device *adev, const struct amba_id *id) | |
113 | { | |
114 | int i, err; | |
115 | struct arm_mhu *mhu; | |
116 | struct device *dev = &adev->dev; | |
117 | int mhu_reg[MHU_CHANS] = {MHU_LP_OFFSET, MHU_HP_OFFSET, MHU_SEC_OFFSET}; | |
118 | ||
119 | /* Allocate memory for device */ | |
120 | mhu = devm_kzalloc(dev, sizeof(*mhu), GFP_KERNEL); | |
121 | if (!mhu) | |
122 | return -ENOMEM; | |
123 | ||
124 | mhu->base = devm_ioremap_resource(dev, &adev->res); | |
125 | if (IS_ERR(mhu->base)) { | |
126 | dev_err(dev, "ioremap failed\n"); | |
127 | return PTR_ERR(mhu->base); | |
128 | } | |
129 | ||
130 | for (i = 0; i < MHU_CHANS; i++) { | |
131 | mhu->chan[i].con_priv = &mhu->mlink[i]; | |
132 | mhu->mlink[i].irq = adev->irq[i]; | |
133 | mhu->mlink[i].rx_reg = mhu->base + mhu_reg[i]; | |
134 | mhu->mlink[i].tx_reg = mhu->mlink[i].rx_reg + TX_REG_OFFSET; | |
135 | } | |
136 | ||
137 | mhu->mbox.dev = dev; | |
138 | mhu->mbox.chans = &mhu->chan[0]; | |
139 | mhu->mbox.num_chans = MHU_CHANS; | |
140 | mhu->mbox.ops = &mhu_ops; | |
141 | mhu->mbox.txdone_irq = false; | |
142 | mhu->mbox.txdone_poll = true; | |
86e488ad | 143 | mhu->mbox.txpoll_period = 1; |
ee23d66a JB |
144 | |
145 | amba_set_drvdata(adev, mhu); | |
146 | ||
6aba2f4a | 147 | err = devm_mbox_controller_register(dev, &mhu->mbox); |
ee23d66a JB |
148 | if (err) { |
149 | dev_err(dev, "Failed to register mailboxes %d\n", err); | |
150 | return err; | |
151 | } | |
152 | ||
153 | dev_info(dev, "ARM MHU Mailbox registered\n"); | |
154 | return 0; | |
155 | } | |
156 | ||
ee23d66a JB |
157 | static struct amba_id mhu_ids[] = { |
158 | { | |
159 | .id = 0x1bb098, | |
160 | .mask = 0xffffff, | |
161 | }, | |
162 | { 0, 0 }, | |
163 | }; | |
164 | MODULE_DEVICE_TABLE(amba, mhu_ids); | |
165 | ||
166 | static struct amba_driver arm_mhu_driver = { | |
167 | .drv = { | |
168 | .name = "mhu", | |
169 | }, | |
170 | .id_table = mhu_ids, | |
171 | .probe = mhu_probe, | |
ee23d66a JB |
172 | }; |
173 | module_amba_driver(arm_mhu_driver); | |
174 | ||
175 | MODULE_LICENSE("GPL v2"); | |
176 | MODULE_DESCRIPTION("ARM MHU Driver"); | |
177 | MODULE_AUTHOR("Jassi Brar <jassisinghbrar@gmail.com>"); |