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8e8e69d6 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
ee23d66a JB |
2 | /* |
3 | * Copyright (C) 2013-2015 Fujitsu Semiconductor Ltd. | |
4 | * Copyright (C) 2015 Linaro Ltd. | |
5 | * Author: Jassi Brar <jaswinder.singh@linaro.org> | |
ee23d66a JB |
6 | */ |
7 | ||
06c182c3 SH |
8 | #include <linux/amba/bus.h> |
9 | #include <linux/device.h> | |
ee23d66a | 10 | #include <linux/err.h> |
06c182c3 | 11 | #include <linux/interrupt.h> |
ee23d66a | 12 | #include <linux/io.h> |
ee23d66a | 13 | #include <linux/mailbox_controller.h> |
06c182c3 | 14 | #include <linux/module.h> |
ee23d66a JB |
15 | |
16 | #define INTR_STAT_OFS 0x0 | |
17 | #define INTR_SET_OFS 0x8 | |
18 | #define INTR_CLR_OFS 0x10 | |
19 | ||
20 | #define MHU_LP_OFFSET 0x0 | |
21 | #define MHU_HP_OFFSET 0x20 | |
22 | #define MHU_SEC_OFFSET 0x200 | |
23 | #define TX_REG_OFFSET 0x100 | |
24 | ||
25 | #define MHU_CHANS 3 | |
26 | ||
27 | struct mhu_link { | |
28 | unsigned irq; | |
29 | void __iomem *tx_reg; | |
30 | void __iomem *rx_reg; | |
31 | }; | |
32 | ||
33 | struct arm_mhu { | |
34 | void __iomem *base; | |
35 | struct mhu_link mlink[MHU_CHANS]; | |
36 | struct mbox_chan chan[MHU_CHANS]; | |
37 | struct mbox_controller mbox; | |
38 | }; | |
39 | ||
40 | static irqreturn_t mhu_rx_interrupt(int irq, void *p) | |
41 | { | |
42 | struct mbox_chan *chan = p; | |
43 | struct mhu_link *mlink = chan->con_priv; | |
44 | u32 val; | |
45 | ||
46 | val = readl_relaxed(mlink->rx_reg + INTR_STAT_OFS); | |
47 | if (!val) | |
48 | return IRQ_NONE; | |
49 | ||
50 | mbox_chan_received_data(chan, (void *)&val); | |
51 | ||
52 | writel_relaxed(val, mlink->rx_reg + INTR_CLR_OFS); | |
53 | ||
54 | return IRQ_HANDLED; | |
55 | } | |
56 | ||
57 | static bool mhu_last_tx_done(struct mbox_chan *chan) | |
58 | { | |
59 | struct mhu_link *mlink = chan->con_priv; | |
60 | u32 val = readl_relaxed(mlink->tx_reg + INTR_STAT_OFS); | |
61 | ||
62 | return (val == 0); | |
63 | } | |
64 | ||
65 | static int mhu_send_data(struct mbox_chan *chan, void *data) | |
66 | { | |
67 | struct mhu_link *mlink = chan->con_priv; | |
68 | u32 *arg = data; | |
69 | ||
70 | writel_relaxed(*arg, mlink->tx_reg + INTR_SET_OFS); | |
71 | ||
72 | return 0; | |
73 | } | |
74 | ||
75 | static int mhu_startup(struct mbox_chan *chan) | |
76 | { | |
77 | struct mhu_link *mlink = chan->con_priv; | |
78 | u32 val; | |
79 | int ret; | |
80 | ||
81 | val = readl_relaxed(mlink->tx_reg + INTR_STAT_OFS); | |
82 | writel_relaxed(val, mlink->tx_reg + INTR_CLR_OFS); | |
83 | ||
84 | ret = request_irq(mlink->irq, mhu_rx_interrupt, | |
85 | IRQF_SHARED, "mhu_link", chan); | |
86 | if (ret) { | |
87 | dev_err(chan->mbox->dev, | |
971bd8fa | 88 | "Unable to acquire IRQ %d\n", mlink->irq); |
ee23d66a JB |
89 | return ret; |
90 | } | |
91 | ||
92 | return 0; | |
93 | } | |
94 | ||
95 | static void mhu_shutdown(struct mbox_chan *chan) | |
96 | { | |
97 | struct mhu_link *mlink = chan->con_priv; | |
98 | ||
99 | free_irq(mlink->irq, chan); | |
100 | } | |
101 | ||
05ae7975 | 102 | static const struct mbox_chan_ops mhu_ops = { |
ee23d66a JB |
103 | .send_data = mhu_send_data, |
104 | .startup = mhu_startup, | |
105 | .shutdown = mhu_shutdown, | |
106 | .last_tx_done = mhu_last_tx_done, | |
107 | }; | |
108 | ||
109 | static int mhu_probe(struct amba_device *adev, const struct amba_id *id) | |
110 | { | |
111 | int i, err; | |
112 | struct arm_mhu *mhu; | |
113 | struct device *dev = &adev->dev; | |
114 | int mhu_reg[MHU_CHANS] = {MHU_LP_OFFSET, MHU_HP_OFFSET, MHU_SEC_OFFSET}; | |
115 | ||
116 | /* Allocate memory for device */ | |
117 | mhu = devm_kzalloc(dev, sizeof(*mhu), GFP_KERNEL); | |
118 | if (!mhu) | |
119 | return -ENOMEM; | |
120 | ||
121 | mhu->base = devm_ioremap_resource(dev, &adev->res); | |
122 | if (IS_ERR(mhu->base)) { | |
123 | dev_err(dev, "ioremap failed\n"); | |
124 | return PTR_ERR(mhu->base); | |
125 | } | |
126 | ||
127 | for (i = 0; i < MHU_CHANS; i++) { | |
128 | mhu->chan[i].con_priv = &mhu->mlink[i]; | |
129 | mhu->mlink[i].irq = adev->irq[i]; | |
130 | mhu->mlink[i].rx_reg = mhu->base + mhu_reg[i]; | |
131 | mhu->mlink[i].tx_reg = mhu->mlink[i].rx_reg + TX_REG_OFFSET; | |
132 | } | |
133 | ||
134 | mhu->mbox.dev = dev; | |
135 | mhu->mbox.chans = &mhu->chan[0]; | |
136 | mhu->mbox.num_chans = MHU_CHANS; | |
137 | mhu->mbox.ops = &mhu_ops; | |
138 | mhu->mbox.txdone_irq = false; | |
139 | mhu->mbox.txdone_poll = true; | |
86e488ad | 140 | mhu->mbox.txpoll_period = 1; |
ee23d66a JB |
141 | |
142 | amba_set_drvdata(adev, mhu); | |
143 | ||
6aba2f4a | 144 | err = devm_mbox_controller_register(dev, &mhu->mbox); |
ee23d66a JB |
145 | if (err) { |
146 | dev_err(dev, "Failed to register mailboxes %d\n", err); | |
147 | return err; | |
148 | } | |
149 | ||
150 | dev_info(dev, "ARM MHU Mailbox registered\n"); | |
151 | return 0; | |
152 | } | |
153 | ||
ee23d66a JB |
154 | static struct amba_id mhu_ids[] = { |
155 | { | |
156 | .id = 0x1bb098, | |
157 | .mask = 0xffffff, | |
158 | }, | |
159 | { 0, 0 }, | |
160 | }; | |
161 | MODULE_DEVICE_TABLE(amba, mhu_ids); | |
162 | ||
163 | static struct amba_driver arm_mhu_driver = { | |
164 | .drv = { | |
165 | .name = "mhu", | |
166 | }, | |
167 | .id_table = mhu_ids, | |
168 | .probe = mhu_probe, | |
ee23d66a JB |
169 | }; |
170 | module_amba_driver(arm_mhu_driver); | |
171 | ||
172 | MODULE_LICENSE("GPL v2"); | |
173 | MODULE_DESCRIPTION("ARM MHU Driver"); | |
174 | MODULE_AUTHOR("Jassi Brar <jassisinghbrar@gmail.com>"); |