Commit | Line | Data |
---|---|---|
30058677 RH |
1 | menuconfig MAILBOX |
2 | bool "Mailbox Hardware Support" | |
3 | help | |
4 | Mailbox is a framework to control hardware communication between | |
5 | on-chip processors through queued messages and interrupt driven | |
6 | signals. Say Y if your platform supports hardware mailboxes. | |
7 | ||
8 | if MAILBOX | |
ee23d66a JB |
9 | |
10 | config ARM_MHU | |
11 | tristate "ARM MHU Mailbox" | |
12 | depends on ARM_AMBA | |
13 | help | |
14 | Say Y here if you want to build the ARM MHU controller driver. | |
15 | The controller has 3 mailbox channels, the last of which can be | |
16 | used in Secure mode only. | |
17 | ||
ad3a212c NA |
18 | config PLATFORM_MHU |
19 | tristate "Platform MHU Mailbox" | |
20 | depends on OF | |
21 | depends on HAS_IOMEM | |
22 | help | |
23 | Say Y here if you want to build a platform specific variant MHU | |
24 | controller driver. | |
25 | The controller has a maximum of 3 mailbox channels, the last of | |
26 | which can be used in Secure mode only. | |
27 | ||
30058677 RH |
28 | config PL320_MBOX |
29 | bool "ARM PL320 Mailbox" | |
30 | depends on ARM_AMBA | |
31 | help | |
32 | An implementation of the ARM PL320 Interprocessor Communication | |
33 | Mailbox (IPCM), tailored for the Calxeda Highbank. It is used to | |
34 | send short messages between Highbank's A9 cores and the EnergyCore | |
35 | Management Engine, primarily for cpufreq. Say Y here if you want | |
36 | to use the PL320 IPCM support. | |
37 | ||
c869c75c SA |
38 | config OMAP2PLUS_MBOX |
39 | tristate "OMAP2+ Mailbox framework support" | |
40 | depends on ARCH_OMAP2PLUS | |
c869c75c SA |
41 | help |
42 | Mailbox implementation for OMAP family chips with hardware for | |
43 | interprocessor communication involving DSP, IVA1.0 and IVA2 in | |
44 | OMAP2/3; or IPU, IVA HD and DSP in OMAP4/5. Say Y here if you | |
45 | want to use OMAP2+ Mailbox framework support. | |
46 | ||
47 | config OMAP_MBOX_KFIFO_SIZE | |
48 | int "Mailbox kfifo default buffer size (bytes)" | |
79859094 | 49 | depends on OMAP2PLUS_MBOX |
c869c75c SA |
50 | default 256 |
51 | help | |
52 | Specify the default size of mailbox's kfifo buffers (bytes). | |
53 | This can also be changed at runtime (via the mbox_kfifo_size | |
54 | module parameter). | |
86c22f8c | 55 | |
f70ed3b5 CW |
56 | config ROCKCHIP_MBOX |
57 | bool "Rockchip Soc Intergrated Mailbox Support" | |
58 | depends on ARCH_ROCKCHIP || COMPILE_TEST | |
59 | help | |
60 | This driver provides support for inter-processor communication | |
61 | between CPU cores and MCU processor on Some Rockchip SOCs. | |
62 | Please check it that the Soc you use have Mailbox hardware. | |
63 | Say Y here if you want to use the Rockchip Mailbox support. | |
64 | ||
86c22f8c AC |
65 | config PCC |
66 | bool "Platform Communication Channel Driver" | |
67 | depends on ACPI | |
b6fc6072 | 68 | default n |
86c22f8c AC |
69 | help |
70 | ACPI 5.0+ spec defines a generic mode of communication | |
71 | between the OS and a platform such as the BMC. This medium | |
72 | (PCC) is typically used by CPPC (ACPI CPU Performance management), | |
73 | RAS (ACPI reliability protocol) and MPST (ACPI Memory power | |
74 | states). Select this driver if your platform implements the | |
75 | PCC clients mentioned above. | |
76 | ||
f62092f6 LFT |
77 | config ALTERA_MBOX |
78 | tristate "Altera Mailbox" | |
59dd3f02 | 79 | depends on HAS_IOMEM |
f62092f6 LFT |
80 | help |
81 | An implementation of the Altera Mailbox soft core. It is used | |
82 | to send message between processors. Say Y here if you want to use the | |
83 | Altera mailbox support. | |
0bae6af6 LR |
84 | |
85 | config BCM2835_MBOX | |
86 | tristate "BCM2835 Mailbox" | |
87 | depends on ARCH_BCM2835 | |
88 | help | |
89 | An implementation of the BCM2385 Mailbox. It is used to invoke | |
90 | the services of the Videocore. Say Y here if you want to use the | |
91 | BCM2835 Mailbox. | |
92 | ||
9ef4546c LJ |
93 | config STI_MBOX |
94 | tristate "STI Mailbox framework support" | |
95 | depends on ARCH_STI && OF | |
96 | help | |
97 | Mailbox implementation for STMicroelectonics family chips with | |
98 | hardware for interprocessor communication. | |
99 | ||
aace66b1 NM |
100 | config TI_MESSAGE_MANAGER |
101 | tristate "Texas Instruments Message Manager Driver" | |
102 | depends on ARCH_KEYSTONE | |
103 | help | |
104 | An implementation of Message Manager slave driver for Keystone | |
105 | architecture SoCs from Texas Instruments. Message Manager is a | |
106 | communication entity found on few of Texas Instrument's keystone | |
107 | architecture SoCs. These may be used for communication between | |
108 | multiple processors within the SoC. Select this driver if your | |
109 | platform has support for the hardware block. | |
110 | ||
41c0e939 | 111 | config HI3660_MBOX |
f83d1cfc DL |
112 | tristate "Hi3660 Mailbox" if EXPERT |
113 | depends on (ARCH_HISI || COMPILE_TEST) | |
114 | depends on OF | |
115 | default ARCH_HISI | |
41c0e939 KZ |
116 | help |
117 | An implementation of the hi3660 mailbox. It is used to send message | |
118 | between application processors and other processors/MCU/DSP. Select | |
119 | Y here if you want to use Hi3660 mailbox controller. | |
120 | ||
9c384189 | 121 | config HI6220_MBOX |
f83d1cfc DL |
122 | tristate "Hi6220 Mailbox" if EXPERT |
123 | depends on (ARCH_HISI || COMPILE_TEST) | |
124 | depends on OF | |
125 | default ARCH_HISI | |
9c384189 LY |
126 | help |
127 | An implementation of the hi6220 mailbox. It is used to send message | |
128 | between application processors and MCU. Say Y here if you want to | |
129 | build Hi6220 mailbox controller driver. | |
130 | ||
8ea4484d LJ |
131 | config MAILBOX_TEST |
132 | tristate "Mailbox Test Client" | |
133 | depends on OF | |
65d3b04a | 134 | depends on HAS_IOMEM |
8ea4484d LJ |
135 | help |
136 | Test client to help with testing new Controller driver | |
137 | implementations. | |
138 | ||
25bfee16 BA |
139 | config QCOM_APCS_IPC |
140 | tristate "Qualcomm APCS IPC driver" | |
141 | depends on ARCH_QCOM || COMPILE_TEST | |
142 | help | |
143 | Say y here to enable support for the APCS IPC mailbox driver, | |
144 | providing an interface for invoking the inter-process communication | |
145 | signals from the application processor to other masters. | |
146 | ||
0fe88461 TR |
147 | config TEGRA_HSP_MBOX |
148 | bool "Tegra HSP (Hardware Synchronization Primitives) Driver" | |
85bd2de4 | 149 | depends on ARCH_TEGRA |
0fe88461 TR |
150 | help |
151 | The Tegra HSP driver is used for the interprocessor communication | |
152 | between different remote processors and host processors on Tegra186 | |
153 | and later SoCs. Say Y here if you want to have this support. | |
154 | If unsure say N. | |
155 | ||
f700e84f DD |
156 | config XGENE_SLIMPRO_MBOX |
157 | tristate "APM SoC X-Gene SLIMpro Mailbox Controller" | |
158 | depends on ARCH_XGENE | |
159 | help | |
160 | An implementation of the APM X-Gene Interprocessor Communication | |
161 | Mailbox (IPCM) between the ARM 64-bit cores and SLIMpro controller. | |
162 | It is used to send short messages between ARM64-bit cores and | |
163 | the SLIMpro Management Engine, primarily for PM. Say Y here if you | |
164 | want to use the APM X-Gene SLIMpro IPCM support. | |
a24532f8 RR |
165 | |
166 | config BCM_PDC_MBOX | |
fc2041c5 SL |
167 | tristate "Broadcom FlexSparx DMA Mailbox" |
168 | depends on ARCH_BCM_IPROC || COMPILE_TEST | |
a24532f8 | 169 | help |
fc2041c5 | 170 | Mailbox implementation for the Broadcom FlexSparx DMA ring manager, |
a24532f8 | 171 | which provides access to various offload engines on Broadcom |
fc2041c5 | 172 | SoCs, including FA2/FA+ on Northstar Plus and PDC on Northstar 2. |
dbc049ee AP |
173 | |
174 | config BCM_FLEXRM_MBOX | |
175 | tristate "Broadcom FlexRM Mailbox" | |
73874913 | 176 | depends on ARM64 |
8f82121d | 177 | depends on ARCH_BCM_IPROC || COMPILE_TEST |
dbc049ee | 178 | select GENERIC_MSI_IRQ_DOMAIN |
22d28b0f | 179 | default m if ARCH_BCM_IPROC |
dbc049ee AP |
180 | help |
181 | Mailbox implementation of the Broadcom FlexRM ring manager, | |
182 | which provides access to various offload engines on Broadcom | |
183 | SoCs. Say Y here if you want to use the Broadcom FlexRM. | |
ffbded7d FD |
184 | |
185 | config STM32_IPCC | |
186 | tristate "STM32 IPCC Mailbox" | |
187 | depends on MACH_STM32MP157 | |
188 | help | |
189 | Mailbox implementation for STMicroelectonics STM32 family chips | |
190 | with hardware for Inter-Processor Communication Controller (IPCC) | |
191 | between processors. Say Y here if you want to have this support. | |
30058677 | 192 | endif |