Commit | Line | Data |
---|---|---|
625efab1 JS |
1 | /* |
2 | * Copyright (C) 2006, Rusty Russell <rusty@rustcorp.com.au> IBM Corporation. | |
3 | * Copyright (C) 2007, Jes Sorensen <jes@sgi.com> SGI. | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License as published by | |
7 | * the Free Software Foundation; either version 2 of the License, or | |
8 | * (at your option) any later version. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, but | |
11 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or | |
13 | * NON INFRINGEMENT. See the GNU General Public License for more | |
14 | * details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, write to the Free Software | |
18 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
19 | */ | |
a6bd8e13 RR |
20 | /*P:450 This file contains the x86-specific lguest code. It used to be all |
21 | * mixed in with drivers/lguest/core.c but several foolhardy code slashers | |
22 | * wrestled most of the dependencies out to here in preparation for porting | |
23 | * lguest to other architectures (see what I mean by foolhardy?). | |
24 | * | |
25 | * This also contains a couple of non-obvious setup and teardown pieces which | |
26 | * were implemented after days of debugging pain. :*/ | |
625efab1 JS |
27 | #include <linux/kernel.h> |
28 | #include <linux/start_kernel.h> | |
29 | #include <linux/string.h> | |
30 | #include <linux/console.h> | |
31 | #include <linux/screen_info.h> | |
32 | #include <linux/irq.h> | |
33 | #include <linux/interrupt.h> | |
34 | #include <linux/clocksource.h> | |
35 | #include <linux/clockchips.h> | |
36 | #include <linux/cpu.h> | |
37 | #include <linux/lguest.h> | |
38 | #include <linux/lguest_launcher.h> | |
625efab1 JS |
39 | #include <asm/paravirt.h> |
40 | #include <asm/param.h> | |
41 | #include <asm/page.h> | |
42 | #include <asm/pgtable.h> | |
43 | #include <asm/desc.h> | |
44 | #include <asm/setup.h> | |
45 | #include <asm/lguest.h> | |
46 | #include <asm/uaccess.h> | |
47 | #include <asm/i387.h> | |
48 | #include "../lg.h" | |
49 | ||
50 | static int cpu_had_pge; | |
51 | ||
52 | static struct { | |
53 | unsigned long offset; | |
54 | unsigned short segment; | |
55 | } lguest_entry; | |
56 | ||
57 | /* Offset from where switcher.S was compiled to where we've copied it */ | |
58 | static unsigned long switcher_offset(void) | |
59 | { | |
60 | return SWITCHER_ADDR - (unsigned long)start_switcher_text; | |
61 | } | |
62 | ||
63 | /* This cpu's struct lguest_pages. */ | |
64 | static struct lguest_pages *lguest_pages(unsigned int cpu) | |
65 | { | |
66 | return &(((struct lguest_pages *) | |
67 | (SWITCHER_ADDR + SHARED_SWITCHER_PAGES*PAGE_SIZE))[cpu]); | |
68 | } | |
69 | ||
c40a9f47 | 70 | static DEFINE_PER_CPU(struct lg_cpu *, last_cpu); |
625efab1 JS |
71 | |
72 | /*S:010 | |
e1e72965 | 73 | * We approach the Switcher. |
625efab1 JS |
74 | * |
75 | * Remember that each CPU has two pages which are visible to the Guest when it | |
76 | * runs on that CPU. This has to contain the state for that Guest: we copy the | |
77 | * state in just before we run the Guest. | |
78 | * | |
79 | * Each Guest has "changed" flags which indicate what has changed in the Guest | |
80 | * since it last ran. We saw this set in interrupts_and_traps.c and | |
81 | * segments.c. | |
82 | */ | |
d0953d42 | 83 | static void copy_in_guest_info(struct lg_cpu *cpu, struct lguest_pages *pages) |
625efab1 JS |
84 | { |
85 | /* Copying all this data can be quite expensive. We usually run the | |
86 | * same Guest we ran last time (and that Guest hasn't run anywhere else | |
87 | * meanwhile). If that's not the case, we pretend everything in the | |
88 | * Guest has changed. */ | |
f34f8c5f | 89 | if (__get_cpu_var(last_cpu) != cpu || cpu->last_pages != pages) { |
c40a9f47 | 90 | __get_cpu_var(last_cpu) = cpu; |
f34f8c5f | 91 | cpu->last_pages = pages; |
ae3749dc | 92 | cpu->changed = CHANGED_ALL; |
625efab1 JS |
93 | } |
94 | ||
95 | /* These copies are pretty cheap, so we do them unconditionally: */ | |
96 | /* Save the current Host top-level page directory. */ | |
97 | pages->state.host_cr3 = __pa(current->mm->pgd); | |
98 | /* Set up the Guest's page tables to see this CPU's pages (and no | |
99 | * other CPU's pages). */ | |
0c78441c | 100 | map_switcher_in_guest(cpu, pages); |
625efab1 JS |
101 | /* Set up the two "TSS" members which tell the CPU what stack to use |
102 | * for traps which do directly into the Guest (ie. traps at privilege | |
103 | * level 1). */ | |
e95035c6 | 104 | pages->state.guest_tss.sp1 = cpu->esp1; |
4665ac8e | 105 | pages->state.guest_tss.ss1 = cpu->ss1; |
625efab1 JS |
106 | |
107 | /* Copy direct-to-Guest trap entries. */ | |
ae3749dc | 108 | if (cpu->changed & CHANGED_IDT) |
fc708b3e | 109 | copy_traps(cpu, pages->state.guest_idt, default_idt_entries); |
625efab1 JS |
110 | |
111 | /* Copy all GDT entries which the Guest can change. */ | |
ae3749dc | 112 | if (cpu->changed & CHANGED_GDT) |
fc708b3e | 113 | copy_gdt(cpu, pages->state.guest_gdt); |
625efab1 | 114 | /* If only the TLS entries have changed, copy them. */ |
ae3749dc | 115 | else if (cpu->changed & CHANGED_GDT_TLS) |
fc708b3e | 116 | copy_gdt_tls(cpu, pages->state.guest_gdt); |
625efab1 JS |
117 | |
118 | /* Mark the Guest as unchanged for next time. */ | |
ae3749dc | 119 | cpu->changed = 0; |
625efab1 JS |
120 | } |
121 | ||
122 | /* Finally: the code to actually call into the Switcher to run the Guest. */ | |
d0953d42 | 123 | static void run_guest_once(struct lg_cpu *cpu, struct lguest_pages *pages) |
625efab1 JS |
124 | { |
125 | /* This is a dummy value we need for GCC's sake. */ | |
126 | unsigned int clobber; | |
127 | ||
128 | /* Copy the guest-specific information into this CPU's "struct | |
129 | * lguest_pages". */ | |
d0953d42 | 130 | copy_in_guest_info(cpu, pages); |
625efab1 JS |
131 | |
132 | /* Set the trap number to 256 (impossible value). If we fault while | |
133 | * switching to the Guest (bad segment registers or bug), this will | |
134 | * cause us to abort the Guest. */ | |
a53a35a8 | 135 | cpu->regs->trapnum = 256; |
625efab1 JS |
136 | |
137 | /* Now: we push the "eflags" register on the stack, then do an "lcall". | |
138 | * This is how we change from using the kernel code segment to using | |
139 | * the dedicated lguest code segment, as well as jumping into the | |
140 | * Switcher. | |
141 | * | |
142 | * The lcall also pushes the old code segment (KERNEL_CS) onto the | |
143 | * stack, then the address of this call. This stack layout happens to | |
e1e72965 | 144 | * exactly match the stack layout created by an interrupt... */ |
625efab1 JS |
145 | asm volatile("pushf; lcall *lguest_entry" |
146 | /* This is how we tell GCC that %eax ("a") and %ebx ("b") | |
147 | * are changed by this routine. The "=" means output. */ | |
148 | : "=a"(clobber), "=b"(clobber) | |
149 | /* %eax contains the pages pointer. ("0" refers to the | |
150 | * 0-th argument above, ie "a"). %ebx contains the | |
151 | * physical address of the Guest's top-level page | |
152 | * directory. */ | |
382ac6b3 | 153 | : "0"(pages), "1"(__pa(cpu->lg->pgdirs[cpu->cpu_pgd].pgdir)) |
625efab1 JS |
154 | /* We tell gcc that all these registers could change, |
155 | * which means we don't have to save and restore them in | |
156 | * the Switcher. */ | |
157 | : "memory", "%edx", "%ecx", "%edi", "%esi"); | |
158 | } | |
159 | /*:*/ | |
160 | ||
e1e72965 RR |
161 | /*M:002 There are hooks in the scheduler which we can register to tell when we |
162 | * get kicked off the CPU (preempt_notifier_register()). This would allow us | |
163 | * to lazily disable SYSENTER which would regain some performance, and should | |
164 | * also simplify copy_in_guest_info(). Note that we'd still need to restore | |
165 | * things when we exit to Launcher userspace, but that's fairly easy. | |
166 | * | |
a6bd8e13 RR |
167 | * We could also try using this hooks for PGE, but that might be too expensive. |
168 | * | |
e1e72965 RR |
169 | * The hooks were designed for KVM, but we can also put them to good use. :*/ |
170 | ||
625efab1 JS |
171 | /*H:040 This is the i386-specific code to setup and run the Guest. Interrupts |
172 | * are disabled: we own the CPU. */ | |
d0953d42 | 173 | void lguest_arch_run_guest(struct lg_cpu *cpu) |
625efab1 | 174 | { |
e1e72965 RR |
175 | /* Remember the awfully-named TS bit? If the Guest has asked to set it |
176 | * we set it now, so we can trap and pass that trap to the Guest if it | |
177 | * uses the FPU. */ | |
4665ac8e | 178 | if (cpu->ts) |
54481cf8 | 179 | unlazy_fpu(current); |
625efab1 | 180 | |
e1e72965 RR |
181 | /* SYSENTER is an optimized way of doing system calls. We can't allow |
182 | * it because it always jumps to privilege level 0. A normal Guest | |
183 | * won't try it because we don't advertise it in CPUID, but a malicious | |
184 | * Guest (or malicious Guest userspace program) could, so we tell the | |
185 | * CPU to disable it before running the Guest. */ | |
625efab1 JS |
186 | if (boot_cpu_has(X86_FEATURE_SEP)) |
187 | wrmsr(MSR_IA32_SYSENTER_CS, 0, 0); | |
188 | ||
e1e72965 RR |
189 | /* Now we actually run the Guest. It will return when something |
190 | * interesting happens, and we can examine its registers to see what it | |
191 | * was doing. */ | |
d0953d42 | 192 | run_guest_once(cpu, lguest_pages(raw_smp_processor_id())); |
625efab1 | 193 | |
a6bd8e13 | 194 | /* Note that the "regs" structure contains two extra entries which are |
e1e72965 RR |
195 | * not really registers: a trap number which says what interrupt or |
196 | * trap made the switcher code come back, and an error code which some | |
197 | * traps set. */ | |
625efab1 | 198 | |
54481cf8 SS |
199 | /* Restore SYSENTER if it's supposed to be on. */ |
200 | if (boot_cpu_has(X86_FEATURE_SEP)) | |
201 | wrmsr(MSR_IA32_SYSENTER_CS, __KERNEL_CS, 0); | |
202 | ||
e1e72965 RR |
203 | /* If the Guest page faulted, then the cr2 register will tell us the |
204 | * bad virtual address. We have to grab this now, because once we | |
205 | * re-enable interrupts an interrupt could fault and thus overwrite | |
206 | * cr2, or we could even move off to a different CPU. */ | |
a53a35a8 | 207 | if (cpu->regs->trapnum == 14) |
fc708b3e | 208 | cpu->arch.last_pagefault = read_cr2(); |
625efab1 | 209 | /* Similarly, if we took a trap because the Guest used the FPU, |
54481cf8 SS |
210 | * we have to restore the FPU it expects to see. |
211 | * math_state_restore() may sleep and we may even move off to | |
212 | * a different CPU. So all the critical stuff should be done | |
213 | * before this. */ | |
a53a35a8 | 214 | else if (cpu->regs->trapnum == 7) |
625efab1 | 215 | math_state_restore(); |
625efab1 JS |
216 | } |
217 | ||
e1e72965 RR |
218 | /*H:130 Now we've examined the hypercall code; our Guest can make requests. |
219 | * Our Guest is usually so well behaved; it never tries to do things it isn't | |
220 | * allowed to, and uses hypercalls instead. Unfortunately, Linux's paravirtual | |
221 | * infrastructure isn't quite complete, because it doesn't contain replacements | |
222 | * for the Intel I/O instructions. As a result, the Guest sometimes fumbles | |
223 | * across one during the boot process as it probes for various things which are | |
224 | * usually attached to a PC. | |
625efab1 | 225 | * |
e1e72965 | 226 | * When the Guest uses one of these instructions, we get a trap (General |
625efab1 JS |
227 | * Protection Fault) and come here. We see if it's one of those troublesome |
228 | * instructions and skip over it. We return true if we did. */ | |
a3863f68 | 229 | static int emulate_insn(struct lg_cpu *cpu) |
625efab1 JS |
230 | { |
231 | u8 insn; | |
232 | unsigned int insnlen = 0, in = 0, shift = 0; | |
233 | /* The eip contains the *virtual* address of the Guest's instruction: | |
234 | * guest_pa just subtracts the Guest's page_offset. */ | |
1713608f | 235 | unsigned long physaddr = guest_pa(cpu, cpu->regs->eip); |
625efab1 | 236 | |
47436aa4 RR |
237 | /* This must be the Guest kernel trying to do something, not userspace! |
238 | * The bottom two bits of the CS segment register are the privilege | |
239 | * level. */ | |
a53a35a8 | 240 | if ((cpu->regs->cs & 3) != GUEST_PL) |
625efab1 JS |
241 | return 0; |
242 | ||
243 | /* Decoding x86 instructions is icky. */ | |
382ac6b3 | 244 | insn = lgread(cpu, physaddr, u8); |
625efab1 JS |
245 | |
246 | /* 0x66 is an "operand prefix". It means it's using the upper 16 bits | |
247 | of the eax register. */ | |
248 | if (insn == 0x66) { | |
249 | shift = 16; | |
250 | /* The instruction is 1 byte so far, read the next byte. */ | |
251 | insnlen = 1; | |
382ac6b3 | 252 | insn = lgread(cpu, physaddr + insnlen, u8); |
625efab1 JS |
253 | } |
254 | ||
255 | /* We can ignore the lower bit for the moment and decode the 4 opcodes | |
256 | * we need to emulate. */ | |
257 | switch (insn & 0xFE) { | |
258 | case 0xE4: /* in <next byte>,%al */ | |
259 | insnlen += 2; | |
260 | in = 1; | |
261 | break; | |
262 | case 0xEC: /* in (%dx),%al */ | |
263 | insnlen += 1; | |
264 | in = 1; | |
265 | break; | |
266 | case 0xE6: /* out %al,<next byte> */ | |
267 | insnlen += 2; | |
268 | break; | |
269 | case 0xEE: /* out %al,(%dx) */ | |
270 | insnlen += 1; | |
271 | break; | |
272 | default: | |
273 | /* OK, we don't know what this is, can't emulate. */ | |
274 | return 0; | |
275 | } | |
276 | ||
277 | /* If it was an "IN" instruction, they expect the result to be read | |
278 | * into %eax, so we change %eax. We always return all-ones, which | |
279 | * traditionally means "there's nothing there". */ | |
280 | if (in) { | |
281 | /* Lower bit tells is whether it's a 16 or 32 bit access */ | |
282 | if (insn & 0x1) | |
a53a35a8 | 283 | cpu->regs->eax = 0xFFFFFFFF; |
625efab1 | 284 | else |
a53a35a8 | 285 | cpu->regs->eax |= (0xFFFF << shift); |
625efab1 JS |
286 | } |
287 | /* Finally, we've "done" the instruction, so move past it. */ | |
a53a35a8 | 288 | cpu->regs->eip += insnlen; |
625efab1 JS |
289 | /* Success! */ |
290 | return 1; | |
291 | } | |
292 | ||
293 | /*H:050 Once we've re-enabled interrupts, we look at why the Guest exited. */ | |
73044f05 | 294 | void lguest_arch_handle_trap(struct lg_cpu *cpu) |
625efab1 | 295 | { |
a53a35a8 | 296 | switch (cpu->regs->trapnum) { |
e1e72965 RR |
297 | case 13: /* We've intercepted a General Protection Fault. */ |
298 | /* Check if this was one of those annoying IN or OUT | |
299 | * instructions which we need to emulate. If so, we just go | |
300 | * back into the Guest after we've done it. */ | |
a53a35a8 | 301 | if (cpu->regs->errcode == 0) { |
a3863f68 | 302 | if (emulate_insn(cpu)) |
625efab1 JS |
303 | return; |
304 | } | |
305 | break; | |
e1e72965 RR |
306 | case 14: /* We've intercepted a Page Fault. */ |
307 | /* The Guest accessed a virtual address that wasn't mapped. | |
a6bd8e13 RR |
308 | * This happens a lot: we don't actually set up most of the page |
309 | * tables for the Guest at all when we start: as it runs it asks | |
310 | * for more and more, and we set them up as required. In this | |
311 | * case, we don't even tell the Guest that the fault happened. | |
e1e72965 RR |
312 | * |
313 | * The errcode tells whether this was a read or a write, and | |
314 | * whether kernel or userspace code. */ | |
1713608f GOC |
315 | if (demand_page(cpu, cpu->arch.last_pagefault, |
316 | cpu->regs->errcode)) | |
625efab1 JS |
317 | return; |
318 | ||
e1e72965 RR |
319 | /* OK, it's really not there (or not OK): the Guest needs to |
320 | * know. We write out the cr2 value so it knows where the | |
321 | * fault occurred. | |
322 | * | |
323 | * Note that if the Guest were really messed up, this could | |
324 | * happen before it's done the LHCALL_LGUEST_INIT hypercall, so | |
325 | * lg->lguest_data could be NULL */ | |
382ac6b3 GOC |
326 | if (cpu->lg->lguest_data && |
327 | put_user(cpu->arch.last_pagefault, | |
328 | &cpu->lg->lguest_data->cr2)) | |
329 | kill_guest(cpu, "Writing cr2"); | |
625efab1 JS |
330 | break; |
331 | case 7: /* We've intercepted a Device Not Available fault. */ | |
e1e72965 RR |
332 | /* If the Guest doesn't want to know, we already restored the |
333 | * Floating Point Unit, so we just continue without telling | |
334 | * it. */ | |
4665ac8e | 335 | if (!cpu->ts) |
625efab1 JS |
336 | return; |
337 | break; | |
338 | case 32 ... 255: | |
cc6d4fbc RR |
339 | /* These values mean a real interrupt occurred, in which case |
340 | * the Host handler has already been run. We just do a | |
341 | * friendly check if another process should now be run, then | |
342 | * return to run the Guest again */ | |
625efab1 | 343 | cond_resched(); |
cc6d4fbc RR |
344 | return; |
345 | case LGUEST_TRAP_ENTRY: | |
b410e7b1 JS |
346 | /* Our 'struct hcall_args' maps directly over our regs: we set |
347 | * up the pointer now to indicate a hypercall is pending. */ | |
a53a35a8 | 348 | cpu->hcall = (struct hcall_args *)cpu->regs; |
625efab1 JS |
349 | return; |
350 | } | |
351 | ||
352 | /* We didn't handle the trap, so it needs to go to the Guest. */ | |
a53a35a8 | 353 | if (!deliver_trap(cpu, cpu->regs->trapnum)) |
625efab1 JS |
354 | /* If the Guest doesn't have a handler (either it hasn't |
355 | * registered any yet, or it's one of the faults we don't let | |
a6bd8e13 | 356 | * it handle), it dies with this cryptic error message. */ |
382ac6b3 | 357 | kill_guest(cpu, "unhandled trap %li at %#lx (%#lx)", |
a53a35a8 | 358 | cpu->regs->trapnum, cpu->regs->eip, |
fc708b3e | 359 | cpu->regs->trapnum == 14 ? cpu->arch.last_pagefault |
a53a35a8 | 360 | : cpu->regs->errcode); |
625efab1 JS |
361 | } |
362 | ||
363 | /* Now we can look at each of the routines this calls, in increasing order of | |
364 | * complexity: do_hypercalls(), emulate_insn(), maybe_do_interrupt(), | |
365 | * deliver_trap() and demand_page(). After all those, we'll be ready to | |
366 | * examine the Switcher, and our philosophical understanding of the Host/Guest | |
367 | * duality will be complete. :*/ | |
368 | static void adjust_pge(void *on) | |
369 | { | |
370 | if (on) | |
371 | write_cr4(read_cr4() | X86_CR4_PGE); | |
372 | else | |
373 | write_cr4(read_cr4() & ~X86_CR4_PGE); | |
374 | } | |
375 | ||
376 | /*H:020 Now the Switcher is mapped and every thing else is ready, we need to do | |
377 | * some more i386-specific initialization. */ | |
378 | void __init lguest_arch_host_init(void) | |
379 | { | |
380 | int i; | |
381 | ||
382 | /* Most of the i386/switcher.S doesn't care that it's been moved; on | |
383 | * Intel, jumps are relative, and it doesn't access any references to | |
384 | * external code or data. | |
385 | * | |
386 | * The only exception is the interrupt handlers in switcher.S: their | |
387 | * addresses are placed in a table (default_idt_entries), so we need to | |
388 | * update the table with the new addresses. switcher_offset() is a | |
a6bd8e13 RR |
389 | * convenience function which returns the distance between the |
390 | * compiled-in switcher code and the high-mapped copy we just made. */ | |
625efab1 JS |
391 | for (i = 0; i < IDT_ENTRIES; i++) |
392 | default_idt_entries[i] += switcher_offset(); | |
393 | ||
394 | /* | |
395 | * Set up the Switcher's per-cpu areas. | |
396 | * | |
397 | * Each CPU gets two pages of its own within the high-mapped region | |
398 | * (aka. "struct lguest_pages"). Much of this can be initialized now, | |
399 | * but some depends on what Guest we are running (which is set up in | |
400 | * copy_in_guest_info()). | |
401 | */ | |
402 | for_each_possible_cpu(i) { | |
403 | /* lguest_pages() returns this CPU's two pages. */ | |
404 | struct lguest_pages *pages = lguest_pages(i); | |
405 | /* This is a convenience pointer to make the code fit one | |
406 | * statement to a line. */ | |
407 | struct lguest_ro_state *state = &pages->state; | |
408 | ||
409 | /* The Global Descriptor Table: the Host has a different one | |
410 | * for each CPU. We keep a descriptor for the GDT which says | |
411 | * where it is and how big it is (the size is actually the last | |
412 | * byte, not the size, hence the "-1"). */ | |
413 | state->host_gdt_desc.size = GDT_SIZE-1; | |
414 | state->host_gdt_desc.address = (long)get_cpu_gdt_table(i); | |
415 | ||
416 | /* All CPUs on the Host use the same Interrupt Descriptor | |
417 | * Table, so we just use store_idt(), which gets this CPU's IDT | |
418 | * descriptor. */ | |
419 | store_idt(&state->host_idt_desc); | |
420 | ||
421 | /* The descriptors for the Guest's GDT and IDT can be filled | |
422 | * out now, too. We copy the GDT & IDT into ->guest_gdt and | |
423 | * ->guest_idt before actually running the Guest. */ | |
424 | state->guest_idt_desc.size = sizeof(state->guest_idt)-1; | |
425 | state->guest_idt_desc.address = (long)&state->guest_idt; | |
426 | state->guest_gdt_desc.size = sizeof(state->guest_gdt)-1; | |
427 | state->guest_gdt_desc.address = (long)&state->guest_gdt; | |
428 | ||
429 | /* We know where we want the stack to be when the Guest enters | |
a6bd8e13 | 430 | * the Switcher: in pages->regs. The stack grows upwards, so |
625efab1 | 431 | * we start it at the end of that structure. */ |
faca6227 | 432 | state->guest_tss.sp0 = (long)(&pages->regs + 1); |
625efab1 JS |
433 | /* And this is the GDT entry to use for the stack: we keep a |
434 | * couple of special LGUEST entries. */ | |
435 | state->guest_tss.ss0 = LGUEST_DS; | |
436 | ||
437 | /* x86 can have a finegrained bitmap which indicates what I/O | |
438 | * ports the process can use. We set it to the end of our | |
439 | * structure, meaning "none". */ | |
440 | state->guest_tss.io_bitmap_base = sizeof(state->guest_tss); | |
441 | ||
442 | /* Some GDT entries are the same across all Guests, so we can | |
443 | * set them up now. */ | |
444 | setup_default_gdt_entries(state); | |
445 | /* Most IDT entries are the same for all Guests, too.*/ | |
446 | setup_default_idt_entries(state, default_idt_entries); | |
447 | ||
448 | /* The Host needs to be able to use the LGUEST segments on this | |
449 | * CPU, too, so put them in the Host GDT. */ | |
450 | get_cpu_gdt_table(i)[GDT_ENTRY_LGUEST_CS] = FULL_EXEC_SEGMENT; | |
451 | get_cpu_gdt_table(i)[GDT_ENTRY_LGUEST_DS] = FULL_SEGMENT; | |
452 | } | |
453 | ||
454 | /* In the Switcher, we want the %cs segment register to use the | |
455 | * LGUEST_CS GDT entry: we've put that in the Host and Guest GDTs, so | |
456 | * it will be undisturbed when we switch. To change %cs and jump we | |
457 | * need this structure to feed to Intel's "lcall" instruction. */ | |
458 | lguest_entry.offset = (long)switch_to_guest + switcher_offset(); | |
459 | lguest_entry.segment = LGUEST_CS; | |
460 | ||
461 | /* Finally, we need to turn off "Page Global Enable". PGE is an | |
462 | * optimization where page table entries are specially marked to show | |
463 | * they never change. The Host kernel marks all the kernel pages this | |
464 | * way because it's always present, even when userspace is running. | |
465 | * | |
466 | * Lguest breaks this: unbeknownst to the rest of the Host kernel, we | |
467 | * switch to the Guest kernel. If you don't disable this on all CPUs, | |
468 | * you'll get really weird bugs that you'll chase for two days. | |
469 | * | |
470 | * I used to turn PGE off every time we switched to the Guest and back | |
471 | * on when we return, but that slowed the Switcher down noticibly. */ | |
472 | ||
473 | /* We don't need the complexity of CPUs coming and going while we're | |
474 | * doing this. */ | |
86ef5c9a | 475 | get_online_cpus(); |
625efab1 JS |
476 | if (cpu_has_pge) { /* We have a broader idea of "global". */ |
477 | /* Remember that this was originally set (for cleanup). */ | |
478 | cpu_had_pge = 1; | |
479 | /* adjust_pge is a helper function which sets or unsets the PGE | |
480 | * bit on its CPU, depending on the argument (0 == unset). */ | |
15c8b6c1 | 481 | on_each_cpu(adjust_pge, (void *)0, 1); |
625efab1 | 482 | /* Turn off the feature in the global feature set. */ |
cf485e56 | 483 | clear_cpu_cap(&boot_cpu_data, X86_FEATURE_PGE); |
625efab1 | 484 | } |
86ef5c9a | 485 | put_online_cpus(); |
625efab1 JS |
486 | }; |
487 | /*:*/ | |
488 | ||
489 | void __exit lguest_arch_host_fini(void) | |
490 | { | |
491 | /* If we had PGE before we started, turn it back on now. */ | |
86ef5c9a | 492 | get_online_cpus(); |
625efab1 | 493 | if (cpu_had_pge) { |
cf485e56 | 494 | set_cpu_cap(&boot_cpu_data, X86_FEATURE_PGE); |
625efab1 | 495 | /* adjust_pge's argument "1" means set PGE. */ |
15c8b6c1 | 496 | on_each_cpu(adjust_pge, (void *)1, 1); |
625efab1 | 497 | } |
86ef5c9a | 498 | put_online_cpus(); |
625efab1 | 499 | } |
b410e7b1 JS |
500 | |
501 | ||
502 | /*H:122 The i386-specific hypercalls simply farm out to the right functions. */ | |
73044f05 | 503 | int lguest_arch_do_hcall(struct lg_cpu *cpu, struct hcall_args *args) |
b410e7b1 JS |
504 | { |
505 | switch (args->arg0) { | |
506 | case LHCALL_LOAD_GDT: | |
fc708b3e | 507 | load_guest_gdt(cpu, args->arg1, args->arg2); |
b410e7b1 JS |
508 | break; |
509 | case LHCALL_LOAD_IDT_ENTRY: | |
fc708b3e | 510 | load_guest_idt_entry(cpu, args->arg1, args->arg2, args->arg3); |
b410e7b1 JS |
511 | break; |
512 | case LHCALL_LOAD_TLS: | |
fc708b3e | 513 | guest_load_tls(cpu, args->arg1); |
b410e7b1 JS |
514 | break; |
515 | default: | |
516 | /* Bad Guest. Bad! */ | |
517 | return -EIO; | |
518 | } | |
519 | return 0; | |
520 | } | |
521 | ||
522 | /*H:126 i386-specific hypercall initialization: */ | |
73044f05 | 523 | int lguest_arch_init_hypercalls(struct lg_cpu *cpu) |
b410e7b1 JS |
524 | { |
525 | u32 tsc_speed; | |
526 | ||
a6bd8e13 RR |
527 | /* The pointer to the Guest's "struct lguest_data" is the only argument. |
528 | * We check that address now. */ | |
382ac6b3 GOC |
529 | if (!lguest_address_ok(cpu->lg, cpu->hcall->arg1, |
530 | sizeof(*cpu->lg->lguest_data))) | |
b410e7b1 JS |
531 | return -EFAULT; |
532 | ||
533 | /* Having checked it, we simply set lg->lguest_data to point straight | |
534 | * into the Launcher's memory at the right place and then use | |
535 | * copy_to_user/from_user from now on, instead of lgread/write. I put | |
536 | * this in to show that I'm not immune to writing stupid | |
537 | * optimizations. */ | |
382ac6b3 | 538 | cpu->lg->lguest_data = cpu->lg->mem_base + cpu->hcall->arg1; |
b410e7b1 JS |
539 | |
540 | /* We insist that the Time Stamp Counter exist and doesn't change with | |
541 | * cpu frequency. Some devious chip manufacturers decided that TSC | |
542 | * changes could be handled in software. I decided that time going | |
543 | * backwards might be good for benchmarks, but it's bad for users. | |
544 | * | |
545 | * We also insist that the TSC be stable: the kernel detects unreliable | |
546 | * TSCs for its own purposes, and we use that here. */ | |
547 | if (boot_cpu_has(X86_FEATURE_CONSTANT_TSC) && !check_tsc_unstable()) | |
548 | tsc_speed = tsc_khz; | |
549 | else | |
550 | tsc_speed = 0; | |
382ac6b3 | 551 | if (put_user(tsc_speed, &cpu->lg->lguest_data->tsc_khz)) |
b410e7b1 JS |
552 | return -EFAULT; |
553 | ||
c18acd73 | 554 | /* The interrupt code might not like the system call vector. */ |
382ac6b3 GOC |
555 | if (!check_syscall_vector(cpu->lg)) |
556 | kill_guest(cpu, "bad syscall vector"); | |
c18acd73 | 557 | |
b410e7b1 JS |
558 | return 0; |
559 | } | |
a6bd8e13 | 560 | /*:*/ |
d612cde0 JS |
561 | |
562 | /*L:030 lguest_arch_setup_regs() | |
563 | * | |
564 | * Most of the Guest's registers are left alone: we used get_zeroed_page() to | |
565 | * allocate the structure, so they will be 0. */ | |
a53a35a8 | 566 | void lguest_arch_setup_regs(struct lg_cpu *cpu, unsigned long start) |
d612cde0 | 567 | { |
a53a35a8 | 568 | struct lguest_regs *regs = cpu->regs; |
d612cde0 JS |
569 | |
570 | /* There are four "segment" registers which the Guest needs to boot: | |
571 | * The "code segment" register (cs) refers to the kernel code segment | |
572 | * __KERNEL_CS, and the "data", "extra" and "stack" segment registers | |
573 | * refer to the kernel data segment __KERNEL_DS. | |
574 | * | |
575 | * The privilege level is packed into the lower bits. The Guest runs | |
576 | * at privilege level 1 (GUEST_PL).*/ | |
577 | regs->ds = regs->es = regs->ss = __KERNEL_DS|GUEST_PL; | |
578 | regs->cs = __KERNEL_CS|GUEST_PL; | |
579 | ||
580 | /* The "eflags" register contains miscellaneous flags. Bit 1 (0x002) | |
581 | * is supposed to always be "1". Bit 9 (0x200) controls whether | |
582 | * interrupts are enabled. We always leave interrupts enabled while | |
583 | * running the Guest. */ | |
25c47bb3 | 584 | regs->eflags = X86_EFLAGS_IF | 0x2; |
d612cde0 JS |
585 | |
586 | /* The "Extended Instruction Pointer" register says where the Guest is | |
587 | * running. */ | |
588 | regs->eip = start; | |
589 | ||
590 | /* %esi points to our boot information, at physical address 0, so don't | |
591 | * touch it. */ | |
e1e72965 | 592 | |
d612cde0 JS |
593 | /* There are a couple of GDT entries the Guest expects when first |
594 | * booting. */ | |
fc708b3e | 595 | setup_guest_gdt(cpu); |
d612cde0 | 596 | } |