Commit | Line | Data |
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6aa8b732 AK |
1 | /* |
2 | * Kernel-based Virtual Machine driver for Linux | |
3 | * | |
4 | * This module enables machines with Intel VT-x extensions to run virtual | |
5 | * machines without emulation or binary translation. | |
6 | * | |
7 | * Copyright (C) 2006 Qumranet, Inc. | |
8 | * | |
9 | * Authors: | |
10 | * Avi Kivity <avi@qumranet.com> | |
11 | * Yaniv Kamay <yaniv@qumranet.com> | |
12 | * | |
13 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
14 | * the COPYING file in the top-level directory. | |
15 | * | |
16 | */ | |
17 | ||
18 | #include "kvm.h" | |
34c16eec | 19 | #include "x86.h" |
e7d5d76c | 20 | #include "x86_emulate.h" |
85f455f7 | 21 | #include "irq.h" |
6aa8b732 | 22 | #include "vmx.h" |
e495606d AK |
23 | #include "segment_descriptor.h" |
24 | ||
6aa8b732 | 25 | #include <linux/module.h> |
9d8f549d | 26 | #include <linux/kernel.h> |
6aa8b732 AK |
27 | #include <linux/mm.h> |
28 | #include <linux/highmem.h> | |
e8edc6e0 | 29 | #include <linux/sched.h> |
c7addb90 | 30 | #include <linux/moduleparam.h> |
e495606d | 31 | |
6aa8b732 | 32 | #include <asm/io.h> |
3b3be0d1 | 33 | #include <asm/desc.h> |
6aa8b732 | 34 | |
6aa8b732 AK |
35 | MODULE_AUTHOR("Qumranet"); |
36 | MODULE_LICENSE("GPL"); | |
37 | ||
c7addb90 AK |
38 | static int bypass_guest_pf = 1; |
39 | module_param(bypass_guest_pf, bool, 0); | |
40 | ||
a2fa3e9f GH |
41 | struct vmcs { |
42 | u32 revision_id; | |
43 | u32 abort; | |
44 | char data[0]; | |
45 | }; | |
46 | ||
47 | struct vcpu_vmx { | |
fb3f0f51 | 48 | struct kvm_vcpu vcpu; |
a2fa3e9f | 49 | int launched; |
29bd8a78 | 50 | u8 fail; |
a2fa3e9f GH |
51 | struct kvm_msr_entry *guest_msrs; |
52 | struct kvm_msr_entry *host_msrs; | |
53 | int nmsrs; | |
54 | int save_nmsrs; | |
55 | int msr_offset_efer; | |
56 | #ifdef CONFIG_X86_64 | |
57 | int msr_offset_kernel_gs_base; | |
58 | #endif | |
59 | struct vmcs *vmcs; | |
60 | struct { | |
61 | int loaded; | |
62 | u16 fs_sel, gs_sel, ldt_sel; | |
152d3f2f LV |
63 | int gs_ldt_reload_needed; |
64 | int fs_reload_needed; | |
51c6cf66 | 65 | int guest_efer_loaded; |
d77c26fc | 66 | } host_state; |
a2fa3e9f GH |
67 | |
68 | }; | |
69 | ||
70 | static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu) | |
71 | { | |
fb3f0f51 | 72 | return container_of(vcpu, struct vcpu_vmx, vcpu); |
a2fa3e9f GH |
73 | } |
74 | ||
75880a01 AK |
75 | static int init_rmode_tss(struct kvm *kvm); |
76 | ||
6aa8b732 AK |
77 | static DEFINE_PER_CPU(struct vmcs *, vmxarea); |
78 | static DEFINE_PER_CPU(struct vmcs *, current_vmcs); | |
79 | ||
fdef3ad1 HQ |
80 | static struct page *vmx_io_bitmap_a; |
81 | static struct page *vmx_io_bitmap_b; | |
82 | ||
1c3d14fe | 83 | static struct vmcs_config { |
6aa8b732 AK |
84 | int size; |
85 | int order; | |
86 | u32 revision_id; | |
1c3d14fe YS |
87 | u32 pin_based_exec_ctrl; |
88 | u32 cpu_based_exec_ctrl; | |
89 | u32 vmexit_ctrl; | |
90 | u32 vmentry_ctrl; | |
91 | } vmcs_config; | |
6aa8b732 AK |
92 | |
93 | #define VMX_SEGMENT_FIELD(seg) \ | |
94 | [VCPU_SREG_##seg] = { \ | |
95 | .selector = GUEST_##seg##_SELECTOR, \ | |
96 | .base = GUEST_##seg##_BASE, \ | |
97 | .limit = GUEST_##seg##_LIMIT, \ | |
98 | .ar_bytes = GUEST_##seg##_AR_BYTES, \ | |
99 | } | |
100 | ||
101 | static struct kvm_vmx_segment_field { | |
102 | unsigned selector; | |
103 | unsigned base; | |
104 | unsigned limit; | |
105 | unsigned ar_bytes; | |
106 | } kvm_vmx_segment_fields[] = { | |
107 | VMX_SEGMENT_FIELD(CS), | |
108 | VMX_SEGMENT_FIELD(DS), | |
109 | VMX_SEGMENT_FIELD(ES), | |
110 | VMX_SEGMENT_FIELD(FS), | |
111 | VMX_SEGMENT_FIELD(GS), | |
112 | VMX_SEGMENT_FIELD(SS), | |
113 | VMX_SEGMENT_FIELD(TR), | |
114 | VMX_SEGMENT_FIELD(LDTR), | |
115 | }; | |
116 | ||
4d56c8a7 AK |
117 | /* |
118 | * Keep MSR_K6_STAR at the end, as setup_msrs() will try to optimize it | |
119 | * away by decrementing the array size. | |
120 | */ | |
6aa8b732 | 121 | static const u32 vmx_msr_index[] = { |
05b3e0c2 | 122 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
123 | MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR, MSR_KERNEL_GS_BASE, |
124 | #endif | |
125 | MSR_EFER, MSR_K6_STAR, | |
126 | }; | |
9d8f549d | 127 | #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index) |
6aa8b732 | 128 | |
a2fa3e9f GH |
129 | static void load_msrs(struct kvm_msr_entry *e, int n) |
130 | { | |
131 | int i; | |
132 | ||
133 | for (i = 0; i < n; ++i) | |
134 | wrmsrl(e[i].index, e[i].data); | |
135 | } | |
136 | ||
137 | static void save_msrs(struct kvm_msr_entry *e, int n) | |
138 | { | |
139 | int i; | |
140 | ||
141 | for (i = 0; i < n; ++i) | |
142 | rdmsrl(e[i].index, e[i].data); | |
143 | } | |
144 | ||
6aa8b732 AK |
145 | static inline int is_page_fault(u32 intr_info) |
146 | { | |
147 | return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK | | |
148 | INTR_INFO_VALID_MASK)) == | |
149 | (INTR_TYPE_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK); | |
150 | } | |
151 | ||
2ab455cc AL |
152 | static inline int is_no_device(u32 intr_info) |
153 | { | |
154 | return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK | | |
155 | INTR_INFO_VALID_MASK)) == | |
156 | (INTR_TYPE_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK); | |
157 | } | |
158 | ||
7aa81cc0 AL |
159 | static inline int is_invalid_opcode(u32 intr_info) |
160 | { | |
161 | return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK | | |
162 | INTR_INFO_VALID_MASK)) == | |
163 | (INTR_TYPE_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK); | |
164 | } | |
165 | ||
6aa8b732 AK |
166 | static inline int is_external_interrupt(u32 intr_info) |
167 | { | |
168 | return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK)) | |
169 | == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK); | |
170 | } | |
171 | ||
6e5d865c YS |
172 | static inline int cpu_has_vmx_tpr_shadow(void) |
173 | { | |
174 | return (vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW); | |
175 | } | |
176 | ||
177 | static inline int vm_need_tpr_shadow(struct kvm *kvm) | |
178 | { | |
179 | return ((cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm))); | |
180 | } | |
181 | ||
8b9cf98c | 182 | static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr) |
7725f0ba AK |
183 | { |
184 | int i; | |
185 | ||
a2fa3e9f GH |
186 | for (i = 0; i < vmx->nmsrs; ++i) |
187 | if (vmx->guest_msrs[i].index == msr) | |
a75beee6 ED |
188 | return i; |
189 | return -1; | |
190 | } | |
191 | ||
8b9cf98c | 192 | static struct kvm_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr) |
a75beee6 ED |
193 | { |
194 | int i; | |
195 | ||
8b9cf98c | 196 | i = __find_msr_index(vmx, msr); |
a75beee6 | 197 | if (i >= 0) |
a2fa3e9f | 198 | return &vmx->guest_msrs[i]; |
8b6d44c7 | 199 | return NULL; |
7725f0ba AK |
200 | } |
201 | ||
6aa8b732 AK |
202 | static void vmcs_clear(struct vmcs *vmcs) |
203 | { | |
204 | u64 phys_addr = __pa(vmcs); | |
205 | u8 error; | |
206 | ||
207 | asm volatile (ASM_VMX_VMCLEAR_RAX "; setna %0" | |
208 | : "=g"(error) : "a"(&phys_addr), "m"(phys_addr) | |
209 | : "cc", "memory"); | |
210 | if (error) | |
211 | printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n", | |
212 | vmcs, phys_addr); | |
213 | } | |
214 | ||
215 | static void __vcpu_clear(void *arg) | |
216 | { | |
8b9cf98c | 217 | struct vcpu_vmx *vmx = arg; |
d3b2c338 | 218 | int cpu = raw_smp_processor_id(); |
6aa8b732 | 219 | |
8b9cf98c | 220 | if (vmx->vcpu.cpu == cpu) |
a2fa3e9f GH |
221 | vmcs_clear(vmx->vmcs); |
222 | if (per_cpu(current_vmcs, cpu) == vmx->vmcs) | |
6aa8b732 | 223 | per_cpu(current_vmcs, cpu) = NULL; |
8b9cf98c | 224 | rdtscll(vmx->vcpu.host_tsc); |
6aa8b732 AK |
225 | } |
226 | ||
8b9cf98c | 227 | static void vcpu_clear(struct vcpu_vmx *vmx) |
8d0be2b3 | 228 | { |
eae5ecb5 AK |
229 | if (vmx->vcpu.cpu == -1) |
230 | return; | |
f566e09f | 231 | smp_call_function_single(vmx->vcpu.cpu, __vcpu_clear, vmx, 0, 1); |
8b9cf98c | 232 | vmx->launched = 0; |
8d0be2b3 AK |
233 | } |
234 | ||
6aa8b732 AK |
235 | static unsigned long vmcs_readl(unsigned long field) |
236 | { | |
237 | unsigned long value; | |
238 | ||
239 | asm volatile (ASM_VMX_VMREAD_RDX_RAX | |
240 | : "=a"(value) : "d"(field) : "cc"); | |
241 | return value; | |
242 | } | |
243 | ||
244 | static u16 vmcs_read16(unsigned long field) | |
245 | { | |
246 | return vmcs_readl(field); | |
247 | } | |
248 | ||
249 | static u32 vmcs_read32(unsigned long field) | |
250 | { | |
251 | return vmcs_readl(field); | |
252 | } | |
253 | ||
254 | static u64 vmcs_read64(unsigned long field) | |
255 | { | |
05b3e0c2 | 256 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
257 | return vmcs_readl(field); |
258 | #else | |
259 | return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32); | |
260 | #endif | |
261 | } | |
262 | ||
e52de1b8 AK |
263 | static noinline void vmwrite_error(unsigned long field, unsigned long value) |
264 | { | |
265 | printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n", | |
266 | field, value, vmcs_read32(VM_INSTRUCTION_ERROR)); | |
267 | dump_stack(); | |
268 | } | |
269 | ||
6aa8b732 AK |
270 | static void vmcs_writel(unsigned long field, unsigned long value) |
271 | { | |
272 | u8 error; | |
273 | ||
274 | asm volatile (ASM_VMX_VMWRITE_RAX_RDX "; setna %0" | |
d77c26fc | 275 | : "=q"(error) : "a"(value), "d"(field) : "cc"); |
e52de1b8 AK |
276 | if (unlikely(error)) |
277 | vmwrite_error(field, value); | |
6aa8b732 AK |
278 | } |
279 | ||
280 | static void vmcs_write16(unsigned long field, u16 value) | |
281 | { | |
282 | vmcs_writel(field, value); | |
283 | } | |
284 | ||
285 | static void vmcs_write32(unsigned long field, u32 value) | |
286 | { | |
287 | vmcs_writel(field, value); | |
288 | } | |
289 | ||
290 | static void vmcs_write64(unsigned long field, u64 value) | |
291 | { | |
05b3e0c2 | 292 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
293 | vmcs_writel(field, value); |
294 | #else | |
295 | vmcs_writel(field, value); | |
296 | asm volatile (""); | |
297 | vmcs_writel(field+1, value >> 32); | |
298 | #endif | |
299 | } | |
300 | ||
2ab455cc AL |
301 | static void vmcs_clear_bits(unsigned long field, u32 mask) |
302 | { | |
303 | vmcs_writel(field, vmcs_readl(field) & ~mask); | |
304 | } | |
305 | ||
306 | static void vmcs_set_bits(unsigned long field, u32 mask) | |
307 | { | |
308 | vmcs_writel(field, vmcs_readl(field) | mask); | |
309 | } | |
310 | ||
abd3f2d6 AK |
311 | static void update_exception_bitmap(struct kvm_vcpu *vcpu) |
312 | { | |
313 | u32 eb; | |
314 | ||
7aa81cc0 | 315 | eb = (1u << PF_VECTOR) | (1u << UD_VECTOR); |
abd3f2d6 AK |
316 | if (!vcpu->fpu_active) |
317 | eb |= 1u << NM_VECTOR; | |
318 | if (vcpu->guest_debug.enabled) | |
319 | eb |= 1u << 1; | |
320 | if (vcpu->rmode.active) | |
321 | eb = ~0; | |
322 | vmcs_write32(EXCEPTION_BITMAP, eb); | |
323 | } | |
324 | ||
33ed6329 AK |
325 | static void reload_tss(void) |
326 | { | |
327 | #ifndef CONFIG_X86_64 | |
328 | ||
329 | /* | |
330 | * VT restores TR but not its size. Useless. | |
331 | */ | |
332 | struct descriptor_table gdt; | |
333 | struct segment_descriptor *descs; | |
334 | ||
335 | get_gdt(&gdt); | |
336 | descs = (void *)gdt.base; | |
337 | descs[GDT_ENTRY_TSS].type = 9; /* available TSS */ | |
338 | load_TR_desc(); | |
339 | #endif | |
340 | } | |
341 | ||
8b9cf98c | 342 | static void load_transition_efer(struct vcpu_vmx *vmx) |
2cc51560 | 343 | { |
a2fa3e9f | 344 | int efer_offset = vmx->msr_offset_efer; |
51c6cf66 AK |
345 | u64 host_efer = vmx->host_msrs[efer_offset].data; |
346 | u64 guest_efer = vmx->guest_msrs[efer_offset].data; | |
347 | u64 ignore_bits; | |
348 | ||
349 | if (efer_offset < 0) | |
350 | return; | |
351 | /* | |
352 | * NX is emulated; LMA and LME handled by hardware; SCE meaninless | |
353 | * outside long mode | |
354 | */ | |
355 | ignore_bits = EFER_NX | EFER_SCE; | |
356 | #ifdef CONFIG_X86_64 | |
357 | ignore_bits |= EFER_LMA | EFER_LME; | |
358 | /* SCE is meaningful only in long mode on Intel */ | |
359 | if (guest_efer & EFER_LMA) | |
360 | ignore_bits &= ~(u64)EFER_SCE; | |
361 | #endif | |
362 | if ((guest_efer & ~ignore_bits) == (host_efer & ~ignore_bits)) | |
363 | return; | |
2cc51560 | 364 | |
51c6cf66 AK |
365 | vmx->host_state.guest_efer_loaded = 1; |
366 | guest_efer &= ~ignore_bits; | |
367 | guest_efer |= host_efer & ignore_bits; | |
368 | wrmsrl(MSR_EFER, guest_efer); | |
8b9cf98c | 369 | vmx->vcpu.stat.efer_reload++; |
2cc51560 ED |
370 | } |
371 | ||
51c6cf66 AK |
372 | static void reload_host_efer(struct vcpu_vmx *vmx) |
373 | { | |
374 | if (vmx->host_state.guest_efer_loaded) { | |
375 | vmx->host_state.guest_efer_loaded = 0; | |
376 | load_msrs(vmx->host_msrs + vmx->msr_offset_efer, 1); | |
377 | } | |
378 | } | |
379 | ||
04d2cc77 | 380 | static void vmx_save_host_state(struct kvm_vcpu *vcpu) |
33ed6329 | 381 | { |
04d2cc77 AK |
382 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
383 | ||
a2fa3e9f | 384 | if (vmx->host_state.loaded) |
33ed6329 AK |
385 | return; |
386 | ||
a2fa3e9f | 387 | vmx->host_state.loaded = 1; |
33ed6329 AK |
388 | /* |
389 | * Set host fs and gs selectors. Unfortunately, 22.2.3 does not | |
390 | * allow segment selectors with cpl > 0 or ti == 1. | |
391 | */ | |
a2fa3e9f | 392 | vmx->host_state.ldt_sel = read_ldt(); |
152d3f2f | 393 | vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel; |
a2fa3e9f | 394 | vmx->host_state.fs_sel = read_fs(); |
152d3f2f | 395 | if (!(vmx->host_state.fs_sel & 7)) { |
a2fa3e9f | 396 | vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel); |
152d3f2f LV |
397 | vmx->host_state.fs_reload_needed = 0; |
398 | } else { | |
33ed6329 | 399 | vmcs_write16(HOST_FS_SELECTOR, 0); |
152d3f2f | 400 | vmx->host_state.fs_reload_needed = 1; |
33ed6329 | 401 | } |
a2fa3e9f GH |
402 | vmx->host_state.gs_sel = read_gs(); |
403 | if (!(vmx->host_state.gs_sel & 7)) | |
404 | vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel); | |
33ed6329 AK |
405 | else { |
406 | vmcs_write16(HOST_GS_SELECTOR, 0); | |
152d3f2f | 407 | vmx->host_state.gs_ldt_reload_needed = 1; |
33ed6329 AK |
408 | } |
409 | ||
410 | #ifdef CONFIG_X86_64 | |
411 | vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE)); | |
412 | vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE)); | |
413 | #else | |
a2fa3e9f GH |
414 | vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel)); |
415 | vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel)); | |
33ed6329 | 416 | #endif |
707c0874 AK |
417 | |
418 | #ifdef CONFIG_X86_64 | |
d77c26fc | 419 | if (is_long_mode(&vmx->vcpu)) |
a2fa3e9f GH |
420 | save_msrs(vmx->host_msrs + |
421 | vmx->msr_offset_kernel_gs_base, 1); | |
d77c26fc | 422 | |
707c0874 | 423 | #endif |
a2fa3e9f | 424 | load_msrs(vmx->guest_msrs, vmx->save_nmsrs); |
51c6cf66 | 425 | load_transition_efer(vmx); |
33ed6329 AK |
426 | } |
427 | ||
8b9cf98c | 428 | static void vmx_load_host_state(struct vcpu_vmx *vmx) |
33ed6329 | 429 | { |
15ad7146 | 430 | unsigned long flags; |
33ed6329 | 431 | |
a2fa3e9f | 432 | if (!vmx->host_state.loaded) |
33ed6329 AK |
433 | return; |
434 | ||
a2fa3e9f | 435 | vmx->host_state.loaded = 0; |
152d3f2f | 436 | if (vmx->host_state.fs_reload_needed) |
a2fa3e9f | 437 | load_fs(vmx->host_state.fs_sel); |
152d3f2f LV |
438 | if (vmx->host_state.gs_ldt_reload_needed) { |
439 | load_ldt(vmx->host_state.ldt_sel); | |
33ed6329 AK |
440 | /* |
441 | * If we have to reload gs, we must take care to | |
442 | * preserve our gs base. | |
443 | */ | |
15ad7146 | 444 | local_irq_save(flags); |
a2fa3e9f | 445 | load_gs(vmx->host_state.gs_sel); |
33ed6329 AK |
446 | #ifdef CONFIG_X86_64 |
447 | wrmsrl(MSR_GS_BASE, vmcs_readl(HOST_GS_BASE)); | |
448 | #endif | |
15ad7146 | 449 | local_irq_restore(flags); |
33ed6329 | 450 | } |
152d3f2f | 451 | reload_tss(); |
a2fa3e9f GH |
452 | save_msrs(vmx->guest_msrs, vmx->save_nmsrs); |
453 | load_msrs(vmx->host_msrs, vmx->save_nmsrs); | |
51c6cf66 | 454 | reload_host_efer(vmx); |
33ed6329 AK |
455 | } |
456 | ||
6aa8b732 AK |
457 | /* |
458 | * Switches to specified vcpu, until a matching vcpu_put(), but assumes | |
459 | * vcpu mutex is already taken. | |
460 | */ | |
15ad7146 | 461 | static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu) |
6aa8b732 | 462 | { |
a2fa3e9f GH |
463 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
464 | u64 phys_addr = __pa(vmx->vmcs); | |
7700270e | 465 | u64 tsc_this, delta; |
6aa8b732 | 466 | |
a3d7f85f | 467 | if (vcpu->cpu != cpu) { |
8b9cf98c | 468 | vcpu_clear(vmx); |
a3d7f85f ED |
469 | kvm_migrate_apic_timer(vcpu); |
470 | } | |
6aa8b732 | 471 | |
a2fa3e9f | 472 | if (per_cpu(current_vmcs, cpu) != vmx->vmcs) { |
6aa8b732 AK |
473 | u8 error; |
474 | ||
a2fa3e9f | 475 | per_cpu(current_vmcs, cpu) = vmx->vmcs; |
6aa8b732 AK |
476 | asm volatile (ASM_VMX_VMPTRLD_RAX "; setna %0" |
477 | : "=g"(error) : "a"(&phys_addr), "m"(phys_addr) | |
478 | : "cc"); | |
479 | if (error) | |
480 | printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n", | |
a2fa3e9f | 481 | vmx->vmcs, phys_addr); |
6aa8b732 AK |
482 | } |
483 | ||
484 | if (vcpu->cpu != cpu) { | |
485 | struct descriptor_table dt; | |
486 | unsigned long sysenter_esp; | |
487 | ||
488 | vcpu->cpu = cpu; | |
489 | /* | |
490 | * Linux uses per-cpu TSS and GDT, so set these when switching | |
491 | * processors. | |
492 | */ | |
493 | vmcs_writel(HOST_TR_BASE, read_tr_base()); /* 22.2.4 */ | |
494 | get_gdt(&dt); | |
495 | vmcs_writel(HOST_GDTR_BASE, dt.base); /* 22.2.4 */ | |
496 | ||
497 | rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp); | |
498 | vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */ | |
7700270e AK |
499 | |
500 | /* | |
501 | * Make sure the time stamp counter is monotonous. | |
502 | */ | |
503 | rdtscll(tsc_this); | |
504 | delta = vcpu->host_tsc - tsc_this; | |
505 | vmcs_write64(TSC_OFFSET, vmcs_read64(TSC_OFFSET) + delta); | |
6aa8b732 | 506 | } |
6aa8b732 AK |
507 | } |
508 | ||
509 | static void vmx_vcpu_put(struct kvm_vcpu *vcpu) | |
510 | { | |
8b9cf98c | 511 | vmx_load_host_state(to_vmx(vcpu)); |
7702fd1f | 512 | kvm_put_guest_fpu(vcpu); |
6aa8b732 AK |
513 | } |
514 | ||
5fd86fcf AK |
515 | static void vmx_fpu_activate(struct kvm_vcpu *vcpu) |
516 | { | |
517 | if (vcpu->fpu_active) | |
518 | return; | |
519 | vcpu->fpu_active = 1; | |
707d92fa RR |
520 | vmcs_clear_bits(GUEST_CR0, X86_CR0_TS); |
521 | if (vcpu->cr0 & X86_CR0_TS) | |
522 | vmcs_set_bits(GUEST_CR0, X86_CR0_TS); | |
5fd86fcf AK |
523 | update_exception_bitmap(vcpu); |
524 | } | |
525 | ||
526 | static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu) | |
527 | { | |
528 | if (!vcpu->fpu_active) | |
529 | return; | |
530 | vcpu->fpu_active = 0; | |
707d92fa | 531 | vmcs_set_bits(GUEST_CR0, X86_CR0_TS); |
5fd86fcf AK |
532 | update_exception_bitmap(vcpu); |
533 | } | |
534 | ||
774c47f1 AK |
535 | static void vmx_vcpu_decache(struct kvm_vcpu *vcpu) |
536 | { | |
8b9cf98c | 537 | vcpu_clear(to_vmx(vcpu)); |
774c47f1 AK |
538 | } |
539 | ||
6aa8b732 AK |
540 | static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu) |
541 | { | |
542 | return vmcs_readl(GUEST_RFLAGS); | |
543 | } | |
544 | ||
545 | static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) | |
546 | { | |
78f78268 | 547 | if (vcpu->rmode.active) |
053de044 | 548 | rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM; |
6aa8b732 AK |
549 | vmcs_writel(GUEST_RFLAGS, rflags); |
550 | } | |
551 | ||
552 | static void skip_emulated_instruction(struct kvm_vcpu *vcpu) | |
553 | { | |
554 | unsigned long rip; | |
555 | u32 interruptibility; | |
556 | ||
557 | rip = vmcs_readl(GUEST_RIP); | |
558 | rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN); | |
559 | vmcs_writel(GUEST_RIP, rip); | |
560 | ||
561 | /* | |
562 | * We emulated an instruction, so temporary interrupt blocking | |
563 | * should be removed, if set. | |
564 | */ | |
565 | interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO); | |
566 | if (interruptibility & 3) | |
567 | vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, | |
568 | interruptibility & ~3); | |
c1150d8c | 569 | vcpu->interrupt_window_open = 1; |
6aa8b732 AK |
570 | } |
571 | ||
572 | static void vmx_inject_gp(struct kvm_vcpu *vcpu, unsigned error_code) | |
573 | { | |
574 | printk(KERN_DEBUG "inject_general_protection: rip 0x%lx\n", | |
575 | vmcs_readl(GUEST_RIP)); | |
576 | vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code); | |
577 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, | |
578 | GP_VECTOR | | |
579 | INTR_TYPE_EXCEPTION | | |
580 | INTR_INFO_DELIEVER_CODE_MASK | | |
581 | INTR_INFO_VALID_MASK); | |
582 | } | |
583 | ||
7aa81cc0 AL |
584 | static void vmx_inject_ud(struct kvm_vcpu *vcpu) |
585 | { | |
586 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, | |
587 | UD_VECTOR | | |
588 | INTR_TYPE_EXCEPTION | | |
589 | INTR_INFO_VALID_MASK); | |
590 | } | |
591 | ||
a75beee6 ED |
592 | /* |
593 | * Swap MSR entry in host/guest MSR entry array. | |
594 | */ | |
54e11fa1 | 595 | #ifdef CONFIG_X86_64 |
8b9cf98c | 596 | static void move_msr_up(struct vcpu_vmx *vmx, int from, int to) |
a75beee6 | 597 | { |
a2fa3e9f GH |
598 | struct kvm_msr_entry tmp; |
599 | ||
600 | tmp = vmx->guest_msrs[to]; | |
601 | vmx->guest_msrs[to] = vmx->guest_msrs[from]; | |
602 | vmx->guest_msrs[from] = tmp; | |
603 | tmp = vmx->host_msrs[to]; | |
604 | vmx->host_msrs[to] = vmx->host_msrs[from]; | |
605 | vmx->host_msrs[from] = tmp; | |
a75beee6 | 606 | } |
54e11fa1 | 607 | #endif |
a75beee6 | 608 | |
e38aea3e AK |
609 | /* |
610 | * Set up the vmcs to automatically save and restore system | |
611 | * msrs. Don't touch the 64-bit msrs if the guest is in legacy | |
612 | * mode, as fiddling with msrs is very expensive. | |
613 | */ | |
8b9cf98c | 614 | static void setup_msrs(struct vcpu_vmx *vmx) |
e38aea3e | 615 | { |
2cc51560 | 616 | int save_nmsrs; |
e38aea3e | 617 | |
a75beee6 ED |
618 | save_nmsrs = 0; |
619 | #ifdef CONFIG_X86_64 | |
8b9cf98c | 620 | if (is_long_mode(&vmx->vcpu)) { |
2cc51560 ED |
621 | int index; |
622 | ||
8b9cf98c | 623 | index = __find_msr_index(vmx, MSR_SYSCALL_MASK); |
a75beee6 | 624 | if (index >= 0) |
8b9cf98c RR |
625 | move_msr_up(vmx, index, save_nmsrs++); |
626 | index = __find_msr_index(vmx, MSR_LSTAR); | |
a75beee6 | 627 | if (index >= 0) |
8b9cf98c RR |
628 | move_msr_up(vmx, index, save_nmsrs++); |
629 | index = __find_msr_index(vmx, MSR_CSTAR); | |
a75beee6 | 630 | if (index >= 0) |
8b9cf98c RR |
631 | move_msr_up(vmx, index, save_nmsrs++); |
632 | index = __find_msr_index(vmx, MSR_KERNEL_GS_BASE); | |
a75beee6 | 633 | if (index >= 0) |
8b9cf98c | 634 | move_msr_up(vmx, index, save_nmsrs++); |
a75beee6 ED |
635 | /* |
636 | * MSR_K6_STAR is only needed on long mode guests, and only | |
637 | * if efer.sce is enabled. | |
638 | */ | |
8b9cf98c RR |
639 | index = __find_msr_index(vmx, MSR_K6_STAR); |
640 | if ((index >= 0) && (vmx->vcpu.shadow_efer & EFER_SCE)) | |
641 | move_msr_up(vmx, index, save_nmsrs++); | |
a75beee6 ED |
642 | } |
643 | #endif | |
a2fa3e9f | 644 | vmx->save_nmsrs = save_nmsrs; |
e38aea3e | 645 | |
4d56c8a7 | 646 | #ifdef CONFIG_X86_64 |
a2fa3e9f | 647 | vmx->msr_offset_kernel_gs_base = |
8b9cf98c | 648 | __find_msr_index(vmx, MSR_KERNEL_GS_BASE); |
4d56c8a7 | 649 | #endif |
8b9cf98c | 650 | vmx->msr_offset_efer = __find_msr_index(vmx, MSR_EFER); |
e38aea3e AK |
651 | } |
652 | ||
6aa8b732 AK |
653 | /* |
654 | * reads and returns guest's timestamp counter "register" | |
655 | * guest_tsc = host_tsc + tsc_offset -- 21.3 | |
656 | */ | |
657 | static u64 guest_read_tsc(void) | |
658 | { | |
659 | u64 host_tsc, tsc_offset; | |
660 | ||
661 | rdtscll(host_tsc); | |
662 | tsc_offset = vmcs_read64(TSC_OFFSET); | |
663 | return host_tsc + tsc_offset; | |
664 | } | |
665 | ||
666 | /* | |
667 | * writes 'guest_tsc' into guest's timestamp counter "register" | |
668 | * guest_tsc = host_tsc + tsc_offset ==> tsc_offset = guest_tsc - host_tsc | |
669 | */ | |
670 | static void guest_write_tsc(u64 guest_tsc) | |
671 | { | |
672 | u64 host_tsc; | |
673 | ||
674 | rdtscll(host_tsc); | |
675 | vmcs_write64(TSC_OFFSET, guest_tsc - host_tsc); | |
676 | } | |
677 | ||
6aa8b732 AK |
678 | /* |
679 | * Reads an msr value (of 'msr_index') into 'pdata'. | |
680 | * Returns 0 on success, non-0 otherwise. | |
681 | * Assumes vcpu_load() was already called. | |
682 | */ | |
683 | static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata) | |
684 | { | |
685 | u64 data; | |
a2fa3e9f | 686 | struct kvm_msr_entry *msr; |
6aa8b732 AK |
687 | |
688 | if (!pdata) { | |
689 | printk(KERN_ERR "BUG: get_msr called with NULL pdata\n"); | |
690 | return -EINVAL; | |
691 | } | |
692 | ||
693 | switch (msr_index) { | |
05b3e0c2 | 694 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
695 | case MSR_FS_BASE: |
696 | data = vmcs_readl(GUEST_FS_BASE); | |
697 | break; | |
698 | case MSR_GS_BASE: | |
699 | data = vmcs_readl(GUEST_GS_BASE); | |
700 | break; | |
701 | case MSR_EFER: | |
3bab1f5d | 702 | return kvm_get_msr_common(vcpu, msr_index, pdata); |
6aa8b732 AK |
703 | #endif |
704 | case MSR_IA32_TIME_STAMP_COUNTER: | |
705 | data = guest_read_tsc(); | |
706 | break; | |
707 | case MSR_IA32_SYSENTER_CS: | |
708 | data = vmcs_read32(GUEST_SYSENTER_CS); | |
709 | break; | |
710 | case MSR_IA32_SYSENTER_EIP: | |
f5b42c33 | 711 | data = vmcs_readl(GUEST_SYSENTER_EIP); |
6aa8b732 AK |
712 | break; |
713 | case MSR_IA32_SYSENTER_ESP: | |
f5b42c33 | 714 | data = vmcs_readl(GUEST_SYSENTER_ESP); |
6aa8b732 | 715 | break; |
6aa8b732 | 716 | default: |
8b9cf98c | 717 | msr = find_msr_entry(to_vmx(vcpu), msr_index); |
3bab1f5d AK |
718 | if (msr) { |
719 | data = msr->data; | |
720 | break; | |
6aa8b732 | 721 | } |
3bab1f5d | 722 | return kvm_get_msr_common(vcpu, msr_index, pdata); |
6aa8b732 AK |
723 | } |
724 | ||
725 | *pdata = data; | |
726 | return 0; | |
727 | } | |
728 | ||
729 | /* | |
730 | * Writes msr value into into the appropriate "register". | |
731 | * Returns 0 on success, non-0 otherwise. | |
732 | * Assumes vcpu_load() was already called. | |
733 | */ | |
734 | static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data) | |
735 | { | |
a2fa3e9f GH |
736 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
737 | struct kvm_msr_entry *msr; | |
2cc51560 ED |
738 | int ret = 0; |
739 | ||
6aa8b732 | 740 | switch (msr_index) { |
05b3e0c2 | 741 | #ifdef CONFIG_X86_64 |
3bab1f5d | 742 | case MSR_EFER: |
2cc51560 | 743 | ret = kvm_set_msr_common(vcpu, msr_index, data); |
51c6cf66 AK |
744 | if (vmx->host_state.loaded) { |
745 | reload_host_efer(vmx); | |
8b9cf98c | 746 | load_transition_efer(vmx); |
51c6cf66 | 747 | } |
2cc51560 | 748 | break; |
6aa8b732 AK |
749 | case MSR_FS_BASE: |
750 | vmcs_writel(GUEST_FS_BASE, data); | |
751 | break; | |
752 | case MSR_GS_BASE: | |
753 | vmcs_writel(GUEST_GS_BASE, data); | |
754 | break; | |
755 | #endif | |
756 | case MSR_IA32_SYSENTER_CS: | |
757 | vmcs_write32(GUEST_SYSENTER_CS, data); | |
758 | break; | |
759 | case MSR_IA32_SYSENTER_EIP: | |
f5b42c33 | 760 | vmcs_writel(GUEST_SYSENTER_EIP, data); |
6aa8b732 AK |
761 | break; |
762 | case MSR_IA32_SYSENTER_ESP: | |
f5b42c33 | 763 | vmcs_writel(GUEST_SYSENTER_ESP, data); |
6aa8b732 | 764 | break; |
d27d4aca | 765 | case MSR_IA32_TIME_STAMP_COUNTER: |
6aa8b732 AK |
766 | guest_write_tsc(data); |
767 | break; | |
6aa8b732 | 768 | default: |
8b9cf98c | 769 | msr = find_msr_entry(vmx, msr_index); |
3bab1f5d AK |
770 | if (msr) { |
771 | msr->data = data; | |
a2fa3e9f GH |
772 | if (vmx->host_state.loaded) |
773 | load_msrs(vmx->guest_msrs, vmx->save_nmsrs); | |
3bab1f5d | 774 | break; |
6aa8b732 | 775 | } |
2cc51560 | 776 | ret = kvm_set_msr_common(vcpu, msr_index, data); |
6aa8b732 AK |
777 | } |
778 | ||
2cc51560 | 779 | return ret; |
6aa8b732 AK |
780 | } |
781 | ||
782 | /* | |
783 | * Sync the rsp and rip registers into the vcpu structure. This allows | |
784 | * registers to be accessed by indexing vcpu->regs. | |
785 | */ | |
786 | static void vcpu_load_rsp_rip(struct kvm_vcpu *vcpu) | |
787 | { | |
788 | vcpu->regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP); | |
789 | vcpu->rip = vmcs_readl(GUEST_RIP); | |
790 | } | |
791 | ||
792 | /* | |
793 | * Syncs rsp and rip back into the vmcs. Should be called after possible | |
794 | * modification. | |
795 | */ | |
796 | static void vcpu_put_rsp_rip(struct kvm_vcpu *vcpu) | |
797 | { | |
798 | vmcs_writel(GUEST_RSP, vcpu->regs[VCPU_REGS_RSP]); | |
799 | vmcs_writel(GUEST_RIP, vcpu->rip); | |
800 | } | |
801 | ||
802 | static int set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_debug_guest *dbg) | |
803 | { | |
804 | unsigned long dr7 = 0x400; | |
6aa8b732 AK |
805 | int old_singlestep; |
806 | ||
6aa8b732 AK |
807 | old_singlestep = vcpu->guest_debug.singlestep; |
808 | ||
809 | vcpu->guest_debug.enabled = dbg->enabled; | |
810 | if (vcpu->guest_debug.enabled) { | |
811 | int i; | |
812 | ||
813 | dr7 |= 0x200; /* exact */ | |
814 | for (i = 0; i < 4; ++i) { | |
815 | if (!dbg->breakpoints[i].enabled) | |
816 | continue; | |
817 | vcpu->guest_debug.bp[i] = dbg->breakpoints[i].address; | |
818 | dr7 |= 2 << (i*2); /* global enable */ | |
819 | dr7 |= 0 << (i*4+16); /* execution breakpoint */ | |
820 | } | |
821 | ||
6aa8b732 | 822 | vcpu->guest_debug.singlestep = dbg->singlestep; |
abd3f2d6 | 823 | } else |
6aa8b732 | 824 | vcpu->guest_debug.singlestep = 0; |
6aa8b732 AK |
825 | |
826 | if (old_singlestep && !vcpu->guest_debug.singlestep) { | |
827 | unsigned long flags; | |
828 | ||
829 | flags = vmcs_readl(GUEST_RFLAGS); | |
830 | flags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF); | |
831 | vmcs_writel(GUEST_RFLAGS, flags); | |
832 | } | |
833 | ||
abd3f2d6 | 834 | update_exception_bitmap(vcpu); |
6aa8b732 AK |
835 | vmcs_writel(GUEST_DR7, dr7); |
836 | ||
837 | return 0; | |
838 | } | |
839 | ||
2a8067f1 ED |
840 | static int vmx_get_irq(struct kvm_vcpu *vcpu) |
841 | { | |
842 | u32 idtv_info_field; | |
843 | ||
844 | idtv_info_field = vmcs_read32(IDT_VECTORING_INFO_FIELD); | |
845 | if (idtv_info_field & INTR_INFO_VALID_MASK) { | |
846 | if (is_external_interrupt(idtv_info_field)) | |
847 | return idtv_info_field & VECTORING_INFO_VECTOR_MASK; | |
848 | else | |
d77c26fc | 849 | printk(KERN_DEBUG "pending exception: not handled yet\n"); |
2a8067f1 ED |
850 | } |
851 | return -1; | |
852 | } | |
853 | ||
6aa8b732 AK |
854 | static __init int cpu_has_kvm_support(void) |
855 | { | |
856 | unsigned long ecx = cpuid_ecx(1); | |
857 | return test_bit(5, &ecx); /* CPUID.1:ECX.VMX[bit 5] -> VT */ | |
858 | } | |
859 | ||
860 | static __init int vmx_disabled_by_bios(void) | |
861 | { | |
862 | u64 msr; | |
863 | ||
864 | rdmsrl(MSR_IA32_FEATURE_CONTROL, msr); | |
62b3ffb8 YS |
865 | return (msr & (MSR_IA32_FEATURE_CONTROL_LOCKED | |
866 | MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED)) | |
867 | == MSR_IA32_FEATURE_CONTROL_LOCKED; | |
868 | /* locked but not enabled */ | |
6aa8b732 AK |
869 | } |
870 | ||
774c47f1 | 871 | static void hardware_enable(void *garbage) |
6aa8b732 AK |
872 | { |
873 | int cpu = raw_smp_processor_id(); | |
874 | u64 phys_addr = __pa(per_cpu(vmxarea, cpu)); | |
875 | u64 old; | |
876 | ||
877 | rdmsrl(MSR_IA32_FEATURE_CONTROL, old); | |
62b3ffb8 YS |
878 | if ((old & (MSR_IA32_FEATURE_CONTROL_LOCKED | |
879 | MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED)) | |
880 | != (MSR_IA32_FEATURE_CONTROL_LOCKED | | |
881 | MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED)) | |
6aa8b732 | 882 | /* enable and lock */ |
62b3ffb8 YS |
883 | wrmsrl(MSR_IA32_FEATURE_CONTROL, old | |
884 | MSR_IA32_FEATURE_CONTROL_LOCKED | | |
885 | MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED); | |
66aee91a | 886 | write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */ |
6aa8b732 AK |
887 | asm volatile (ASM_VMX_VMXON_RAX : : "a"(&phys_addr), "m"(phys_addr) |
888 | : "memory", "cc"); | |
889 | } | |
890 | ||
891 | static void hardware_disable(void *garbage) | |
892 | { | |
893 | asm volatile (ASM_VMX_VMXOFF : : : "cc"); | |
894 | } | |
895 | ||
1c3d14fe | 896 | static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt, |
d77c26fc | 897 | u32 msr, u32 *result) |
1c3d14fe YS |
898 | { |
899 | u32 vmx_msr_low, vmx_msr_high; | |
900 | u32 ctl = ctl_min | ctl_opt; | |
901 | ||
902 | rdmsr(msr, vmx_msr_low, vmx_msr_high); | |
903 | ||
904 | ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */ | |
905 | ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */ | |
906 | ||
907 | /* Ensure minimum (required) set of control bits are supported. */ | |
908 | if (ctl_min & ~ctl) | |
002c7f7c | 909 | return -EIO; |
1c3d14fe YS |
910 | |
911 | *result = ctl; | |
912 | return 0; | |
913 | } | |
914 | ||
002c7f7c | 915 | static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf) |
6aa8b732 AK |
916 | { |
917 | u32 vmx_msr_low, vmx_msr_high; | |
1c3d14fe YS |
918 | u32 min, opt; |
919 | u32 _pin_based_exec_control = 0; | |
920 | u32 _cpu_based_exec_control = 0; | |
921 | u32 _vmexit_control = 0; | |
922 | u32 _vmentry_control = 0; | |
923 | ||
924 | min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING; | |
925 | opt = 0; | |
926 | if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS, | |
927 | &_pin_based_exec_control) < 0) | |
002c7f7c | 928 | return -EIO; |
1c3d14fe YS |
929 | |
930 | min = CPU_BASED_HLT_EXITING | | |
931 | #ifdef CONFIG_X86_64 | |
932 | CPU_BASED_CR8_LOAD_EXITING | | |
933 | CPU_BASED_CR8_STORE_EXITING | | |
934 | #endif | |
935 | CPU_BASED_USE_IO_BITMAPS | | |
936 | CPU_BASED_MOV_DR_EXITING | | |
937 | CPU_BASED_USE_TSC_OFFSETING; | |
6e5d865c YS |
938 | #ifdef CONFIG_X86_64 |
939 | opt = CPU_BASED_TPR_SHADOW; | |
940 | #else | |
1c3d14fe | 941 | opt = 0; |
6e5d865c | 942 | #endif |
1c3d14fe YS |
943 | if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS, |
944 | &_cpu_based_exec_control) < 0) | |
002c7f7c | 945 | return -EIO; |
6e5d865c YS |
946 | #ifdef CONFIG_X86_64 |
947 | if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW)) | |
948 | _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING & | |
949 | ~CPU_BASED_CR8_STORE_EXITING; | |
950 | #endif | |
1c3d14fe YS |
951 | |
952 | min = 0; | |
953 | #ifdef CONFIG_X86_64 | |
954 | min |= VM_EXIT_HOST_ADDR_SPACE_SIZE; | |
955 | #endif | |
956 | opt = 0; | |
957 | if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS, | |
958 | &_vmexit_control) < 0) | |
002c7f7c | 959 | return -EIO; |
1c3d14fe YS |
960 | |
961 | min = opt = 0; | |
962 | if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS, | |
963 | &_vmentry_control) < 0) | |
002c7f7c | 964 | return -EIO; |
6aa8b732 | 965 | |
c68876fd | 966 | rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high); |
1c3d14fe YS |
967 | |
968 | /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */ | |
969 | if ((vmx_msr_high & 0x1fff) > PAGE_SIZE) | |
002c7f7c | 970 | return -EIO; |
1c3d14fe YS |
971 | |
972 | #ifdef CONFIG_X86_64 | |
973 | /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */ | |
974 | if (vmx_msr_high & (1u<<16)) | |
002c7f7c | 975 | return -EIO; |
1c3d14fe YS |
976 | #endif |
977 | ||
978 | /* Require Write-Back (WB) memory type for VMCS accesses. */ | |
979 | if (((vmx_msr_high >> 18) & 15) != 6) | |
002c7f7c | 980 | return -EIO; |
1c3d14fe | 981 | |
002c7f7c YS |
982 | vmcs_conf->size = vmx_msr_high & 0x1fff; |
983 | vmcs_conf->order = get_order(vmcs_config.size); | |
984 | vmcs_conf->revision_id = vmx_msr_low; | |
1c3d14fe | 985 | |
002c7f7c YS |
986 | vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control; |
987 | vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control; | |
988 | vmcs_conf->vmexit_ctrl = _vmexit_control; | |
989 | vmcs_conf->vmentry_ctrl = _vmentry_control; | |
1c3d14fe YS |
990 | |
991 | return 0; | |
c68876fd | 992 | } |
6aa8b732 AK |
993 | |
994 | static struct vmcs *alloc_vmcs_cpu(int cpu) | |
995 | { | |
996 | int node = cpu_to_node(cpu); | |
997 | struct page *pages; | |
998 | struct vmcs *vmcs; | |
999 | ||
1c3d14fe | 1000 | pages = alloc_pages_node(node, GFP_KERNEL, vmcs_config.order); |
6aa8b732 AK |
1001 | if (!pages) |
1002 | return NULL; | |
1003 | vmcs = page_address(pages); | |
1c3d14fe YS |
1004 | memset(vmcs, 0, vmcs_config.size); |
1005 | vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */ | |
6aa8b732 AK |
1006 | return vmcs; |
1007 | } | |
1008 | ||
1009 | static struct vmcs *alloc_vmcs(void) | |
1010 | { | |
d3b2c338 | 1011 | return alloc_vmcs_cpu(raw_smp_processor_id()); |
6aa8b732 AK |
1012 | } |
1013 | ||
1014 | static void free_vmcs(struct vmcs *vmcs) | |
1015 | { | |
1c3d14fe | 1016 | free_pages((unsigned long)vmcs, vmcs_config.order); |
6aa8b732 AK |
1017 | } |
1018 | ||
39959588 | 1019 | static void free_kvm_area(void) |
6aa8b732 AK |
1020 | { |
1021 | int cpu; | |
1022 | ||
1023 | for_each_online_cpu(cpu) | |
1024 | free_vmcs(per_cpu(vmxarea, cpu)); | |
1025 | } | |
1026 | ||
6aa8b732 AK |
1027 | static __init int alloc_kvm_area(void) |
1028 | { | |
1029 | int cpu; | |
1030 | ||
1031 | for_each_online_cpu(cpu) { | |
1032 | struct vmcs *vmcs; | |
1033 | ||
1034 | vmcs = alloc_vmcs_cpu(cpu); | |
1035 | if (!vmcs) { | |
1036 | free_kvm_area(); | |
1037 | return -ENOMEM; | |
1038 | } | |
1039 | ||
1040 | per_cpu(vmxarea, cpu) = vmcs; | |
1041 | } | |
1042 | return 0; | |
1043 | } | |
1044 | ||
1045 | static __init int hardware_setup(void) | |
1046 | { | |
002c7f7c YS |
1047 | if (setup_vmcs_config(&vmcs_config) < 0) |
1048 | return -EIO; | |
6aa8b732 AK |
1049 | return alloc_kvm_area(); |
1050 | } | |
1051 | ||
1052 | static __exit void hardware_unsetup(void) | |
1053 | { | |
1054 | free_kvm_area(); | |
1055 | } | |
1056 | ||
6aa8b732 AK |
1057 | static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save) |
1058 | { | |
1059 | struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; | |
1060 | ||
6af11b9e | 1061 | if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) { |
6aa8b732 AK |
1062 | vmcs_write16(sf->selector, save->selector); |
1063 | vmcs_writel(sf->base, save->base); | |
1064 | vmcs_write32(sf->limit, save->limit); | |
1065 | vmcs_write32(sf->ar_bytes, save->ar); | |
1066 | } else { | |
1067 | u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK) | |
1068 | << AR_DPL_SHIFT; | |
1069 | vmcs_write32(sf->ar_bytes, 0x93 | dpl); | |
1070 | } | |
1071 | } | |
1072 | ||
1073 | static void enter_pmode(struct kvm_vcpu *vcpu) | |
1074 | { | |
1075 | unsigned long flags; | |
1076 | ||
1077 | vcpu->rmode.active = 0; | |
1078 | ||
1079 | vmcs_writel(GUEST_TR_BASE, vcpu->rmode.tr.base); | |
1080 | vmcs_write32(GUEST_TR_LIMIT, vcpu->rmode.tr.limit); | |
1081 | vmcs_write32(GUEST_TR_AR_BYTES, vcpu->rmode.tr.ar); | |
1082 | ||
1083 | flags = vmcs_readl(GUEST_RFLAGS); | |
053de044 | 1084 | flags &= ~(X86_EFLAGS_IOPL | X86_EFLAGS_VM); |
6aa8b732 AK |
1085 | flags |= (vcpu->rmode.save_iopl << IOPL_SHIFT); |
1086 | vmcs_writel(GUEST_RFLAGS, flags); | |
1087 | ||
66aee91a RR |
1088 | vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) | |
1089 | (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME)); | |
6aa8b732 AK |
1090 | |
1091 | update_exception_bitmap(vcpu); | |
1092 | ||
1093 | fix_pmode_dataseg(VCPU_SREG_ES, &vcpu->rmode.es); | |
1094 | fix_pmode_dataseg(VCPU_SREG_DS, &vcpu->rmode.ds); | |
1095 | fix_pmode_dataseg(VCPU_SREG_GS, &vcpu->rmode.gs); | |
1096 | fix_pmode_dataseg(VCPU_SREG_FS, &vcpu->rmode.fs); | |
1097 | ||
1098 | vmcs_write16(GUEST_SS_SELECTOR, 0); | |
1099 | vmcs_write32(GUEST_SS_AR_BYTES, 0x93); | |
1100 | ||
1101 | vmcs_write16(GUEST_CS_SELECTOR, | |
1102 | vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK); | |
1103 | vmcs_write32(GUEST_CS_AR_BYTES, 0x9b); | |
1104 | } | |
1105 | ||
d77c26fc | 1106 | static gva_t rmode_tss_base(struct kvm *kvm) |
6aa8b732 | 1107 | { |
cbc94022 IE |
1108 | if (!kvm->tss_addr) { |
1109 | gfn_t base_gfn = kvm->memslots[0].base_gfn + | |
1110 | kvm->memslots[0].npages - 3; | |
1111 | return base_gfn << PAGE_SHIFT; | |
1112 | } | |
1113 | return kvm->tss_addr; | |
6aa8b732 AK |
1114 | } |
1115 | ||
1116 | static void fix_rmode_seg(int seg, struct kvm_save_segment *save) | |
1117 | { | |
1118 | struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; | |
1119 | ||
1120 | save->selector = vmcs_read16(sf->selector); | |
1121 | save->base = vmcs_readl(sf->base); | |
1122 | save->limit = vmcs_read32(sf->limit); | |
1123 | save->ar = vmcs_read32(sf->ar_bytes); | |
1124 | vmcs_write16(sf->selector, vmcs_readl(sf->base) >> 4); | |
1125 | vmcs_write32(sf->limit, 0xffff); | |
1126 | vmcs_write32(sf->ar_bytes, 0xf3); | |
1127 | } | |
1128 | ||
1129 | static void enter_rmode(struct kvm_vcpu *vcpu) | |
1130 | { | |
1131 | unsigned long flags; | |
1132 | ||
1133 | vcpu->rmode.active = 1; | |
1134 | ||
1135 | vcpu->rmode.tr.base = vmcs_readl(GUEST_TR_BASE); | |
1136 | vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm)); | |
1137 | ||
1138 | vcpu->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT); | |
1139 | vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1); | |
1140 | ||
1141 | vcpu->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES); | |
1142 | vmcs_write32(GUEST_TR_AR_BYTES, 0x008b); | |
1143 | ||
1144 | flags = vmcs_readl(GUEST_RFLAGS); | |
053de044 | 1145 | vcpu->rmode.save_iopl = (flags & X86_EFLAGS_IOPL) >> IOPL_SHIFT; |
6aa8b732 | 1146 | |
053de044 | 1147 | flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM; |
6aa8b732 AK |
1148 | |
1149 | vmcs_writel(GUEST_RFLAGS, flags); | |
66aee91a | 1150 | vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME); |
6aa8b732 AK |
1151 | update_exception_bitmap(vcpu); |
1152 | ||
1153 | vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4); | |
1154 | vmcs_write32(GUEST_SS_LIMIT, 0xffff); | |
1155 | vmcs_write32(GUEST_SS_AR_BYTES, 0xf3); | |
1156 | ||
1157 | vmcs_write32(GUEST_CS_AR_BYTES, 0xf3); | |
abacf8df | 1158 | vmcs_write32(GUEST_CS_LIMIT, 0xffff); |
8cb5b033 AK |
1159 | if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000) |
1160 | vmcs_writel(GUEST_CS_BASE, 0xf0000); | |
6aa8b732 AK |
1161 | vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4); |
1162 | ||
1163 | fix_rmode_seg(VCPU_SREG_ES, &vcpu->rmode.es); | |
1164 | fix_rmode_seg(VCPU_SREG_DS, &vcpu->rmode.ds); | |
1165 | fix_rmode_seg(VCPU_SREG_GS, &vcpu->rmode.gs); | |
1166 | fix_rmode_seg(VCPU_SREG_FS, &vcpu->rmode.fs); | |
75880a01 | 1167 | |
8668a3c4 | 1168 | kvm_mmu_reset_context(vcpu); |
75880a01 | 1169 | init_rmode_tss(vcpu->kvm); |
6aa8b732 AK |
1170 | } |
1171 | ||
05b3e0c2 | 1172 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
1173 | |
1174 | static void enter_lmode(struct kvm_vcpu *vcpu) | |
1175 | { | |
1176 | u32 guest_tr_ar; | |
1177 | ||
1178 | guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES); | |
1179 | if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) { | |
1180 | printk(KERN_DEBUG "%s: tss fixup for long mode. \n", | |
1181 | __FUNCTION__); | |
1182 | vmcs_write32(GUEST_TR_AR_BYTES, | |
1183 | (guest_tr_ar & ~AR_TYPE_MASK) | |
1184 | | AR_TYPE_BUSY_64_TSS); | |
1185 | } | |
1186 | ||
1187 | vcpu->shadow_efer |= EFER_LMA; | |
1188 | ||
8b9cf98c | 1189 | find_msr_entry(to_vmx(vcpu), MSR_EFER)->data |= EFER_LMA | EFER_LME; |
6aa8b732 AK |
1190 | vmcs_write32(VM_ENTRY_CONTROLS, |
1191 | vmcs_read32(VM_ENTRY_CONTROLS) | |
1e4e6e00 | 1192 | | VM_ENTRY_IA32E_MODE); |
6aa8b732 AK |
1193 | } |
1194 | ||
1195 | static void exit_lmode(struct kvm_vcpu *vcpu) | |
1196 | { | |
1197 | vcpu->shadow_efer &= ~EFER_LMA; | |
1198 | ||
1199 | vmcs_write32(VM_ENTRY_CONTROLS, | |
1200 | vmcs_read32(VM_ENTRY_CONTROLS) | |
1e4e6e00 | 1201 | & ~VM_ENTRY_IA32E_MODE); |
6aa8b732 AK |
1202 | } |
1203 | ||
1204 | #endif | |
1205 | ||
25c4c276 | 1206 | static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu) |
399badf3 | 1207 | { |
399badf3 AK |
1208 | vcpu->cr4 &= KVM_GUEST_CR4_MASK; |
1209 | vcpu->cr4 |= vmcs_readl(GUEST_CR4) & ~KVM_GUEST_CR4_MASK; | |
1210 | } | |
1211 | ||
6aa8b732 AK |
1212 | static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) |
1213 | { | |
5fd86fcf AK |
1214 | vmx_fpu_deactivate(vcpu); |
1215 | ||
707d92fa | 1216 | if (vcpu->rmode.active && (cr0 & X86_CR0_PE)) |
6aa8b732 AK |
1217 | enter_pmode(vcpu); |
1218 | ||
707d92fa | 1219 | if (!vcpu->rmode.active && !(cr0 & X86_CR0_PE)) |
6aa8b732 AK |
1220 | enter_rmode(vcpu); |
1221 | ||
05b3e0c2 | 1222 | #ifdef CONFIG_X86_64 |
6aa8b732 | 1223 | if (vcpu->shadow_efer & EFER_LME) { |
707d92fa | 1224 | if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) |
6aa8b732 | 1225 | enter_lmode(vcpu); |
707d92fa | 1226 | if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) |
6aa8b732 AK |
1227 | exit_lmode(vcpu); |
1228 | } | |
1229 | #endif | |
1230 | ||
1231 | vmcs_writel(CR0_READ_SHADOW, cr0); | |
1232 | vmcs_writel(GUEST_CR0, | |
1233 | (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON); | |
1234 | vcpu->cr0 = cr0; | |
5fd86fcf | 1235 | |
707d92fa | 1236 | if (!(cr0 & X86_CR0_TS) || !(cr0 & X86_CR0_PE)) |
5fd86fcf | 1237 | vmx_fpu_activate(vcpu); |
6aa8b732 AK |
1238 | } |
1239 | ||
6aa8b732 AK |
1240 | static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3) |
1241 | { | |
1242 | vmcs_writel(GUEST_CR3, cr3); | |
707d92fa | 1243 | if (vcpu->cr0 & X86_CR0_PE) |
5fd86fcf | 1244 | vmx_fpu_deactivate(vcpu); |
6aa8b732 AK |
1245 | } |
1246 | ||
1247 | static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) | |
1248 | { | |
1249 | vmcs_writel(CR4_READ_SHADOW, cr4); | |
1250 | vmcs_writel(GUEST_CR4, cr4 | (vcpu->rmode.active ? | |
1251 | KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON)); | |
1252 | vcpu->cr4 = cr4; | |
1253 | } | |
1254 | ||
05b3e0c2 | 1255 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
1256 | |
1257 | static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer) | |
1258 | { | |
8b9cf98c RR |
1259 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
1260 | struct kvm_msr_entry *msr = find_msr_entry(vmx, MSR_EFER); | |
6aa8b732 AK |
1261 | |
1262 | vcpu->shadow_efer = efer; | |
1263 | if (efer & EFER_LMA) { | |
1264 | vmcs_write32(VM_ENTRY_CONTROLS, | |
1265 | vmcs_read32(VM_ENTRY_CONTROLS) | | |
1e4e6e00 | 1266 | VM_ENTRY_IA32E_MODE); |
6aa8b732 AK |
1267 | msr->data = efer; |
1268 | ||
1269 | } else { | |
1270 | vmcs_write32(VM_ENTRY_CONTROLS, | |
1271 | vmcs_read32(VM_ENTRY_CONTROLS) & | |
1e4e6e00 | 1272 | ~VM_ENTRY_IA32E_MODE); |
6aa8b732 AK |
1273 | |
1274 | msr->data = efer & ~EFER_LME; | |
1275 | } | |
8b9cf98c | 1276 | setup_msrs(vmx); |
6aa8b732 AK |
1277 | } |
1278 | ||
1279 | #endif | |
1280 | ||
1281 | static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg) | |
1282 | { | |
1283 | struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; | |
1284 | ||
1285 | return vmcs_readl(sf->base); | |
1286 | } | |
1287 | ||
1288 | static void vmx_get_segment(struct kvm_vcpu *vcpu, | |
1289 | struct kvm_segment *var, int seg) | |
1290 | { | |
1291 | struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; | |
1292 | u32 ar; | |
1293 | ||
1294 | var->base = vmcs_readl(sf->base); | |
1295 | var->limit = vmcs_read32(sf->limit); | |
1296 | var->selector = vmcs_read16(sf->selector); | |
1297 | ar = vmcs_read32(sf->ar_bytes); | |
1298 | if (ar & AR_UNUSABLE_MASK) | |
1299 | ar = 0; | |
1300 | var->type = ar & 15; | |
1301 | var->s = (ar >> 4) & 1; | |
1302 | var->dpl = (ar >> 5) & 3; | |
1303 | var->present = (ar >> 7) & 1; | |
1304 | var->avl = (ar >> 12) & 1; | |
1305 | var->l = (ar >> 13) & 1; | |
1306 | var->db = (ar >> 14) & 1; | |
1307 | var->g = (ar >> 15) & 1; | |
1308 | var->unusable = (ar >> 16) & 1; | |
1309 | } | |
1310 | ||
653e3108 | 1311 | static u32 vmx_segment_access_rights(struct kvm_segment *var) |
6aa8b732 | 1312 | { |
6aa8b732 AK |
1313 | u32 ar; |
1314 | ||
653e3108 | 1315 | if (var->unusable) |
6aa8b732 AK |
1316 | ar = 1 << 16; |
1317 | else { | |
1318 | ar = var->type & 15; | |
1319 | ar |= (var->s & 1) << 4; | |
1320 | ar |= (var->dpl & 3) << 5; | |
1321 | ar |= (var->present & 1) << 7; | |
1322 | ar |= (var->avl & 1) << 12; | |
1323 | ar |= (var->l & 1) << 13; | |
1324 | ar |= (var->db & 1) << 14; | |
1325 | ar |= (var->g & 1) << 15; | |
1326 | } | |
f7fbf1fd UL |
1327 | if (ar == 0) /* a 0 value means unusable */ |
1328 | ar = AR_UNUSABLE_MASK; | |
653e3108 AK |
1329 | |
1330 | return ar; | |
1331 | } | |
1332 | ||
1333 | static void vmx_set_segment(struct kvm_vcpu *vcpu, | |
1334 | struct kvm_segment *var, int seg) | |
1335 | { | |
1336 | struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; | |
1337 | u32 ar; | |
1338 | ||
1339 | if (vcpu->rmode.active && seg == VCPU_SREG_TR) { | |
1340 | vcpu->rmode.tr.selector = var->selector; | |
1341 | vcpu->rmode.tr.base = var->base; | |
1342 | vcpu->rmode.tr.limit = var->limit; | |
1343 | vcpu->rmode.tr.ar = vmx_segment_access_rights(var); | |
1344 | return; | |
1345 | } | |
1346 | vmcs_writel(sf->base, var->base); | |
1347 | vmcs_write32(sf->limit, var->limit); | |
1348 | vmcs_write16(sf->selector, var->selector); | |
1349 | if (vcpu->rmode.active && var->s) { | |
1350 | /* | |
1351 | * Hack real-mode segments into vm86 compatibility. | |
1352 | */ | |
1353 | if (var->base == 0xffff0000 && var->selector == 0xf000) | |
1354 | vmcs_writel(sf->base, 0xf0000); | |
1355 | ar = 0xf3; | |
1356 | } else | |
1357 | ar = vmx_segment_access_rights(var); | |
6aa8b732 AK |
1358 | vmcs_write32(sf->ar_bytes, ar); |
1359 | } | |
1360 | ||
6aa8b732 AK |
1361 | static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l) |
1362 | { | |
1363 | u32 ar = vmcs_read32(GUEST_CS_AR_BYTES); | |
1364 | ||
1365 | *db = (ar >> 14) & 1; | |
1366 | *l = (ar >> 13) & 1; | |
1367 | } | |
1368 | ||
1369 | static void vmx_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt) | |
1370 | { | |
1371 | dt->limit = vmcs_read32(GUEST_IDTR_LIMIT); | |
1372 | dt->base = vmcs_readl(GUEST_IDTR_BASE); | |
1373 | } | |
1374 | ||
1375 | static void vmx_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt) | |
1376 | { | |
1377 | vmcs_write32(GUEST_IDTR_LIMIT, dt->limit); | |
1378 | vmcs_writel(GUEST_IDTR_BASE, dt->base); | |
1379 | } | |
1380 | ||
1381 | static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt) | |
1382 | { | |
1383 | dt->limit = vmcs_read32(GUEST_GDTR_LIMIT); | |
1384 | dt->base = vmcs_readl(GUEST_GDTR_BASE); | |
1385 | } | |
1386 | ||
1387 | static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt) | |
1388 | { | |
1389 | vmcs_write32(GUEST_GDTR_LIMIT, dt->limit); | |
1390 | vmcs_writel(GUEST_GDTR_BASE, dt->base); | |
1391 | } | |
1392 | ||
d77c26fc | 1393 | static int init_rmode_tss(struct kvm *kvm) |
6aa8b732 | 1394 | { |
6aa8b732 | 1395 | gfn_t fn = rmode_tss_base(kvm) >> PAGE_SHIFT; |
195aefde IE |
1396 | u16 data = 0; |
1397 | int r; | |
6aa8b732 | 1398 | |
195aefde IE |
1399 | r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE); |
1400 | if (r < 0) | |
1401 | return 0; | |
1402 | data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE; | |
1403 | r = kvm_write_guest_page(kvm, fn++, &data, 0x66, sizeof(u16)); | |
1404 | if (r < 0) | |
1405 | return 0; | |
1406 | r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE); | |
1407 | if (r < 0) | |
1408 | return 0; | |
1409 | r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE); | |
1410 | if (r < 0) | |
1411 | return 0; | |
1412 | data = ~0; | |
1413 | r = kvm_write_guest_page(kvm, fn, &data, RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1, | |
1414 | sizeof(u8)); | |
1415 | if (r < 0) | |
6aa8b732 | 1416 | return 0; |
6aa8b732 AK |
1417 | return 1; |
1418 | } | |
1419 | ||
6aa8b732 AK |
1420 | static void seg_setup(int seg) |
1421 | { | |
1422 | struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; | |
1423 | ||
1424 | vmcs_write16(sf->selector, 0); | |
1425 | vmcs_writel(sf->base, 0); | |
1426 | vmcs_write32(sf->limit, 0xffff); | |
1427 | vmcs_write32(sf->ar_bytes, 0x93); | |
1428 | } | |
1429 | ||
1430 | /* | |
1431 | * Sets up the vmcs for emulated real mode. | |
1432 | */ | |
8b9cf98c | 1433 | static int vmx_vcpu_setup(struct vcpu_vmx *vmx) |
6aa8b732 AK |
1434 | { |
1435 | u32 host_sysenter_cs; | |
1436 | u32 junk; | |
1437 | unsigned long a; | |
1438 | struct descriptor_table dt; | |
1439 | int i; | |
cd2276a7 | 1440 | unsigned long kvm_vmx_return; |
6e5d865c | 1441 | u32 exec_control; |
6aa8b732 | 1442 | |
6aa8b732 | 1443 | /* I/O */ |
fdef3ad1 HQ |
1444 | vmcs_write64(IO_BITMAP_A, page_to_phys(vmx_io_bitmap_a)); |
1445 | vmcs_write64(IO_BITMAP_B, page_to_phys(vmx_io_bitmap_b)); | |
6aa8b732 | 1446 | |
6aa8b732 AK |
1447 | vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */ |
1448 | ||
6aa8b732 | 1449 | /* Control */ |
1c3d14fe YS |
1450 | vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, |
1451 | vmcs_config.pin_based_exec_ctrl); | |
6e5d865c YS |
1452 | |
1453 | exec_control = vmcs_config.cpu_based_exec_ctrl; | |
1454 | if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) { | |
1455 | exec_control &= ~CPU_BASED_TPR_SHADOW; | |
1456 | #ifdef CONFIG_X86_64 | |
1457 | exec_control |= CPU_BASED_CR8_STORE_EXITING | | |
1458 | CPU_BASED_CR8_LOAD_EXITING; | |
1459 | #endif | |
1460 | } | |
1461 | vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control); | |
6aa8b732 | 1462 | |
c7addb90 AK |
1463 | vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, !!bypass_guest_pf); |
1464 | vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, !!bypass_guest_pf); | |
6aa8b732 AK |
1465 | vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */ |
1466 | ||
1467 | vmcs_writel(HOST_CR0, read_cr0()); /* 22.2.3 */ | |
1468 | vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */ | |
1469 | vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */ | |
1470 | ||
1471 | vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */ | |
1472 | vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */ | |
1473 | vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */ | |
1474 | vmcs_write16(HOST_FS_SELECTOR, read_fs()); /* 22.2.4 */ | |
1475 | vmcs_write16(HOST_GS_SELECTOR, read_gs()); /* 22.2.4 */ | |
1476 | vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */ | |
05b3e0c2 | 1477 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
1478 | rdmsrl(MSR_FS_BASE, a); |
1479 | vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */ | |
1480 | rdmsrl(MSR_GS_BASE, a); | |
1481 | vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */ | |
1482 | #else | |
1483 | vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */ | |
1484 | vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */ | |
1485 | #endif | |
1486 | ||
1487 | vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */ | |
1488 | ||
1489 | get_idt(&dt); | |
1490 | vmcs_writel(HOST_IDTR_BASE, dt.base); /* 22.2.4 */ | |
1491 | ||
d77c26fc | 1492 | asm("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return)); |
cd2276a7 | 1493 | vmcs_writel(HOST_RIP, kvm_vmx_return); /* 22.2.5 */ |
2cc51560 ED |
1494 | vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0); |
1495 | vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0); | |
1496 | vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0); | |
6aa8b732 AK |
1497 | |
1498 | rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk); | |
1499 | vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs); | |
1500 | rdmsrl(MSR_IA32_SYSENTER_ESP, a); | |
1501 | vmcs_writel(HOST_IA32_SYSENTER_ESP, a); /* 22.2.3 */ | |
1502 | rdmsrl(MSR_IA32_SYSENTER_EIP, a); | |
1503 | vmcs_writel(HOST_IA32_SYSENTER_EIP, a); /* 22.2.3 */ | |
1504 | ||
6aa8b732 AK |
1505 | for (i = 0; i < NR_VMX_MSR; ++i) { |
1506 | u32 index = vmx_msr_index[i]; | |
1507 | u32 data_low, data_high; | |
1508 | u64 data; | |
a2fa3e9f | 1509 | int j = vmx->nmsrs; |
6aa8b732 AK |
1510 | |
1511 | if (rdmsr_safe(index, &data_low, &data_high) < 0) | |
1512 | continue; | |
432bd6cb AK |
1513 | if (wrmsr_safe(index, data_low, data_high) < 0) |
1514 | continue; | |
6aa8b732 | 1515 | data = data_low | ((u64)data_high << 32); |
a2fa3e9f GH |
1516 | vmx->host_msrs[j].index = index; |
1517 | vmx->host_msrs[j].reserved = 0; | |
1518 | vmx->host_msrs[j].data = data; | |
1519 | vmx->guest_msrs[j] = vmx->host_msrs[j]; | |
1520 | ++vmx->nmsrs; | |
6aa8b732 | 1521 | } |
6aa8b732 | 1522 | |
1c3d14fe | 1523 | vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl); |
6aa8b732 AK |
1524 | |
1525 | /* 22.2.1, 20.8.1 */ | |
1c3d14fe YS |
1526 | vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl); |
1527 | ||
e00c8cf2 AK |
1528 | vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL); |
1529 | vmcs_writel(CR4_GUEST_HOST_MASK, KVM_GUEST_CR4_MASK); | |
1530 | ||
1531 | return 0; | |
1532 | } | |
1533 | ||
1534 | static int vmx_vcpu_reset(struct kvm_vcpu *vcpu) | |
1535 | { | |
1536 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
1537 | u64 msr; | |
1538 | int ret; | |
1539 | ||
1540 | if (!init_rmode_tss(vmx->vcpu.kvm)) { | |
1541 | ret = -ENOMEM; | |
1542 | goto out; | |
1543 | } | |
1544 | ||
1545 | vmx->vcpu.rmode.active = 0; | |
1546 | ||
1547 | vmx->vcpu.regs[VCPU_REGS_RDX] = get_rdx_init_val(); | |
1548 | set_cr8(&vmx->vcpu, 0); | |
1549 | msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE; | |
1550 | if (vmx->vcpu.vcpu_id == 0) | |
1551 | msr |= MSR_IA32_APICBASE_BSP; | |
1552 | kvm_set_apic_base(&vmx->vcpu, msr); | |
1553 | ||
1554 | fx_init(&vmx->vcpu); | |
1555 | ||
1556 | /* | |
1557 | * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode | |
1558 | * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh. | |
1559 | */ | |
1560 | if (vmx->vcpu.vcpu_id == 0) { | |
1561 | vmcs_write16(GUEST_CS_SELECTOR, 0xf000); | |
1562 | vmcs_writel(GUEST_CS_BASE, 0x000f0000); | |
1563 | } else { | |
1564 | vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.sipi_vector << 8); | |
1565 | vmcs_writel(GUEST_CS_BASE, vmx->vcpu.sipi_vector << 12); | |
1566 | } | |
1567 | vmcs_write32(GUEST_CS_LIMIT, 0xffff); | |
1568 | vmcs_write32(GUEST_CS_AR_BYTES, 0x9b); | |
1569 | ||
1570 | seg_setup(VCPU_SREG_DS); | |
1571 | seg_setup(VCPU_SREG_ES); | |
1572 | seg_setup(VCPU_SREG_FS); | |
1573 | seg_setup(VCPU_SREG_GS); | |
1574 | seg_setup(VCPU_SREG_SS); | |
1575 | ||
1576 | vmcs_write16(GUEST_TR_SELECTOR, 0); | |
1577 | vmcs_writel(GUEST_TR_BASE, 0); | |
1578 | vmcs_write32(GUEST_TR_LIMIT, 0xffff); | |
1579 | vmcs_write32(GUEST_TR_AR_BYTES, 0x008b); | |
1580 | ||
1581 | vmcs_write16(GUEST_LDTR_SELECTOR, 0); | |
1582 | vmcs_writel(GUEST_LDTR_BASE, 0); | |
1583 | vmcs_write32(GUEST_LDTR_LIMIT, 0xffff); | |
1584 | vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082); | |
1585 | ||
1586 | vmcs_write32(GUEST_SYSENTER_CS, 0); | |
1587 | vmcs_writel(GUEST_SYSENTER_ESP, 0); | |
1588 | vmcs_writel(GUEST_SYSENTER_EIP, 0); | |
1589 | ||
1590 | vmcs_writel(GUEST_RFLAGS, 0x02); | |
1591 | if (vmx->vcpu.vcpu_id == 0) | |
1592 | vmcs_writel(GUEST_RIP, 0xfff0); | |
1593 | else | |
1594 | vmcs_writel(GUEST_RIP, 0); | |
1595 | vmcs_writel(GUEST_RSP, 0); | |
1596 | ||
1597 | /* todo: dr0 = dr1 = dr2 = dr3 = 0; dr6 = 0xffff0ff0 */ | |
1598 | vmcs_writel(GUEST_DR7, 0x400); | |
1599 | ||
1600 | vmcs_writel(GUEST_GDTR_BASE, 0); | |
1601 | vmcs_write32(GUEST_GDTR_LIMIT, 0xffff); | |
1602 | ||
1603 | vmcs_writel(GUEST_IDTR_BASE, 0); | |
1604 | vmcs_write32(GUEST_IDTR_LIMIT, 0xffff); | |
1605 | ||
1606 | vmcs_write32(GUEST_ACTIVITY_STATE, 0); | |
1607 | vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0); | |
1608 | vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0); | |
1609 | ||
1610 | guest_write_tsc(0); | |
1611 | ||
1612 | /* Special registers */ | |
1613 | vmcs_write64(GUEST_IA32_DEBUGCTL, 0); | |
1614 | ||
1615 | setup_msrs(vmx); | |
1616 | ||
6aa8b732 AK |
1617 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */ |
1618 | ||
3b99ab24 | 1619 | #ifdef CONFIG_X86_64 |
6e5d865c YS |
1620 | vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0); |
1621 | if (vm_need_tpr_shadow(vmx->vcpu.kvm)) | |
1622 | vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, | |
1623 | page_to_phys(vmx->vcpu.apic->regs_page)); | |
1624 | vmcs_write32(TPR_THRESHOLD, 0); | |
3b99ab24 | 1625 | #endif |
6aa8b732 | 1626 | |
8b9cf98c | 1627 | vmx->vcpu.cr0 = 0x60000010; |
d77c26fc | 1628 | vmx_set_cr0(&vmx->vcpu, vmx->vcpu.cr0); /* enter rmode */ |
8b9cf98c | 1629 | vmx_set_cr4(&vmx->vcpu, 0); |
05b3e0c2 | 1630 | #ifdef CONFIG_X86_64 |
8b9cf98c | 1631 | vmx_set_efer(&vmx->vcpu, 0); |
6aa8b732 | 1632 | #endif |
8b9cf98c RR |
1633 | vmx_fpu_activate(&vmx->vcpu); |
1634 | update_exception_bitmap(&vmx->vcpu); | |
6aa8b732 AK |
1635 | |
1636 | return 0; | |
1637 | ||
6aa8b732 AK |
1638 | out: |
1639 | return ret; | |
1640 | } | |
1641 | ||
1642 | static void inject_rmode_irq(struct kvm_vcpu *vcpu, int irq) | |
1643 | { | |
1644 | u16 ent[2]; | |
1645 | u16 cs; | |
1646 | u16 ip; | |
1647 | unsigned long flags; | |
1648 | unsigned long ss_base = vmcs_readl(GUEST_SS_BASE); | |
1649 | u16 sp = vmcs_readl(GUEST_RSP); | |
1650 | u32 ss_limit = vmcs_read32(GUEST_SS_LIMIT); | |
1651 | ||
d77c26fc | 1652 | if (sp > ss_limit || sp < 6) { |
6aa8b732 AK |
1653 | vcpu_printf(vcpu, "%s: #SS, rsp 0x%lx ss 0x%lx limit 0x%x\n", |
1654 | __FUNCTION__, | |
1655 | vmcs_readl(GUEST_RSP), | |
1656 | vmcs_readl(GUEST_SS_BASE), | |
1657 | vmcs_read32(GUEST_SS_LIMIT)); | |
1658 | return; | |
1659 | } | |
1660 | ||
e7d5d76c LV |
1661 | if (emulator_read_std(irq * sizeof(ent), &ent, sizeof(ent), vcpu) != |
1662 | X86EMUL_CONTINUE) { | |
6aa8b732 AK |
1663 | vcpu_printf(vcpu, "%s: read guest err\n", __FUNCTION__); |
1664 | return; | |
1665 | } | |
1666 | ||
1667 | flags = vmcs_readl(GUEST_RFLAGS); | |
1668 | cs = vmcs_readl(GUEST_CS_BASE) >> 4; | |
1669 | ip = vmcs_readl(GUEST_RIP); | |
1670 | ||
1671 | ||
d77c26fc MD |
1672 | if (emulator_write_emulated( |
1673 | ss_base + sp - 2, &flags, 2, vcpu) != X86EMUL_CONTINUE || | |
1674 | emulator_write_emulated( | |
1675 | ss_base + sp - 4, &cs, 2, vcpu) != X86EMUL_CONTINUE || | |
1676 | emulator_write_emulated( | |
1677 | ss_base + sp - 6, &ip, 2, vcpu) != X86EMUL_CONTINUE) { | |
6aa8b732 AK |
1678 | vcpu_printf(vcpu, "%s: write guest err\n", __FUNCTION__); |
1679 | return; | |
1680 | } | |
1681 | ||
1682 | vmcs_writel(GUEST_RFLAGS, flags & | |
d77c26fc | 1683 | ~(X86_EFLAGS_IF | X86_EFLAGS_AC | X86_EFLAGS_TF)); |
6aa8b732 AK |
1684 | vmcs_write16(GUEST_CS_SELECTOR, ent[1]) ; |
1685 | vmcs_writel(GUEST_CS_BASE, ent[1] << 4); | |
1686 | vmcs_writel(GUEST_RIP, ent[0]); | |
1687 | vmcs_writel(GUEST_RSP, (vmcs_readl(GUEST_RSP) & ~0xffff) | (sp - 6)); | |
1688 | } | |
1689 | ||
85f455f7 ED |
1690 | static void vmx_inject_irq(struct kvm_vcpu *vcpu, int irq) |
1691 | { | |
1692 | if (vcpu->rmode.active) { | |
1693 | inject_rmode_irq(vcpu, irq); | |
1694 | return; | |
1695 | } | |
1696 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, | |
1697 | irq | INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK); | |
1698 | } | |
1699 | ||
6aa8b732 AK |
1700 | static void kvm_do_inject_irq(struct kvm_vcpu *vcpu) |
1701 | { | |
1702 | int word_index = __ffs(vcpu->irq_summary); | |
1703 | int bit_index = __ffs(vcpu->irq_pending[word_index]); | |
1704 | int irq = word_index * BITS_PER_LONG + bit_index; | |
1705 | ||
1706 | clear_bit(bit_index, &vcpu->irq_pending[word_index]); | |
1707 | if (!vcpu->irq_pending[word_index]) | |
1708 | clear_bit(word_index, &vcpu->irq_summary); | |
85f455f7 | 1709 | vmx_inject_irq(vcpu, irq); |
6aa8b732 AK |
1710 | } |
1711 | ||
c1150d8c DL |
1712 | |
1713 | static void do_interrupt_requests(struct kvm_vcpu *vcpu, | |
1714 | struct kvm_run *kvm_run) | |
6aa8b732 | 1715 | { |
c1150d8c DL |
1716 | u32 cpu_based_vm_exec_control; |
1717 | ||
1718 | vcpu->interrupt_window_open = | |
1719 | ((vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) && | |
1720 | (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 3) == 0); | |
1721 | ||
1722 | if (vcpu->interrupt_window_open && | |
1723 | vcpu->irq_summary && | |
1724 | !(vmcs_read32(VM_ENTRY_INTR_INFO_FIELD) & INTR_INFO_VALID_MASK)) | |
6aa8b732 | 1725 | /* |
c1150d8c | 1726 | * If interrupts enabled, and not blocked by sti or mov ss. Good. |
6aa8b732 AK |
1727 | */ |
1728 | kvm_do_inject_irq(vcpu); | |
c1150d8c DL |
1729 | |
1730 | cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL); | |
1731 | if (!vcpu->interrupt_window_open && | |
1732 | (vcpu->irq_summary || kvm_run->request_interrupt_window)) | |
6aa8b732 AK |
1733 | /* |
1734 | * Interrupts blocked. Wait for unblock. | |
1735 | */ | |
c1150d8c DL |
1736 | cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING; |
1737 | else | |
1738 | cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING; | |
1739 | vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control); | |
6aa8b732 AK |
1740 | } |
1741 | ||
cbc94022 IE |
1742 | static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr) |
1743 | { | |
1744 | int ret; | |
1745 | struct kvm_userspace_memory_region tss_mem = { | |
1746 | .slot = 8, | |
1747 | .guest_phys_addr = addr, | |
1748 | .memory_size = PAGE_SIZE * 3, | |
1749 | .flags = 0, | |
1750 | }; | |
1751 | ||
1752 | ret = kvm_set_memory_region(kvm, &tss_mem, 0); | |
1753 | if (ret) | |
1754 | return ret; | |
1755 | kvm->tss_addr = addr; | |
1756 | return 0; | |
1757 | } | |
1758 | ||
6aa8b732 AK |
1759 | static void kvm_guest_debug_pre(struct kvm_vcpu *vcpu) |
1760 | { | |
1761 | struct kvm_guest_debug *dbg = &vcpu->guest_debug; | |
1762 | ||
1763 | set_debugreg(dbg->bp[0], 0); | |
1764 | set_debugreg(dbg->bp[1], 1); | |
1765 | set_debugreg(dbg->bp[2], 2); | |
1766 | set_debugreg(dbg->bp[3], 3); | |
1767 | ||
1768 | if (dbg->singlestep) { | |
1769 | unsigned long flags; | |
1770 | ||
1771 | flags = vmcs_readl(GUEST_RFLAGS); | |
1772 | flags |= X86_EFLAGS_TF | X86_EFLAGS_RF; | |
1773 | vmcs_writel(GUEST_RFLAGS, flags); | |
1774 | } | |
1775 | } | |
1776 | ||
1777 | static int handle_rmode_exception(struct kvm_vcpu *vcpu, | |
1778 | int vec, u32 err_code) | |
1779 | { | |
1780 | if (!vcpu->rmode.active) | |
1781 | return 0; | |
1782 | ||
b3f37707 NK |
1783 | /* |
1784 | * Instruction with address size override prefix opcode 0x67 | |
1785 | * Cause the #SS fault with 0 error code in VM86 mode. | |
1786 | */ | |
1787 | if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) | |
3427318f | 1788 | if (emulate_instruction(vcpu, NULL, 0, 0, 0) == EMULATE_DONE) |
6aa8b732 AK |
1789 | return 1; |
1790 | return 0; | |
1791 | } | |
1792 | ||
1793 | static int handle_exception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) | |
1794 | { | |
1795 | u32 intr_info, error_code; | |
1796 | unsigned long cr2, rip; | |
1797 | u32 vect_info; | |
1798 | enum emulation_result er; | |
e2dec939 | 1799 | int r; |
6aa8b732 AK |
1800 | |
1801 | vect_info = vmcs_read32(IDT_VECTORING_INFO_FIELD); | |
1802 | intr_info = vmcs_read32(VM_EXIT_INTR_INFO); | |
1803 | ||
1804 | if ((vect_info & VECTORING_INFO_VALID_MASK) && | |
d77c26fc | 1805 | !is_page_fault(intr_info)) |
6aa8b732 AK |
1806 | printk(KERN_ERR "%s: unexpected, vectoring info 0x%x " |
1807 | "intr info 0x%x\n", __FUNCTION__, vect_info, intr_info); | |
6aa8b732 | 1808 | |
85f455f7 | 1809 | if (!irqchip_in_kernel(vcpu->kvm) && is_external_interrupt(vect_info)) { |
6aa8b732 AK |
1810 | int irq = vect_info & VECTORING_INFO_VECTOR_MASK; |
1811 | set_bit(irq, vcpu->irq_pending); | |
1812 | set_bit(irq / BITS_PER_LONG, &vcpu->irq_summary); | |
1813 | } | |
1814 | ||
1b6269db AK |
1815 | if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == 0x200) /* nmi */ |
1816 | return 1; /* already handled by vmx_vcpu_run() */ | |
2ab455cc AL |
1817 | |
1818 | if (is_no_device(intr_info)) { | |
5fd86fcf | 1819 | vmx_fpu_activate(vcpu); |
2ab455cc AL |
1820 | return 1; |
1821 | } | |
1822 | ||
7aa81cc0 | 1823 | if (is_invalid_opcode(intr_info)) { |
3427318f | 1824 | er = emulate_instruction(vcpu, kvm_run, 0, 0, 0); |
7aa81cc0 AL |
1825 | if (er != EMULATE_DONE) |
1826 | vmx_inject_ud(vcpu); | |
1827 | ||
1828 | return 1; | |
1829 | } | |
1830 | ||
6aa8b732 AK |
1831 | error_code = 0; |
1832 | rip = vmcs_readl(GUEST_RIP); | |
1833 | if (intr_info & INTR_INFO_DELIEVER_CODE_MASK) | |
1834 | error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE); | |
1835 | if (is_page_fault(intr_info)) { | |
1836 | cr2 = vmcs_readl(EXIT_QUALIFICATION); | |
1837 | ||
11ec2804 | 1838 | mutex_lock(&vcpu->kvm->lock); |
e2dec939 AK |
1839 | r = kvm_mmu_page_fault(vcpu, cr2, error_code); |
1840 | if (r < 0) { | |
11ec2804 | 1841 | mutex_unlock(&vcpu->kvm->lock); |
e2dec939 AK |
1842 | return r; |
1843 | } | |
1844 | if (!r) { | |
11ec2804 | 1845 | mutex_unlock(&vcpu->kvm->lock); |
6aa8b732 AK |
1846 | return 1; |
1847 | } | |
1848 | ||
3427318f | 1849 | er = emulate_instruction(vcpu, kvm_run, cr2, error_code, 0); |
11ec2804 | 1850 | mutex_unlock(&vcpu->kvm->lock); |
6aa8b732 AK |
1851 | |
1852 | switch (er) { | |
1853 | case EMULATE_DONE: | |
1854 | return 1; | |
1855 | case EMULATE_DO_MMIO: | |
1165f5fe | 1856 | ++vcpu->stat.mmio_exits; |
6aa8b732 | 1857 | return 0; |
d77c26fc | 1858 | case EMULATE_FAIL: |
054b1369 | 1859 | kvm_report_emulation_failure(vcpu, "pagetable"); |
6aa8b732 AK |
1860 | break; |
1861 | default: | |
1862 | BUG(); | |
1863 | } | |
1864 | } | |
1865 | ||
1866 | if (vcpu->rmode.active && | |
1867 | handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK, | |
72d6e5a0 AK |
1868 | error_code)) { |
1869 | if (vcpu->halt_request) { | |
1870 | vcpu->halt_request = 0; | |
1871 | return kvm_emulate_halt(vcpu); | |
1872 | } | |
6aa8b732 | 1873 | return 1; |
72d6e5a0 | 1874 | } |
6aa8b732 | 1875 | |
d77c26fc MD |
1876 | if ((intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK)) == |
1877 | (INTR_TYPE_EXCEPTION | 1)) { | |
6aa8b732 AK |
1878 | kvm_run->exit_reason = KVM_EXIT_DEBUG; |
1879 | return 0; | |
1880 | } | |
1881 | kvm_run->exit_reason = KVM_EXIT_EXCEPTION; | |
1882 | kvm_run->ex.exception = intr_info & INTR_INFO_VECTOR_MASK; | |
1883 | kvm_run->ex.error_code = error_code; | |
1884 | return 0; | |
1885 | } | |
1886 | ||
1887 | static int handle_external_interrupt(struct kvm_vcpu *vcpu, | |
1888 | struct kvm_run *kvm_run) | |
1889 | { | |
1165f5fe | 1890 | ++vcpu->stat.irq_exits; |
6aa8b732 AK |
1891 | return 1; |
1892 | } | |
1893 | ||
988ad74f AK |
1894 | static int handle_triple_fault(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) |
1895 | { | |
1896 | kvm_run->exit_reason = KVM_EXIT_SHUTDOWN; | |
1897 | return 0; | |
1898 | } | |
6aa8b732 | 1899 | |
6aa8b732 AK |
1900 | static int handle_io(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) |
1901 | { | |
bfdaab09 | 1902 | unsigned long exit_qualification; |
039576c0 AK |
1903 | int size, down, in, string, rep; |
1904 | unsigned port; | |
6aa8b732 | 1905 | |
1165f5fe | 1906 | ++vcpu->stat.io_exits; |
bfdaab09 | 1907 | exit_qualification = vmcs_readl(EXIT_QUALIFICATION); |
039576c0 | 1908 | string = (exit_qualification & 16) != 0; |
e70669ab LV |
1909 | |
1910 | if (string) { | |
3427318f LV |
1911 | if (emulate_instruction(vcpu, |
1912 | kvm_run, 0, 0, 0) == EMULATE_DO_MMIO) | |
e70669ab LV |
1913 | return 0; |
1914 | return 1; | |
1915 | } | |
1916 | ||
1917 | size = (exit_qualification & 7) + 1; | |
1918 | in = (exit_qualification & 8) != 0; | |
039576c0 | 1919 | down = (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_DF) != 0; |
039576c0 AK |
1920 | rep = (exit_qualification & 32) != 0; |
1921 | port = exit_qualification >> 16; | |
e70669ab | 1922 | |
3090dd73 | 1923 | return kvm_emulate_pio(vcpu, kvm_run, in, size, port); |
6aa8b732 AK |
1924 | } |
1925 | ||
102d8325 IM |
1926 | static void |
1927 | vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall) | |
1928 | { | |
1929 | /* | |
1930 | * Patch in the VMCALL instruction: | |
1931 | */ | |
1932 | hypercall[0] = 0x0f; | |
1933 | hypercall[1] = 0x01; | |
1934 | hypercall[2] = 0xc1; | |
102d8325 IM |
1935 | } |
1936 | ||
6aa8b732 AK |
1937 | static int handle_cr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) |
1938 | { | |
bfdaab09 | 1939 | unsigned long exit_qualification; |
6aa8b732 AK |
1940 | int cr; |
1941 | int reg; | |
1942 | ||
bfdaab09 | 1943 | exit_qualification = vmcs_readl(EXIT_QUALIFICATION); |
6aa8b732 AK |
1944 | cr = exit_qualification & 15; |
1945 | reg = (exit_qualification >> 8) & 15; | |
1946 | switch ((exit_qualification >> 4) & 3) { | |
1947 | case 0: /* mov to cr */ | |
1948 | switch (cr) { | |
1949 | case 0: | |
1950 | vcpu_load_rsp_rip(vcpu); | |
1951 | set_cr0(vcpu, vcpu->regs[reg]); | |
1952 | skip_emulated_instruction(vcpu); | |
1953 | return 1; | |
1954 | case 3: | |
1955 | vcpu_load_rsp_rip(vcpu); | |
1956 | set_cr3(vcpu, vcpu->regs[reg]); | |
1957 | skip_emulated_instruction(vcpu); | |
1958 | return 1; | |
1959 | case 4: | |
1960 | vcpu_load_rsp_rip(vcpu); | |
1961 | set_cr4(vcpu, vcpu->regs[reg]); | |
1962 | skip_emulated_instruction(vcpu); | |
1963 | return 1; | |
1964 | case 8: | |
1965 | vcpu_load_rsp_rip(vcpu); | |
1966 | set_cr8(vcpu, vcpu->regs[reg]); | |
1967 | skip_emulated_instruction(vcpu); | |
253abdee YS |
1968 | kvm_run->exit_reason = KVM_EXIT_SET_TPR; |
1969 | return 0; | |
6aa8b732 AK |
1970 | }; |
1971 | break; | |
25c4c276 AL |
1972 | case 2: /* clts */ |
1973 | vcpu_load_rsp_rip(vcpu); | |
5fd86fcf | 1974 | vmx_fpu_deactivate(vcpu); |
707d92fa | 1975 | vcpu->cr0 &= ~X86_CR0_TS; |
2ab455cc | 1976 | vmcs_writel(CR0_READ_SHADOW, vcpu->cr0); |
5fd86fcf | 1977 | vmx_fpu_activate(vcpu); |
25c4c276 AL |
1978 | skip_emulated_instruction(vcpu); |
1979 | return 1; | |
6aa8b732 AK |
1980 | case 1: /*mov from cr*/ |
1981 | switch (cr) { | |
1982 | case 3: | |
1983 | vcpu_load_rsp_rip(vcpu); | |
1984 | vcpu->regs[reg] = vcpu->cr3; | |
1985 | vcpu_put_rsp_rip(vcpu); | |
1986 | skip_emulated_instruction(vcpu); | |
1987 | return 1; | |
1988 | case 8: | |
6aa8b732 | 1989 | vcpu_load_rsp_rip(vcpu); |
7017fc3d | 1990 | vcpu->regs[reg] = get_cr8(vcpu); |
6aa8b732 AK |
1991 | vcpu_put_rsp_rip(vcpu); |
1992 | skip_emulated_instruction(vcpu); | |
1993 | return 1; | |
1994 | } | |
1995 | break; | |
1996 | case 3: /* lmsw */ | |
1997 | lmsw(vcpu, (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f); | |
1998 | ||
1999 | skip_emulated_instruction(vcpu); | |
2000 | return 1; | |
2001 | default: | |
2002 | break; | |
2003 | } | |
2004 | kvm_run->exit_reason = 0; | |
f0242478 | 2005 | pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n", |
6aa8b732 AK |
2006 | (int)(exit_qualification >> 4) & 3, cr); |
2007 | return 0; | |
2008 | } | |
2009 | ||
2010 | static int handle_dr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) | |
2011 | { | |
bfdaab09 | 2012 | unsigned long exit_qualification; |
6aa8b732 AK |
2013 | unsigned long val; |
2014 | int dr, reg; | |
2015 | ||
2016 | /* | |
2017 | * FIXME: this code assumes the host is debugging the guest. | |
2018 | * need to deal with guest debugging itself too. | |
2019 | */ | |
bfdaab09 | 2020 | exit_qualification = vmcs_readl(EXIT_QUALIFICATION); |
6aa8b732 AK |
2021 | dr = exit_qualification & 7; |
2022 | reg = (exit_qualification >> 8) & 15; | |
2023 | vcpu_load_rsp_rip(vcpu); | |
2024 | if (exit_qualification & 16) { | |
2025 | /* mov from dr */ | |
2026 | switch (dr) { | |
2027 | case 6: | |
2028 | val = 0xffff0ff0; | |
2029 | break; | |
2030 | case 7: | |
2031 | val = 0x400; | |
2032 | break; | |
2033 | default: | |
2034 | val = 0; | |
2035 | } | |
2036 | vcpu->regs[reg] = val; | |
2037 | } else { | |
2038 | /* mov to dr */ | |
2039 | } | |
2040 | vcpu_put_rsp_rip(vcpu); | |
2041 | skip_emulated_instruction(vcpu); | |
2042 | return 1; | |
2043 | } | |
2044 | ||
2045 | static int handle_cpuid(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) | |
2046 | { | |
06465c5a AK |
2047 | kvm_emulate_cpuid(vcpu); |
2048 | return 1; | |
6aa8b732 AK |
2049 | } |
2050 | ||
2051 | static int handle_rdmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) | |
2052 | { | |
2053 | u32 ecx = vcpu->regs[VCPU_REGS_RCX]; | |
2054 | u64 data; | |
2055 | ||
2056 | if (vmx_get_msr(vcpu, ecx, &data)) { | |
2057 | vmx_inject_gp(vcpu, 0); | |
2058 | return 1; | |
2059 | } | |
2060 | ||
2061 | /* FIXME: handling of bits 32:63 of rax, rdx */ | |
2062 | vcpu->regs[VCPU_REGS_RAX] = data & -1u; | |
2063 | vcpu->regs[VCPU_REGS_RDX] = (data >> 32) & -1u; | |
2064 | skip_emulated_instruction(vcpu); | |
2065 | return 1; | |
2066 | } | |
2067 | ||
2068 | static int handle_wrmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) | |
2069 | { | |
2070 | u32 ecx = vcpu->regs[VCPU_REGS_RCX]; | |
2071 | u64 data = (vcpu->regs[VCPU_REGS_RAX] & -1u) | |
2072 | | ((u64)(vcpu->regs[VCPU_REGS_RDX] & -1u) << 32); | |
2073 | ||
2074 | if (vmx_set_msr(vcpu, ecx, data) != 0) { | |
2075 | vmx_inject_gp(vcpu, 0); | |
2076 | return 1; | |
2077 | } | |
2078 | ||
2079 | skip_emulated_instruction(vcpu); | |
2080 | return 1; | |
2081 | } | |
2082 | ||
6e5d865c YS |
2083 | static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu, |
2084 | struct kvm_run *kvm_run) | |
2085 | { | |
2086 | return 1; | |
2087 | } | |
2088 | ||
6aa8b732 AK |
2089 | static int handle_interrupt_window(struct kvm_vcpu *vcpu, |
2090 | struct kvm_run *kvm_run) | |
2091 | { | |
85f455f7 ED |
2092 | u32 cpu_based_vm_exec_control; |
2093 | ||
2094 | /* clear pending irq */ | |
2095 | cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL); | |
2096 | cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING; | |
2097 | vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control); | |
c1150d8c DL |
2098 | /* |
2099 | * If the user space waits to inject interrupts, exit as soon as | |
2100 | * possible | |
2101 | */ | |
2102 | if (kvm_run->request_interrupt_window && | |
022a9308 | 2103 | !vcpu->irq_summary) { |
c1150d8c | 2104 | kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN; |
1165f5fe | 2105 | ++vcpu->stat.irq_window_exits; |
c1150d8c DL |
2106 | return 0; |
2107 | } | |
6aa8b732 AK |
2108 | return 1; |
2109 | } | |
2110 | ||
2111 | static int handle_halt(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) | |
2112 | { | |
2113 | skip_emulated_instruction(vcpu); | |
d3bef15f | 2114 | return kvm_emulate_halt(vcpu); |
6aa8b732 AK |
2115 | } |
2116 | ||
c21415e8 IM |
2117 | static int handle_vmcall(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) |
2118 | { | |
510043da | 2119 | skip_emulated_instruction(vcpu); |
7aa81cc0 AL |
2120 | kvm_emulate_hypercall(vcpu); |
2121 | return 1; | |
c21415e8 IM |
2122 | } |
2123 | ||
6aa8b732 AK |
2124 | /* |
2125 | * The exit handlers return 1 if the exit was handled fully and guest execution | |
2126 | * may resume. Otherwise they set the kvm_run parameter to indicate what needs | |
2127 | * to be done to userspace and return 0. | |
2128 | */ | |
2129 | static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu, | |
2130 | struct kvm_run *kvm_run) = { | |
2131 | [EXIT_REASON_EXCEPTION_NMI] = handle_exception, | |
2132 | [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt, | |
988ad74f | 2133 | [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault, |
6aa8b732 | 2134 | [EXIT_REASON_IO_INSTRUCTION] = handle_io, |
6aa8b732 AK |
2135 | [EXIT_REASON_CR_ACCESS] = handle_cr, |
2136 | [EXIT_REASON_DR_ACCESS] = handle_dr, | |
2137 | [EXIT_REASON_CPUID] = handle_cpuid, | |
2138 | [EXIT_REASON_MSR_READ] = handle_rdmsr, | |
2139 | [EXIT_REASON_MSR_WRITE] = handle_wrmsr, | |
2140 | [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window, | |
2141 | [EXIT_REASON_HLT] = handle_halt, | |
c21415e8 | 2142 | [EXIT_REASON_VMCALL] = handle_vmcall, |
6e5d865c | 2143 | [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold |
6aa8b732 AK |
2144 | }; |
2145 | ||
2146 | static const int kvm_vmx_max_exit_handlers = | |
50a3485c | 2147 | ARRAY_SIZE(kvm_vmx_exit_handlers); |
6aa8b732 AK |
2148 | |
2149 | /* | |
2150 | * The guest has exited. See if we can fix it or if we need userspace | |
2151 | * assistance. | |
2152 | */ | |
2153 | static int kvm_handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu) | |
2154 | { | |
2155 | u32 vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD); | |
2156 | u32 exit_reason = vmcs_read32(VM_EXIT_REASON); | |
29bd8a78 AK |
2157 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
2158 | ||
2159 | if (unlikely(vmx->fail)) { | |
2160 | kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY; | |
2161 | kvm_run->fail_entry.hardware_entry_failure_reason | |
2162 | = vmcs_read32(VM_INSTRUCTION_ERROR); | |
2163 | return 0; | |
2164 | } | |
6aa8b732 | 2165 | |
d77c26fc MD |
2166 | if ((vectoring_info & VECTORING_INFO_VALID_MASK) && |
2167 | exit_reason != EXIT_REASON_EXCEPTION_NMI) | |
6aa8b732 AK |
2168 | printk(KERN_WARNING "%s: unexpected, valid vectoring info and " |
2169 | "exit reason is 0x%x\n", __FUNCTION__, exit_reason); | |
6aa8b732 AK |
2170 | if (exit_reason < kvm_vmx_max_exit_handlers |
2171 | && kvm_vmx_exit_handlers[exit_reason]) | |
2172 | return kvm_vmx_exit_handlers[exit_reason](vcpu, kvm_run); | |
2173 | else { | |
2174 | kvm_run->exit_reason = KVM_EXIT_UNKNOWN; | |
2175 | kvm_run->hw.hardware_exit_reason = exit_reason; | |
2176 | } | |
2177 | return 0; | |
2178 | } | |
2179 | ||
d9e368d6 AK |
2180 | static void vmx_flush_tlb(struct kvm_vcpu *vcpu) |
2181 | { | |
d9e368d6 AK |
2182 | } |
2183 | ||
6e5d865c YS |
2184 | static void update_tpr_threshold(struct kvm_vcpu *vcpu) |
2185 | { | |
2186 | int max_irr, tpr; | |
2187 | ||
2188 | if (!vm_need_tpr_shadow(vcpu->kvm)) | |
2189 | return; | |
2190 | ||
2191 | if (!kvm_lapic_enabled(vcpu) || | |
2192 | ((max_irr = kvm_lapic_find_highest_irr(vcpu)) == -1)) { | |
2193 | vmcs_write32(TPR_THRESHOLD, 0); | |
2194 | return; | |
2195 | } | |
2196 | ||
2197 | tpr = (kvm_lapic_get_cr8(vcpu) & 0x0f) << 4; | |
2198 | vmcs_write32(TPR_THRESHOLD, (max_irr > tpr) ? tpr >> 4 : max_irr >> 4); | |
2199 | } | |
2200 | ||
85f455f7 ED |
2201 | static void enable_irq_window(struct kvm_vcpu *vcpu) |
2202 | { | |
2203 | u32 cpu_based_vm_exec_control; | |
2204 | ||
2205 | cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL); | |
2206 | cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING; | |
2207 | vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control); | |
2208 | } | |
2209 | ||
2210 | static void vmx_intr_assist(struct kvm_vcpu *vcpu) | |
2211 | { | |
2212 | u32 idtv_info_field, intr_info_field; | |
2213 | int has_ext_irq, interrupt_window_open; | |
1b9778da | 2214 | int vector; |
85f455f7 | 2215 | |
6e5d865c YS |
2216 | update_tpr_threshold(vcpu); |
2217 | ||
85f455f7 ED |
2218 | has_ext_irq = kvm_cpu_has_interrupt(vcpu); |
2219 | intr_info_field = vmcs_read32(VM_ENTRY_INTR_INFO_FIELD); | |
2220 | idtv_info_field = vmcs_read32(IDT_VECTORING_INFO_FIELD); | |
2221 | if (intr_info_field & INTR_INFO_VALID_MASK) { | |
2222 | if (idtv_info_field & INTR_INFO_VALID_MASK) { | |
2223 | /* TODO: fault when IDT_Vectoring */ | |
2224 | printk(KERN_ERR "Fault when IDT_Vectoring\n"); | |
2225 | } | |
2226 | if (has_ext_irq) | |
2227 | enable_irq_window(vcpu); | |
2228 | return; | |
2229 | } | |
2230 | if (unlikely(idtv_info_field & INTR_INFO_VALID_MASK)) { | |
2231 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, idtv_info_field); | |
2232 | vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, | |
2233 | vmcs_read32(VM_EXIT_INSTRUCTION_LEN)); | |
2234 | ||
2235 | if (unlikely(idtv_info_field & INTR_INFO_DELIEVER_CODE_MASK)) | |
2236 | vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, | |
2237 | vmcs_read32(IDT_VECTORING_ERROR_CODE)); | |
2238 | if (unlikely(has_ext_irq)) | |
2239 | enable_irq_window(vcpu); | |
2240 | return; | |
2241 | } | |
2242 | if (!has_ext_irq) | |
2243 | return; | |
2244 | interrupt_window_open = | |
2245 | ((vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) && | |
2246 | (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 3) == 0); | |
1b9778da ED |
2247 | if (interrupt_window_open) { |
2248 | vector = kvm_cpu_get_interrupt(vcpu); | |
2249 | vmx_inject_irq(vcpu, vector); | |
2250 | kvm_timer_intr_post(vcpu, vector); | |
2251 | } else | |
85f455f7 ED |
2252 | enable_irq_window(vcpu); |
2253 | } | |
2254 | ||
04d2cc77 | 2255 | static void vmx_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) |
6aa8b732 | 2256 | { |
a2fa3e9f | 2257 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
1b6269db | 2258 | u32 intr_info; |
e6adf283 AK |
2259 | |
2260 | /* | |
2261 | * Loading guest fpu may have cleared host cr0.ts | |
2262 | */ | |
2263 | vmcs_writel(HOST_CR0, read_cr0()); | |
2264 | ||
d77c26fc | 2265 | asm( |
6aa8b732 | 2266 | /* Store host registers */ |
05b3e0c2 | 2267 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
2268 | "push %%rax; push %%rbx; push %%rdx;" |
2269 | "push %%rsi; push %%rdi; push %%rbp;" | |
2270 | "push %%r8; push %%r9; push %%r10; push %%r11;" | |
2271 | "push %%r12; push %%r13; push %%r14; push %%r15;" | |
2272 | "push %%rcx \n\t" | |
2273 | ASM_VMX_VMWRITE_RSP_RDX "\n\t" | |
2274 | #else | |
2275 | "pusha; push %%ecx \n\t" | |
2276 | ASM_VMX_VMWRITE_RSP_RDX "\n\t" | |
2277 | #endif | |
2278 | /* Check if vmlaunch of vmresume is needed */ | |
2279 | "cmp $0, %1 \n\t" | |
2280 | /* Load guest registers. Don't clobber flags. */ | |
05b3e0c2 | 2281 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
2282 | "mov %c[cr2](%3), %%rax \n\t" |
2283 | "mov %%rax, %%cr2 \n\t" | |
2284 | "mov %c[rax](%3), %%rax \n\t" | |
2285 | "mov %c[rbx](%3), %%rbx \n\t" | |
2286 | "mov %c[rdx](%3), %%rdx \n\t" | |
2287 | "mov %c[rsi](%3), %%rsi \n\t" | |
2288 | "mov %c[rdi](%3), %%rdi \n\t" | |
2289 | "mov %c[rbp](%3), %%rbp \n\t" | |
2290 | "mov %c[r8](%3), %%r8 \n\t" | |
2291 | "mov %c[r9](%3), %%r9 \n\t" | |
2292 | "mov %c[r10](%3), %%r10 \n\t" | |
2293 | "mov %c[r11](%3), %%r11 \n\t" | |
2294 | "mov %c[r12](%3), %%r12 \n\t" | |
2295 | "mov %c[r13](%3), %%r13 \n\t" | |
2296 | "mov %c[r14](%3), %%r14 \n\t" | |
2297 | "mov %c[r15](%3), %%r15 \n\t" | |
2298 | "mov %c[rcx](%3), %%rcx \n\t" /* kills %3 (rcx) */ | |
2299 | #else | |
2300 | "mov %c[cr2](%3), %%eax \n\t" | |
2301 | "mov %%eax, %%cr2 \n\t" | |
2302 | "mov %c[rax](%3), %%eax \n\t" | |
2303 | "mov %c[rbx](%3), %%ebx \n\t" | |
2304 | "mov %c[rdx](%3), %%edx \n\t" | |
2305 | "mov %c[rsi](%3), %%esi \n\t" | |
2306 | "mov %c[rdi](%3), %%edi \n\t" | |
2307 | "mov %c[rbp](%3), %%ebp \n\t" | |
2308 | "mov %c[rcx](%3), %%ecx \n\t" /* kills %3 (ecx) */ | |
2309 | #endif | |
2310 | /* Enter guest mode */ | |
cd2276a7 | 2311 | "jne .Llaunched \n\t" |
6aa8b732 | 2312 | ASM_VMX_VMLAUNCH "\n\t" |
cd2276a7 AK |
2313 | "jmp .Lkvm_vmx_return \n\t" |
2314 | ".Llaunched: " ASM_VMX_VMRESUME "\n\t" | |
2315 | ".Lkvm_vmx_return: " | |
6aa8b732 | 2316 | /* Save guest registers, load host registers, keep flags */ |
05b3e0c2 | 2317 | #ifdef CONFIG_X86_64 |
96958231 | 2318 | "xchg %3, (%%rsp) \n\t" |
6aa8b732 AK |
2319 | "mov %%rax, %c[rax](%3) \n\t" |
2320 | "mov %%rbx, %c[rbx](%3) \n\t" | |
96958231 | 2321 | "pushq (%%rsp); popq %c[rcx](%3) \n\t" |
6aa8b732 AK |
2322 | "mov %%rdx, %c[rdx](%3) \n\t" |
2323 | "mov %%rsi, %c[rsi](%3) \n\t" | |
2324 | "mov %%rdi, %c[rdi](%3) \n\t" | |
2325 | "mov %%rbp, %c[rbp](%3) \n\t" | |
2326 | "mov %%r8, %c[r8](%3) \n\t" | |
2327 | "mov %%r9, %c[r9](%3) \n\t" | |
2328 | "mov %%r10, %c[r10](%3) \n\t" | |
2329 | "mov %%r11, %c[r11](%3) \n\t" | |
2330 | "mov %%r12, %c[r12](%3) \n\t" | |
2331 | "mov %%r13, %c[r13](%3) \n\t" | |
2332 | "mov %%r14, %c[r14](%3) \n\t" | |
2333 | "mov %%r15, %c[r15](%3) \n\t" | |
2334 | "mov %%cr2, %%rax \n\t" | |
2335 | "mov %%rax, %c[cr2](%3) \n\t" | |
96958231 | 2336 | "mov (%%rsp), %3 \n\t" |
6aa8b732 AK |
2337 | |
2338 | "pop %%rcx; pop %%r15; pop %%r14; pop %%r13; pop %%r12;" | |
2339 | "pop %%r11; pop %%r10; pop %%r9; pop %%r8;" | |
2340 | "pop %%rbp; pop %%rdi; pop %%rsi;" | |
2341 | "pop %%rdx; pop %%rbx; pop %%rax \n\t" | |
2342 | #else | |
96958231 | 2343 | "xchg %3, (%%esp) \n\t" |
6aa8b732 AK |
2344 | "mov %%eax, %c[rax](%3) \n\t" |
2345 | "mov %%ebx, %c[rbx](%3) \n\t" | |
96958231 | 2346 | "pushl (%%esp); popl %c[rcx](%3) \n\t" |
6aa8b732 AK |
2347 | "mov %%edx, %c[rdx](%3) \n\t" |
2348 | "mov %%esi, %c[rsi](%3) \n\t" | |
2349 | "mov %%edi, %c[rdi](%3) \n\t" | |
2350 | "mov %%ebp, %c[rbp](%3) \n\t" | |
2351 | "mov %%cr2, %%eax \n\t" | |
2352 | "mov %%eax, %c[cr2](%3) \n\t" | |
96958231 | 2353 | "mov (%%esp), %3 \n\t" |
6aa8b732 AK |
2354 | |
2355 | "pop %%ecx; popa \n\t" | |
2356 | #endif | |
2357 | "setbe %0 \n\t" | |
29bd8a78 | 2358 | : "=q" (vmx->fail) |
a2fa3e9f | 2359 | : "r"(vmx->launched), "d"((unsigned long)HOST_RSP), |
6aa8b732 AK |
2360 | "c"(vcpu), |
2361 | [rax]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RAX])), | |
2362 | [rbx]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RBX])), | |
2363 | [rcx]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RCX])), | |
2364 | [rdx]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RDX])), | |
2365 | [rsi]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RSI])), | |
2366 | [rdi]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RDI])), | |
2367 | [rbp]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RBP])), | |
05b3e0c2 | 2368 | #ifdef CONFIG_X86_64 |
d77c26fc MD |
2369 | [r8]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R8])), |
2370 | [r9]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R9])), | |
6aa8b732 AK |
2371 | [r10]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R10])), |
2372 | [r11]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R11])), | |
2373 | [r12]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R12])), | |
2374 | [r13]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R13])), | |
2375 | [r14]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R14])), | |
2376 | [r15]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R15])), | |
2377 | #endif | |
2378 | [cr2]"i"(offsetof(struct kvm_vcpu, cr2)) | |
d77c26fc | 2379 | : "cc", "memory"); |
6aa8b732 | 2380 | |
d77c26fc MD |
2381 | vcpu->interrupt_window_open = |
2382 | (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 3) == 0; | |
6aa8b732 | 2383 | |
d77c26fc | 2384 | asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS)); |
15ad7146 | 2385 | vmx->launched = 1; |
1b6269db AK |
2386 | |
2387 | intr_info = vmcs_read32(VM_EXIT_INTR_INFO); | |
2388 | ||
2389 | /* We need to handle NMIs before interrupts are enabled */ | |
2390 | if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == 0x200) /* nmi */ | |
2391 | asm("int $2"); | |
6aa8b732 AK |
2392 | } |
2393 | ||
6aa8b732 AK |
2394 | static void vmx_inject_page_fault(struct kvm_vcpu *vcpu, |
2395 | unsigned long addr, | |
2396 | u32 err_code) | |
2397 | { | |
2398 | u32 vect_info = vmcs_read32(IDT_VECTORING_INFO_FIELD); | |
2399 | ||
1165f5fe | 2400 | ++vcpu->stat.pf_guest; |
6aa8b732 AK |
2401 | |
2402 | if (is_page_fault(vect_info)) { | |
2403 | printk(KERN_DEBUG "inject_page_fault: " | |
2404 | "double fault 0x%lx @ 0x%lx\n", | |
2405 | addr, vmcs_readl(GUEST_RIP)); | |
2406 | vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, 0); | |
2407 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, | |
2408 | DF_VECTOR | | |
2409 | INTR_TYPE_EXCEPTION | | |
2410 | INTR_INFO_DELIEVER_CODE_MASK | | |
2411 | INTR_INFO_VALID_MASK); | |
2412 | return; | |
2413 | } | |
2414 | vcpu->cr2 = addr; | |
2415 | vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, err_code); | |
2416 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, | |
2417 | PF_VECTOR | | |
2418 | INTR_TYPE_EXCEPTION | | |
2419 | INTR_INFO_DELIEVER_CODE_MASK | | |
2420 | INTR_INFO_VALID_MASK); | |
2421 | ||
2422 | } | |
2423 | ||
2424 | static void vmx_free_vmcs(struct kvm_vcpu *vcpu) | |
2425 | { | |
a2fa3e9f GH |
2426 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
2427 | ||
2428 | if (vmx->vmcs) { | |
8b9cf98c | 2429 | on_each_cpu(__vcpu_clear, vmx, 0, 1); |
a2fa3e9f GH |
2430 | free_vmcs(vmx->vmcs); |
2431 | vmx->vmcs = NULL; | |
6aa8b732 AK |
2432 | } |
2433 | } | |
2434 | ||
2435 | static void vmx_free_vcpu(struct kvm_vcpu *vcpu) | |
2436 | { | |
fb3f0f51 RR |
2437 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
2438 | ||
6aa8b732 | 2439 | vmx_free_vmcs(vcpu); |
fb3f0f51 RR |
2440 | kfree(vmx->host_msrs); |
2441 | kfree(vmx->guest_msrs); | |
2442 | kvm_vcpu_uninit(vcpu); | |
a4770347 | 2443 | kmem_cache_free(kvm_vcpu_cache, vmx); |
6aa8b732 AK |
2444 | } |
2445 | ||
fb3f0f51 | 2446 | static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id) |
6aa8b732 | 2447 | { |
fb3f0f51 | 2448 | int err; |
c16f862d | 2449 | struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL); |
15ad7146 | 2450 | int cpu; |
6aa8b732 | 2451 | |
a2fa3e9f | 2452 | if (!vmx) |
fb3f0f51 RR |
2453 | return ERR_PTR(-ENOMEM); |
2454 | ||
2455 | err = kvm_vcpu_init(&vmx->vcpu, kvm, id); | |
2456 | if (err) | |
2457 | goto free_vcpu; | |
965b58a5 | 2458 | |
a2fa3e9f | 2459 | vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL); |
fb3f0f51 RR |
2460 | if (!vmx->guest_msrs) { |
2461 | err = -ENOMEM; | |
2462 | goto uninit_vcpu; | |
2463 | } | |
965b58a5 | 2464 | |
a2fa3e9f GH |
2465 | vmx->host_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL); |
2466 | if (!vmx->host_msrs) | |
fb3f0f51 | 2467 | goto free_guest_msrs; |
965b58a5 | 2468 | |
a2fa3e9f GH |
2469 | vmx->vmcs = alloc_vmcs(); |
2470 | if (!vmx->vmcs) | |
fb3f0f51 | 2471 | goto free_msrs; |
a2fa3e9f GH |
2472 | |
2473 | vmcs_clear(vmx->vmcs); | |
2474 | ||
15ad7146 AK |
2475 | cpu = get_cpu(); |
2476 | vmx_vcpu_load(&vmx->vcpu, cpu); | |
8b9cf98c | 2477 | err = vmx_vcpu_setup(vmx); |
fb3f0f51 | 2478 | vmx_vcpu_put(&vmx->vcpu); |
15ad7146 | 2479 | put_cpu(); |
fb3f0f51 RR |
2480 | if (err) |
2481 | goto free_vmcs; | |
2482 | ||
2483 | return &vmx->vcpu; | |
2484 | ||
2485 | free_vmcs: | |
2486 | free_vmcs(vmx->vmcs); | |
2487 | free_msrs: | |
2488 | kfree(vmx->host_msrs); | |
2489 | free_guest_msrs: | |
2490 | kfree(vmx->guest_msrs); | |
2491 | uninit_vcpu: | |
2492 | kvm_vcpu_uninit(&vmx->vcpu); | |
2493 | free_vcpu: | |
a4770347 | 2494 | kmem_cache_free(kvm_vcpu_cache, vmx); |
fb3f0f51 | 2495 | return ERR_PTR(err); |
6aa8b732 AK |
2496 | } |
2497 | ||
002c7f7c YS |
2498 | static void __init vmx_check_processor_compat(void *rtn) |
2499 | { | |
2500 | struct vmcs_config vmcs_conf; | |
2501 | ||
2502 | *(int *)rtn = 0; | |
2503 | if (setup_vmcs_config(&vmcs_conf) < 0) | |
2504 | *(int *)rtn = -EIO; | |
2505 | if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) { | |
2506 | printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n", | |
2507 | smp_processor_id()); | |
2508 | *(int *)rtn = -EIO; | |
2509 | } | |
2510 | } | |
2511 | ||
cbdd1bea | 2512 | static struct kvm_x86_ops vmx_x86_ops = { |
6aa8b732 AK |
2513 | .cpu_has_kvm_support = cpu_has_kvm_support, |
2514 | .disabled_by_bios = vmx_disabled_by_bios, | |
2515 | .hardware_setup = hardware_setup, | |
2516 | .hardware_unsetup = hardware_unsetup, | |
002c7f7c | 2517 | .check_processor_compatibility = vmx_check_processor_compat, |
6aa8b732 AK |
2518 | .hardware_enable = hardware_enable, |
2519 | .hardware_disable = hardware_disable, | |
2520 | ||
2521 | .vcpu_create = vmx_create_vcpu, | |
2522 | .vcpu_free = vmx_free_vcpu, | |
04d2cc77 | 2523 | .vcpu_reset = vmx_vcpu_reset, |
6aa8b732 | 2524 | |
04d2cc77 | 2525 | .prepare_guest_switch = vmx_save_host_state, |
6aa8b732 AK |
2526 | .vcpu_load = vmx_vcpu_load, |
2527 | .vcpu_put = vmx_vcpu_put, | |
774c47f1 | 2528 | .vcpu_decache = vmx_vcpu_decache, |
6aa8b732 AK |
2529 | |
2530 | .set_guest_debug = set_guest_debug, | |
04d2cc77 | 2531 | .guest_debug_pre = kvm_guest_debug_pre, |
6aa8b732 AK |
2532 | .get_msr = vmx_get_msr, |
2533 | .set_msr = vmx_set_msr, | |
2534 | .get_segment_base = vmx_get_segment_base, | |
2535 | .get_segment = vmx_get_segment, | |
2536 | .set_segment = vmx_set_segment, | |
6aa8b732 | 2537 | .get_cs_db_l_bits = vmx_get_cs_db_l_bits, |
25c4c276 | 2538 | .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits, |
6aa8b732 | 2539 | .set_cr0 = vmx_set_cr0, |
6aa8b732 AK |
2540 | .set_cr3 = vmx_set_cr3, |
2541 | .set_cr4 = vmx_set_cr4, | |
05b3e0c2 | 2542 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
2543 | .set_efer = vmx_set_efer, |
2544 | #endif | |
2545 | .get_idt = vmx_get_idt, | |
2546 | .set_idt = vmx_set_idt, | |
2547 | .get_gdt = vmx_get_gdt, | |
2548 | .set_gdt = vmx_set_gdt, | |
2549 | .cache_regs = vcpu_load_rsp_rip, | |
2550 | .decache_regs = vcpu_put_rsp_rip, | |
2551 | .get_rflags = vmx_get_rflags, | |
2552 | .set_rflags = vmx_set_rflags, | |
2553 | ||
2554 | .tlb_flush = vmx_flush_tlb, | |
2555 | .inject_page_fault = vmx_inject_page_fault, | |
2556 | ||
2557 | .inject_gp = vmx_inject_gp, | |
2558 | ||
2559 | .run = vmx_vcpu_run, | |
04d2cc77 | 2560 | .handle_exit = kvm_handle_exit, |
6aa8b732 | 2561 | .skip_emulated_instruction = skip_emulated_instruction, |
102d8325 | 2562 | .patch_hypercall = vmx_patch_hypercall, |
2a8067f1 ED |
2563 | .get_irq = vmx_get_irq, |
2564 | .set_irq = vmx_inject_irq, | |
04d2cc77 AK |
2565 | .inject_pending_irq = vmx_intr_assist, |
2566 | .inject_pending_vectors = do_interrupt_requests, | |
cbc94022 IE |
2567 | |
2568 | .set_tss_addr = vmx_set_tss_addr, | |
6aa8b732 AK |
2569 | }; |
2570 | ||
2571 | static int __init vmx_init(void) | |
2572 | { | |
fdef3ad1 HQ |
2573 | void *iova; |
2574 | int r; | |
2575 | ||
2576 | vmx_io_bitmap_a = alloc_page(GFP_KERNEL | __GFP_HIGHMEM); | |
2577 | if (!vmx_io_bitmap_a) | |
2578 | return -ENOMEM; | |
2579 | ||
2580 | vmx_io_bitmap_b = alloc_page(GFP_KERNEL | __GFP_HIGHMEM); | |
2581 | if (!vmx_io_bitmap_b) { | |
2582 | r = -ENOMEM; | |
2583 | goto out; | |
2584 | } | |
2585 | ||
2586 | /* | |
2587 | * Allow direct access to the PC debug port (it is often used for I/O | |
2588 | * delays, but the vmexits simply slow things down). | |
2589 | */ | |
2590 | iova = kmap(vmx_io_bitmap_a); | |
2591 | memset(iova, 0xff, PAGE_SIZE); | |
2592 | clear_bit(0x80, iova); | |
cd0536d7 | 2593 | kunmap(vmx_io_bitmap_a); |
fdef3ad1 HQ |
2594 | |
2595 | iova = kmap(vmx_io_bitmap_b); | |
2596 | memset(iova, 0xff, PAGE_SIZE); | |
cd0536d7 | 2597 | kunmap(vmx_io_bitmap_b); |
fdef3ad1 | 2598 | |
cbdd1bea | 2599 | r = kvm_init_x86(&vmx_x86_ops, sizeof(struct vcpu_vmx), THIS_MODULE); |
fdef3ad1 HQ |
2600 | if (r) |
2601 | goto out1; | |
2602 | ||
c7addb90 AK |
2603 | if (bypass_guest_pf) |
2604 | kvm_mmu_set_nonpresent_ptes(~0xffeull, 0ull); | |
2605 | ||
fdef3ad1 HQ |
2606 | return 0; |
2607 | ||
2608 | out1: | |
2609 | __free_page(vmx_io_bitmap_b); | |
2610 | out: | |
2611 | __free_page(vmx_io_bitmap_a); | |
2612 | return r; | |
6aa8b732 AK |
2613 | } |
2614 | ||
2615 | static void __exit vmx_exit(void) | |
2616 | { | |
fdef3ad1 HQ |
2617 | __free_page(vmx_io_bitmap_b); |
2618 | __free_page(vmx_io_bitmap_a); | |
2619 | ||
cbdd1bea | 2620 | kvm_exit_x86(); |
6aa8b732 AK |
2621 | } |
2622 | ||
2623 | module_init(vmx_init) | |
2624 | module_exit(vmx_exit) |