Commit | Line | Data |
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6aa8b732 AK |
1 | /* |
2 | * Kernel-based Virtual Machine driver for Linux | |
3 | * | |
4 | * AMD SVM support | |
5 | * | |
6 | * Copyright (C) 2006 Qumranet, Inc. | |
7 | * | |
8 | * Authors: | |
9 | * Yaniv Kamay <yaniv@qumranet.com> | |
10 | * Avi Kivity <avi@qumranet.com> | |
11 | * | |
12 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
13 | * the COPYING file in the top-level directory. | |
14 | * | |
15 | */ | |
16 | ||
17 | #include <linux/module.h> | |
9d8f549d | 18 | #include <linux/kernel.h> |
6aa8b732 AK |
19 | #include <linux/vmalloc.h> |
20 | #include <linux/highmem.h> | |
07031e14 | 21 | #include <linux/profile.h> |
e8edc6e0 | 22 | #include <linux/sched.h> |
6aa8b732 AK |
23 | #include <asm/desc.h> |
24 | ||
25 | #include "kvm_svm.h" | |
26 | #include "x86_emulate.h" | |
27 | ||
28 | MODULE_AUTHOR("Qumranet"); | |
29 | MODULE_LICENSE("GPL"); | |
30 | ||
31 | #define IOPM_ALLOC_ORDER 2 | |
32 | #define MSRPM_ALLOC_ORDER 1 | |
33 | ||
34 | #define DB_VECTOR 1 | |
35 | #define UD_VECTOR 6 | |
36 | #define GP_VECTOR 13 | |
37 | ||
38 | #define DR7_GD_MASK (1 << 13) | |
39 | #define DR6_BD_MASK (1 << 13) | |
40 | #define CR4_DE_MASK (1UL << 3) | |
41 | ||
42 | #define SEG_TYPE_LDT 2 | |
43 | #define SEG_TYPE_BUSY_TSS16 3 | |
44 | ||
45 | #define KVM_EFER_LMA (1 << 10) | |
46 | #define KVM_EFER_LME (1 << 8) | |
47 | ||
80b7706e JR |
48 | #define SVM_FEATURE_NPT (1 << 0) |
49 | #define SVM_FEATURE_LBRV (1 << 1) | |
50 | #define SVM_DEATURE_SVML (1 << 2) | |
51 | ||
6aa8b732 AK |
52 | unsigned long iopm_base; |
53 | unsigned long msrpm_base; | |
54 | ||
55 | struct kvm_ldttss_desc { | |
56 | u16 limit0; | |
57 | u16 base0; | |
58 | unsigned base1 : 8, type : 5, dpl : 2, p : 1; | |
59 | unsigned limit1 : 4, zero0 : 3, g : 1, base2 : 8; | |
60 | u32 base3; | |
61 | u32 zero1; | |
62 | } __attribute__((packed)); | |
63 | ||
64 | struct svm_cpu_data { | |
65 | int cpu; | |
66 | ||
5008fdf5 AK |
67 | u64 asid_generation; |
68 | u32 max_asid; | |
69 | u32 next_asid; | |
6aa8b732 AK |
70 | struct kvm_ldttss_desc *tss_desc; |
71 | ||
72 | struct page *save_area; | |
73 | }; | |
74 | ||
75 | static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data); | |
80b7706e | 76 | static uint32_t svm_features; |
6aa8b732 AK |
77 | |
78 | struct svm_init_data { | |
79 | int cpu; | |
80 | int r; | |
81 | }; | |
82 | ||
83 | static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000}; | |
84 | ||
9d8f549d | 85 | #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges) |
6aa8b732 AK |
86 | #define MSRS_RANGE_SIZE 2048 |
87 | #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2) | |
88 | ||
89 | #define MAX_INST_SIZE 15 | |
90 | ||
80b7706e JR |
91 | static inline u32 svm_has(u32 feat) |
92 | { | |
93 | return svm_features & feat; | |
94 | } | |
95 | ||
6aa8b732 AK |
96 | static unsigned get_addr_size(struct kvm_vcpu *vcpu) |
97 | { | |
98 | struct vmcb_save_area *sa = &vcpu->svm->vmcb->save; | |
99 | u16 cs_attrib; | |
100 | ||
101 | if (!(sa->cr0 & CR0_PE_MASK) || (sa->rflags & X86_EFLAGS_VM)) | |
102 | return 2; | |
103 | ||
104 | cs_attrib = sa->cs.attrib; | |
105 | ||
106 | return (cs_attrib & SVM_SELECTOR_L_MASK) ? 8 : | |
107 | (cs_attrib & SVM_SELECTOR_DB_MASK) ? 4 : 2; | |
108 | } | |
109 | ||
110 | static inline u8 pop_irq(struct kvm_vcpu *vcpu) | |
111 | { | |
112 | int word_index = __ffs(vcpu->irq_summary); | |
113 | int bit_index = __ffs(vcpu->irq_pending[word_index]); | |
114 | int irq = word_index * BITS_PER_LONG + bit_index; | |
115 | ||
116 | clear_bit(bit_index, &vcpu->irq_pending[word_index]); | |
117 | if (!vcpu->irq_pending[word_index]) | |
118 | clear_bit(word_index, &vcpu->irq_summary); | |
119 | return irq; | |
120 | } | |
121 | ||
122 | static inline void push_irq(struct kvm_vcpu *vcpu, u8 irq) | |
123 | { | |
124 | set_bit(irq, vcpu->irq_pending); | |
125 | set_bit(irq / BITS_PER_LONG, &vcpu->irq_summary); | |
126 | } | |
127 | ||
128 | static inline void clgi(void) | |
129 | { | |
130 | asm volatile (SVM_CLGI); | |
131 | } | |
132 | ||
133 | static inline void stgi(void) | |
134 | { | |
135 | asm volatile (SVM_STGI); | |
136 | } | |
137 | ||
138 | static inline void invlpga(unsigned long addr, u32 asid) | |
139 | { | |
140 | asm volatile (SVM_INVLPGA :: "a"(addr), "c"(asid)); | |
141 | } | |
142 | ||
143 | static inline unsigned long kvm_read_cr2(void) | |
144 | { | |
145 | unsigned long cr2; | |
146 | ||
147 | asm volatile ("mov %%cr2, %0" : "=r" (cr2)); | |
148 | return cr2; | |
149 | } | |
150 | ||
151 | static inline void kvm_write_cr2(unsigned long val) | |
152 | { | |
153 | asm volatile ("mov %0, %%cr2" :: "r" (val)); | |
154 | } | |
155 | ||
156 | static inline unsigned long read_dr6(void) | |
157 | { | |
158 | unsigned long dr6; | |
159 | ||
160 | asm volatile ("mov %%dr6, %0" : "=r" (dr6)); | |
161 | return dr6; | |
162 | } | |
163 | ||
164 | static inline void write_dr6(unsigned long val) | |
165 | { | |
166 | asm volatile ("mov %0, %%dr6" :: "r" (val)); | |
167 | } | |
168 | ||
169 | static inline unsigned long read_dr7(void) | |
170 | { | |
171 | unsigned long dr7; | |
172 | ||
173 | asm volatile ("mov %%dr7, %0" : "=r" (dr7)); | |
174 | return dr7; | |
175 | } | |
176 | ||
177 | static inline void write_dr7(unsigned long val) | |
178 | { | |
179 | asm volatile ("mov %0, %%dr7" :: "r" (val)); | |
180 | } | |
181 | ||
6aa8b732 AK |
182 | static inline void force_new_asid(struct kvm_vcpu *vcpu) |
183 | { | |
184 | vcpu->svm->asid_generation--; | |
185 | } | |
186 | ||
187 | static inline void flush_guest_tlb(struct kvm_vcpu *vcpu) | |
188 | { | |
189 | force_new_asid(vcpu); | |
190 | } | |
191 | ||
192 | static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer) | |
193 | { | |
194 | if (!(efer & KVM_EFER_LMA)) | |
195 | efer &= ~KVM_EFER_LME; | |
196 | ||
197 | vcpu->svm->vmcb->save.efer = efer | MSR_EFER_SVME_MASK; | |
198 | vcpu->shadow_efer = efer; | |
199 | } | |
200 | ||
201 | static void svm_inject_gp(struct kvm_vcpu *vcpu, unsigned error_code) | |
202 | { | |
203 | vcpu->svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | | |
204 | SVM_EVTINJ_VALID_ERR | | |
205 | SVM_EVTINJ_TYPE_EXEPT | | |
206 | GP_VECTOR; | |
207 | vcpu->svm->vmcb->control.event_inj_err = error_code; | |
208 | } | |
209 | ||
210 | static void inject_ud(struct kvm_vcpu *vcpu) | |
211 | { | |
212 | vcpu->svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | | |
213 | SVM_EVTINJ_TYPE_EXEPT | | |
214 | UD_VECTOR; | |
215 | } | |
216 | ||
6aa8b732 AK |
217 | static int is_page_fault(uint32_t info) |
218 | { | |
219 | info &= SVM_EVTINJ_VEC_MASK | SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID; | |
220 | return info == (PF_VECTOR | SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_EXEPT); | |
221 | } | |
222 | ||
223 | static int is_external_interrupt(u32 info) | |
224 | { | |
225 | info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID; | |
226 | return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR); | |
227 | } | |
228 | ||
229 | static void skip_emulated_instruction(struct kvm_vcpu *vcpu) | |
230 | { | |
231 | if (!vcpu->svm->next_rip) { | |
232 | printk(KERN_DEBUG "%s: NOP\n", __FUNCTION__); | |
233 | return; | |
234 | } | |
235 | if (vcpu->svm->next_rip - vcpu->svm->vmcb->save.rip > 15) { | |
236 | printk(KERN_ERR "%s: ip 0x%llx next 0x%llx\n", | |
237 | __FUNCTION__, | |
238 | vcpu->svm->vmcb->save.rip, | |
239 | vcpu->svm->next_rip); | |
240 | } | |
241 | ||
242 | vcpu->rip = vcpu->svm->vmcb->save.rip = vcpu->svm->next_rip; | |
243 | vcpu->svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK; | |
c1150d8c DL |
244 | |
245 | vcpu->interrupt_window_open = 1; | |
6aa8b732 AK |
246 | } |
247 | ||
248 | static int has_svm(void) | |
249 | { | |
250 | uint32_t eax, ebx, ecx, edx; | |
251 | ||
1e885461 | 252 | if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD) { |
6aa8b732 AK |
253 | printk(KERN_INFO "has_svm: not amd\n"); |
254 | return 0; | |
255 | } | |
256 | ||
257 | cpuid(0x80000000, &eax, &ebx, &ecx, &edx); | |
258 | if (eax < SVM_CPUID_FUNC) { | |
259 | printk(KERN_INFO "has_svm: can't execute cpuid_8000000a\n"); | |
260 | return 0; | |
261 | } | |
262 | ||
263 | cpuid(0x80000001, &eax, &ebx, &ecx, &edx); | |
264 | if (!(ecx & (1 << SVM_CPUID_FEATURE_SHIFT))) { | |
265 | printk(KERN_DEBUG "has_svm: svm not available\n"); | |
266 | return 0; | |
267 | } | |
268 | return 1; | |
269 | } | |
270 | ||
271 | static void svm_hardware_disable(void *garbage) | |
272 | { | |
273 | struct svm_cpu_data *svm_data | |
274 | = per_cpu(svm_data, raw_smp_processor_id()); | |
275 | ||
276 | if (svm_data) { | |
277 | uint64_t efer; | |
278 | ||
279 | wrmsrl(MSR_VM_HSAVE_PA, 0); | |
280 | rdmsrl(MSR_EFER, efer); | |
281 | wrmsrl(MSR_EFER, efer & ~MSR_EFER_SVME_MASK); | |
8b6d44c7 | 282 | per_cpu(svm_data, raw_smp_processor_id()) = NULL; |
6aa8b732 AK |
283 | __free_page(svm_data->save_area); |
284 | kfree(svm_data); | |
285 | } | |
286 | } | |
287 | ||
288 | static void svm_hardware_enable(void *garbage) | |
289 | { | |
290 | ||
291 | struct svm_cpu_data *svm_data; | |
292 | uint64_t efer; | |
05b3e0c2 | 293 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
294 | struct desc_ptr gdt_descr; |
295 | #else | |
296 | struct Xgt_desc_struct gdt_descr; | |
297 | #endif | |
298 | struct desc_struct *gdt; | |
299 | int me = raw_smp_processor_id(); | |
300 | ||
301 | if (!has_svm()) { | |
302 | printk(KERN_ERR "svm_cpu_init: err EOPNOTSUPP on %d\n", me); | |
303 | return; | |
304 | } | |
305 | svm_data = per_cpu(svm_data, me); | |
306 | ||
307 | if (!svm_data) { | |
308 | printk(KERN_ERR "svm_cpu_init: svm_data is NULL on %d\n", | |
309 | me); | |
310 | return; | |
311 | } | |
312 | ||
313 | svm_data->asid_generation = 1; | |
314 | svm_data->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1; | |
315 | svm_data->next_asid = svm_data->max_asid + 1; | |
80b7706e | 316 | svm_features = cpuid_edx(SVM_CPUID_FUNC); |
6aa8b732 AK |
317 | |
318 | asm volatile ( "sgdt %0" : "=m"(gdt_descr) ); | |
319 | gdt = (struct desc_struct *)gdt_descr.address; | |
320 | svm_data->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS); | |
321 | ||
322 | rdmsrl(MSR_EFER, efer); | |
323 | wrmsrl(MSR_EFER, efer | MSR_EFER_SVME_MASK); | |
324 | ||
325 | wrmsrl(MSR_VM_HSAVE_PA, | |
326 | page_to_pfn(svm_data->save_area) << PAGE_SHIFT); | |
327 | } | |
328 | ||
329 | static int svm_cpu_init(int cpu) | |
330 | { | |
331 | struct svm_cpu_data *svm_data; | |
332 | int r; | |
333 | ||
334 | svm_data = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL); | |
335 | if (!svm_data) | |
336 | return -ENOMEM; | |
337 | svm_data->cpu = cpu; | |
338 | svm_data->save_area = alloc_page(GFP_KERNEL); | |
339 | r = -ENOMEM; | |
340 | if (!svm_data->save_area) | |
341 | goto err_1; | |
342 | ||
343 | per_cpu(svm_data, cpu) = svm_data; | |
344 | ||
345 | return 0; | |
346 | ||
347 | err_1: | |
348 | kfree(svm_data); | |
349 | return r; | |
350 | ||
351 | } | |
352 | ||
353 | static int set_msr_interception(u32 *msrpm, unsigned msr, | |
354 | int read, int write) | |
355 | { | |
356 | int i; | |
357 | ||
358 | for (i = 0; i < NUM_MSR_MAPS; i++) { | |
359 | if (msr >= msrpm_ranges[i] && | |
360 | msr < msrpm_ranges[i] + MSRS_IN_RANGE) { | |
361 | u32 msr_offset = (i * MSRS_IN_RANGE + msr - | |
362 | msrpm_ranges[i]) * 2; | |
363 | ||
364 | u32 *base = msrpm + (msr_offset / 32); | |
365 | u32 msr_shift = msr_offset % 32; | |
366 | u32 mask = ((write) ? 0 : 2) | ((read) ? 0 : 1); | |
367 | *base = (*base & ~(0x3 << msr_shift)) | | |
368 | (mask << msr_shift); | |
369 | return 1; | |
370 | } | |
371 | } | |
372 | printk(KERN_DEBUG "%s: not found 0x%x\n", __FUNCTION__, msr); | |
373 | return 0; | |
374 | } | |
375 | ||
376 | static __init int svm_hardware_setup(void) | |
377 | { | |
378 | int cpu; | |
379 | struct page *iopm_pages; | |
380 | struct page *msrpm_pages; | |
c8681339 | 381 | void *iopm_va, *msrpm_va; |
6aa8b732 AK |
382 | int r; |
383 | ||
873a7c42 | 384 | kvm_emulator_want_group7_invlpg(); |
6aa8b732 AK |
385 | |
386 | iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER); | |
387 | ||
388 | if (!iopm_pages) | |
389 | return -ENOMEM; | |
c8681339 AL |
390 | |
391 | iopm_va = page_address(iopm_pages); | |
392 | memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER)); | |
393 | clear_bit(0x80, iopm_va); /* allow direct access to PC debug port */ | |
6aa8b732 AK |
394 | iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT; |
395 | ||
396 | ||
397 | msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER); | |
398 | ||
399 | r = -ENOMEM; | |
400 | if (!msrpm_pages) | |
401 | goto err_1; | |
402 | ||
403 | msrpm_va = page_address(msrpm_pages); | |
404 | memset(msrpm_va, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER)); | |
405 | msrpm_base = page_to_pfn(msrpm_pages) << PAGE_SHIFT; | |
406 | ||
05b3e0c2 | 407 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
408 | set_msr_interception(msrpm_va, MSR_GS_BASE, 1, 1); |
409 | set_msr_interception(msrpm_va, MSR_FS_BASE, 1, 1); | |
410 | set_msr_interception(msrpm_va, MSR_KERNEL_GS_BASE, 1, 1); | |
6aa8b732 AK |
411 | set_msr_interception(msrpm_va, MSR_LSTAR, 1, 1); |
412 | set_msr_interception(msrpm_va, MSR_CSTAR, 1, 1); | |
413 | set_msr_interception(msrpm_va, MSR_SYSCALL_MASK, 1, 1); | |
414 | #endif | |
0e859cac | 415 | set_msr_interception(msrpm_va, MSR_K6_STAR, 1, 1); |
6aa8b732 AK |
416 | set_msr_interception(msrpm_va, MSR_IA32_SYSENTER_CS, 1, 1); |
417 | set_msr_interception(msrpm_va, MSR_IA32_SYSENTER_ESP, 1, 1); | |
418 | set_msr_interception(msrpm_va, MSR_IA32_SYSENTER_EIP, 1, 1); | |
419 | ||
420 | for_each_online_cpu(cpu) { | |
421 | r = svm_cpu_init(cpu); | |
422 | if (r) | |
423 | goto err_2; | |
424 | } | |
425 | return 0; | |
426 | ||
427 | err_2: | |
428 | __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER); | |
429 | msrpm_base = 0; | |
430 | err_1: | |
431 | __free_pages(iopm_pages, IOPM_ALLOC_ORDER); | |
432 | iopm_base = 0; | |
433 | return r; | |
434 | } | |
435 | ||
436 | static __exit void svm_hardware_unsetup(void) | |
437 | { | |
438 | __free_pages(pfn_to_page(msrpm_base >> PAGE_SHIFT), MSRPM_ALLOC_ORDER); | |
439 | __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER); | |
440 | iopm_base = msrpm_base = 0; | |
441 | } | |
442 | ||
443 | static void init_seg(struct vmcb_seg *seg) | |
444 | { | |
445 | seg->selector = 0; | |
446 | seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK | | |
447 | SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */ | |
448 | seg->limit = 0xffff; | |
449 | seg->base = 0; | |
450 | } | |
451 | ||
452 | static void init_sys_seg(struct vmcb_seg *seg, uint32_t type) | |
453 | { | |
454 | seg->selector = 0; | |
455 | seg->attrib = SVM_SELECTOR_P_MASK | type; | |
456 | seg->limit = 0xffff; | |
457 | seg->base = 0; | |
458 | } | |
459 | ||
460 | static int svm_vcpu_setup(struct kvm_vcpu *vcpu) | |
461 | { | |
462 | return 0; | |
463 | } | |
464 | ||
465 | static void init_vmcb(struct vmcb *vmcb) | |
466 | { | |
467 | struct vmcb_control_area *control = &vmcb->control; | |
468 | struct vmcb_save_area *save = &vmcb->save; | |
6aa8b732 AK |
469 | |
470 | control->intercept_cr_read = INTERCEPT_CR0_MASK | | |
471 | INTERCEPT_CR3_MASK | | |
472 | INTERCEPT_CR4_MASK; | |
473 | ||
474 | control->intercept_cr_write = INTERCEPT_CR0_MASK | | |
475 | INTERCEPT_CR3_MASK | | |
476 | INTERCEPT_CR4_MASK; | |
477 | ||
478 | control->intercept_dr_read = INTERCEPT_DR0_MASK | | |
479 | INTERCEPT_DR1_MASK | | |
480 | INTERCEPT_DR2_MASK | | |
481 | INTERCEPT_DR3_MASK; | |
482 | ||
483 | control->intercept_dr_write = INTERCEPT_DR0_MASK | | |
484 | INTERCEPT_DR1_MASK | | |
485 | INTERCEPT_DR2_MASK | | |
486 | INTERCEPT_DR3_MASK | | |
487 | INTERCEPT_DR5_MASK | | |
488 | INTERCEPT_DR7_MASK; | |
489 | ||
490 | control->intercept_exceptions = 1 << PF_VECTOR; | |
491 | ||
492 | ||
493 | control->intercept = (1ULL << INTERCEPT_INTR) | | |
494 | (1ULL << INTERCEPT_NMI) | | |
0152527b | 495 | (1ULL << INTERCEPT_SMI) | |
6aa8b732 AK |
496 | /* |
497 | * selective cr0 intercept bug? | |
498 | * 0: 0f 22 d8 mov %eax,%cr3 | |
499 | * 3: 0f 20 c0 mov %cr0,%eax | |
500 | * 6: 0d 00 00 00 80 or $0x80000000,%eax | |
501 | * b: 0f 22 c0 mov %eax,%cr0 | |
502 | * set cr3 ->interception | |
503 | * get cr0 ->interception | |
504 | * set cr0 -> no interception | |
505 | */ | |
506 | /* (1ULL << INTERCEPT_SELECTIVE_CR0) | */ | |
507 | (1ULL << INTERCEPT_CPUID) | | |
508 | (1ULL << INTERCEPT_HLT) | | |
6aa8b732 AK |
509 | (1ULL << INTERCEPT_INVLPGA) | |
510 | (1ULL << INTERCEPT_IOIO_PROT) | | |
511 | (1ULL << INTERCEPT_MSR_PROT) | | |
512 | (1ULL << INTERCEPT_TASK_SWITCH) | | |
46fe4ddd | 513 | (1ULL << INTERCEPT_SHUTDOWN) | |
6aa8b732 AK |
514 | (1ULL << INTERCEPT_VMRUN) | |
515 | (1ULL << INTERCEPT_VMMCALL) | | |
516 | (1ULL << INTERCEPT_VMLOAD) | | |
517 | (1ULL << INTERCEPT_VMSAVE) | | |
518 | (1ULL << INTERCEPT_STGI) | | |
519 | (1ULL << INTERCEPT_CLGI) | | |
916ce236 JR |
520 | (1ULL << INTERCEPT_SKINIT) | |
521 | (1ULL << INTERCEPT_MONITOR) | | |
522 | (1ULL << INTERCEPT_MWAIT); | |
6aa8b732 AK |
523 | |
524 | control->iopm_base_pa = iopm_base; | |
525 | control->msrpm_base_pa = msrpm_base; | |
0cc5064d | 526 | control->tsc_offset = 0; |
6aa8b732 AK |
527 | control->int_ctl = V_INTR_MASKING_MASK; |
528 | ||
529 | init_seg(&save->es); | |
530 | init_seg(&save->ss); | |
531 | init_seg(&save->ds); | |
532 | init_seg(&save->fs); | |
533 | init_seg(&save->gs); | |
534 | ||
535 | save->cs.selector = 0xf000; | |
536 | /* Executable/Readable Code Segment */ | |
537 | save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK | | |
538 | SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK; | |
539 | save->cs.limit = 0xffff; | |
d92899a0 AK |
540 | /* |
541 | * cs.base should really be 0xffff0000, but vmx can't handle that, so | |
542 | * be consistent with it. | |
543 | * | |
544 | * Replace when we have real mode working for vmx. | |
545 | */ | |
546 | save->cs.base = 0xf0000; | |
6aa8b732 AK |
547 | |
548 | save->gdtr.limit = 0xffff; | |
549 | save->idtr.limit = 0xffff; | |
550 | ||
551 | init_sys_seg(&save->ldtr, SEG_TYPE_LDT); | |
552 | init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16); | |
553 | ||
554 | save->efer = MSR_EFER_SVME_MASK; | |
555 | ||
556 | save->dr6 = 0xffff0ff0; | |
557 | save->dr7 = 0x400; | |
558 | save->rflags = 2; | |
559 | save->rip = 0x0000fff0; | |
560 | ||
561 | /* | |
562 | * cr0 val on cpu init should be 0x60000010, we enable cpu | |
563 | * cache by default. the orderly way is to enable cache in bios. | |
564 | */ | |
cd205625 | 565 | save->cr0 = 0x00000010 | CR0_PG_MASK | CR0_WP_MASK; |
6aa8b732 AK |
566 | save->cr4 = CR4_PAE_MASK; |
567 | /* rdx = ?? */ | |
568 | } | |
569 | ||
570 | static int svm_create_vcpu(struct kvm_vcpu *vcpu) | |
571 | { | |
572 | struct page *page; | |
573 | int r; | |
574 | ||
575 | r = -ENOMEM; | |
576 | vcpu->svm = kzalloc(sizeof *vcpu->svm, GFP_KERNEL); | |
577 | if (!vcpu->svm) | |
578 | goto out1; | |
579 | page = alloc_page(GFP_KERNEL); | |
580 | if (!page) | |
581 | goto out2; | |
582 | ||
583 | vcpu->svm->vmcb = page_address(page); | |
129ee910 | 584 | clear_page(vcpu->svm->vmcb); |
6aa8b732 | 585 | vcpu->svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT; |
6aa8b732 AK |
586 | vcpu->svm->asid_generation = 0; |
587 | memset(vcpu->svm->db_regs, 0, sizeof(vcpu->svm->db_regs)); | |
588 | init_vmcb(vcpu->svm->vmcb); | |
589 | ||
36241b8c | 590 | fx_init(vcpu); |
7807fa6c | 591 | vcpu->fpu_active = 1; |
94cea1bb AK |
592 | vcpu->apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE; |
593 | if (vcpu == &vcpu->kvm->vcpus[0]) | |
594 | vcpu->apic_base |= MSR_IA32_APICBASE_BSP; | |
36241b8c | 595 | |
6aa8b732 AK |
596 | return 0; |
597 | ||
598 | out2: | |
599 | kfree(vcpu->svm); | |
600 | out1: | |
601 | return r; | |
602 | } | |
603 | ||
604 | static void svm_free_vcpu(struct kvm_vcpu *vcpu) | |
605 | { | |
606 | if (!vcpu->svm) | |
607 | return; | |
608 | if (vcpu->svm->vmcb) | |
609 | __free_page(pfn_to_page(vcpu->svm->vmcb_pa >> PAGE_SHIFT)); | |
610 | kfree(vcpu->svm); | |
611 | } | |
612 | ||
bccf2150 | 613 | static void svm_vcpu_load(struct kvm_vcpu *vcpu) |
6aa8b732 | 614 | { |
94dfbdb3 | 615 | int cpu, i; |
0cc5064d AK |
616 | |
617 | cpu = get_cpu(); | |
618 | if (unlikely(cpu != vcpu->cpu)) { | |
619 | u64 tsc_this, delta; | |
620 | ||
621 | /* | |
622 | * Make sure that the guest sees a monotonically | |
623 | * increasing TSC. | |
624 | */ | |
625 | rdtscll(tsc_this); | |
626 | delta = vcpu->host_tsc - tsc_this; | |
627 | vcpu->svm->vmcb->control.tsc_offset += delta; | |
628 | vcpu->cpu = cpu; | |
629 | } | |
94dfbdb3 AL |
630 | |
631 | for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++) | |
632 | rdmsrl(host_save_user_msrs[i], vcpu->svm->host_user_msrs[i]); | |
6aa8b732 AK |
633 | } |
634 | ||
635 | static void svm_vcpu_put(struct kvm_vcpu *vcpu) | |
636 | { | |
94dfbdb3 AL |
637 | int i; |
638 | ||
639 | for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++) | |
640 | wrmsrl(host_save_user_msrs[i], vcpu->svm->host_user_msrs[i]); | |
641 | ||
0cc5064d | 642 | rdtscll(vcpu->host_tsc); |
6aa8b732 AK |
643 | put_cpu(); |
644 | } | |
645 | ||
774c47f1 AK |
646 | static void svm_vcpu_decache(struct kvm_vcpu *vcpu) |
647 | { | |
648 | } | |
649 | ||
6aa8b732 AK |
650 | static void svm_cache_regs(struct kvm_vcpu *vcpu) |
651 | { | |
652 | vcpu->regs[VCPU_REGS_RAX] = vcpu->svm->vmcb->save.rax; | |
653 | vcpu->regs[VCPU_REGS_RSP] = vcpu->svm->vmcb->save.rsp; | |
654 | vcpu->rip = vcpu->svm->vmcb->save.rip; | |
655 | } | |
656 | ||
657 | static void svm_decache_regs(struct kvm_vcpu *vcpu) | |
658 | { | |
659 | vcpu->svm->vmcb->save.rax = vcpu->regs[VCPU_REGS_RAX]; | |
660 | vcpu->svm->vmcb->save.rsp = vcpu->regs[VCPU_REGS_RSP]; | |
661 | vcpu->svm->vmcb->save.rip = vcpu->rip; | |
662 | } | |
663 | ||
664 | static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu) | |
665 | { | |
666 | return vcpu->svm->vmcb->save.rflags; | |
667 | } | |
668 | ||
669 | static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) | |
670 | { | |
671 | vcpu->svm->vmcb->save.rflags = rflags; | |
672 | } | |
673 | ||
674 | static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg) | |
675 | { | |
676 | struct vmcb_save_area *save = &vcpu->svm->vmcb->save; | |
677 | ||
678 | switch (seg) { | |
679 | case VCPU_SREG_CS: return &save->cs; | |
680 | case VCPU_SREG_DS: return &save->ds; | |
681 | case VCPU_SREG_ES: return &save->es; | |
682 | case VCPU_SREG_FS: return &save->fs; | |
683 | case VCPU_SREG_GS: return &save->gs; | |
684 | case VCPU_SREG_SS: return &save->ss; | |
685 | case VCPU_SREG_TR: return &save->tr; | |
686 | case VCPU_SREG_LDTR: return &save->ldtr; | |
687 | } | |
688 | BUG(); | |
8b6d44c7 | 689 | return NULL; |
6aa8b732 AK |
690 | } |
691 | ||
692 | static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg) | |
693 | { | |
694 | struct vmcb_seg *s = svm_seg(vcpu, seg); | |
695 | ||
696 | return s->base; | |
697 | } | |
698 | ||
699 | static void svm_get_segment(struct kvm_vcpu *vcpu, | |
700 | struct kvm_segment *var, int seg) | |
701 | { | |
702 | struct vmcb_seg *s = svm_seg(vcpu, seg); | |
703 | ||
704 | var->base = s->base; | |
705 | var->limit = s->limit; | |
706 | var->selector = s->selector; | |
707 | var->type = s->attrib & SVM_SELECTOR_TYPE_MASK; | |
708 | var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1; | |
709 | var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3; | |
710 | var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1; | |
711 | var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1; | |
712 | var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1; | |
713 | var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1; | |
714 | var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1; | |
715 | var->unusable = !var->present; | |
716 | } | |
717 | ||
718 | static void svm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l) | |
719 | { | |
720 | struct vmcb_seg *s = svm_seg(vcpu, VCPU_SREG_CS); | |
721 | ||
722 | *db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1; | |
723 | *l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1; | |
724 | } | |
725 | ||
726 | static void svm_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt) | |
727 | { | |
bce66ca4 LN |
728 | dt->limit = vcpu->svm->vmcb->save.idtr.limit; |
729 | dt->base = vcpu->svm->vmcb->save.idtr.base; | |
6aa8b732 AK |
730 | } |
731 | ||
732 | static void svm_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt) | |
733 | { | |
bce66ca4 LN |
734 | vcpu->svm->vmcb->save.idtr.limit = dt->limit; |
735 | vcpu->svm->vmcb->save.idtr.base = dt->base ; | |
6aa8b732 AK |
736 | } |
737 | ||
738 | static void svm_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt) | |
739 | { | |
740 | dt->limit = vcpu->svm->vmcb->save.gdtr.limit; | |
741 | dt->base = vcpu->svm->vmcb->save.gdtr.base; | |
742 | } | |
743 | ||
744 | static void svm_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt) | |
745 | { | |
746 | vcpu->svm->vmcb->save.gdtr.limit = dt->limit; | |
747 | vcpu->svm->vmcb->save.gdtr.base = dt->base ; | |
748 | } | |
749 | ||
25c4c276 | 750 | static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu) |
399badf3 AK |
751 | { |
752 | } | |
753 | ||
6aa8b732 AK |
754 | static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) |
755 | { | |
05b3e0c2 | 756 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
757 | if (vcpu->shadow_efer & KVM_EFER_LME) { |
758 | if (!is_paging(vcpu) && (cr0 & CR0_PG_MASK)) { | |
759 | vcpu->shadow_efer |= KVM_EFER_LMA; | |
760 | vcpu->svm->vmcb->save.efer |= KVM_EFER_LMA | KVM_EFER_LME; | |
761 | } | |
762 | ||
763 | if (is_paging(vcpu) && !(cr0 & CR0_PG_MASK) ) { | |
764 | vcpu->shadow_efer &= ~KVM_EFER_LMA; | |
765 | vcpu->svm->vmcb->save.efer &= ~(KVM_EFER_LMA | KVM_EFER_LME); | |
766 | } | |
767 | } | |
768 | #endif | |
7807fa6c AL |
769 | if ((vcpu->cr0 & CR0_TS_MASK) && !(cr0 & CR0_TS_MASK)) { |
770 | vcpu->svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR); | |
771 | vcpu->fpu_active = 1; | |
772 | } | |
773 | ||
6aa8b732 | 774 | vcpu->cr0 = cr0; |
6da63cf9 AK |
775 | cr0 |= CR0_PG_MASK | CR0_WP_MASK; |
776 | cr0 &= ~(CR0_CD_MASK | CR0_NW_MASK); | |
777 | vcpu->svm->vmcb->save.cr0 = cr0; | |
6aa8b732 AK |
778 | } |
779 | ||
780 | static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) | |
781 | { | |
782 | vcpu->cr4 = cr4; | |
783 | vcpu->svm->vmcb->save.cr4 = cr4 | CR4_PAE_MASK; | |
784 | } | |
785 | ||
786 | static void svm_set_segment(struct kvm_vcpu *vcpu, | |
787 | struct kvm_segment *var, int seg) | |
788 | { | |
789 | struct vmcb_seg *s = svm_seg(vcpu, seg); | |
790 | ||
791 | s->base = var->base; | |
792 | s->limit = var->limit; | |
793 | s->selector = var->selector; | |
794 | if (var->unusable) | |
795 | s->attrib = 0; | |
796 | else { | |
797 | s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK); | |
798 | s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT; | |
799 | s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT; | |
800 | s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT; | |
801 | s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT; | |
802 | s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT; | |
803 | s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT; | |
804 | s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT; | |
805 | } | |
806 | if (seg == VCPU_SREG_CS) | |
807 | vcpu->svm->vmcb->save.cpl | |
808 | = (vcpu->svm->vmcb->save.cs.attrib | |
809 | >> SVM_SELECTOR_DPL_SHIFT) & 3; | |
810 | ||
811 | } | |
812 | ||
813 | /* FIXME: | |
814 | ||
815 | vcpu->svm->vmcb->control.int_ctl &= ~V_TPR_MASK; | |
816 | vcpu->svm->vmcb->control.int_ctl |= (sregs->cr8 & V_TPR_MASK); | |
817 | ||
818 | */ | |
819 | ||
820 | static int svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_debug_guest *dbg) | |
821 | { | |
822 | return -EOPNOTSUPP; | |
823 | } | |
824 | ||
825 | static void load_host_msrs(struct kvm_vcpu *vcpu) | |
826 | { | |
94dfbdb3 AL |
827 | #ifdef CONFIG_X86_64 |
828 | wrmsrl(MSR_GS_BASE, vcpu->svm->host_gs_base); | |
829 | #endif | |
6aa8b732 AK |
830 | } |
831 | ||
832 | static void save_host_msrs(struct kvm_vcpu *vcpu) | |
833 | { | |
94dfbdb3 AL |
834 | #ifdef CONFIG_X86_64 |
835 | rdmsrl(MSR_GS_BASE, vcpu->svm->host_gs_base); | |
836 | #endif | |
6aa8b732 AK |
837 | } |
838 | ||
839 | static void new_asid(struct kvm_vcpu *vcpu, struct svm_cpu_data *svm_data) | |
840 | { | |
841 | if (svm_data->next_asid > svm_data->max_asid) { | |
842 | ++svm_data->asid_generation; | |
843 | svm_data->next_asid = 1; | |
844 | vcpu->svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID; | |
845 | } | |
846 | ||
847 | vcpu->cpu = svm_data->cpu; | |
848 | vcpu->svm->asid_generation = svm_data->asid_generation; | |
849 | vcpu->svm->vmcb->control.asid = svm_data->next_asid++; | |
850 | } | |
851 | ||
852 | static void svm_invlpg(struct kvm_vcpu *vcpu, gva_t address) | |
853 | { | |
854 | invlpga(address, vcpu->svm->vmcb->control.asid); // is needed? | |
855 | } | |
856 | ||
857 | static unsigned long svm_get_dr(struct kvm_vcpu *vcpu, int dr) | |
858 | { | |
859 | return vcpu->svm->db_regs[dr]; | |
860 | } | |
861 | ||
862 | static void svm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long value, | |
863 | int *exception) | |
864 | { | |
865 | *exception = 0; | |
866 | ||
867 | if (vcpu->svm->vmcb->save.dr7 & DR7_GD_MASK) { | |
868 | vcpu->svm->vmcb->save.dr7 &= ~DR7_GD_MASK; | |
869 | vcpu->svm->vmcb->save.dr6 |= DR6_BD_MASK; | |
870 | *exception = DB_VECTOR; | |
871 | return; | |
872 | } | |
873 | ||
874 | switch (dr) { | |
875 | case 0 ... 3: | |
876 | vcpu->svm->db_regs[dr] = value; | |
877 | return; | |
878 | case 4 ... 5: | |
879 | if (vcpu->cr4 & CR4_DE_MASK) { | |
880 | *exception = UD_VECTOR; | |
881 | return; | |
882 | } | |
883 | case 7: { | |
884 | if (value & ~((1ULL << 32) - 1)) { | |
885 | *exception = GP_VECTOR; | |
886 | return; | |
887 | } | |
888 | vcpu->svm->vmcb->save.dr7 = value; | |
889 | return; | |
890 | } | |
891 | default: | |
892 | printk(KERN_DEBUG "%s: unexpected dr %u\n", | |
893 | __FUNCTION__, dr); | |
894 | *exception = UD_VECTOR; | |
895 | return; | |
896 | } | |
897 | } | |
898 | ||
899 | static int pf_interception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) | |
900 | { | |
901 | u32 exit_int_info = vcpu->svm->vmcb->control.exit_int_info; | |
902 | u64 fault_address; | |
903 | u32 error_code; | |
904 | enum emulation_result er; | |
e2dec939 | 905 | int r; |
6aa8b732 AK |
906 | |
907 | if (is_external_interrupt(exit_int_info)) | |
908 | push_irq(vcpu, exit_int_info & SVM_EVTINJ_VEC_MASK); | |
909 | ||
910 | spin_lock(&vcpu->kvm->lock); | |
911 | ||
912 | fault_address = vcpu->svm->vmcb->control.exit_info_2; | |
913 | error_code = vcpu->svm->vmcb->control.exit_info_1; | |
e2dec939 AK |
914 | r = kvm_mmu_page_fault(vcpu, fault_address, error_code); |
915 | if (r < 0) { | |
916 | spin_unlock(&vcpu->kvm->lock); | |
917 | return r; | |
918 | } | |
919 | if (!r) { | |
6aa8b732 AK |
920 | spin_unlock(&vcpu->kvm->lock); |
921 | return 1; | |
922 | } | |
923 | er = emulate_instruction(vcpu, kvm_run, fault_address, error_code); | |
924 | spin_unlock(&vcpu->kvm->lock); | |
925 | ||
926 | switch (er) { | |
927 | case EMULATE_DONE: | |
928 | return 1; | |
929 | case EMULATE_DO_MMIO: | |
1165f5fe | 930 | ++vcpu->stat.mmio_exits; |
6aa8b732 AK |
931 | kvm_run->exit_reason = KVM_EXIT_MMIO; |
932 | return 0; | |
933 | case EMULATE_FAIL: | |
934 | vcpu_printf(vcpu, "%s: emulate fail\n", __FUNCTION__); | |
935 | break; | |
936 | default: | |
937 | BUG(); | |
938 | } | |
939 | ||
940 | kvm_run->exit_reason = KVM_EXIT_UNKNOWN; | |
941 | return 0; | |
942 | } | |
943 | ||
7807fa6c AL |
944 | static int nm_interception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) |
945 | { | |
946 | vcpu->svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR); | |
947 | if (!(vcpu->cr0 & CR0_TS_MASK)) | |
948 | vcpu->svm->vmcb->save.cr0 &= ~CR0_TS_MASK; | |
949 | vcpu->fpu_active = 1; | |
950 | ||
951 | return 1; | |
952 | } | |
953 | ||
46fe4ddd JR |
954 | static int shutdown_interception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) |
955 | { | |
956 | /* | |
957 | * VMCB is undefined after a SHUTDOWN intercept | |
958 | * so reinitialize it. | |
959 | */ | |
129ee910 | 960 | clear_page(vcpu->svm->vmcb); |
46fe4ddd JR |
961 | init_vmcb(vcpu->svm->vmcb); |
962 | ||
963 | kvm_run->exit_reason = KVM_EXIT_SHUTDOWN; | |
964 | return 0; | |
965 | } | |
966 | ||
6aa8b732 AK |
967 | static int io_get_override(struct kvm_vcpu *vcpu, |
968 | struct vmcb_seg **seg, | |
969 | int *addr_override) | |
970 | { | |
971 | u8 inst[MAX_INST_SIZE]; | |
972 | unsigned ins_length; | |
973 | gva_t rip; | |
974 | int i; | |
975 | ||
976 | rip = vcpu->svm->vmcb->save.rip; | |
977 | ins_length = vcpu->svm->next_rip - rip; | |
978 | rip += vcpu->svm->vmcb->save.cs.base; | |
979 | ||
980 | if (ins_length > MAX_INST_SIZE) | |
981 | printk(KERN_DEBUG | |
982 | "%s: inst length err, cs base 0x%llx rip 0x%llx " | |
983 | "next rip 0x%llx ins_length %u\n", | |
984 | __FUNCTION__, | |
985 | vcpu->svm->vmcb->save.cs.base, | |
986 | vcpu->svm->vmcb->save.rip, | |
987 | vcpu->svm->vmcb->control.exit_info_2, | |
988 | ins_length); | |
989 | ||
990 | if (kvm_read_guest(vcpu, rip, ins_length, inst) != ins_length) | |
991 | /* #PF */ | |
992 | return 0; | |
993 | ||
994 | *addr_override = 0; | |
8b6d44c7 | 995 | *seg = NULL; |
6aa8b732 AK |
996 | for (i = 0; i < ins_length; i++) |
997 | switch (inst[i]) { | |
998 | case 0xf0: | |
999 | case 0xf2: | |
1000 | case 0xf3: | |
1001 | case 0x66: | |
1002 | continue; | |
1003 | case 0x67: | |
1004 | *addr_override = 1; | |
1005 | continue; | |
1006 | case 0x2e: | |
1007 | *seg = &vcpu->svm->vmcb->save.cs; | |
1008 | continue; | |
1009 | case 0x36: | |
1010 | *seg = &vcpu->svm->vmcb->save.ss; | |
1011 | continue; | |
1012 | case 0x3e: | |
1013 | *seg = &vcpu->svm->vmcb->save.ds; | |
1014 | continue; | |
1015 | case 0x26: | |
1016 | *seg = &vcpu->svm->vmcb->save.es; | |
1017 | continue; | |
1018 | case 0x64: | |
1019 | *seg = &vcpu->svm->vmcb->save.fs; | |
1020 | continue; | |
1021 | case 0x65: | |
1022 | *seg = &vcpu->svm->vmcb->save.gs; | |
1023 | continue; | |
1024 | default: | |
1025 | return 1; | |
1026 | } | |
1027 | printk(KERN_DEBUG "%s: unexpected\n", __FUNCTION__); | |
1028 | return 0; | |
1029 | } | |
1030 | ||
039576c0 | 1031 | static unsigned long io_adress(struct kvm_vcpu *vcpu, int ins, gva_t *address) |
6aa8b732 AK |
1032 | { |
1033 | unsigned long addr_mask; | |
1034 | unsigned long *reg; | |
1035 | struct vmcb_seg *seg; | |
1036 | int addr_override; | |
1037 | struct vmcb_save_area *save_area = &vcpu->svm->vmcb->save; | |
1038 | u16 cs_attrib = save_area->cs.attrib; | |
1039 | unsigned addr_size = get_addr_size(vcpu); | |
1040 | ||
1041 | if (!io_get_override(vcpu, &seg, &addr_override)) | |
1042 | return 0; | |
1043 | ||
1044 | if (addr_override) | |
1045 | addr_size = (addr_size == 2) ? 4: (addr_size >> 1); | |
1046 | ||
1047 | if (ins) { | |
1048 | reg = &vcpu->regs[VCPU_REGS_RDI]; | |
1049 | seg = &vcpu->svm->vmcb->save.es; | |
1050 | } else { | |
1051 | reg = &vcpu->regs[VCPU_REGS_RSI]; | |
1052 | seg = (seg) ? seg : &vcpu->svm->vmcb->save.ds; | |
1053 | } | |
1054 | ||
1055 | addr_mask = ~0ULL >> (64 - (addr_size * 8)); | |
1056 | ||
1057 | if ((cs_attrib & SVM_SELECTOR_L_MASK) && | |
1058 | !(vcpu->svm->vmcb->save.rflags & X86_EFLAGS_VM)) { | |
1059 | *address = (*reg & addr_mask); | |
1060 | return addr_mask; | |
1061 | } | |
1062 | ||
1063 | if (!(seg->attrib & SVM_SELECTOR_P_SHIFT)) { | |
1064 | svm_inject_gp(vcpu, 0); | |
1065 | return 0; | |
1066 | } | |
1067 | ||
1068 | *address = (*reg & addr_mask) + seg->base; | |
1069 | return addr_mask; | |
1070 | } | |
1071 | ||
1072 | static int io_interception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) | |
1073 | { | |
1074 | u32 io_info = vcpu->svm->vmcb->control.exit_info_1; //address size bug? | |
039576c0 AK |
1075 | int size, down, in, string, rep; |
1076 | unsigned port; | |
1077 | unsigned long count; | |
1078 | gva_t address = 0; | |
6aa8b732 | 1079 | |
1165f5fe | 1080 | ++vcpu->stat.io_exits; |
6aa8b732 AK |
1081 | |
1082 | vcpu->svm->next_rip = vcpu->svm->vmcb->control.exit_info_2; | |
1083 | ||
039576c0 AK |
1084 | in = (io_info & SVM_IOIO_TYPE_MASK) != 0; |
1085 | port = io_info >> 16; | |
1086 | size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT; | |
1087 | string = (io_info & SVM_IOIO_STR_MASK) != 0; | |
1088 | rep = (io_info & SVM_IOIO_REP_MASK) != 0; | |
1089 | count = 1; | |
1090 | down = (vcpu->svm->vmcb->save.rflags & X86_EFLAGS_DF) != 0; | |
6aa8b732 | 1091 | |
039576c0 | 1092 | if (string) { |
6aa8b732 AK |
1093 | unsigned addr_mask; |
1094 | ||
039576c0 | 1095 | addr_mask = io_adress(vcpu, in, &address); |
6aa8b732 | 1096 | if (!addr_mask) { |
d27d4aca AK |
1097 | printk(KERN_DEBUG "%s: get io address failed\n", |
1098 | __FUNCTION__); | |
6aa8b732 AK |
1099 | return 1; |
1100 | } | |
1101 | ||
039576c0 AK |
1102 | if (rep) |
1103 | count = vcpu->regs[VCPU_REGS_RCX] & addr_mask; | |
1104 | } | |
1105 | return kvm_setup_pio(vcpu, kvm_run, in, size, count, string, down, | |
1106 | address, rep, port); | |
6aa8b732 AK |
1107 | } |
1108 | ||
6aa8b732 AK |
1109 | static int nop_on_interception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) |
1110 | { | |
1111 | return 1; | |
1112 | } | |
1113 | ||
1114 | static int halt_interception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) | |
1115 | { | |
1116 | vcpu->svm->next_rip = vcpu->svm->vmcb->save.rip + 1; | |
1117 | skip_emulated_instruction(vcpu); | |
d3bef15f | 1118 | return kvm_emulate_halt(vcpu); |
6aa8b732 AK |
1119 | } |
1120 | ||
02e235bc AK |
1121 | static int vmmcall_interception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) |
1122 | { | |
510043da DL |
1123 | vcpu->svm->next_rip = vcpu->svm->vmcb->save.rip + 3; |
1124 | skip_emulated_instruction(vcpu); | |
270fd9b9 | 1125 | return kvm_hypercall(vcpu, kvm_run); |
02e235bc AK |
1126 | } |
1127 | ||
6aa8b732 AK |
1128 | static int invalid_op_interception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) |
1129 | { | |
1130 | inject_ud(vcpu); | |
1131 | return 1; | |
1132 | } | |
1133 | ||
1134 | static int task_switch_interception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) | |
1135 | { | |
1136 | printk(KERN_DEBUG "%s: task swiche is unsupported\n", __FUNCTION__); | |
1137 | kvm_run->exit_reason = KVM_EXIT_UNKNOWN; | |
1138 | return 0; | |
1139 | } | |
1140 | ||
1141 | static int cpuid_interception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) | |
1142 | { | |
1143 | vcpu->svm->next_rip = vcpu->svm->vmcb->save.rip + 2; | |
06465c5a AK |
1144 | kvm_emulate_cpuid(vcpu); |
1145 | return 1; | |
6aa8b732 AK |
1146 | } |
1147 | ||
1148 | static int emulate_on_interception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) | |
1149 | { | |
8b6d44c7 | 1150 | if (emulate_instruction(vcpu, NULL, 0, 0) != EMULATE_DONE) |
6aa8b732 AK |
1151 | printk(KERN_ERR "%s: failed\n", __FUNCTION__); |
1152 | return 1; | |
1153 | } | |
1154 | ||
1155 | static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data) | |
1156 | { | |
1157 | switch (ecx) { | |
6aa8b732 AK |
1158 | case MSR_IA32_TIME_STAMP_COUNTER: { |
1159 | u64 tsc; | |
1160 | ||
1161 | rdtscll(tsc); | |
1162 | *data = vcpu->svm->vmcb->control.tsc_offset + tsc; | |
1163 | break; | |
1164 | } | |
0e859cac | 1165 | case MSR_K6_STAR: |
6aa8b732 AK |
1166 | *data = vcpu->svm->vmcb->save.star; |
1167 | break; | |
0e859cac | 1168 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
1169 | case MSR_LSTAR: |
1170 | *data = vcpu->svm->vmcb->save.lstar; | |
1171 | break; | |
1172 | case MSR_CSTAR: | |
1173 | *data = vcpu->svm->vmcb->save.cstar; | |
1174 | break; | |
1175 | case MSR_KERNEL_GS_BASE: | |
1176 | *data = vcpu->svm->vmcb->save.kernel_gs_base; | |
1177 | break; | |
1178 | case MSR_SYSCALL_MASK: | |
1179 | *data = vcpu->svm->vmcb->save.sfmask; | |
1180 | break; | |
1181 | #endif | |
1182 | case MSR_IA32_SYSENTER_CS: | |
1183 | *data = vcpu->svm->vmcb->save.sysenter_cs; | |
1184 | break; | |
1185 | case MSR_IA32_SYSENTER_EIP: | |
1186 | *data = vcpu->svm->vmcb->save.sysenter_eip; | |
1187 | break; | |
1188 | case MSR_IA32_SYSENTER_ESP: | |
1189 | *data = vcpu->svm->vmcb->save.sysenter_esp; | |
1190 | break; | |
1191 | default: | |
3bab1f5d | 1192 | return kvm_get_msr_common(vcpu, ecx, data); |
6aa8b732 AK |
1193 | } |
1194 | return 0; | |
1195 | } | |
1196 | ||
1197 | static int rdmsr_interception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) | |
1198 | { | |
1199 | u32 ecx = vcpu->regs[VCPU_REGS_RCX]; | |
1200 | u64 data; | |
1201 | ||
1202 | if (svm_get_msr(vcpu, ecx, &data)) | |
1203 | svm_inject_gp(vcpu, 0); | |
1204 | else { | |
1205 | vcpu->svm->vmcb->save.rax = data & 0xffffffff; | |
1206 | vcpu->regs[VCPU_REGS_RDX] = data >> 32; | |
1207 | vcpu->svm->next_rip = vcpu->svm->vmcb->save.rip + 2; | |
1208 | skip_emulated_instruction(vcpu); | |
1209 | } | |
1210 | return 1; | |
1211 | } | |
1212 | ||
1213 | static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data) | |
1214 | { | |
1215 | switch (ecx) { | |
6aa8b732 AK |
1216 | case MSR_IA32_TIME_STAMP_COUNTER: { |
1217 | u64 tsc; | |
1218 | ||
1219 | rdtscll(tsc); | |
1220 | vcpu->svm->vmcb->control.tsc_offset = data - tsc; | |
1221 | break; | |
1222 | } | |
0e859cac | 1223 | case MSR_K6_STAR: |
6aa8b732 AK |
1224 | vcpu->svm->vmcb->save.star = data; |
1225 | break; | |
49b14f24 | 1226 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
1227 | case MSR_LSTAR: |
1228 | vcpu->svm->vmcb->save.lstar = data; | |
1229 | break; | |
1230 | case MSR_CSTAR: | |
1231 | vcpu->svm->vmcb->save.cstar = data; | |
1232 | break; | |
1233 | case MSR_KERNEL_GS_BASE: | |
1234 | vcpu->svm->vmcb->save.kernel_gs_base = data; | |
1235 | break; | |
1236 | case MSR_SYSCALL_MASK: | |
1237 | vcpu->svm->vmcb->save.sfmask = data; | |
1238 | break; | |
1239 | #endif | |
1240 | case MSR_IA32_SYSENTER_CS: | |
1241 | vcpu->svm->vmcb->save.sysenter_cs = data; | |
1242 | break; | |
1243 | case MSR_IA32_SYSENTER_EIP: | |
1244 | vcpu->svm->vmcb->save.sysenter_eip = data; | |
1245 | break; | |
1246 | case MSR_IA32_SYSENTER_ESP: | |
1247 | vcpu->svm->vmcb->save.sysenter_esp = data; | |
1248 | break; | |
1249 | default: | |
3bab1f5d | 1250 | return kvm_set_msr_common(vcpu, ecx, data); |
6aa8b732 AK |
1251 | } |
1252 | return 0; | |
1253 | } | |
1254 | ||
1255 | static int wrmsr_interception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) | |
1256 | { | |
1257 | u32 ecx = vcpu->regs[VCPU_REGS_RCX]; | |
1258 | u64 data = (vcpu->svm->vmcb->save.rax & -1u) | |
1259 | | ((u64)(vcpu->regs[VCPU_REGS_RDX] & -1u) << 32); | |
1260 | vcpu->svm->next_rip = vcpu->svm->vmcb->save.rip + 2; | |
1261 | if (svm_set_msr(vcpu, ecx, data)) | |
1262 | svm_inject_gp(vcpu, 0); | |
1263 | else | |
1264 | skip_emulated_instruction(vcpu); | |
1265 | return 1; | |
1266 | } | |
1267 | ||
1268 | static int msr_interception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) | |
1269 | { | |
1270 | if (vcpu->svm->vmcb->control.exit_info_1) | |
1271 | return wrmsr_interception(vcpu, kvm_run); | |
1272 | else | |
1273 | return rdmsr_interception(vcpu, kvm_run); | |
1274 | } | |
1275 | ||
c1150d8c DL |
1276 | static int interrupt_window_interception(struct kvm_vcpu *vcpu, |
1277 | struct kvm_run *kvm_run) | |
1278 | { | |
1279 | /* | |
1280 | * If the user space waits to inject interrupts, exit as soon as | |
1281 | * possible | |
1282 | */ | |
1283 | if (kvm_run->request_interrupt_window && | |
022a9308 | 1284 | !vcpu->irq_summary) { |
1165f5fe | 1285 | ++vcpu->stat.irq_window_exits; |
c1150d8c DL |
1286 | kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN; |
1287 | return 0; | |
1288 | } | |
1289 | ||
1290 | return 1; | |
1291 | } | |
1292 | ||
6aa8b732 AK |
1293 | static int (*svm_exit_handlers[])(struct kvm_vcpu *vcpu, |
1294 | struct kvm_run *kvm_run) = { | |
1295 | [SVM_EXIT_READ_CR0] = emulate_on_interception, | |
1296 | [SVM_EXIT_READ_CR3] = emulate_on_interception, | |
1297 | [SVM_EXIT_READ_CR4] = emulate_on_interception, | |
1298 | /* for now: */ | |
1299 | [SVM_EXIT_WRITE_CR0] = emulate_on_interception, | |
1300 | [SVM_EXIT_WRITE_CR3] = emulate_on_interception, | |
1301 | [SVM_EXIT_WRITE_CR4] = emulate_on_interception, | |
1302 | [SVM_EXIT_READ_DR0] = emulate_on_interception, | |
1303 | [SVM_EXIT_READ_DR1] = emulate_on_interception, | |
1304 | [SVM_EXIT_READ_DR2] = emulate_on_interception, | |
1305 | [SVM_EXIT_READ_DR3] = emulate_on_interception, | |
1306 | [SVM_EXIT_WRITE_DR0] = emulate_on_interception, | |
1307 | [SVM_EXIT_WRITE_DR1] = emulate_on_interception, | |
1308 | [SVM_EXIT_WRITE_DR2] = emulate_on_interception, | |
1309 | [SVM_EXIT_WRITE_DR3] = emulate_on_interception, | |
1310 | [SVM_EXIT_WRITE_DR5] = emulate_on_interception, | |
1311 | [SVM_EXIT_WRITE_DR7] = emulate_on_interception, | |
1312 | [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception, | |
7807fa6c | 1313 | [SVM_EXIT_EXCP_BASE + NM_VECTOR] = nm_interception, |
6aa8b732 AK |
1314 | [SVM_EXIT_INTR] = nop_on_interception, |
1315 | [SVM_EXIT_NMI] = nop_on_interception, | |
1316 | [SVM_EXIT_SMI] = nop_on_interception, | |
1317 | [SVM_EXIT_INIT] = nop_on_interception, | |
c1150d8c | 1318 | [SVM_EXIT_VINTR] = interrupt_window_interception, |
6aa8b732 AK |
1319 | /* [SVM_EXIT_CR0_SEL_WRITE] = emulate_on_interception, */ |
1320 | [SVM_EXIT_CPUID] = cpuid_interception, | |
1321 | [SVM_EXIT_HLT] = halt_interception, | |
1322 | [SVM_EXIT_INVLPG] = emulate_on_interception, | |
1323 | [SVM_EXIT_INVLPGA] = invalid_op_interception, | |
1324 | [SVM_EXIT_IOIO] = io_interception, | |
1325 | [SVM_EXIT_MSR] = msr_interception, | |
1326 | [SVM_EXIT_TASK_SWITCH] = task_switch_interception, | |
46fe4ddd | 1327 | [SVM_EXIT_SHUTDOWN] = shutdown_interception, |
6aa8b732 | 1328 | [SVM_EXIT_VMRUN] = invalid_op_interception, |
02e235bc | 1329 | [SVM_EXIT_VMMCALL] = vmmcall_interception, |
6aa8b732 AK |
1330 | [SVM_EXIT_VMLOAD] = invalid_op_interception, |
1331 | [SVM_EXIT_VMSAVE] = invalid_op_interception, | |
1332 | [SVM_EXIT_STGI] = invalid_op_interception, | |
1333 | [SVM_EXIT_CLGI] = invalid_op_interception, | |
1334 | [SVM_EXIT_SKINIT] = invalid_op_interception, | |
916ce236 JR |
1335 | [SVM_EXIT_MONITOR] = invalid_op_interception, |
1336 | [SVM_EXIT_MWAIT] = invalid_op_interception, | |
6aa8b732 AK |
1337 | }; |
1338 | ||
1339 | ||
1340 | static int handle_exit(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) | |
1341 | { | |
1342 | u32 exit_code = vcpu->svm->vmcb->control.exit_code; | |
1343 | ||
6aa8b732 AK |
1344 | if (is_external_interrupt(vcpu->svm->vmcb->control.exit_int_info) && |
1345 | exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR) | |
1346 | printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x " | |
1347 | "exit_code 0x%x\n", | |
1348 | __FUNCTION__, vcpu->svm->vmcb->control.exit_int_info, | |
1349 | exit_code); | |
1350 | ||
9d8f549d | 1351 | if (exit_code >= ARRAY_SIZE(svm_exit_handlers) |
6aa8b732 AK |
1352 | || svm_exit_handlers[exit_code] == 0) { |
1353 | kvm_run->exit_reason = KVM_EXIT_UNKNOWN; | |
364b625b | 1354 | kvm_run->hw.hardware_exit_reason = exit_code; |
6aa8b732 AK |
1355 | return 0; |
1356 | } | |
1357 | ||
1358 | return svm_exit_handlers[exit_code](vcpu, kvm_run); | |
1359 | } | |
1360 | ||
1361 | static void reload_tss(struct kvm_vcpu *vcpu) | |
1362 | { | |
1363 | int cpu = raw_smp_processor_id(); | |
1364 | ||
1365 | struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu); | |
1366 | svm_data->tss_desc->type = 9; //available 32/64-bit TSS | |
1367 | load_TR_desc(); | |
1368 | } | |
1369 | ||
1370 | static void pre_svm_run(struct kvm_vcpu *vcpu) | |
1371 | { | |
1372 | int cpu = raw_smp_processor_id(); | |
1373 | ||
1374 | struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu); | |
1375 | ||
1376 | vcpu->svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING; | |
1377 | if (vcpu->cpu != cpu || | |
1378 | vcpu->svm->asid_generation != svm_data->asid_generation) | |
1379 | new_asid(vcpu, svm_data); | |
1380 | } | |
1381 | ||
1382 | ||
c1150d8c | 1383 | static inline void kvm_do_inject_irq(struct kvm_vcpu *vcpu) |
6aa8b732 AK |
1384 | { |
1385 | struct vmcb_control_area *control; | |
1386 | ||
6aa8b732 | 1387 | control = &vcpu->svm->vmcb->control; |
6aa8b732 AK |
1388 | control->int_vector = pop_irq(vcpu); |
1389 | control->int_ctl &= ~V_INTR_PRIO_MASK; | |
1390 | control->int_ctl |= V_IRQ_MASK | | |
1391 | ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT); | |
1392 | } | |
1393 | ||
1394 | static void kvm_reput_irq(struct kvm_vcpu *vcpu) | |
1395 | { | |
1396 | struct vmcb_control_area *control = &vcpu->svm->vmcb->control; | |
1397 | ||
1398 | if (control->int_ctl & V_IRQ_MASK) { | |
1399 | control->int_ctl &= ~V_IRQ_MASK; | |
1400 | push_irq(vcpu, control->int_vector); | |
1401 | } | |
c1150d8c DL |
1402 | |
1403 | vcpu->interrupt_window_open = | |
1404 | !(control->int_state & SVM_INTERRUPT_SHADOW_MASK); | |
1405 | } | |
1406 | ||
1407 | static void do_interrupt_requests(struct kvm_vcpu *vcpu, | |
1408 | struct kvm_run *kvm_run) | |
1409 | { | |
1410 | struct vmcb_control_area *control = &vcpu->svm->vmcb->control; | |
1411 | ||
1412 | vcpu->interrupt_window_open = | |
1413 | (!(control->int_state & SVM_INTERRUPT_SHADOW_MASK) && | |
1414 | (vcpu->svm->vmcb->save.rflags & X86_EFLAGS_IF)); | |
1415 | ||
1416 | if (vcpu->interrupt_window_open && vcpu->irq_summary) | |
1417 | /* | |
1418 | * If interrupts enabled, and not blocked by sti or mov ss. Good. | |
1419 | */ | |
1420 | kvm_do_inject_irq(vcpu); | |
1421 | ||
1422 | /* | |
1423 | * Interrupts blocked. Wait for unblock. | |
1424 | */ | |
1425 | if (!vcpu->interrupt_window_open && | |
1426 | (vcpu->irq_summary || kvm_run->request_interrupt_window)) { | |
1427 | control->intercept |= 1ULL << INTERCEPT_VINTR; | |
1428 | } else | |
1429 | control->intercept &= ~(1ULL << INTERCEPT_VINTR); | |
1430 | } | |
1431 | ||
1432 | static void post_kvm_run_save(struct kvm_vcpu *vcpu, | |
1433 | struct kvm_run *kvm_run) | |
1434 | { | |
1435 | kvm_run->ready_for_interrupt_injection = (vcpu->interrupt_window_open && | |
1436 | vcpu->irq_summary == 0); | |
1437 | kvm_run->if_flag = (vcpu->svm->vmcb->save.rflags & X86_EFLAGS_IF) != 0; | |
1438 | kvm_run->cr8 = vcpu->cr8; | |
1439 | kvm_run->apic_base = vcpu->apic_base; | |
1440 | } | |
1441 | ||
1442 | /* | |
1443 | * Check if userspace requested an interrupt window, and that the | |
1444 | * interrupt window is open. | |
1445 | * | |
1446 | * No need to exit to userspace if we already have an interrupt queued. | |
1447 | */ | |
1448 | static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu, | |
1449 | struct kvm_run *kvm_run) | |
1450 | { | |
1451 | return (!vcpu->irq_summary && | |
1452 | kvm_run->request_interrupt_window && | |
1453 | vcpu->interrupt_window_open && | |
1454 | (vcpu->svm->vmcb->save.rflags & X86_EFLAGS_IF)); | |
6aa8b732 AK |
1455 | } |
1456 | ||
1457 | static void save_db_regs(unsigned long *db_regs) | |
1458 | { | |
5aff458e AK |
1459 | asm volatile ("mov %%dr0, %0" : "=r"(db_regs[0])); |
1460 | asm volatile ("mov %%dr1, %0" : "=r"(db_regs[1])); | |
1461 | asm volatile ("mov %%dr2, %0" : "=r"(db_regs[2])); | |
1462 | asm volatile ("mov %%dr3, %0" : "=r"(db_regs[3])); | |
6aa8b732 AK |
1463 | } |
1464 | ||
1465 | static void load_db_regs(unsigned long *db_regs) | |
1466 | { | |
5aff458e AK |
1467 | asm volatile ("mov %0, %%dr0" : : "r"(db_regs[0])); |
1468 | asm volatile ("mov %0, %%dr1" : : "r"(db_regs[1])); | |
1469 | asm volatile ("mov %0, %%dr2" : : "r"(db_regs[2])); | |
1470 | asm volatile ("mov %0, %%dr3" : : "r"(db_regs[3])); | |
6aa8b732 AK |
1471 | } |
1472 | ||
d9e368d6 AK |
1473 | static void svm_flush_tlb(struct kvm_vcpu *vcpu) |
1474 | { | |
1475 | force_new_asid(vcpu); | |
1476 | } | |
1477 | ||
6aa8b732 AK |
1478 | static int svm_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) |
1479 | { | |
1480 | u16 fs_selector; | |
1481 | u16 gs_selector; | |
1482 | u16 ldt_selector; | |
e2dec939 | 1483 | int r; |
6aa8b732 AK |
1484 | |
1485 | again: | |
17c3ba9d AK |
1486 | r = kvm_mmu_reload(vcpu); |
1487 | if (unlikely(r)) | |
1488 | return r; | |
1489 | ||
cccf748b AK |
1490 | if (!vcpu->mmio_read_completed) |
1491 | do_interrupt_requests(vcpu, kvm_run); | |
6aa8b732 AK |
1492 | |
1493 | clgi(); | |
1494 | ||
d9e368d6 AK |
1495 | vcpu->guest_mode = 1; |
1496 | if (vcpu->requests) | |
1497 | if (test_and_clear_bit(KVM_TLB_FLUSH, &vcpu->requests)) | |
1498 | svm_flush_tlb(vcpu); | |
1499 | ||
6aa8b732 AK |
1500 | pre_svm_run(vcpu); |
1501 | ||
1502 | save_host_msrs(vcpu); | |
1503 | fs_selector = read_fs(); | |
1504 | gs_selector = read_gs(); | |
1505 | ldt_selector = read_ldt(); | |
1506 | vcpu->svm->host_cr2 = kvm_read_cr2(); | |
1507 | vcpu->svm->host_dr6 = read_dr6(); | |
1508 | vcpu->svm->host_dr7 = read_dr7(); | |
1509 | vcpu->svm->vmcb->save.cr2 = vcpu->cr2; | |
1510 | ||
1511 | if (vcpu->svm->vmcb->save.dr7 & 0xff) { | |
1512 | write_dr7(0); | |
1513 | save_db_regs(vcpu->svm->host_db_regs); | |
1514 | load_db_regs(vcpu->svm->db_regs); | |
1515 | } | |
36241b8c | 1516 | |
7807fa6c AL |
1517 | if (vcpu->fpu_active) { |
1518 | fx_save(vcpu->host_fx_image); | |
1519 | fx_restore(vcpu->guest_fx_image); | |
1520 | } | |
36241b8c | 1521 | |
6aa8b732 | 1522 | asm volatile ( |
05b3e0c2 | 1523 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
1524 | "push %%rbx; push %%rcx; push %%rdx;" |
1525 | "push %%rsi; push %%rdi; push %%rbp;" | |
1526 | "push %%r8; push %%r9; push %%r10; push %%r11;" | |
1527 | "push %%r12; push %%r13; push %%r14; push %%r15;" | |
1528 | #else | |
1529 | "push %%ebx; push %%ecx; push %%edx;" | |
1530 | "push %%esi; push %%edi; push %%ebp;" | |
1531 | #endif | |
1532 | ||
05b3e0c2 | 1533 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
1534 | "mov %c[rbx](%[vcpu]), %%rbx \n\t" |
1535 | "mov %c[rcx](%[vcpu]), %%rcx \n\t" | |
1536 | "mov %c[rdx](%[vcpu]), %%rdx \n\t" | |
1537 | "mov %c[rsi](%[vcpu]), %%rsi \n\t" | |
1538 | "mov %c[rdi](%[vcpu]), %%rdi \n\t" | |
1539 | "mov %c[rbp](%[vcpu]), %%rbp \n\t" | |
1540 | "mov %c[r8](%[vcpu]), %%r8 \n\t" | |
1541 | "mov %c[r9](%[vcpu]), %%r9 \n\t" | |
1542 | "mov %c[r10](%[vcpu]), %%r10 \n\t" | |
1543 | "mov %c[r11](%[vcpu]), %%r11 \n\t" | |
1544 | "mov %c[r12](%[vcpu]), %%r12 \n\t" | |
1545 | "mov %c[r13](%[vcpu]), %%r13 \n\t" | |
1546 | "mov %c[r14](%[vcpu]), %%r14 \n\t" | |
1547 | "mov %c[r15](%[vcpu]), %%r15 \n\t" | |
1548 | #else | |
1549 | "mov %c[rbx](%[vcpu]), %%ebx \n\t" | |
1550 | "mov %c[rcx](%[vcpu]), %%ecx \n\t" | |
1551 | "mov %c[rdx](%[vcpu]), %%edx \n\t" | |
1552 | "mov %c[rsi](%[vcpu]), %%esi \n\t" | |
1553 | "mov %c[rdi](%[vcpu]), %%edi \n\t" | |
1554 | "mov %c[rbp](%[vcpu]), %%ebp \n\t" | |
1555 | #endif | |
1556 | ||
05b3e0c2 | 1557 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
1558 | /* Enter guest mode */ |
1559 | "push %%rax \n\t" | |
1560 | "mov %c[svm](%[vcpu]), %%rax \n\t" | |
1561 | "mov %c[vmcb](%%rax), %%rax \n\t" | |
1562 | SVM_VMLOAD "\n\t" | |
1563 | SVM_VMRUN "\n\t" | |
1564 | SVM_VMSAVE "\n\t" | |
1565 | "pop %%rax \n\t" | |
1566 | #else | |
1567 | /* Enter guest mode */ | |
1568 | "push %%eax \n\t" | |
1569 | "mov %c[svm](%[vcpu]), %%eax \n\t" | |
1570 | "mov %c[vmcb](%%eax), %%eax \n\t" | |
1571 | SVM_VMLOAD "\n\t" | |
1572 | SVM_VMRUN "\n\t" | |
1573 | SVM_VMSAVE "\n\t" | |
1574 | "pop %%eax \n\t" | |
1575 | #endif | |
1576 | ||
1577 | /* Save guest registers, load host registers */ | |
05b3e0c2 | 1578 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
1579 | "mov %%rbx, %c[rbx](%[vcpu]) \n\t" |
1580 | "mov %%rcx, %c[rcx](%[vcpu]) \n\t" | |
1581 | "mov %%rdx, %c[rdx](%[vcpu]) \n\t" | |
1582 | "mov %%rsi, %c[rsi](%[vcpu]) \n\t" | |
1583 | "mov %%rdi, %c[rdi](%[vcpu]) \n\t" | |
1584 | "mov %%rbp, %c[rbp](%[vcpu]) \n\t" | |
1585 | "mov %%r8, %c[r8](%[vcpu]) \n\t" | |
1586 | "mov %%r9, %c[r9](%[vcpu]) \n\t" | |
1587 | "mov %%r10, %c[r10](%[vcpu]) \n\t" | |
1588 | "mov %%r11, %c[r11](%[vcpu]) \n\t" | |
1589 | "mov %%r12, %c[r12](%[vcpu]) \n\t" | |
1590 | "mov %%r13, %c[r13](%[vcpu]) \n\t" | |
1591 | "mov %%r14, %c[r14](%[vcpu]) \n\t" | |
1592 | "mov %%r15, %c[r15](%[vcpu]) \n\t" | |
1593 | ||
1594 | "pop %%r15; pop %%r14; pop %%r13; pop %%r12;" | |
1595 | "pop %%r11; pop %%r10; pop %%r9; pop %%r8;" | |
1596 | "pop %%rbp; pop %%rdi; pop %%rsi;" | |
1597 | "pop %%rdx; pop %%rcx; pop %%rbx; \n\t" | |
1598 | #else | |
1599 | "mov %%ebx, %c[rbx](%[vcpu]) \n\t" | |
1600 | "mov %%ecx, %c[rcx](%[vcpu]) \n\t" | |
1601 | "mov %%edx, %c[rdx](%[vcpu]) \n\t" | |
1602 | "mov %%esi, %c[rsi](%[vcpu]) \n\t" | |
1603 | "mov %%edi, %c[rdi](%[vcpu]) \n\t" | |
1604 | "mov %%ebp, %c[rbp](%[vcpu]) \n\t" | |
1605 | ||
1606 | "pop %%ebp; pop %%edi; pop %%esi;" | |
1607 | "pop %%edx; pop %%ecx; pop %%ebx; \n\t" | |
1608 | #endif | |
1609 | : | |
1610 | : [vcpu]"a"(vcpu), | |
1611 | [svm]"i"(offsetof(struct kvm_vcpu, svm)), | |
1612 | [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)), | |
1613 | [rbx]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RBX])), | |
1614 | [rcx]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RCX])), | |
1615 | [rdx]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RDX])), | |
1616 | [rsi]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RSI])), | |
1617 | [rdi]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RDI])), | |
1618 | [rbp]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RBP])) | |
05b3e0c2 | 1619 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
1620 | ,[r8 ]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R8 ])), |
1621 | [r9 ]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R9 ])), | |
1622 | [r10]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R10])), | |
1623 | [r11]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R11])), | |
1624 | [r12]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R12])), | |
1625 | [r13]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R13])), | |
1626 | [r14]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R14])), | |
1627 | [r15]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R15])) | |
1628 | #endif | |
1629 | : "cc", "memory" ); | |
1630 | ||
d9e368d6 AK |
1631 | vcpu->guest_mode = 0; |
1632 | ||
7807fa6c AL |
1633 | if (vcpu->fpu_active) { |
1634 | fx_save(vcpu->guest_fx_image); | |
1635 | fx_restore(vcpu->host_fx_image); | |
1636 | } | |
36241b8c | 1637 | |
6aa8b732 AK |
1638 | if ((vcpu->svm->vmcb->save.dr7 & 0xff)) |
1639 | load_db_regs(vcpu->svm->host_db_regs); | |
1640 | ||
1641 | vcpu->cr2 = vcpu->svm->vmcb->save.cr2; | |
1642 | ||
1643 | write_dr6(vcpu->svm->host_dr6); | |
1644 | write_dr7(vcpu->svm->host_dr7); | |
1645 | kvm_write_cr2(vcpu->svm->host_cr2); | |
1646 | ||
1647 | load_fs(fs_selector); | |
1648 | load_gs(gs_selector); | |
1649 | load_ldt(ldt_selector); | |
1650 | load_host_msrs(vcpu); | |
1651 | ||
1652 | reload_tss(vcpu); | |
1653 | ||
07031e14 IM |
1654 | /* |
1655 | * Profile KVM exit RIPs: | |
1656 | */ | |
1657 | if (unlikely(prof_on == KVM_PROFILING)) | |
1658 | profile_hit(KVM_PROFILING, | |
1659 | (void *)(unsigned long)vcpu->svm->vmcb->save.rip); | |
1660 | ||
6aa8b732 AK |
1661 | stgi(); |
1662 | ||
1663 | kvm_reput_irq(vcpu); | |
1664 | ||
1665 | vcpu->svm->next_rip = 0; | |
1666 | ||
1667 | if (vcpu->svm->vmcb->control.exit_code == SVM_EXIT_ERR) { | |
8eb7d334 AK |
1668 | kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY; |
1669 | kvm_run->fail_entry.hardware_entry_failure_reason | |
1670 | = vcpu->svm->vmcb->control.exit_code; | |
c1150d8c | 1671 | post_kvm_run_save(vcpu, kvm_run); |
6aa8b732 AK |
1672 | return 0; |
1673 | } | |
1674 | ||
e2dec939 AK |
1675 | r = handle_exit(vcpu, kvm_run); |
1676 | if (r > 0) { | |
6aa8b732 | 1677 | if (signal_pending(current)) { |
1165f5fe | 1678 | ++vcpu->stat.signal_exits; |
c1150d8c | 1679 | post_kvm_run_save(vcpu, kvm_run); |
1b19f3e6 | 1680 | kvm_run->exit_reason = KVM_EXIT_INTR; |
c1150d8c DL |
1681 | return -EINTR; |
1682 | } | |
1683 | ||
1684 | if (dm_request_for_irq_injection(vcpu, kvm_run)) { | |
1165f5fe | 1685 | ++vcpu->stat.request_irq_exits; |
c1150d8c | 1686 | post_kvm_run_save(vcpu, kvm_run); |
1b19f3e6 | 1687 | kvm_run->exit_reason = KVM_EXIT_INTR; |
6aa8b732 AK |
1688 | return -EINTR; |
1689 | } | |
1690 | kvm_resched(vcpu); | |
1691 | goto again; | |
1692 | } | |
c1150d8c | 1693 | post_kvm_run_save(vcpu, kvm_run); |
e2dec939 | 1694 | return r; |
6aa8b732 AK |
1695 | } |
1696 | ||
6aa8b732 AK |
1697 | static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root) |
1698 | { | |
1699 | vcpu->svm->vmcb->save.cr3 = root; | |
1700 | force_new_asid(vcpu); | |
7807fa6c AL |
1701 | |
1702 | if (vcpu->fpu_active) { | |
1703 | vcpu->svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR); | |
1704 | vcpu->svm->vmcb->save.cr0 |= CR0_TS_MASK; | |
1705 | vcpu->fpu_active = 0; | |
1706 | } | |
6aa8b732 AK |
1707 | } |
1708 | ||
1709 | static void svm_inject_page_fault(struct kvm_vcpu *vcpu, | |
1710 | unsigned long addr, | |
1711 | uint32_t err_code) | |
1712 | { | |
1713 | uint32_t exit_int_info = vcpu->svm->vmcb->control.exit_int_info; | |
1714 | ||
1165f5fe | 1715 | ++vcpu->stat.pf_guest; |
6aa8b732 AK |
1716 | |
1717 | if (is_page_fault(exit_int_info)) { | |
1718 | ||
1719 | vcpu->svm->vmcb->control.event_inj_err = 0; | |
1720 | vcpu->svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | | |
1721 | SVM_EVTINJ_VALID_ERR | | |
1722 | SVM_EVTINJ_TYPE_EXEPT | | |
1723 | DF_VECTOR; | |
1724 | return; | |
1725 | } | |
1726 | vcpu->cr2 = addr; | |
1727 | vcpu->svm->vmcb->save.cr2 = addr; | |
1728 | vcpu->svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | | |
1729 | SVM_EVTINJ_VALID_ERR | | |
1730 | SVM_EVTINJ_TYPE_EXEPT | | |
1731 | PF_VECTOR; | |
1732 | vcpu->svm->vmcb->control.event_inj_err = err_code; | |
1733 | } | |
1734 | ||
1735 | ||
1736 | static int is_disabled(void) | |
1737 | { | |
6031a61c JR |
1738 | u64 vm_cr; |
1739 | ||
1740 | rdmsrl(MSR_VM_CR, vm_cr); | |
1741 | if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE)) | |
1742 | return 1; | |
1743 | ||
6aa8b732 AK |
1744 | return 0; |
1745 | } | |
1746 | ||
102d8325 IM |
1747 | static void |
1748 | svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall) | |
1749 | { | |
1750 | /* | |
1751 | * Patch in the VMMCALL instruction: | |
1752 | */ | |
1753 | hypercall[0] = 0x0f; | |
1754 | hypercall[1] = 0x01; | |
1755 | hypercall[2] = 0xd9; | |
1756 | hypercall[3] = 0xc3; | |
1757 | } | |
1758 | ||
6aa8b732 AK |
1759 | static struct kvm_arch_ops svm_arch_ops = { |
1760 | .cpu_has_kvm_support = has_svm, | |
1761 | .disabled_by_bios = is_disabled, | |
1762 | .hardware_setup = svm_hardware_setup, | |
1763 | .hardware_unsetup = svm_hardware_unsetup, | |
1764 | .hardware_enable = svm_hardware_enable, | |
1765 | .hardware_disable = svm_hardware_disable, | |
1766 | ||
1767 | .vcpu_create = svm_create_vcpu, | |
1768 | .vcpu_free = svm_free_vcpu, | |
1769 | ||
1770 | .vcpu_load = svm_vcpu_load, | |
1771 | .vcpu_put = svm_vcpu_put, | |
774c47f1 | 1772 | .vcpu_decache = svm_vcpu_decache, |
6aa8b732 AK |
1773 | |
1774 | .set_guest_debug = svm_guest_debug, | |
1775 | .get_msr = svm_get_msr, | |
1776 | .set_msr = svm_set_msr, | |
1777 | .get_segment_base = svm_get_segment_base, | |
1778 | .get_segment = svm_get_segment, | |
1779 | .set_segment = svm_set_segment, | |
6aa8b732 | 1780 | .get_cs_db_l_bits = svm_get_cs_db_l_bits, |
25c4c276 | 1781 | .decache_cr4_guest_bits = svm_decache_cr4_guest_bits, |
6aa8b732 | 1782 | .set_cr0 = svm_set_cr0, |
6aa8b732 AK |
1783 | .set_cr3 = svm_set_cr3, |
1784 | .set_cr4 = svm_set_cr4, | |
1785 | .set_efer = svm_set_efer, | |
1786 | .get_idt = svm_get_idt, | |
1787 | .set_idt = svm_set_idt, | |
1788 | .get_gdt = svm_get_gdt, | |
1789 | .set_gdt = svm_set_gdt, | |
1790 | .get_dr = svm_get_dr, | |
1791 | .set_dr = svm_set_dr, | |
1792 | .cache_regs = svm_cache_regs, | |
1793 | .decache_regs = svm_decache_regs, | |
1794 | .get_rflags = svm_get_rflags, | |
1795 | .set_rflags = svm_set_rflags, | |
1796 | ||
1797 | .invlpg = svm_invlpg, | |
1798 | .tlb_flush = svm_flush_tlb, | |
1799 | .inject_page_fault = svm_inject_page_fault, | |
1800 | ||
1801 | .inject_gp = svm_inject_gp, | |
1802 | ||
1803 | .run = svm_vcpu_run, | |
1804 | .skip_emulated_instruction = skip_emulated_instruction, | |
1805 | .vcpu_setup = svm_vcpu_setup, | |
102d8325 | 1806 | .patch_hypercall = svm_patch_hypercall, |
6aa8b732 AK |
1807 | }; |
1808 | ||
1809 | static int __init svm_init(void) | |
1810 | { | |
873a7c42 | 1811 | return kvm_init_arch(&svm_arch_ops, THIS_MODULE); |
6aa8b732 AK |
1812 | } |
1813 | ||
1814 | static void __exit svm_exit(void) | |
1815 | { | |
1816 | kvm_exit_arch(); | |
1817 | } | |
1818 | ||
1819 | module_init(svm_init) | |
1820 | module_exit(svm_exit) |