Commit | Line | Data |
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6aa8b732 AK |
1 | /* |
2 | * Kernel-based Virtual Machine driver for Linux | |
3 | * | |
4 | * This module enables machines with Intel VT-x extensions to run virtual | |
5 | * machines without emulation or binary translation. | |
6 | * | |
7 | * MMU support | |
8 | * | |
9 | * Copyright (C) 2006 Qumranet, Inc. | |
10 | * | |
11 | * Authors: | |
12 | * Yaniv Kamay <yaniv@qumranet.com> | |
13 | * Avi Kivity <avi@qumranet.com> | |
14 | * | |
15 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
16 | * the COPYING file in the top-level directory. | |
17 | * | |
18 | */ | |
19 | ||
20 | /* | |
21 | * We need the mmu code to access both 32-bit and 64-bit guest ptes, | |
22 | * so the code in this file is compiled twice, once per pte size. | |
23 | */ | |
24 | ||
25 | #if PTTYPE == 64 | |
26 | #define pt_element_t u64 | |
27 | #define guest_walker guest_walker64 | |
28 | #define FNAME(name) paging##64_##name | |
29 | #define PT_BASE_ADDR_MASK PT64_BASE_ADDR_MASK | |
30 | #define PT_DIR_BASE_ADDR_MASK PT64_DIR_BASE_ADDR_MASK | |
31 | #define PT_INDEX(addr, level) PT64_INDEX(addr, level) | |
32 | #define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level) | |
33 | #define PT_LEVEL_MASK(level) PT64_LEVEL_MASK(level) | |
c7addb90 | 34 | #define PT_LEVEL_BITS PT64_LEVEL_BITS |
cea0f0e7 AK |
35 | #ifdef CONFIG_X86_64 |
36 | #define PT_MAX_FULL_LEVELS 4 | |
b3e4e63f | 37 | #define CMPXCHG cmpxchg |
cea0f0e7 | 38 | #else |
b3e4e63f | 39 | #define CMPXCHG cmpxchg64 |
cea0f0e7 AK |
40 | #define PT_MAX_FULL_LEVELS 2 |
41 | #endif | |
6aa8b732 AK |
42 | #elif PTTYPE == 32 |
43 | #define pt_element_t u32 | |
44 | #define guest_walker guest_walker32 | |
45 | #define FNAME(name) paging##32_##name | |
46 | #define PT_BASE_ADDR_MASK PT32_BASE_ADDR_MASK | |
47 | #define PT_DIR_BASE_ADDR_MASK PT32_DIR_BASE_ADDR_MASK | |
48 | #define PT_INDEX(addr, level) PT32_INDEX(addr, level) | |
49 | #define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level) | |
50 | #define PT_LEVEL_MASK(level) PT32_LEVEL_MASK(level) | |
c7addb90 | 51 | #define PT_LEVEL_BITS PT32_LEVEL_BITS |
cea0f0e7 | 52 | #define PT_MAX_FULL_LEVELS 2 |
b3e4e63f | 53 | #define CMPXCHG cmpxchg |
6aa8b732 AK |
54 | #else |
55 | #error Invalid PTTYPE value | |
56 | #endif | |
57 | ||
5fb07ddb AK |
58 | #define gpte_to_gfn FNAME(gpte_to_gfn) |
59 | #define gpte_to_gfn_pde FNAME(gpte_to_gfn_pde) | |
60 | ||
6aa8b732 AK |
61 | /* |
62 | * The guest_walker structure emulates the behavior of the hardware page | |
63 | * table walker. | |
64 | */ | |
65 | struct guest_walker { | |
66 | int level; | |
cea0f0e7 | 67 | gfn_t table_gfn[PT_MAX_FULL_LEVELS]; |
fe551881 | 68 | pt_element_t pte; |
fe135d2c AK |
69 | unsigned pt_access; |
70 | unsigned pte_access; | |
815af8d4 | 71 | gfn_t gfn; |
7993ba43 | 72 | u32 error_code; |
6aa8b732 AK |
73 | }; |
74 | ||
5fb07ddb AK |
75 | static gfn_t gpte_to_gfn(pt_element_t gpte) |
76 | { | |
77 | return (gpte & PT_BASE_ADDR_MASK) >> PAGE_SHIFT; | |
78 | } | |
79 | ||
80 | static gfn_t gpte_to_gfn_pde(pt_element_t gpte) | |
81 | { | |
82 | return (gpte & PT_DIR_BASE_ADDR_MASK) >> PAGE_SHIFT; | |
83 | } | |
84 | ||
b3e4e63f MT |
85 | static bool FNAME(cmpxchg_gpte)(struct kvm *kvm, |
86 | gfn_t table_gfn, unsigned index, | |
87 | pt_element_t orig_pte, pt_element_t new_pte) | |
88 | { | |
89 | pt_element_t ret; | |
90 | pt_element_t *table; | |
91 | struct page *page; | |
92 | ||
93 | page = gfn_to_page(kvm, table_gfn); | |
94 | table = kmap_atomic(page, KM_USER0); | |
95 | ||
96 | ret = CMPXCHG(&table[index], orig_pte, new_pte); | |
97 | ||
98 | kunmap_atomic(table, KM_USER0); | |
99 | ||
100 | kvm_release_page_dirty(page); | |
101 | ||
102 | return (ret != orig_pte); | |
103 | } | |
104 | ||
bedbe4ee AK |
105 | static unsigned FNAME(gpte_access)(struct kvm_vcpu *vcpu, pt_element_t gpte) |
106 | { | |
107 | unsigned access; | |
108 | ||
109 | access = (gpte & (PT_WRITABLE_MASK | PT_USER_MASK)) | ACC_EXEC_MASK; | |
110 | #if PTTYPE == 64 | |
111 | if (is_nx(vcpu)) | |
112 | access &= ~(gpte >> PT64_NX_SHIFT); | |
113 | #endif | |
114 | return access; | |
115 | } | |
116 | ||
ac79c978 AK |
117 | /* |
118 | * Fetch a guest pte for a guest virtual address | |
119 | */ | |
7993ba43 AK |
120 | static int FNAME(walk_addr)(struct guest_walker *walker, |
121 | struct kvm_vcpu *vcpu, gva_t addr, | |
73b1087e | 122 | int write_fault, int user_fault, int fetch_fault) |
6aa8b732 | 123 | { |
42bf3f0a | 124 | pt_element_t pte; |
cea0f0e7 | 125 | gfn_t table_gfn; |
fe135d2c | 126 | unsigned index, pt_access, pte_access; |
42bf3f0a | 127 | gpa_t pte_gpa; |
6aa8b732 | 128 | |
cea0f0e7 | 129 | pgprintk("%s: addr %lx\n", __FUNCTION__, addr); |
b3e4e63f | 130 | walk: |
6aa8b732 | 131 | walker->level = vcpu->mmu.root_level; |
42bf3f0a | 132 | pte = vcpu->cr3; |
1b0973bd AK |
133 | #if PTTYPE == 64 |
134 | if (!is_long_mode(vcpu)) { | |
42bf3f0a AK |
135 | pte = vcpu->pdptrs[(addr >> 30) & 3]; |
136 | if (!is_present_pte(pte)) | |
7993ba43 | 137 | goto not_present; |
1b0973bd AK |
138 | --walker->level; |
139 | } | |
140 | #endif | |
a9058ecd | 141 | ASSERT((!is_long_mode(vcpu) && is_pae(vcpu)) || |
f802a307 | 142 | (vcpu->cr3 & CR3_NONPAE_RESERVED_BITS) == 0); |
6aa8b732 | 143 | |
fe135d2c | 144 | pt_access = ACC_ALL; |
ac79c978 AK |
145 | |
146 | for (;;) { | |
42bf3f0a | 147 | index = PT_INDEX(addr, walker->level); |
ac79c978 | 148 | |
5fb07ddb | 149 | table_gfn = gpte_to_gfn(pte); |
1755fbcc | 150 | pte_gpa = gfn_to_gpa(table_gfn); |
ec8d4eae | 151 | pte_gpa += index * sizeof(pt_element_t); |
42bf3f0a AK |
152 | walker->table_gfn[walker->level - 1] = table_gfn; |
153 | pgprintk("%s: table_gfn[%d] %lx\n", __FUNCTION__, | |
154 | walker->level - 1, table_gfn); | |
155 | ||
ec8d4eae | 156 | kvm_read_guest(vcpu->kvm, pte_gpa, &pte, sizeof(pte)); |
42bf3f0a AK |
157 | |
158 | if (!is_present_pte(pte)) | |
7993ba43 AK |
159 | goto not_present; |
160 | ||
42bf3f0a | 161 | if (write_fault && !is_writeble_pte(pte)) |
7993ba43 AK |
162 | if (user_fault || is_write_protection(vcpu)) |
163 | goto access_error; | |
164 | ||
42bf3f0a | 165 | if (user_fault && !(pte & PT_USER_MASK)) |
7993ba43 AK |
166 | goto access_error; |
167 | ||
73b1087e | 168 | #if PTTYPE == 64 |
42bf3f0a | 169 | if (fetch_fault && is_nx(vcpu) && (pte & PT64_NX_MASK)) |
73b1087e AK |
170 | goto access_error; |
171 | #endif | |
172 | ||
42bf3f0a | 173 | if (!(pte & PT_ACCESSED_MASK)) { |
bf3f8e86 | 174 | mark_page_dirty(vcpu->kvm, table_gfn); |
b3e4e63f MT |
175 | if (FNAME(cmpxchg_gpte)(vcpu->kvm, table_gfn, |
176 | index, pte, pte|PT_ACCESSED_MASK)) | |
177 | goto walk; | |
42bf3f0a | 178 | pte |= PT_ACCESSED_MASK; |
bf3f8e86 | 179 | } |
815af8d4 | 180 | |
bedbe4ee | 181 | pte_access = pt_access & FNAME(gpte_access)(vcpu, pte); |
fe135d2c | 182 | |
815af8d4 | 183 | if (walker->level == PT_PAGE_TABLE_LEVEL) { |
5fb07ddb | 184 | walker->gfn = gpte_to_gfn(pte); |
815af8d4 AK |
185 | break; |
186 | } | |
187 | ||
188 | if (walker->level == PT_DIRECTORY_LEVEL | |
42bf3f0a | 189 | && (pte & PT_PAGE_SIZE_MASK) |
815af8d4 | 190 | && (PTTYPE == 64 || is_pse(vcpu))) { |
5fb07ddb | 191 | walker->gfn = gpte_to_gfn_pde(pte); |
815af8d4 | 192 | walker->gfn += PT_INDEX(addr, PT_PAGE_TABLE_LEVEL); |
da928521 AK |
193 | if (PTTYPE == 32 && is_cpuid_PSE36()) |
194 | walker->gfn += pse36_gfn_delta(pte); | |
ac79c978 | 195 | break; |
815af8d4 | 196 | } |
ac79c978 | 197 | |
fe135d2c | 198 | pt_access = pte_access; |
ac79c978 AK |
199 | --walker->level; |
200 | } | |
42bf3f0a AK |
201 | |
202 | if (write_fault && !is_dirty_pte(pte)) { | |
b3e4e63f MT |
203 | bool ret; |
204 | ||
42bf3f0a | 205 | mark_page_dirty(vcpu->kvm, table_gfn); |
b3e4e63f MT |
206 | ret = FNAME(cmpxchg_gpte)(vcpu->kvm, table_gfn, index, pte, |
207 | pte|PT_DIRTY_MASK); | |
208 | if (ret) | |
209 | goto walk; | |
42bf3f0a | 210 | pte |= PT_DIRTY_MASK; |
42bf3f0a AK |
211 | kvm_mmu_pte_write(vcpu, pte_gpa, (u8 *)&pte, sizeof(pte)); |
212 | } | |
213 | ||
214 | walker->pte = pte; | |
fe135d2c AK |
215 | walker->pt_access = pt_access; |
216 | walker->pte_access = pte_access; | |
217 | pgprintk("%s: pte %llx pte_access %x pt_access %x\n", | |
218 | __FUNCTION__, (u64)pte, pt_access, pte_access); | |
7993ba43 AK |
219 | return 1; |
220 | ||
221 | not_present: | |
222 | walker->error_code = 0; | |
223 | goto err; | |
224 | ||
225 | access_error: | |
226 | walker->error_code = PFERR_PRESENT_MASK; | |
227 | ||
228 | err: | |
229 | if (write_fault) | |
230 | walker->error_code |= PFERR_WRITE_MASK; | |
231 | if (user_fault) | |
232 | walker->error_code |= PFERR_USER_MASK; | |
73b1087e AK |
233 | if (fetch_fault) |
234 | walker->error_code |= PFERR_FETCH_MASK; | |
fe551881 | 235 | return 0; |
6aa8b732 AK |
236 | } |
237 | ||
230c9a8f | 238 | static void FNAME(set_pte)(struct kvm_vcpu *vcpu, pt_element_t gpte, |
fe135d2c AK |
239 | u64 *shadow_pte, unsigned pt_access, |
240 | unsigned pte_access, | |
230c9a8f AK |
241 | int user_fault, int write_fault, |
242 | int *ptwrite, struct guest_walker *walker, | |
243 | gfn_t gfn) | |
e60d75ea | 244 | { |
fe551881 | 245 | int dirty = gpte & PT_DIRTY_MASK; |
c7addb90 AK |
246 | u64 spte; |
247 | int was_rmapped = is_rmap_pte(*shadow_pte); | |
b238f7bc | 248 | struct page *page; |
97a0a01e | 249 | |
fe135d2c | 250 | pgprintk("%s: spte %llx gpte %llx access %x write_fault %d" |
97a0a01e | 251 | " user_fault %d gfn %lx\n", |
fe135d2c | 252 | __FUNCTION__, *shadow_pte, (u64)gpte, pt_access, |
97a0a01e AK |
253 | write_fault, user_fault, gfn); |
254 | ||
12b7d28f AK |
255 | /* |
256 | * We don't set the accessed bit, since we sometimes want to see | |
257 | * whether the guest actually used the pte (in order to detect | |
258 | * demand paging). | |
259 | */ | |
260 | spte = PT_PRESENT_MASK | PT_DIRTY_MASK; | |
fe551881 | 261 | spte |= gpte & PT64_NX_MASK; |
e60d75ea | 262 | if (!dirty) |
fe135d2c | 263 | pte_access &= ~ACC_WRITE_MASK; |
8d87a03a AK |
264 | if (!(pte_access & ACC_EXEC_MASK)) |
265 | spte |= PT64_NX_MASK; | |
e60d75ea | 266 | |
4e542370 | 267 | page = gfn_to_page(vcpu->kvm, gfn); |
b238f7bc | 268 | |
0d551bb6 | 269 | spte |= PT_PRESENT_MASK; |
fe135d2c | 270 | if (pte_access & ACC_USER_MASK) |
0d551bb6 | 271 | spte |= PT_USER_MASK; |
e60d75ea | 272 | |
4e542370 | 273 | if (is_error_page(page)) { |
c7addb90 AK |
274 | set_shadow_pte(shadow_pte, |
275 | shadow_trap_nonpresent_pte | PT_SHADOW_IO_MARK); | |
b238f7bc | 276 | kvm_release_page_clean(page); |
e60d75ea AK |
277 | return; |
278 | } | |
279 | ||
4e542370 | 280 | spte |= page_to_phys(page); |
e60d75ea | 281 | |
fe135d2c | 282 | if ((pte_access & ACC_WRITE_MASK) |
97a0a01e | 283 | || (write_fault && !is_write_protection(vcpu) && !user_fault)) { |
e60d75ea AK |
284 | struct kvm_mmu_page *shadow; |
285 | ||
0d551bb6 | 286 | spte |= PT_WRITABLE_MASK; |
97a0a01e | 287 | if (user_fault) { |
f67a46f4 | 288 | mmu_unshadow(vcpu->kvm, gfn); |
97a0a01e AK |
289 | goto unshadowed; |
290 | } | |
291 | ||
f67a46f4 | 292 | shadow = kvm_mmu_lookup_page(vcpu->kvm, gfn); |
e60d75ea AK |
293 | if (shadow) { |
294 | pgprintk("%s: found shadow page for %lx, marking ro\n", | |
295 | __FUNCTION__, gfn); | |
fe135d2c | 296 | pte_access &= ~ACC_WRITE_MASK; |
0d551bb6 AK |
297 | if (is_writeble_pte(spte)) { |
298 | spte &= ~PT_WRITABLE_MASK; | |
cbdd1bea | 299 | kvm_x86_ops->tlb_flush(vcpu); |
e60d75ea | 300 | } |
97a0a01e AK |
301 | if (write_fault) |
302 | *ptwrite = 1; | |
e60d75ea AK |
303 | } |
304 | } | |
305 | ||
97a0a01e AK |
306 | unshadowed: |
307 | ||
fe135d2c | 308 | if (pte_access & ACC_WRITE_MASK) |
4e542370 | 309 | mark_page_dirty(vcpu->kvm, gfn); |
e60d75ea | 310 | |
c7addb90 | 311 | pgprintk("%s: setting spte %llx\n", __FUNCTION__, spte); |
e663ee64 | 312 | set_shadow_pte(shadow_pte, spte); |
38c335f1 | 313 | page_header_update_slot(vcpu->kvm, shadow_pte, gfn); |
8a7ae055 | 314 | if (!was_rmapped) { |
4e542370 | 315 | rmap_add(vcpu, shadow_pte, gfn); |
b238f7bc | 316 | if (!is_rmap_pte(*shadow_pte)) |
b4231d61 | 317 | kvm_release_page_clean(page); |
8a7ae055 IE |
318 | } |
319 | else | |
b238f7bc | 320 | kvm_release_page_clean(page); |
12b7d28f AK |
321 | if (!ptwrite || !*ptwrite) |
322 | vcpu->last_pte_updated = shadow_pte; | |
e60d75ea AK |
323 | } |
324 | ||
0028425f | 325 | static void FNAME(update_pte)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *page, |
c7addb90 AK |
326 | u64 *spte, const void *pte, int bytes, |
327 | int offset_in_pte) | |
0028425f AK |
328 | { |
329 | pt_element_t gpte; | |
330 | ||
0028425f | 331 | gpte = *(const pt_element_t *)pte; |
c7addb90 AK |
332 | if (~gpte & (PT_PRESENT_MASK | PT_ACCESSED_MASK)) { |
333 | if (!offset_in_pte && !is_present_pte(gpte)) | |
334 | set_shadow_pte(spte, shadow_notrap_nonpresent_pte); | |
335 | return; | |
336 | } | |
337 | if (bytes < sizeof(pt_element_t)) | |
0028425f AK |
338 | return; |
339 | pgprintk("%s: gpte %llx spte %p\n", __FUNCTION__, (u64)gpte, spte); | |
fe135d2c AK |
340 | FNAME(set_pte)(vcpu, gpte, spte, ACC_ALL, ACC_ALL, |
341 | 0, 0, NULL, NULL, gpte_to_gfn(gpte)); | |
0028425f AK |
342 | } |
343 | ||
6aa8b732 AK |
344 | /* |
345 | * Fetch a shadow pte for a specific level in the paging hierarchy. | |
346 | */ | |
347 | static u64 *FNAME(fetch)(struct kvm_vcpu *vcpu, gva_t addr, | |
97a0a01e AK |
348 | struct guest_walker *walker, |
349 | int user_fault, int write_fault, int *ptwrite) | |
6aa8b732 AK |
350 | { |
351 | hpa_t shadow_addr; | |
352 | int level; | |
ef0197e8 | 353 | u64 *shadow_ent; |
fe135d2c | 354 | unsigned access = walker->pt_access; |
ac79c978 | 355 | |
fe551881 | 356 | if (!is_present_pte(walker->pte)) |
ac79c978 | 357 | return NULL; |
6aa8b732 AK |
358 | |
359 | shadow_addr = vcpu->mmu.root_hpa; | |
360 | level = vcpu->mmu.shadow_root_level; | |
aef3d3fe AK |
361 | if (level == PT32E_ROOT_LEVEL) { |
362 | shadow_addr = vcpu->mmu.pae_root[(addr >> 30) & 3]; | |
363 | shadow_addr &= PT64_BASE_ADDR_MASK; | |
364 | --level; | |
365 | } | |
6aa8b732 AK |
366 | |
367 | for (; ; level--) { | |
368 | u32 index = SHADOW_PT_INDEX(addr, level); | |
25c0de2c | 369 | struct kvm_mmu_page *shadow_page; |
8c7bb723 | 370 | u64 shadow_pte; |
cea0f0e7 AK |
371 | int metaphysical; |
372 | gfn_t table_gfn; | |
6aa8b732 | 373 | |
ef0197e8 | 374 | shadow_ent = ((u64 *)__va(shadow_addr)) + index; |
c7addb90 | 375 | if (is_shadow_present_pte(*shadow_ent)) { |
6aa8b732 | 376 | if (level == PT_PAGE_TABLE_LEVEL) |
97a0a01e | 377 | break; |
6aa8b732 | 378 | shadow_addr = *shadow_ent & PT64_BASE_ADDR_MASK; |
6aa8b732 AK |
379 | continue; |
380 | } | |
381 | ||
ef0197e8 AK |
382 | if (level == PT_PAGE_TABLE_LEVEL) |
383 | break; | |
6aa8b732 | 384 | |
cea0f0e7 AK |
385 | if (level - 1 == PT_PAGE_TABLE_LEVEL |
386 | && walker->level == PT_DIRECTORY_LEVEL) { | |
387 | metaphysical = 1; | |
cc70e737 | 388 | if (!is_dirty_pte(walker->pte)) |
fe135d2c | 389 | access &= ~ACC_WRITE_MASK; |
5fb07ddb | 390 | table_gfn = gpte_to_gfn(walker->pte); |
cea0f0e7 AK |
391 | } else { |
392 | metaphysical = 0; | |
393 | table_gfn = walker->table_gfn[level - 2]; | |
394 | } | |
395 | shadow_page = kvm_mmu_get_page(vcpu, table_gfn, addr, level-1, | |
fe135d2c | 396 | metaphysical, access, |
d28c6cfb | 397 | shadow_ent); |
47ad8e68 | 398 | shadow_addr = __pa(shadow_page->spt); |
aef3d3fe AK |
399 | shadow_pte = shadow_addr | PT_PRESENT_MASK | PT_ACCESSED_MASK |
400 | | PT_WRITABLE_MASK | PT_USER_MASK; | |
8c7bb723 | 401 | *shadow_ent = shadow_pte; |
6aa8b732 | 402 | } |
ef0197e8 | 403 | |
050e6499 | 404 | FNAME(set_pte)(vcpu, walker->pte, shadow_ent, |
fe135d2c AK |
405 | access, walker->pte_access & access, |
406 | user_fault, write_fault, | |
050e6499 AK |
407 | ptwrite, walker, walker->gfn); |
408 | ||
ef0197e8 | 409 | return shadow_ent; |
6aa8b732 AK |
410 | } |
411 | ||
6aa8b732 AK |
412 | /* |
413 | * Page fault handler. There are several causes for a page fault: | |
414 | * - there is no shadow pte for the guest pte | |
415 | * - write access through a shadow pte marked read only so that we can set | |
416 | * the dirty bit | |
417 | * - write access to a shadow pte marked read only so we can update the page | |
418 | * dirty bitmap, when userspace requests it | |
419 | * - mmio access; in this case we will never install a present shadow pte | |
420 | * - normal guest page fault due to the guest pte marked not present, not | |
421 | * writable, or not executable | |
422 | * | |
e2dec939 AK |
423 | * Returns: 1 if we need to emulate the instruction, 0 otherwise, or |
424 | * a negative value on error. | |
6aa8b732 AK |
425 | */ |
426 | static int FNAME(page_fault)(struct kvm_vcpu *vcpu, gva_t addr, | |
427 | u32 error_code) | |
428 | { | |
429 | int write_fault = error_code & PFERR_WRITE_MASK; | |
6aa8b732 | 430 | int user_fault = error_code & PFERR_USER_MASK; |
73b1087e | 431 | int fetch_fault = error_code & PFERR_FETCH_MASK; |
6aa8b732 AK |
432 | struct guest_walker walker; |
433 | u64 *shadow_pte; | |
cea0f0e7 | 434 | int write_pt = 0; |
e2dec939 | 435 | int r; |
6aa8b732 | 436 | |
cea0f0e7 | 437 | pgprintk("%s: addr %lx err %x\n", __FUNCTION__, addr, error_code); |
37a7d8b0 | 438 | kvm_mmu_audit(vcpu, "pre page fault"); |
714b93da | 439 | |
e2dec939 AK |
440 | r = mmu_topup_memory_caches(vcpu); |
441 | if (r) | |
442 | return r; | |
714b93da | 443 | |
6aa8b732 AK |
444 | /* |
445 | * Look up the shadow pte for the faulting address. | |
446 | */ | |
73b1087e AK |
447 | r = FNAME(walk_addr)(&walker, vcpu, addr, write_fault, user_fault, |
448 | fetch_fault); | |
6aa8b732 AK |
449 | |
450 | /* | |
451 | * The page is not mapped by the guest. Let the guest handle it. | |
452 | */ | |
7993ba43 AK |
453 | if (!r) { |
454 | pgprintk("%s: guest page fault\n", __FUNCTION__); | |
455 | inject_page_fault(vcpu, addr, walker.error_code); | |
a25f7e1f | 456 | vcpu->last_pt_write_count = 0; /* reset fork detector */ |
6aa8b732 AK |
457 | return 0; |
458 | } | |
459 | ||
97a0a01e AK |
460 | shadow_pte = FNAME(fetch)(vcpu, addr, &walker, user_fault, write_fault, |
461 | &write_pt); | |
462 | pgprintk("%s: shadow pte %p %llx ptwrite %d\n", __FUNCTION__, | |
463 | shadow_pte, *shadow_pte, write_pt); | |
cea0f0e7 | 464 | |
a25f7e1f AK |
465 | if (!write_pt) |
466 | vcpu->last_pt_write_count = 0; /* reset fork detector */ | |
467 | ||
6aa8b732 AK |
468 | /* |
469 | * mmio: emulate if accessible, otherwise its a guest fault. | |
470 | */ | |
d27d4aca | 471 | if (is_io_pte(*shadow_pte)) |
7993ba43 | 472 | return 1; |
6aa8b732 | 473 | |
1165f5fe | 474 | ++vcpu->stat.pf_fixed; |
37a7d8b0 | 475 | kvm_mmu_audit(vcpu, "post page fault (fixed)"); |
6aa8b732 | 476 | |
cea0f0e7 | 477 | return write_pt; |
6aa8b732 AK |
478 | } |
479 | ||
480 | static gpa_t FNAME(gva_to_gpa)(struct kvm_vcpu *vcpu, gva_t vaddr) | |
481 | { | |
482 | struct guest_walker walker; | |
e119d117 AK |
483 | gpa_t gpa = UNMAPPED_GVA; |
484 | int r; | |
6aa8b732 | 485 | |
e119d117 | 486 | r = FNAME(walk_addr)(&walker, vcpu, vaddr, 0, 0, 0); |
6aa8b732 | 487 | |
e119d117 | 488 | if (r) { |
1755fbcc | 489 | gpa = gfn_to_gpa(walker.gfn); |
e119d117 | 490 | gpa |= vaddr & ~PAGE_MASK; |
6aa8b732 AK |
491 | } |
492 | ||
493 | return gpa; | |
494 | } | |
495 | ||
c7addb90 AK |
496 | static void FNAME(prefetch_page)(struct kvm_vcpu *vcpu, |
497 | struct kvm_mmu_page *sp) | |
498 | { | |
e5a4c8ca | 499 | int i, offset = 0; |
c7addb90 | 500 | pt_element_t *gpt; |
8a7ae055 | 501 | struct page *page; |
c7addb90 | 502 | |
e5a4c8ca AK |
503 | if (sp->role.metaphysical |
504 | || (PTTYPE == 32 && sp->role.level > PT_PAGE_TABLE_LEVEL)) { | |
c7addb90 AK |
505 | nonpaging_prefetch_page(vcpu, sp); |
506 | return; | |
507 | } | |
508 | ||
e5a4c8ca AK |
509 | if (PTTYPE == 32) |
510 | offset = sp->role.quadrant << PT64_LEVEL_BITS; | |
8a7ae055 IE |
511 | page = gfn_to_page(vcpu->kvm, sp->gfn); |
512 | gpt = kmap_atomic(page, KM_USER0); | |
c7addb90 | 513 | for (i = 0; i < PT64_ENT_PER_PAGE; ++i) |
e5a4c8ca | 514 | if (is_present_pte(gpt[offset + i])) |
c7addb90 AK |
515 | sp->spt[i] = shadow_trap_nonpresent_pte; |
516 | else | |
517 | sp->spt[i] = shadow_notrap_nonpresent_pte; | |
518 | kunmap_atomic(gpt, KM_USER0); | |
b4231d61 | 519 | kvm_release_page_clean(page); |
c7addb90 AK |
520 | } |
521 | ||
6aa8b732 AK |
522 | #undef pt_element_t |
523 | #undef guest_walker | |
524 | #undef FNAME | |
525 | #undef PT_BASE_ADDR_MASK | |
526 | #undef PT_INDEX | |
527 | #undef SHADOW_PT_INDEX | |
528 | #undef PT_LEVEL_MASK | |
6aa8b732 | 529 | #undef PT_DIR_BASE_ADDR_MASK |
c7addb90 | 530 | #undef PT_LEVEL_BITS |
cea0f0e7 | 531 | #undef PT_MAX_FULL_LEVELS |
5fb07ddb AK |
532 | #undef gpte_to_gfn |
533 | #undef gpte_to_gfn_pde | |
b3e4e63f | 534 | #undef CMPXCHG |