[linux-block.git] / drivers / kvm / paging_tmpl.h

/*
 * Kernel-based Virtual Machine driver for Linux
 *
 * This module enables machines with Intel VT-x extensions to run virtual
 * machines without emulation or binary translation.
 *
 * MMU support
 *
 * Copyright (C) 2006 Qumranet, Inc.
 *
 * Authors:
 *   Yaniv Kamay  <yaniv@qumranet.com>
 *   Avi Kivity   <avi@qumranet.com>
 *
 * This work is licensed under the terms of the GNU GPL, version 2.  See
 * the COPYING file in the top-level directory.
 *
 */

/*
 * We need the mmu code to access both 32-bit and 64-bit guest ptes,
 * so the code in this file is compiled twice, once per pte size.
 */

#if PTTYPE == 64
	#define pt_element_t u64
	#define guest_walker guest_walker64
	#define FNAME(name) paging##64_##name
	#define PT_BASE_ADDR_MASK PT64_BASE_ADDR_MASK
	#define PT_DIR_BASE_ADDR_MASK PT64_DIR_BASE_ADDR_MASK
	#define PT_INDEX(addr, level) PT64_INDEX(addr, level)
	#define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level)
	#define PT_LEVEL_MASK(level) PT64_LEVEL_MASK(level)
	#ifdef CONFIG_X86_64
	#define PT_MAX_FULL_LEVELS 4
	#else
	#define PT_MAX_FULL_LEVELS 2
	#endif
#elif PTTYPE == 32
	#define pt_element_t u32
	#define guest_walker guest_walker32
	#define FNAME(name) paging##32_##name
	#define PT_BASE_ADDR_MASK PT32_BASE_ADDR_MASK
	#define PT_DIR_BASE_ADDR_MASK PT32_DIR_BASE_ADDR_MASK
	#define PT_INDEX(addr, level) PT32_INDEX(addr, level)
	#define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level)
	#define PT_LEVEL_MASK(level) PT32_LEVEL_MASK(level)
	#define PT_MAX_FULL_LEVELS 2
#else
	#error Invalid PTTYPE value
#endif

/*
 * The guest_walker structure emulates the behavior of the hardware page
 * table walker.
 */
struct guest_walker {
	int level;
	gfn_t table_gfn[PT_MAX_FULL_LEVELS];
	pt_element_t *table;
	pt_element_t *ptep;
	pt_element_t inherited_ar;
	gfn_t gfn;
	u32 error_code;
};

/*
 * Fetch a guest pte for a guest virtual address
 */
static int FNAME(walk_addr)(struct guest_walker *walker,
			    struct kvm_vcpu *vcpu, gva_t addr,
			    int write_fault, int user_fault, int fetch_fault)
{
	hpa_t hpa;
	struct kvm_memory_slot *slot;
	pt_element_t *ptep;
	pt_element_t root;
	gfn_t table_gfn;

	pgprintk("%s: addr %lx\n", __FUNCTION__, addr);
	walker->level = vcpu->mmu.root_level;
	walker->table = NULL;
	root = vcpu->cr3;
#if PTTYPE == 64
	if (!is_long_mode(vcpu)) {
		walker->ptep = &vcpu->pdptrs[(addr >> 30) & 3];
		root = *walker->ptep;
		if (!(root & PT_PRESENT_MASK))
			goto not_present;
		--walker->level;
	}
#endif
	table_gfn = (root & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT;
	walker->table_gfn[walker->level - 1] = table_gfn;
	pgprintk("%s: table_gfn[%d] %lx\n", __FUNCTION__,
		 walker->level - 1, table_gfn);
	slot = gfn_to_memslot(vcpu->kvm, table_gfn);
	hpa = safe_gpa_to_hpa(vcpu, root & PT64_BASE_ADDR_MASK);
	walker->table = kmap_atomic(pfn_to_page(hpa >> PAGE_SHIFT), KM_USER0);

	ASSERT((!is_long_mode(vcpu) && is_pae(vcpu)) ||
	       (vcpu->cr3 & CR3_NONPAE_RESERVED_BITS) == 0);

	walker->inherited_ar = PT_USER_MASK | PT_WRITABLE_MASK;

	for (;;) {
		int index = PT_INDEX(addr, walker->level);
		hpa_t paddr;

		ptep = &walker->table[index];
		ASSERT(((unsigned long)walker->table & PAGE_MASK) ==
		       ((unsigned long)ptep & PAGE_MASK));

		if (!is_present_pte(*ptep))
			goto not_present;

		if (write_fault && !is_writeble_pte(*ptep))
			if (user_fault || is_write_protection(vcpu))
				goto access_error;

		if (user_fault && !(*ptep & PT_USER_MASK))
			goto access_error;

#if PTTYPE == 64
		if (fetch_fault && is_nx(vcpu) && (*ptep & PT64_NX_MASK))
			goto access_error;
#endif

		if (!(*ptep & PT_ACCESSED_MASK)) {
			mark_page_dirty(vcpu->kvm, table_gfn);
			*ptep |= PT_ACCESSED_MASK;
		}

		if (walker->level == PT_PAGE_TABLE_LEVEL) {
			walker->gfn = (*ptep & PT_BASE_ADDR_MASK)
				>> PAGE_SHIFT;
			break;
		}

		if (walker->level == PT_DIRECTORY_LEVEL
		    && (*ptep & PT_PAGE_SIZE_MASK)
		    && (PTTYPE == 64 || is_pse(vcpu))) {
			walker->gfn = (*ptep & PT_DIR_BASE_ADDR_MASK)
				>> PAGE_SHIFT;
			walker->gfn += PT_INDEX(addr, PT_PAGE_TABLE_LEVEL);
			break;
		}

		walker->inherited_ar &= walker->table[index];
		table_gfn = (*ptep & PT_BASE_ADDR_MASK) >> PAGE_SHIFT;
		paddr = safe_gpa_to_hpa(vcpu, *ptep & PT_BASE_ADDR_MASK);
		kunmap_atomic(walker->table, KM_USER0);
		walker->table = kmap_atomic(pfn_to_page(paddr >> PAGE_SHIFT),
					    KM_USER0);
		--walker->level;
		walker->table_gfn[walker->level - 1 ] = table_gfn;
		pgprintk("%s: table_gfn[%d] %lx\n", __FUNCTION__,
			 walker->level - 1, table_gfn);
	}
	walker->ptep = ptep;
	pgprintk("%s: pte %llx\n", __FUNCTION__, (u64)*ptep);
	return 1;

not_present:
	walker->error_code = 0;
	goto err;

access_error:
	walker->error_code = PFERR_PRESENT_MASK;

err:
	if (write_fault)
		walker->error_code |= PFERR_WRITE_MASK;
	if (user_fault)
		walker->error_code |= PFERR_USER_MASK;
	if (fetch_fault)
		walker->error_code |= PFERR_FETCH_MASK;
	return 0;
}

static void FNAME(release_walker)(struct guest_walker *walker)
{
	if (walker->table)
		kunmap_atomic(walker->table, KM_USER0);
}

static void FNAME(mark_pagetable_dirty)(struct kvm *kvm,
					struct guest_walker *walker)
{
	mark_page_dirty(kvm, walker->table_gfn[walker->level - 1]);
}

static void FNAME(set_pte_common)(struct kvm_vcpu *vcpu,
				  u64 *shadow_pte,
				  gpa_t gaddr,
				  pt_element_t *gpte,
				  u64 access_bits,
				  int user_fault,
				  int write_fault,
				  int *ptwrite,
				  struct guest_walker *walker,
				  gfn_t gfn)
{
	hpa_t paddr;
	int dirty = *gpte & PT_DIRTY_MASK;
	u64 spte = *shadow_pte;
	int was_rmapped = is_rmap_pte(spte);

	pgprintk("%s: spte %llx gpte %llx access %llx write_fault %d"
		 " user_fault %d gfn %lx\n",
		 __FUNCTION__, spte, (u64)*gpte, access_bits,
		 write_fault, user_fault, gfn);

	if (write_fault && !dirty) {
		*gpte |= PT_DIRTY_MASK;
		dirty = 1;
		FNAME(mark_pagetable_dirty)(vcpu->kvm, walker);
	}

	spte |= PT_PRESENT_MASK | PT_ACCESSED_MASK | PT_DIRTY_MASK;
	spte |= *gpte & PT64_NX_MASK;
	if (!dirty)
		access_bits &= ~PT_WRITABLE_MASK;

	paddr = gpa_to_hpa(vcpu, gaddr & PT64_BASE_ADDR_MASK);

	spte |= PT_PRESENT_MASK;
	if (access_bits & PT_USER_MASK)
		spte |= PT_USER_MASK;

	if (is_error_hpa(paddr)) {
		spte |= gaddr;
		spte |= PT_SHADOW_IO_MARK;
		spte &= ~PT_PRESENT_MASK;
		set_shadow_pte(shadow_pte, spte);
		return;
	}

	spte |= paddr;

	if ((access_bits & PT_WRITABLE_MASK)
	    || (write_fault && !is_write_protection(vcpu) && !user_fault)) {
		struct kvm_mmu_page *shadow;

		spte |= PT_WRITABLE_MASK;
		if (user_fault) {
			mmu_unshadow(vcpu, gfn);
			goto unshadowed;
		}

		shadow = kvm_mmu_lookup_page(vcpu, gfn);
		if (shadow) {
			pgprintk("%s: found shadow page for %lx, marking ro\n",
				 __FUNCTION__, gfn);
			access_bits &= ~PT_WRITABLE_MASK;
			if (is_writeble_pte(spte)) {
				spte &= ~PT_WRITABLE_MASK;
				kvm_arch_ops->tlb_flush(vcpu);
			}
			if (write_fault)
				*ptwrite = 1;
		}
	}

unshadowed:

	if (access_bits & PT_WRITABLE_MASK)
		mark_page_dirty(vcpu->kvm, gaddr >> PAGE_SHIFT);

	set_shadow_pte(shadow_pte, spte);
	page_header_update_slot(vcpu->kvm, shadow_pte, gaddr);
	if (!was_rmapped)
		rmap_add(vcpu, shadow_pte);
}

static void FNAME(set_pte)(struct kvm_vcpu *vcpu, pt_element_t *gpte,
			   u64 *shadow_pte, u64 access_bits,
			   int user_fault, int write_fault, int *ptwrite,
			   struct guest_walker *walker, gfn_t gfn)
{
	access_bits &= *gpte;
	FNAME(set_pte_common)(vcpu, shadow_pte, *gpte & PT_BASE_ADDR_MASK,
			      gpte, access_bits, user_fault, write_fault,
			      ptwrite, walker, gfn);
}

static void FNAME(update_pte)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *page,
			      u64 *spte, const void *pte, int bytes)
{
	pt_element_t gpte;

	if (bytes < sizeof(pt_element_t))
		return;
	gpte = *(const pt_element_t *)pte;
	if (~gpte & (PT_PRESENT_MASK | PT_ACCESSED_MASK))
		return;
	pgprintk("%s: gpte %llx spte %p\n", __FUNCTION__, (u64)gpte, spte);
	FNAME(set_pte)(vcpu, &gpte, spte, PT_USER_MASK | PT_WRITABLE_MASK, 0,
		       0, NULL, NULL,
		       (gpte & PT_BASE_ADDR_MASK) >> PAGE_SHIFT);
}

static void FNAME(set_pde)(struct kvm_vcpu *vcpu, pt_element_t *gpde,
			   u64 *shadow_pte, u64 access_bits,
			   int user_fault, int write_fault, int *ptwrite,
			   struct guest_walker *walker, gfn_t gfn)
{
	gpa_t gaddr;

	access_bits &= *gpde;
	gaddr = (gpa_t)gfn << PAGE_SHIFT;
	if (PTTYPE == 32 && is_cpuid_PSE36())
		gaddr |= (*gpde & PT32_DIR_PSE36_MASK) <<
			(32 - PT32_DIR_PSE36_SHIFT);
	FNAME(set_pte_common)(vcpu, shadow_pte, gaddr,
			      gpde, access_bits, user_fault, write_fault,
			      ptwrite, walker, gfn);
}

/*
 * Fetch a shadow pte for a specific level in the paging hierarchy.
 */
static u64 *FNAME(fetch)(struct kvm_vcpu *vcpu, gva_t addr,
			 struct guest_walker *walker,
			 int user_fault, int write_fault, int *ptwrite)
{
	hpa_t shadow_addr;
	int level;
	u64 *shadow_ent;
	u64 *prev_shadow_ent = NULL;
	pt_element_t *guest_ent = walker->ptep;

	if (!is_present_pte(*guest_ent))
		return NULL;

	shadow_addr = vcpu->mmu.root_hpa;
	level = vcpu->mmu.shadow_root_level;
	if (level == PT32E_ROOT_LEVEL) {
		shadow_addr = vcpu->mmu.pae_root[(addr >> 30) & 3];
		shadow_addr &= PT64_BASE_ADDR_MASK;
		--level;
	}

	for (; ; level--) {
		u32 index = SHADOW_PT_INDEX(addr, level);
		struct kvm_mmu_page *shadow_page;
		u64 shadow_pte;
		int metaphysical;
		gfn_t table_gfn;
		unsigned hugepage_access = 0;

		shadow_ent = ((u64 *)__va(shadow_addr)) + index;
		if (is_present_pte(*shadow_ent) || is_io_pte(*shadow_ent)) {
			if (level == PT_PAGE_TABLE_LEVEL)
				break;
			shadow_addr = *shadow_ent & PT64_BASE_ADDR_MASK;
			prev_shadow_ent = shadow_ent;
			continue;
		}

		if (level == PT_PAGE_TABLE_LEVEL)
			break;

		if (level - 1 == PT_PAGE_TABLE_LEVEL
		    && walker->level == PT_DIRECTORY_LEVEL) {
			metaphysical = 1;
			hugepage_access = *guest_ent;
			hugepage_access &= PT_USER_MASK | PT_WRITABLE_MASK;
			if (*guest_ent & PT64_NX_MASK)
				hugepage_access |= (1 << 2);
			hugepage_access >>= PT_WRITABLE_SHIFT;
			table_gfn = (*guest_ent & PT_BASE_ADDR_MASK)
				>> PAGE_SHIFT;
		} else {
			metaphysical = 0;
			table_gfn = walker->table_gfn[level - 2];
		}
		shadow_page = kvm_mmu_get_page(vcpu, table_gfn, addr, level-1,
					       metaphysical, hugepage_access,
					       shadow_ent);
		shadow_addr = __pa(shadow_page->spt);
		shadow_pte = shadow_addr | PT_PRESENT_MASK | PT_ACCESSED_MASK
			| PT_WRITABLE_MASK | PT_USER_MASK;
		*shadow_ent = shadow_pte;
		prev_shadow_ent = shadow_ent;
	}

	if (walker->level == PT_DIRECTORY_LEVEL) {
		FNAME(set_pde)(vcpu, guest_ent, shadow_ent,
			       walker->inherited_ar, user_fault, write_fault,
			       ptwrite, walker, walker->gfn);
	} else {
		ASSERT(walker->level == PT_PAGE_TABLE_LEVEL);
		FNAME(set_pte)(vcpu, guest_ent, shadow_ent,
			       walker->inherited_ar, user_fault, write_fault,
			       ptwrite, walker, walker->gfn);
	}
	return shadow_ent;
}

/*
 * Page fault handler.  There are several causes for a page fault:
 *   - there is no shadow pte for the guest pte
 *   - write access through a shadow pte marked read only so that we can set
 *     the dirty bit
 *   - write access to a shadow pte marked read only so we can update the page
 *     dirty bitmap, when userspace requests it
 *   - mmio access; in this case we will never install a present shadow pte
 *   - normal guest page fault due to the guest pte marked not present, not
 *     writable, or not executable
 *
 *  Returns: 1 if we need to emulate the instruction, 0 otherwise, or
 *           a negative value on error.
 */
static int FNAME(page_fault)(struct kvm_vcpu *vcpu, gva_t addr,
			       u32 error_code)
{
	int write_fault = error_code & PFERR_WRITE_MASK;
	int user_fault = error_code & PFERR_USER_MASK;
	int fetch_fault = error_code & PFERR_FETCH_MASK;
	struct guest_walker walker;
	u64 *shadow_pte;
	int write_pt = 0;
	int r;

	pgprintk("%s: addr %lx err %x\n", __FUNCTION__, addr, error_code);
	kvm_mmu_audit(vcpu, "pre page fault");

	r = mmu_topup_memory_caches(vcpu);
	if (r)
		return r;

	/*
	 * Look up the shadow pte for the faulting address.
	 */
	r = FNAME(walk_addr)(&walker, vcpu, addr, write_fault, user_fault,
			     fetch_fault);

	/*
	 * The page is not mapped by the guest.  Let the guest handle it.
	 */
	if (!r) {
		pgprintk("%s: guest page fault\n", __FUNCTION__);
		inject_page_fault(vcpu, addr, walker.error_code);
		FNAME(release_walker)(&walker);
		vcpu->last_pt_write_count = 0; /* reset fork detector */
		return 0;
	}

	shadow_pte = FNAME(fetch)(vcpu, addr, &walker, user_fault, write_fault,
				  &write_pt);
	pgprintk("%s: shadow pte %p %llx ptwrite %d\n", __FUNCTION__,
		 shadow_pte, *shadow_pte, write_pt);

	FNAME(release_walker)(&walker);

	if (!write_pt)
		vcpu->last_pt_write_count = 0; /* reset fork detector */

	/*
	 * mmio: emulate if accessible, otherwise its a guest fault.
	 */
	if (is_io_pte(*shadow_pte))
		return 1;

	++vcpu->stat.pf_fixed;
	kvm_mmu_audit(vcpu, "post page fault (fixed)");

	return write_pt;
}

static gpa_t FNAME(gva_to_gpa)(struct kvm_vcpu *vcpu, gva_t vaddr)
{
	struct guest_walker walker;
	gpa_t gpa = UNMAPPED_GVA;
	int r;

	r = FNAME(walk_addr)(&walker, vcpu, vaddr, 0, 0, 0);

	if (r) {
		gpa = (gpa_t)walker.gfn << PAGE_SHIFT;
		gpa |= vaddr & ~PAGE_MASK;
	}

	FNAME(release_walker)(&walker);
	return gpa;
}

#undef pt_element_t
#undef guest_walker
#undef FNAME
#undef PT_BASE_ADDR_MASK
#undef PT_INDEX
#undef SHADOW_PT_INDEX
#undef PT_LEVEL_MASK
#undef PT_DIR_BASE_ADDR_MASK
#undef PT_MAX_FULL_LEVELS
Commit	Line	Data
6aa8b732 AK	1	/*
	2	* Kernel-based Virtual Machine driver for Linux
	3	*
	4	* This module enables machines with Intel VT-x extensions to run virtual
	5	* machines without emulation or binary translation.
	6	*
	7	* MMU support
	8	*
	9	* Copyright (C) 2006 Qumranet, Inc.
	10	*
	11	* Authors:
	12	* Yaniv Kamay <yaniv@qumranet.com>
	13	* Avi Kivity <avi@qumranet.com>
	14	*
	15	* This work is licensed under the terms of the GNU GPL, version 2. See
	16	* the COPYING file in the top-level directory.
	17	*
	18	*/
	19
	20	/*
	21	* We need the mmu code to access both 32-bit and 64-bit guest ptes,
	22	* so the code in this file is compiled twice, once per pte size.
	23	*/
	24
	25	#if PTTYPE == 64
	26	#define pt_element_t u64
	27	#define guest_walker guest_walker64
	28	#define FNAME(name) paging##64_##name
	29	#define PT_BASE_ADDR_MASK PT64_BASE_ADDR_MASK
	30	#define PT_DIR_BASE_ADDR_MASK PT64_DIR_BASE_ADDR_MASK
	31	#define PT_INDEX(addr, level) PT64_INDEX(addr, level)
	32	#define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level)
	33	#define PT_LEVEL_MASK(level) PT64_LEVEL_MASK(level)
cea0f0e7 AK	34	#ifdef CONFIG_X86_64
	35	#define PT_MAX_FULL_LEVELS 4
	36	#else
	37	#define PT_MAX_FULL_LEVELS 2
	38	#endif
6aa8b732 AK	39	#elif PTTYPE == 32
	40	#define pt_element_t u32
	41	#define guest_walker guest_walker32
	42	#define FNAME(name) paging##32_##name
	43	#define PT_BASE_ADDR_MASK PT32_BASE_ADDR_MASK
	44	#define PT_DIR_BASE_ADDR_MASK PT32_DIR_BASE_ADDR_MASK
	45	#define PT_INDEX(addr, level) PT32_INDEX(addr, level)
	46	#define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level)
	47	#define PT_LEVEL_MASK(level) PT32_LEVEL_MASK(level)
cea0f0e7	48	#define PT_MAX_FULL_LEVELS 2
6aa8b732 AK	49	#else
	50	#error Invalid PTTYPE value
	51	#endif
	52
	53	/*
	54	* The guest_walker structure emulates the behavior of the hardware page
	55	* table walker.
	56	*/
	57	struct guest_walker {
	58	int level;
cea0f0e7	59	gfn_t table_gfn[PT_MAX_FULL_LEVELS];
6aa8b732	60	pt_element_t *table;
ac79c978	61	pt_element_t *ptep;
6aa8b732	62	pt_element_t inherited_ar;
815af8d4	63	gfn_t gfn;
7993ba43	64	u32 error_code;
6aa8b732 AK	65	};
6aa8b732 AK	66
ac79c978 AK	67	/*
	68	* Fetch a guest pte for a guest virtual address
	69	*/
7993ba43 AK	70	static int FNAME(walk_addr)(struct guest_walker *walker,
7993ba43 AK	71	struct kvm_vcpu *vcpu, gva_t addr,
73b1087e	72	int write_fault, int user_fault, int fetch_fault)
6aa8b732 AK	73	{
	74	hpa_t hpa;
	75	struct kvm_memory_slot *slot;
ac79c978	76	pt_element_t *ptep;
1b0973bd	77	pt_element_t root;
cea0f0e7	78	gfn_t table_gfn;
6aa8b732	79
cea0f0e7	80	pgprintk("%s: addr %lx\n", __FUNCTION__, addr);
6aa8b732	81	walker->level = vcpu->mmu.root_level;
1b0973bd AK	82	walker->table = NULL;
	83	root = vcpu->cr3;
	84	#if PTTYPE == 64
	85	if (!is_long_mode(vcpu)) {
	86	walker->ptep = &vcpu->pdptrs[(addr >> 30) & 3];
	87	root = *walker->ptep;
	88	if (!(root & PT_PRESENT_MASK))
7993ba43	89	goto not_present;
1b0973bd AK	90	--walker->level;
	91	}
	92	#endif
cea0f0e7 AK	93	table_gfn = (root & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT;
	94	walker->table_gfn[walker->level - 1] = table_gfn;
	95	pgprintk("%s: table_gfn[%d] %lx\n", __FUNCTION__,
	96	walker->level - 1, table_gfn);
	97	slot = gfn_to_memslot(vcpu->kvm, table_gfn);
1b0973bd	98	hpa = safe_gpa_to_hpa(vcpu, root & PT64_BASE_ADDR_MASK);
6aa8b732 AK	99	walker->table = kmap_atomic(pfn_to_page(hpa >> PAGE_SHIFT), KM_USER0);
6aa8b732 AK	100
a9058ecd	101	ASSERT((!is_long_mode(vcpu) && is_pae(vcpu)) \|\|
f802a307	102	(vcpu->cr3 & CR3_NONPAE_RESERVED_BITS) == 0);
6aa8b732	103
6aa8b732	104	walker->inherited_ar = PT_USER_MASK \| PT_WRITABLE_MASK;
ac79c978 AK	105
	106	for (;;) {
	107	int index = PT_INDEX(addr, walker->level);
	108	hpa_t paddr;
	109
	110	ptep = &walker->table[index];
	111	ASSERT(((unsigned long)walker->table & PAGE_MASK) ==
	112	((unsigned long)ptep & PAGE_MASK));
	113
815af8d4	114	if (!is_present_pte(*ptep))
7993ba43 AK	115	goto not_present;
	116
	117	if (write_fault && !is_writeble_pte(*ptep))
	118	if (user_fault \|\| is_write_protection(vcpu))
	119	goto access_error;
	120
	121	if (user_fault && !(*ptep & PT_USER_MASK))
	122	goto access_error;
	123
73b1087e AK	124	#if PTTYPE == 64
	125	if (fetch_fault && is_nx(vcpu) && (*ptep & PT64_NX_MASK))
	126	goto access_error;
	127	#endif
	128
bf3f8e86 AK	129	if (!(*ptep & PT_ACCESSED_MASK)) {
	130	mark_page_dirty(vcpu->kvm, table_gfn);
	131	*ptep \|= PT_ACCESSED_MASK;
	132	}
815af8d4 AK	133
	134	if (walker->level == PT_PAGE_TABLE_LEVEL) {
	135	walker->gfn = (*ptep & PT_BASE_ADDR_MASK)
	136	>> PAGE_SHIFT;
	137	break;
	138	}
	139
	140	if (walker->level == PT_DIRECTORY_LEVEL
	141	&& (*ptep & PT_PAGE_SIZE_MASK)
	142	&& (PTTYPE == 64 \|\| is_pse(vcpu))) {
	143	walker->gfn = (*ptep & PT_DIR_BASE_ADDR_MASK)
	144	>> PAGE_SHIFT;
	145	walker->gfn += PT_INDEX(addr, PT_PAGE_TABLE_LEVEL);
ac79c978	146	break;
815af8d4	147	}
ac79c978	148
ca5aac1f	149	walker->inherited_ar &= walker->table[index];
cea0f0e7	150	table_gfn = (*ptep & PT_BASE_ADDR_MASK) >> PAGE_SHIFT;
ac79c978 AK	151	paddr = safe_gpa_to_hpa(vcpu, *ptep & PT_BASE_ADDR_MASK);
	152	kunmap_atomic(walker->table, KM_USER0);
	153	walker->table = kmap_atomic(pfn_to_page(paddr >> PAGE_SHIFT),
	154	KM_USER0);
	155	--walker->level;
cea0f0e7 AK	156	walker->table_gfn[walker->level - 1 ] = table_gfn;
	157	pgprintk("%s: table_gfn[%d] %lx\n", __FUNCTION__,
	158	walker->level - 1, table_gfn);
ac79c978 AK	159	}
ac79c978 AK	160	walker->ptep = ptep;
374cbac0	161	pgprintk("%s: pte %llx\n", __FUNCTION__, (u64)*ptep);
7993ba43 AK	162	return 1;
	163
	164	not_present:
	165	walker->error_code = 0;
	166	goto err;
	167
	168	access_error:
	169	walker->error_code = PFERR_PRESENT_MASK;
	170
	171	err:
	172	if (write_fault)
	173	walker->error_code \|= PFERR_WRITE_MASK;
	174	if (user_fault)
	175	walker->error_code \|= PFERR_USER_MASK;
73b1087e AK	176	if (fetch_fault)
73b1087e AK	177	walker->error_code \|= PFERR_FETCH_MASK;
7993ba43	178	return 0;
6aa8b732 AK	179	}
	180
	181	static void FNAME(release_walker)(struct guest_walker *walker)
	182	{
1b0973bd AK	183	if (walker->table)
1b0973bd AK	184	kunmap_atomic(walker->table, KM_USER0);
6aa8b732 AK	185	}
6aa8b732 AK	186
bf3f8e86 AK	187	static void FNAME(mark_pagetable_dirty)(struct kvm *kvm,
	188	struct guest_walker *walker)
	189	{
	190	mark_page_dirty(kvm, walker->table_gfn[walker->level - 1]);
	191	}
	192
e60d75ea AK	193	static void FNAME(set_pte_common)(struct kvm_vcpu *vcpu,
	194	u64 *shadow_pte,
	195	gpa_t gaddr,
6598c8b2	196	pt_element_t *gpte,
e60d75ea	197	u64 access_bits,
97a0a01e	198	int user_fault,
63b1ad24	199	int write_fault,
97a0a01e AK	200	int *ptwrite,
97a0a01e AK	201	struct guest_walker *walker,
e60d75ea AK	202	gfn_t gfn)
	203	{
	204	hpa_t paddr;
6598c8b2	205	int dirty = *gpte & PT_DIRTY_MASK;
0d551bb6 AK	206	u64 spte = *shadow_pte;
0d551bb6 AK	207	int was_rmapped = is_rmap_pte(spte);
97a0a01e AK	208
	209	pgprintk("%s: spte %llx gpte %llx access %llx write_fault %d"
	210	" user_fault %d gfn %lx\n",
0d551bb6	211	__FUNCTION__, spte, (u64)*gpte, access_bits,
97a0a01e AK	212	write_fault, user_fault, gfn);
	213
	214	if (write_fault && !dirty) {
	215	*gpte \|= PT_DIRTY_MASK;
	216	dirty = 1;
	217	FNAME(mark_pagetable_dirty)(vcpu->kvm, walker);
	218	}
e60d75ea	219
fd97dc51 AK	220	spte \|= PT_PRESENT_MASK \| PT_ACCESSED_MASK \| PT_DIRTY_MASK;
fd97dc51 AK	221	spte \|= *gpte & PT64_NX_MASK;
e60d75ea AK	222	if (!dirty)
	223	access_bits &= ~PT_WRITABLE_MASK;
	224
	225	paddr = gpa_to_hpa(vcpu, gaddr & PT64_BASE_ADDR_MASK);
	226
0d551bb6	227	spte \|= PT_PRESENT_MASK;
97a0a01e	228	if (access_bits & PT_USER_MASK)
0d551bb6	229	spte \|= PT_USER_MASK;
e60d75ea AK	230
e60d75ea AK	231	if (is_error_hpa(paddr)) {
0d551bb6 AK	232	spte \|= gaddr;
	233	spte \|= PT_SHADOW_IO_MARK;
	234	spte &= ~PT_PRESENT_MASK;
e663ee64	235	set_shadow_pte(shadow_pte, spte);
e60d75ea AK	236	return;
	237	}
	238
0d551bb6	239	spte \|= paddr;
e60d75ea	240
97a0a01e AK	241	if ((access_bits & PT_WRITABLE_MASK)
97a0a01e AK	242	\|\| (write_fault && !is_write_protection(vcpu) && !user_fault)) {
e60d75ea AK	243	struct kvm_mmu_page *shadow;
e60d75ea AK	244
0d551bb6	245	spte \|= PT_WRITABLE_MASK;
97a0a01e AK	246	if (user_fault) {
	247	mmu_unshadow(vcpu, gfn);
	248	goto unshadowed;
	249	}
	250
e60d75ea AK	251	shadow = kvm_mmu_lookup_page(vcpu, gfn);
	252	if (shadow) {
	253	pgprintk("%s: found shadow page for %lx, marking ro\n",
	254	__FUNCTION__, gfn);
	255	access_bits &= ~PT_WRITABLE_MASK;
0d551bb6 AK	256	if (is_writeble_pte(spte)) {
0d551bb6 AK	257	spte &= ~PT_WRITABLE_MASK;
97a0a01e	258	kvm_arch_ops->tlb_flush(vcpu);
e60d75ea	259	}
97a0a01e AK	260	if (write_fault)
97a0a01e AK	261	*ptwrite = 1;
e60d75ea AK	262	}
	263	}
	264
97a0a01e AK	265	unshadowed:
97a0a01e AK	266
e60d75ea AK	267	if (access_bits & PT_WRITABLE_MASK)
	268	mark_page_dirty(vcpu->kvm, gaddr >> PAGE_SHIFT);
	269
e663ee64	270	set_shadow_pte(shadow_pte, spte);
e60d75ea	271	page_header_update_slot(vcpu->kvm, shadow_pte, gaddr);
97a0a01e AK	272	if (!was_rmapped)
97a0a01e AK	273	rmap_add(vcpu, shadow_pte);
e60d75ea AK	274	}
e60d75ea AK	275
6598c8b2	276	static void FNAME(set_pte)(struct kvm_vcpu vcpu, pt_element_t gpte,
63b1ad24	277	u64 *shadow_pte, u64 access_bits,
97a0a01e AK	278	int user_fault, int write_fault, int *ptwrite,
97a0a01e AK	279	struct guest_walker *walker, gfn_t gfn)
6aa8b732	280	{
6598c8b2	281	access_bits &= *gpte;
6598c8b2	282	FNAME(set_pte_common)(vcpu, shadow_pte, *gpte & PT_BASE_ADDR_MASK,
97a0a01e AK	283	gpte, access_bits, user_fault, write_fault,
97a0a01e AK	284	ptwrite, walker, gfn);
6aa8b732 AK	285	}
6aa8b732 AK	286
0028425f AK	287	static void FNAME(update_pte)(struct kvm_vcpu vcpu, struct kvm_mmu_page page,
	288	u64 spte, const void pte, int bytes)
	289	{
	290	pt_element_t gpte;
	291
	292	if (bytes < sizeof(pt_element_t))
	293	return;
	294	gpte = (const pt_element_t )pte;
	295	if (~gpte & (PT_PRESENT_MASK \| PT_ACCESSED_MASK))
	296	return;
	297	pgprintk("%s: gpte %llx spte %p\n", __FUNCTION__, (u64)gpte, spte);
63b1ad24	298	FNAME(set_pte)(vcpu, &gpte, spte, PT_USER_MASK \| PT_WRITABLE_MASK, 0,
97a0a01e	299	0, NULL, NULL,
0028425f AK	300	(gpte & PT_BASE_ADDR_MASK) >> PAGE_SHIFT);
	301	}
	302
6598c8b2	303	static void FNAME(set_pde)(struct kvm_vcpu vcpu, pt_element_t gpde,
97a0a01e AK	304	u64 *shadow_pte, u64 access_bits,
	305	int user_fault, int write_fault, int *ptwrite,
	306	struct guest_walker *walker, gfn_t gfn)
6aa8b732 AK	307	{
	308	gpa_t gaddr;
	309
6598c8b2	310	access_bits &= *gpde;
815af8d4	311	gaddr = (gpa_t)gfn << PAGE_SHIFT;
6aa8b732	312	if (PTTYPE == 32 && is_cpuid_PSE36())
6598c8b2	313	gaddr \|= (*gpde & PT32_DIR_PSE36_MASK) <<
6aa8b732	314	(32 - PT32_DIR_PSE36_SHIFT);
e60d75ea	315	FNAME(set_pte_common)(vcpu, shadow_pte, gaddr,
97a0a01e AK	316	gpde, access_bits, user_fault, write_fault,
97a0a01e AK	317	ptwrite, walker, gfn);
6aa8b732 AK	318	}
6aa8b732 AK	319
6aa8b732 AK	320	/*
	321	* Fetch a shadow pte for a specific level in the paging hierarchy.
	322	*/
	323	static u64 FNAME(fetch)(struct kvm_vcpu vcpu, gva_t addr,
97a0a01e AK	324	struct guest_walker *walker,
97a0a01e AK	325	int user_fault, int write_fault, int *ptwrite)
6aa8b732 AK	326	{
	327	hpa_t shadow_addr;
	328	int level;
ef0197e8	329	u64 *shadow_ent;
6aa8b732	330	u64 *prev_shadow_ent = NULL;
ac79c978 AK	331	pt_element_t *guest_ent = walker->ptep;
	332
	333	if (!is_present_pte(*guest_ent))
	334	return NULL;
6aa8b732 AK	335
	336	shadow_addr = vcpu->mmu.root_hpa;
	337	level = vcpu->mmu.shadow_root_level;
aef3d3fe AK	338	if (level == PT32E_ROOT_LEVEL) {
	339	shadow_addr = vcpu->mmu.pae_root[(addr >> 30) & 3];
	340	shadow_addr &= PT64_BASE_ADDR_MASK;
	341	--level;
	342	}
6aa8b732 AK	343
	344	for (; ; level--) {
	345	u32 index = SHADOW_PT_INDEX(addr, level);
25c0de2c	346	struct kvm_mmu_page *shadow_page;
8c7bb723	347	u64 shadow_pte;
cea0f0e7 AK	348	int metaphysical;
cea0f0e7 AK	349	gfn_t table_gfn;
d28c6cfb	350	unsigned hugepage_access = 0;
6aa8b732	351
ef0197e8	352	shadow_ent = ((u64 *)__va(shadow_addr)) + index;
6aa8b732 AK	353	if (is_present_pte(shadow_ent) \|\| is_io_pte(shadow_ent)) {
6aa8b732 AK	354	if (level == PT_PAGE_TABLE_LEVEL)
97a0a01e	355	break;
6aa8b732 AK	356	shadow_addr = *shadow_ent & PT64_BASE_ADDR_MASK;
	357	prev_shadow_ent = shadow_ent;
	358	continue;
	359	}
	360
ef0197e8 AK	361	if (level == PT_PAGE_TABLE_LEVEL)
ef0197e8 AK	362	break;
6aa8b732	363
cea0f0e7 AK	364	if (level - 1 == PT_PAGE_TABLE_LEVEL
	365	&& walker->level == PT_DIRECTORY_LEVEL) {
	366	metaphysical = 1;
d28c6cfb AK	367	hugepage_access = *guest_ent;
d28c6cfb AK	368	hugepage_access &= PT_USER_MASK \| PT_WRITABLE_MASK;
d55e2cb2 AK	369	if (*guest_ent & PT64_NX_MASK)
d55e2cb2 AK	370	hugepage_access \|= (1 << 2);
d28c6cfb	371	hugepage_access >>= PT_WRITABLE_SHIFT;
cea0f0e7 AK	372	table_gfn = (*guest_ent & PT_BASE_ADDR_MASK)
	373	>> PAGE_SHIFT;
	374	} else {
	375	metaphysical = 0;
	376	table_gfn = walker->table_gfn[level - 2];
	377	}
	378	shadow_page = kvm_mmu_get_page(vcpu, table_gfn, addr, level-1,
d28c6cfb AK	379	metaphysical, hugepage_access,
d28c6cfb AK	380	shadow_ent);
47ad8e68	381	shadow_addr = __pa(shadow_page->spt);
aef3d3fe AK	382	shadow_pte = shadow_addr \| PT_PRESENT_MASK \| PT_ACCESSED_MASK
aef3d3fe AK	383	\| PT_WRITABLE_MASK \| PT_USER_MASK;
8c7bb723	384	*shadow_ent = shadow_pte;
6aa8b732 AK	385	prev_shadow_ent = shadow_ent;
6aa8b732 AK	386	}
ef0197e8 AK	387
ef0197e8 AK	388	if (walker->level == PT_DIRECTORY_LEVEL) {
6598c8b2	389	FNAME(set_pde)(vcpu, guest_ent, shadow_ent,
97a0a01e AK	390	walker->inherited_ar, user_fault, write_fault,
97a0a01e AK	391	ptwrite, walker, walker->gfn);
ef0197e8 AK	392	} else {
ef0197e8 AK	393	ASSERT(walker->level == PT_PAGE_TABLE_LEVEL);
6598c8b2	394	FNAME(set_pte)(vcpu, guest_ent, shadow_ent,
97a0a01e AK	395	walker->inherited_ar, user_fault, write_fault,
97a0a01e AK	396	ptwrite, walker, walker->gfn);
ef0197e8 AK	397	}
ef0197e8 AK	398	return shadow_ent;
6aa8b732 AK	399	}
6aa8b732 AK	400
6aa8b732 AK	401	/*
	402	* Page fault handler. There are several causes for a page fault:
	403	* - there is no shadow pte for the guest pte
	404	* - write access through a shadow pte marked read only so that we can set
	405	* the dirty bit
	406	* - write access to a shadow pte marked read only so we can update the page
	407	* dirty bitmap, when userspace requests it
	408	* - mmio access; in this case we will never install a present shadow pte
	409	* - normal guest page fault due to the guest pte marked not present, not
	410	* writable, or not executable
	411	*
e2dec939 AK	412	* Returns: 1 if we need to emulate the instruction, 0 otherwise, or
e2dec939 AK	413	* a negative value on error.
6aa8b732 AK	414	*/
	415	static int FNAME(page_fault)(struct kvm_vcpu *vcpu, gva_t addr,
	416	u32 error_code)
	417	{
	418	int write_fault = error_code & PFERR_WRITE_MASK;
6aa8b732	419	int user_fault = error_code & PFERR_USER_MASK;
73b1087e	420	int fetch_fault = error_code & PFERR_FETCH_MASK;
6aa8b732 AK	421	struct guest_walker walker;
6aa8b732 AK	422	u64 *shadow_pte;
cea0f0e7	423	int write_pt = 0;
e2dec939	424	int r;
6aa8b732	425
cea0f0e7	426	pgprintk("%s: addr %lx err %x\n", __FUNCTION__, addr, error_code);
37a7d8b0	427	kvm_mmu_audit(vcpu, "pre page fault");
714b93da	428
e2dec939 AK	429	r = mmu_topup_memory_caches(vcpu);
	430	if (r)
	431	return r;
714b93da	432
6aa8b732 AK	433	/*
	434	* Look up the shadow pte for the faulting address.
	435	*/
73b1087e AK	436	r = FNAME(walk_addr)(&walker, vcpu, addr, write_fault, user_fault,
73b1087e AK	437	fetch_fault);
6aa8b732 AK	438
	439	/*
	440	* The page is not mapped by the guest. Let the guest handle it.
	441	*/
7993ba43 AK	442	if (!r) {
	443	pgprintk("%s: guest page fault\n", __FUNCTION__);
	444	inject_page_fault(vcpu, addr, walker.error_code);
6aa8b732	445	FNAME(release_walker)(&walker);
a25f7e1f	446	vcpu->last_pt_write_count = 0; /* reset fork detector */
6aa8b732 AK	447	return 0;
	448	}
	449
97a0a01e AK	450	shadow_pte = FNAME(fetch)(vcpu, addr, &walker, user_fault, write_fault,
	451	&write_pt);
	452	pgprintk("%s: shadow pte %p %llx ptwrite %d\n", __FUNCTION__,
	453	shadow_pte, *shadow_pte, write_pt);
cea0f0e7	454
6aa8b732 AK	455	FNAME(release_walker)(&walker);
6aa8b732 AK	456
a25f7e1f AK	457	if (!write_pt)
	458	vcpu->last_pt_write_count = 0; /* reset fork detector */
	459
6aa8b732 AK	460	/*
	461	* mmio: emulate if accessible, otherwise its a guest fault.
	462	*/
d27d4aca	463	if (is_io_pte(*shadow_pte))
7993ba43	464	return 1;
6aa8b732	465
1165f5fe	466	++vcpu->stat.pf_fixed;
37a7d8b0	467	kvm_mmu_audit(vcpu, "post page fault (fixed)");
6aa8b732	468
cea0f0e7	469	return write_pt;
6aa8b732 AK	470	}
	471
	472	static gpa_t FNAME(gva_to_gpa)(struct kvm_vcpu *vcpu, gva_t vaddr)
	473	{
	474	struct guest_walker walker;
e119d117 AK	475	gpa_t gpa = UNMAPPED_GVA;
e119d117 AK	476	int r;
6aa8b732	477
e119d117	478	r = FNAME(walk_addr)(&walker, vcpu, vaddr, 0, 0, 0);
6aa8b732	479
e119d117 AK	480	if (r) {
	481	gpa = (gpa_t)walker.gfn << PAGE_SHIFT;
	482	gpa \|= vaddr & ~PAGE_MASK;
6aa8b732 AK	483	}
6aa8b732 AK	484
e119d117	485	FNAME(release_walker)(&walker);
6aa8b732 AK	486	return gpa;
	487	}
	488
	489	#undef pt_element_t
	490	#undef guest_walker
	491	#undef FNAME
	492	#undef PT_BASE_ADDR_MASK
	493	#undef PT_INDEX
	494	#undef SHADOW_PT_INDEX
	495	#undef PT_LEVEL_MASK
6aa8b732	496	#undef PT_DIR_BASE_ADDR_MASK
cea0f0e7	497	#undef PT_MAX_FULL_LEVELS