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6aa8b732 AK |
1 | /* |
2 | * Kernel-based Virtual Machine driver for Linux | |
3 | * | |
4 | * This module enables machines with Intel VT-x extensions to run virtual | |
5 | * machines without emulation or binary translation. | |
6 | * | |
7 | * MMU support | |
8 | * | |
9 | * Copyright (C) 2006 Qumranet, Inc. | |
10 | * | |
11 | * Authors: | |
12 | * Yaniv Kamay <yaniv@qumranet.com> | |
13 | * Avi Kivity <avi@qumranet.com> | |
14 | * | |
15 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
16 | * the COPYING file in the top-level directory. | |
17 | * | |
18 | */ | |
19 | ||
20 | /* | |
21 | * We need the mmu code to access both 32-bit and 64-bit guest ptes, | |
22 | * so the code in this file is compiled twice, once per pte size. | |
23 | */ | |
24 | ||
25 | #if PTTYPE == 64 | |
26 | #define pt_element_t u64 | |
27 | #define guest_walker guest_walker64 | |
28 | #define FNAME(name) paging##64_##name | |
29 | #define PT_BASE_ADDR_MASK PT64_BASE_ADDR_MASK | |
30 | #define PT_DIR_BASE_ADDR_MASK PT64_DIR_BASE_ADDR_MASK | |
31 | #define PT_INDEX(addr, level) PT64_INDEX(addr, level) | |
32 | #define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level) | |
33 | #define PT_LEVEL_MASK(level) PT64_LEVEL_MASK(level) | |
34 | #define PT_PTE_COPY_MASK PT64_PTE_COPY_MASK | |
cea0f0e7 AK |
35 | #ifdef CONFIG_X86_64 |
36 | #define PT_MAX_FULL_LEVELS 4 | |
37 | #else | |
38 | #define PT_MAX_FULL_LEVELS 2 | |
39 | #endif | |
6aa8b732 AK |
40 | #elif PTTYPE == 32 |
41 | #define pt_element_t u32 | |
42 | #define guest_walker guest_walker32 | |
43 | #define FNAME(name) paging##32_##name | |
44 | #define PT_BASE_ADDR_MASK PT32_BASE_ADDR_MASK | |
45 | #define PT_DIR_BASE_ADDR_MASK PT32_DIR_BASE_ADDR_MASK | |
46 | #define PT_INDEX(addr, level) PT32_INDEX(addr, level) | |
47 | #define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level) | |
48 | #define PT_LEVEL_MASK(level) PT32_LEVEL_MASK(level) | |
49 | #define PT_PTE_COPY_MASK PT32_PTE_COPY_MASK | |
cea0f0e7 | 50 | #define PT_MAX_FULL_LEVELS 2 |
6aa8b732 AK |
51 | #else |
52 | #error Invalid PTTYPE value | |
53 | #endif | |
54 | ||
55 | /* | |
56 | * The guest_walker structure emulates the behavior of the hardware page | |
57 | * table walker. | |
58 | */ | |
59 | struct guest_walker { | |
60 | int level; | |
cea0f0e7 | 61 | gfn_t table_gfn[PT_MAX_FULL_LEVELS]; |
6aa8b732 | 62 | pt_element_t *table; |
ac79c978 | 63 | pt_element_t *ptep; |
6aa8b732 | 64 | pt_element_t inherited_ar; |
815af8d4 | 65 | gfn_t gfn; |
6aa8b732 AK |
66 | }; |
67 | ||
ac79c978 AK |
68 | /* |
69 | * Fetch a guest pte for a guest virtual address | |
70 | */ | |
71 | static void FNAME(walk_addr)(struct guest_walker *walker, | |
72 | struct kvm_vcpu *vcpu, gva_t addr) | |
6aa8b732 AK |
73 | { |
74 | hpa_t hpa; | |
75 | struct kvm_memory_slot *slot; | |
ac79c978 | 76 | pt_element_t *ptep; |
1b0973bd | 77 | pt_element_t root; |
cea0f0e7 | 78 | gfn_t table_gfn; |
6aa8b732 | 79 | |
cea0f0e7 | 80 | pgprintk("%s: addr %lx\n", __FUNCTION__, addr); |
6aa8b732 | 81 | walker->level = vcpu->mmu.root_level; |
1b0973bd AK |
82 | walker->table = NULL; |
83 | root = vcpu->cr3; | |
84 | #if PTTYPE == 64 | |
85 | if (!is_long_mode(vcpu)) { | |
86 | walker->ptep = &vcpu->pdptrs[(addr >> 30) & 3]; | |
87 | root = *walker->ptep; | |
88 | if (!(root & PT_PRESENT_MASK)) | |
89 | return; | |
90 | --walker->level; | |
91 | } | |
92 | #endif | |
cea0f0e7 AK |
93 | table_gfn = (root & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT; |
94 | walker->table_gfn[walker->level - 1] = table_gfn; | |
95 | pgprintk("%s: table_gfn[%d] %lx\n", __FUNCTION__, | |
96 | walker->level - 1, table_gfn); | |
97 | slot = gfn_to_memslot(vcpu->kvm, table_gfn); | |
1b0973bd | 98 | hpa = safe_gpa_to_hpa(vcpu, root & PT64_BASE_ADDR_MASK); |
6aa8b732 AK |
99 | walker->table = kmap_atomic(pfn_to_page(hpa >> PAGE_SHIFT), KM_USER0); |
100 | ||
a9058ecd | 101 | ASSERT((!is_long_mode(vcpu) && is_pae(vcpu)) || |
6aa8b732 AK |
102 | (vcpu->cr3 & ~(PAGE_MASK | CR3_FLAGS_MASK)) == 0); |
103 | ||
6aa8b732 | 104 | walker->inherited_ar = PT_USER_MASK | PT_WRITABLE_MASK; |
ac79c978 AK |
105 | |
106 | for (;;) { | |
107 | int index = PT_INDEX(addr, walker->level); | |
108 | hpa_t paddr; | |
109 | ||
110 | ptep = &walker->table[index]; | |
111 | ASSERT(((unsigned long)walker->table & PAGE_MASK) == | |
112 | ((unsigned long)ptep & PAGE_MASK)); | |
113 | ||
1b0973bd AK |
114 | if (is_present_pte(*ptep) && !(*ptep & PT_ACCESSED_MASK)) |
115 | *ptep |= PT_ACCESSED_MASK; | |
ac79c978 | 116 | |
815af8d4 AK |
117 | if (!is_present_pte(*ptep)) |
118 | break; | |
119 | ||
120 | if (walker->level == PT_PAGE_TABLE_LEVEL) { | |
121 | walker->gfn = (*ptep & PT_BASE_ADDR_MASK) | |
122 | >> PAGE_SHIFT; | |
123 | break; | |
124 | } | |
125 | ||
126 | if (walker->level == PT_DIRECTORY_LEVEL | |
127 | && (*ptep & PT_PAGE_SIZE_MASK) | |
128 | && (PTTYPE == 64 || is_pse(vcpu))) { | |
129 | walker->gfn = (*ptep & PT_DIR_BASE_ADDR_MASK) | |
130 | >> PAGE_SHIFT; | |
131 | walker->gfn += PT_INDEX(addr, PT_PAGE_TABLE_LEVEL); | |
ac79c978 | 132 | break; |
815af8d4 | 133 | } |
ac79c978 AK |
134 | |
135 | if (walker->level != 3 || is_long_mode(vcpu)) | |
136 | walker->inherited_ar &= walker->table[index]; | |
cea0f0e7 | 137 | table_gfn = (*ptep & PT_BASE_ADDR_MASK) >> PAGE_SHIFT; |
ac79c978 AK |
138 | paddr = safe_gpa_to_hpa(vcpu, *ptep & PT_BASE_ADDR_MASK); |
139 | kunmap_atomic(walker->table, KM_USER0); | |
140 | walker->table = kmap_atomic(pfn_to_page(paddr >> PAGE_SHIFT), | |
141 | KM_USER0); | |
142 | --walker->level; | |
cea0f0e7 AK |
143 | walker->table_gfn[walker->level - 1 ] = table_gfn; |
144 | pgprintk("%s: table_gfn[%d] %lx\n", __FUNCTION__, | |
145 | walker->level - 1, table_gfn); | |
ac79c978 AK |
146 | } |
147 | walker->ptep = ptep; | |
374cbac0 | 148 | pgprintk("%s: pte %llx\n", __FUNCTION__, (u64)*ptep); |
6aa8b732 AK |
149 | } |
150 | ||
151 | static void FNAME(release_walker)(struct guest_walker *walker) | |
152 | { | |
1b0973bd AK |
153 | if (walker->table) |
154 | kunmap_atomic(walker->table, KM_USER0); | |
6aa8b732 AK |
155 | } |
156 | ||
157 | static void FNAME(set_pte)(struct kvm_vcpu *vcpu, u64 guest_pte, | |
815af8d4 | 158 | u64 *shadow_pte, u64 access_bits, gfn_t gfn) |
6aa8b732 AK |
159 | { |
160 | ASSERT(*shadow_pte == 0); | |
161 | access_bits &= guest_pte; | |
162 | *shadow_pte = (guest_pte & PT_PTE_COPY_MASK); | |
163 | set_pte_common(vcpu, shadow_pte, guest_pte & PT_BASE_ADDR_MASK, | |
815af8d4 | 164 | guest_pte & PT_DIRTY_MASK, access_bits, gfn); |
6aa8b732 AK |
165 | } |
166 | ||
167 | static void FNAME(set_pde)(struct kvm_vcpu *vcpu, u64 guest_pde, | |
815af8d4 | 168 | u64 *shadow_pte, u64 access_bits, gfn_t gfn) |
6aa8b732 AK |
169 | { |
170 | gpa_t gaddr; | |
171 | ||
172 | ASSERT(*shadow_pte == 0); | |
173 | access_bits &= guest_pde; | |
815af8d4 | 174 | gaddr = (gpa_t)gfn << PAGE_SHIFT; |
6aa8b732 AK |
175 | if (PTTYPE == 32 && is_cpuid_PSE36()) |
176 | gaddr |= (guest_pde & PT32_DIR_PSE36_MASK) << | |
177 | (32 - PT32_DIR_PSE36_SHIFT); | |
8c7bb723 | 178 | *shadow_pte = guest_pde & PT_PTE_COPY_MASK; |
6aa8b732 | 179 | set_pte_common(vcpu, shadow_pte, gaddr, |
815af8d4 | 180 | guest_pde & PT_DIRTY_MASK, access_bits, gfn); |
6aa8b732 AK |
181 | } |
182 | ||
6aa8b732 AK |
183 | /* |
184 | * Fetch a shadow pte for a specific level in the paging hierarchy. | |
185 | */ | |
186 | static u64 *FNAME(fetch)(struct kvm_vcpu *vcpu, gva_t addr, | |
187 | struct guest_walker *walker) | |
188 | { | |
189 | hpa_t shadow_addr; | |
190 | int level; | |
191 | u64 *prev_shadow_ent = NULL; | |
ac79c978 AK |
192 | pt_element_t *guest_ent = walker->ptep; |
193 | ||
194 | if (!is_present_pte(*guest_ent)) | |
195 | return NULL; | |
6aa8b732 AK |
196 | |
197 | shadow_addr = vcpu->mmu.root_hpa; | |
198 | level = vcpu->mmu.shadow_root_level; | |
aef3d3fe AK |
199 | if (level == PT32E_ROOT_LEVEL) { |
200 | shadow_addr = vcpu->mmu.pae_root[(addr >> 30) & 3]; | |
201 | shadow_addr &= PT64_BASE_ADDR_MASK; | |
202 | --level; | |
203 | } | |
6aa8b732 AK |
204 | |
205 | for (; ; level--) { | |
206 | u32 index = SHADOW_PT_INDEX(addr, level); | |
207 | u64 *shadow_ent = ((u64 *)__va(shadow_addr)) + index; | |
25c0de2c | 208 | struct kvm_mmu_page *shadow_page; |
8c7bb723 | 209 | u64 shadow_pte; |
cea0f0e7 AK |
210 | int metaphysical; |
211 | gfn_t table_gfn; | |
6aa8b732 AK |
212 | |
213 | if (is_present_pte(*shadow_ent) || is_io_pte(*shadow_ent)) { | |
214 | if (level == PT_PAGE_TABLE_LEVEL) | |
215 | return shadow_ent; | |
216 | shadow_addr = *shadow_ent & PT64_BASE_ADDR_MASK; | |
217 | prev_shadow_ent = shadow_ent; | |
218 | continue; | |
219 | } | |
220 | ||
6aa8b732 AK |
221 | if (level == PT_PAGE_TABLE_LEVEL) { |
222 | ||
223 | if (walker->level == PT_DIRECTORY_LEVEL) { | |
224 | if (prev_shadow_ent) | |
225 | *prev_shadow_ent |= PT_SHADOW_PS_MARK; | |
226 | FNAME(set_pde)(vcpu, *guest_ent, shadow_ent, | |
227 | walker->inherited_ar, | |
815af8d4 | 228 | walker->gfn); |
6aa8b732 AK |
229 | } else { |
230 | ASSERT(walker->level == PT_PAGE_TABLE_LEVEL); | |
815af8d4 AK |
231 | FNAME(set_pte)(vcpu, *guest_ent, shadow_ent, |
232 | walker->inherited_ar, | |
233 | walker->gfn); | |
6aa8b732 AK |
234 | } |
235 | return shadow_ent; | |
236 | } | |
237 | ||
cea0f0e7 AK |
238 | if (level - 1 == PT_PAGE_TABLE_LEVEL |
239 | && walker->level == PT_DIRECTORY_LEVEL) { | |
240 | metaphysical = 1; | |
241 | table_gfn = (*guest_ent & PT_BASE_ADDR_MASK) | |
242 | >> PAGE_SHIFT; | |
243 | } else { | |
244 | metaphysical = 0; | |
245 | table_gfn = walker->table_gfn[level - 2]; | |
246 | } | |
247 | shadow_page = kvm_mmu_get_page(vcpu, table_gfn, addr, level-1, | |
248 | metaphysical, shadow_ent); | |
25c0de2c | 249 | shadow_addr = shadow_page->page_hpa; |
aef3d3fe AK |
250 | shadow_pte = shadow_addr | PT_PRESENT_MASK | PT_ACCESSED_MASK |
251 | | PT_WRITABLE_MASK | PT_USER_MASK; | |
8c7bb723 | 252 | *shadow_ent = shadow_pte; |
6aa8b732 AK |
253 | prev_shadow_ent = shadow_ent; |
254 | } | |
255 | } | |
256 | ||
257 | /* | |
258 | * The guest faulted for write. We need to | |
259 | * | |
260 | * - check write permissions | |
261 | * - update the guest pte dirty bit | |
262 | * - update our own dirty page tracking structures | |
263 | */ | |
264 | static int FNAME(fix_write_pf)(struct kvm_vcpu *vcpu, | |
265 | u64 *shadow_ent, | |
266 | struct guest_walker *walker, | |
267 | gva_t addr, | |
cea0f0e7 AK |
268 | int user, |
269 | int *write_pt) | |
6aa8b732 AK |
270 | { |
271 | pt_element_t *guest_ent; | |
272 | int writable_shadow; | |
273 | gfn_t gfn; | |
274 | ||
275 | if (is_writeble_pte(*shadow_ent)) | |
276 | return 0; | |
277 | ||
278 | writable_shadow = *shadow_ent & PT_SHADOW_WRITABLE_MASK; | |
279 | if (user) { | |
280 | /* | |
281 | * User mode access. Fail if it's a kernel page or a read-only | |
282 | * page. | |
283 | */ | |
284 | if (!(*shadow_ent & PT_SHADOW_USER_MASK) || !writable_shadow) | |
285 | return 0; | |
286 | ASSERT(*shadow_ent & PT_USER_MASK); | |
287 | } else | |
288 | /* | |
289 | * Kernel mode access. Fail if it's a read-only page and | |
290 | * supervisor write protection is enabled. | |
291 | */ | |
292 | if (!writable_shadow) { | |
293 | if (is_write_protection(vcpu)) | |
294 | return 0; | |
295 | *shadow_ent &= ~PT_USER_MASK; | |
296 | } | |
297 | ||
ac79c978 | 298 | guest_ent = walker->ptep; |
6aa8b732 AK |
299 | |
300 | if (!is_present_pte(*guest_ent)) { | |
301 | *shadow_ent = 0; | |
302 | return 0; | |
303 | } | |
304 | ||
815af8d4 | 305 | gfn = walker->gfn; |
cea0f0e7 AK |
306 | if (kvm_mmu_lookup_page(vcpu, gfn)) { |
307 | pgprintk("%s: found shadow page for %lx, marking ro\n", | |
308 | __FUNCTION__, gfn); | |
309 | *write_pt = 1; | |
310 | return 0; | |
311 | } | |
6aa8b732 AK |
312 | mark_page_dirty(vcpu->kvm, gfn); |
313 | *shadow_ent |= PT_WRITABLE_MASK; | |
314 | *guest_ent |= PT_DIRTY_MASK; | |
cd4a4e53 | 315 | rmap_add(vcpu->kvm, shadow_ent); |
6aa8b732 AK |
316 | |
317 | return 1; | |
318 | } | |
319 | ||
320 | /* | |
321 | * Page fault handler. There are several causes for a page fault: | |
322 | * - there is no shadow pte for the guest pte | |
323 | * - write access through a shadow pte marked read only so that we can set | |
324 | * the dirty bit | |
325 | * - write access to a shadow pte marked read only so we can update the page | |
326 | * dirty bitmap, when userspace requests it | |
327 | * - mmio access; in this case we will never install a present shadow pte | |
328 | * - normal guest page fault due to the guest pte marked not present, not | |
329 | * writable, or not executable | |
330 | * | |
331 | * Returns: 1 if we need to emulate the instruction, 0 otherwise | |
332 | */ | |
333 | static int FNAME(page_fault)(struct kvm_vcpu *vcpu, gva_t addr, | |
334 | u32 error_code) | |
335 | { | |
336 | int write_fault = error_code & PFERR_WRITE_MASK; | |
337 | int pte_present = error_code & PFERR_PRESENT_MASK; | |
338 | int user_fault = error_code & PFERR_USER_MASK; | |
339 | struct guest_walker walker; | |
340 | u64 *shadow_pte; | |
341 | int fixed; | |
cea0f0e7 | 342 | int write_pt = 0; |
6aa8b732 | 343 | |
cea0f0e7 | 344 | pgprintk("%s: addr %lx err %x\n", __FUNCTION__, addr, error_code); |
6aa8b732 AK |
345 | /* |
346 | * Look up the shadow pte for the faulting address. | |
347 | */ | |
ebeace86 AK |
348 | FNAME(walk_addr)(&walker, vcpu, addr); |
349 | shadow_pte = FNAME(fetch)(vcpu, addr, &walker); | |
6aa8b732 AK |
350 | |
351 | /* | |
352 | * The page is not mapped by the guest. Let the guest handle it. | |
353 | */ | |
354 | if (!shadow_pte) { | |
cea0f0e7 | 355 | pgprintk("%s: not mapped\n", __FUNCTION__); |
6aa8b732 AK |
356 | inject_page_fault(vcpu, addr, error_code); |
357 | FNAME(release_walker)(&walker); | |
358 | return 0; | |
359 | } | |
360 | ||
cea0f0e7 AK |
361 | pgprintk("%s: shadow pte %p %llx\n", __FUNCTION__, |
362 | shadow_pte, *shadow_pte); | |
363 | ||
6aa8b732 AK |
364 | /* |
365 | * Update the shadow pte. | |
366 | */ | |
367 | if (write_fault) | |
368 | fixed = FNAME(fix_write_pf)(vcpu, shadow_pte, &walker, addr, | |
cea0f0e7 | 369 | user_fault, &write_pt); |
6aa8b732 AK |
370 | else |
371 | fixed = fix_read_pf(shadow_pte); | |
372 | ||
cea0f0e7 AK |
373 | pgprintk("%s: updated shadow pte %p %llx\n", __FUNCTION__, |
374 | shadow_pte, *shadow_pte); | |
375 | ||
6aa8b732 AK |
376 | FNAME(release_walker)(&walker); |
377 | ||
378 | /* | |
379 | * mmio: emulate if accessible, otherwise its a guest fault. | |
380 | */ | |
381 | if (is_io_pte(*shadow_pte)) { | |
382 | if (may_access(*shadow_pte, write_fault, user_fault)) | |
383 | return 1; | |
384 | pgprintk("%s: io work, no access\n", __FUNCTION__); | |
385 | inject_page_fault(vcpu, addr, | |
386 | error_code | PFERR_PRESENT_MASK); | |
387 | return 0; | |
388 | } | |
389 | ||
390 | /* | |
391 | * pte not present, guest page fault. | |
392 | */ | |
cea0f0e7 | 393 | if (pte_present && !fixed && !write_pt) { |
6aa8b732 AK |
394 | inject_page_fault(vcpu, addr, error_code); |
395 | return 0; | |
396 | } | |
397 | ||
398 | ++kvm_stat.pf_fixed; | |
399 | ||
cea0f0e7 | 400 | return write_pt; |
6aa8b732 AK |
401 | } |
402 | ||
403 | static gpa_t FNAME(gva_to_gpa)(struct kvm_vcpu *vcpu, gva_t vaddr) | |
404 | { | |
405 | struct guest_walker walker; | |
406 | pt_element_t guest_pte; | |
407 | gpa_t gpa; | |
408 | ||
ac79c978 AK |
409 | FNAME(walk_addr)(&walker, vcpu, vaddr); |
410 | guest_pte = *walker.ptep; | |
6aa8b732 AK |
411 | FNAME(release_walker)(&walker); |
412 | ||
413 | if (!is_present_pte(guest_pte)) | |
414 | return UNMAPPED_GVA; | |
415 | ||
416 | if (walker.level == PT_DIRECTORY_LEVEL) { | |
417 | ASSERT((guest_pte & PT_PAGE_SIZE_MASK)); | |
418 | ASSERT(PTTYPE == 64 || is_pse(vcpu)); | |
419 | ||
420 | gpa = (guest_pte & PT_DIR_BASE_ADDR_MASK) | (vaddr & | |
421 | (PT_LEVEL_MASK(PT_PAGE_TABLE_LEVEL) | ~PAGE_MASK)); | |
422 | ||
423 | if (PTTYPE == 32 && is_cpuid_PSE36()) | |
424 | gpa |= (guest_pte & PT32_DIR_PSE36_MASK) << | |
425 | (32 - PT32_DIR_PSE36_SHIFT); | |
426 | } else { | |
427 | gpa = (guest_pte & PT_BASE_ADDR_MASK); | |
428 | gpa |= (vaddr & ~PAGE_MASK); | |
429 | } | |
430 | ||
431 | return gpa; | |
432 | } | |
433 | ||
434 | #undef pt_element_t | |
435 | #undef guest_walker | |
436 | #undef FNAME | |
437 | #undef PT_BASE_ADDR_MASK | |
438 | #undef PT_INDEX | |
439 | #undef SHADOW_PT_INDEX | |
440 | #undef PT_LEVEL_MASK | |
441 | #undef PT_PTE_COPY_MASK | |
442 | #undef PT_NON_PTE_COPY_MASK | |
443 | #undef PT_DIR_BASE_ADDR_MASK | |
cea0f0e7 | 444 | #undef PT_MAX_FULL_LEVELS |