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KVM: Keep track of missed timer irq injections
[linux-2.6-block.git] / drivers / kvm / lapic.c
CommitLineData
97222cc8
ED		 1
2/*
3 * Local APIC virtualization
4 *
5 * Copyright (C) 2006 Qumranet, Inc.
6 * Copyright (C) 2007 Novell
7 * Copyright (C) 2007 Intel
8 *
9 * Authors:
10 * Dor Laor <dor.laor@qumranet.com>
11 * Gregory Haskins <ghaskins@novell.com>
12 * Yaozu (Eddie) Dong <eddie.dong@intel.com>
13 *
14 * Based on Xen 3.1 code, Copyright (c) 2004, Intel Corporation.
15 *
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
18 */
19
20#include "kvm.h"
21#include <linux/kvm.h>
22#include <linux/mm.h>
23#include <linux/highmem.h>
24#include <linux/smp.h>
25#include <linux/hrtimer.h>
26#include <linux/io.h>
27#include <linux/module.h>
28#include <asm/processor.h>
29#include <asm/msr.h>
30#include <asm/page.h>
31#include <asm/current.h>
32#include <asm/apicdef.h>
33#include <asm/atomic.h>
34#include <asm/div64.h>
35#include "irq.h"
36
37#define PRId64 "d"
38#define PRIx64 "llx"
39#define PRIu64 "u"
40#define PRIo64 "o"
41
42#define APIC_BUS_CYCLE_NS 1
43
44/* #define apic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg) */
45#define apic_debug(fmt, arg...)
46
47#define APIC_LVT_NUM 6
48/* 14 is the version for Xeon and Pentium 8.4.8*/
49#define APIC_VERSION (0x14UL | ((APIC_LVT_NUM - 1) << 16))
50#define LAPIC_MMIO_LENGTH (1 << 12)
51/* followed define is not in apicdef.h */
52#define APIC_SHORT_MASK 0xc0000
53#define APIC_DEST_NOSHORT 0x0
54#define APIC_DEST_MASK 0x800
55#define MAX_APIC_VECTOR 256
56
57#define VEC_POS(v) ((v) & (32 - 1))
58#define REG_POS(v) (((v) >> 5) << 4)
59static inline u32 apic_get_reg(struct kvm_lapic *apic, int reg_off)
60{
61 return *((u32 *) (apic->regs + reg_off));
62}
63
64static inline void apic_set_reg(struct kvm_lapic *apic, int reg_off, u32 val)
65{
66 *((u32 *) (apic->regs + reg_off)) = val;
67}
68
69static inline int apic_test_and_set_vector(int vec, void *bitmap)
70{
71 return test_and_set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
72}
73
74static inline int apic_test_and_clear_vector(int vec, void *bitmap)
75{
76 return test_and_clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
77}
78
79static inline void apic_set_vector(int vec, void *bitmap)
80{
81 set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
82}
83
84static inline void apic_clear_vector(int vec, void *bitmap)
85{
86 clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
87}
88
89static inline int apic_hw_enabled(struct kvm_lapic *apic)
90{
91 return (apic)->vcpu->apic_base & MSR_IA32_APICBASE_ENABLE;
92}
93
94static inline int apic_sw_enabled(struct kvm_lapic *apic)
95{
96 return apic_get_reg(apic, APIC_SPIV) & APIC_SPIV_APIC_ENABLED;
97}
98
99static inline int apic_enabled(struct kvm_lapic *apic)
100{
101 return apic_sw_enabled(apic) && apic_hw_enabled(apic);
102}
103
104#define LVT_MASK \
105 (APIC_LVT_MASKED | APIC_SEND_PENDING | APIC_VECTOR_MASK)
106
107#define LINT_MASK \
108 (LVT_MASK | APIC_MODE_MASK | APIC_INPUT_POLARITY | \
109 APIC_LVT_REMOTE_IRR | APIC_LVT_LEVEL_TRIGGER)
110
111static inline int kvm_apic_id(struct kvm_lapic *apic)
112{
113 return (apic_get_reg(apic, APIC_ID) >> 24) & 0xff;
114}
115
116static inline int apic_lvt_enabled(struct kvm_lapic *apic, int lvt_type)
117{
118 return !(apic_get_reg(apic, lvt_type) & APIC_LVT_MASKED);
119}
120
121static inline int apic_lvt_vector(struct kvm_lapic *apic, int lvt_type)
122{
123 return apic_get_reg(apic, lvt_type) & APIC_VECTOR_MASK;
124}
125
126static inline int apic_lvtt_period(struct kvm_lapic *apic)
127{
128 return apic_get_reg(apic, APIC_LVTT) & APIC_LVT_TIMER_PERIODIC;
129}
130
131static unsigned int apic_lvt_mask[APIC_LVT_NUM] = {
132 LVT_MASK | APIC_LVT_TIMER_PERIODIC, /* LVTT */
133 LVT_MASK | APIC_MODE_MASK, /* LVTTHMR */
134 LVT_MASK | APIC_MODE_MASK, /* LVTPC */
135 LINT_MASK, LINT_MASK, /* LVT0-1 */
136 LVT_MASK /* LVTERR */
137};
138
139static int find_highest_vector(void *bitmap)
140{
141 u32 *word = bitmap;
142 int word_offset = MAX_APIC_VECTOR >> 5;
143
144 while ((word_offset != 0) && (word[(--word_offset) << 2] == 0))
145 continue;
146
147 if (likely(!word_offset && !word[0]))
148 return -1;
149 else
150 return fls(word[word_offset << 2]) - 1 + (word_offset << 5);
151}
152
153static inline int apic_test_and_set_irr(int vec, struct kvm_lapic *apic)
154{
155 return apic_test_and_set_vector(vec, apic->regs + APIC_IRR);
156}
157
158static inline void apic_clear_irr(int vec, struct kvm_lapic *apic)
159{
160 apic_clear_vector(vec, apic->regs + APIC_IRR);
161}
162
163static inline int apic_find_highest_irr(struct kvm_lapic *apic)
164{
165 int result;
166
167 result = find_highest_vector(apic->regs + APIC_IRR);
168 ASSERT(result == -1 || result >= 16);
169
170 return result;
171}
172
6e5d865c
YS		 173int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu)
174{
175 struct kvm_lapic *apic = (struct kvm_lapic *)vcpu->apic;
176 int highest_irr;
177
178 if (!apic)
179 return 0;
180 highest_irr = apic_find_highest_irr(apic);
181
182 return highest_irr;
183}
184EXPORT_SYMBOL_GPL(kvm_lapic_find_highest_irr);
185
97222cc8
ED		 186int kvm_apic_set_irq(struct kvm_lapic *apic, u8 vec, u8 trig)
187{
188 if (!apic_test_and_set_irr(vec, apic)) {
189 /* a new pending irq is set in IRR */
190 if (trig)
191 apic_set_vector(vec, apic->regs + APIC_TMR);
192 else
193 apic_clear_vector(vec, apic->regs + APIC_TMR);
194 kvm_vcpu_kick(apic->vcpu);
195 return 1;
196 }
197 return 0;
198}
199
200static inline int apic_find_highest_isr(struct kvm_lapic *apic)
201{
202 int result;
203
204 result = find_highest_vector(apic->regs + APIC_ISR);
205 ASSERT(result == -1 || result >= 16);
206
207 return result;
208}
209
210static void apic_update_ppr(struct kvm_lapic *apic)
211{
212 u32 tpr, isrv, ppr;
213 int isr;
214
215 tpr = apic_get_reg(apic, APIC_TASKPRI);
216 isr = apic_find_highest_isr(apic);
217 isrv = (isr != -1) ? isr : 0;
218
219 if ((tpr & 0xf0) >= (isrv & 0xf0))
220 ppr = tpr & 0xff;
221 else
222 ppr = isrv & 0xf0;
223
224 apic_debug("vlapic %p, ppr 0x%x, isr 0x%x, isrv 0x%x",
225 apic, ppr, isr, isrv);
226
227 apic_set_reg(apic, APIC_PROCPRI, ppr);
228}
229
230static void apic_set_tpr(struct kvm_lapic *apic, u32 tpr)
231{
232 apic_set_reg(apic, APIC_TASKPRI, tpr);
233 apic_update_ppr(apic);
234}
235
236int kvm_apic_match_physical_addr(struct kvm_lapic *apic, u16 dest)
237{
238 return kvm_apic_id(apic) == dest;
239}
240
241int kvm_apic_match_logical_addr(struct kvm_lapic *apic, u8 mda)
242{
243 int result = 0;
244 u8 logical_id;
245
246 logical_id = GET_APIC_LOGICAL_ID(apic_get_reg(apic, APIC_LDR));
247
248 switch (apic_get_reg(apic, APIC_DFR)) {
249 case APIC_DFR_FLAT:
250 if (logical_id & mda)
251 result = 1;
252 break;
253 case APIC_DFR_CLUSTER:
254 if (((logical_id >> 4) == (mda >> 0x4))
255 && (logical_id & mda & 0xf))
256 result = 1;
257 break;
258 default:
259 printk(KERN_WARNING "Bad DFR vcpu %d: %08x\n",
260 apic->vcpu->vcpu_id, apic_get_reg(apic, APIC_DFR));
261 break;
262 }
263
264 return result;
265}
266
267static int apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source,
268 int short_hand, int dest, int dest_mode)
269{
270 int result = 0;
271 struct kvm_lapic *target = vcpu->apic;
272
273 apic_debug("target %p, source %p, dest 0x%x, "
274 "dest_mode 0x%x, short_hand 0x%x",
275 target, source, dest, dest_mode, short_hand);
276
277 ASSERT(!target);
278 switch (short_hand) {
279 case APIC_DEST_NOSHORT:
280 if (dest_mode == 0) {
281 /* Physical mode. */
282 if ((dest == 0xFF) || (dest == kvm_apic_id(target)))
283 result = 1;
284 } else
285 /* Logical mode. */
286 result = kvm_apic_match_logical_addr(target, dest);
287 break;
288 case APIC_DEST_SELF:
289 if (target == source)
290 result = 1;
291 break;
292 case APIC_DEST_ALLINC:
293 result = 1;
294 break;
295 case APIC_DEST_ALLBUT:
296 if (target != source)
297 result = 1;
298 break;
299 default:
300 printk(KERN_WARNING "Bad dest shorthand value %x\n",
301 short_hand);
302 break;
303 }
304
305 return result;
306}
307
308/*
309 * Add a pending IRQ into lapic.
310 * Return 1 if successfully added and 0 if discarded.
311 */
312static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
313 int vector, int level, int trig_mode)
314{
315 int result = 0;
1b9778da 316 int orig_irr;
97222cc8
ED		 317
318 switch (delivery_mode) {
319 case APIC_DM_FIXED:
320 case APIC_DM_LOWEST:
321 /* FIXME add logic for vcpu on reset */
322 if (unlikely(!apic_enabled(apic)))
323 break;
324
1b9778da
ED		 325 orig_irr = apic_test_and_set_irr(vector, apic);
326 if (orig_irr && trig_mode) {
97222cc8
ED		 327 apic_debug("level trig mode repeatedly for vector %d",
328 vector);
329 break;
330 }
331
332 if (trig_mode) {
333 apic_debug("level trig mode for vector %d", vector);
334 apic_set_vector(vector, apic->regs + APIC_TMR);
335 } else
336 apic_clear_vector(vector, apic->regs + APIC_TMR);
337
338 kvm_vcpu_kick(apic->vcpu);
339
1b9778da 340 result = (orig_irr == 0);
97222cc8
ED		 341 break;
342
343 case APIC_DM_REMRD:
344 printk(KERN_DEBUG "Ignoring delivery mode 3\n");
345 break;
346
347 case APIC_DM_SMI:
348 printk(KERN_DEBUG "Ignoring guest SMI\n");
349 break;
350 case APIC_DM_NMI:
351 printk(KERN_DEBUG "Ignoring guest NMI\n");
352 break;
353
354 case APIC_DM_INIT:
355 printk(KERN_DEBUG "Ignoring guest INIT\n");
356 break;
357
358 case APIC_DM_STARTUP:
359 printk(KERN_DEBUG "Ignoring guest STARTUP\n");
360 break;
361
362 default:
363 printk(KERN_ERR "TODO: unsupported delivery mode %x\n",
364 delivery_mode);
365 break;
366 }
367 return result;
368}
369
370struct kvm_lapic *kvm_apic_round_robin(struct kvm *kvm, u8 vector,
371 unsigned long bitmap)
372{
373 int vcpu_id;
374
375 /* TODO for real round robin */
376 vcpu_id = fls(bitmap) - 1;
377 if (vcpu_id < 0)
378 printk(KERN_DEBUG "vcpu not ready for apic_round_robin\n");
379 return kvm->vcpus[vcpu_id]->apic;
380}
381
382static void apic_set_eoi(struct kvm_lapic *apic)
383{
384 int vector = apic_find_highest_isr(apic);
385
386 /*
387 * Not every write EOI will has corresponding ISR,
388 * one example is when Kernel check timer on setup_IO_APIC
389 */
390 if (vector == -1)
391 return;
392
393 apic_clear_vector(vector, apic->regs + APIC_ISR);
394 apic_update_ppr(apic);
395
396 if (apic_test_and_clear_vector(vector, apic->regs + APIC_TMR))
397 kvm_ioapic_update_eoi(apic->vcpu->kvm, vector);
398}
399
400static void apic_send_ipi(struct kvm_lapic *apic)
401{
402 u32 icr_low = apic_get_reg(apic, APIC_ICR);
403 u32 icr_high = apic_get_reg(apic, APIC_ICR2);
404
405 unsigned int dest = GET_APIC_DEST_FIELD(icr_high);
406 unsigned int short_hand = icr_low & APIC_SHORT_MASK;
407 unsigned int trig_mode = icr_low & APIC_INT_LEVELTRIG;
408 unsigned int level = icr_low & APIC_INT_ASSERT;
409 unsigned int dest_mode = icr_low & APIC_DEST_MASK;
410 unsigned int delivery_mode = icr_low & APIC_MODE_MASK;
411 unsigned int vector = icr_low & APIC_VECTOR_MASK;
412
413 struct kvm_lapic *target;
414 struct kvm_vcpu *vcpu;
415 unsigned long lpr_map = 0;
416 int i;
417
418 apic_debug("icr_high 0x%x, icr_low 0x%x, "
419 "short_hand 0x%x, dest 0x%x, trig_mode 0x%x, level 0x%x, "
420 "dest_mode 0x%x, delivery_mode 0x%x, vector 0x%x\n",
421 icr_high, icr_low, short_hand, dest,
422 trig_mode, level, dest_mode, delivery_mode, vector);
423
424 for (i = 0; i < KVM_MAX_VCPUS; i++) {
425 vcpu = apic->vcpu->kvm->vcpus[i];
426 if (!vcpu)
427 continue;
428
429 if (vcpu->apic &&
430 apic_match_dest(vcpu, apic, short_hand, dest, dest_mode)) {
431 if (delivery_mode == APIC_DM_LOWEST)
432 set_bit(vcpu->vcpu_id, &lpr_map);
433 else
434 __apic_accept_irq(vcpu->apic, delivery_mode,
435 vector, level, trig_mode);
436 }
437 }
438
439 if (delivery_mode == APIC_DM_LOWEST) {
440 target = kvm_apic_round_robin(vcpu->kvm, vector, lpr_map);
441 if (target != NULL)
442 __apic_accept_irq(target, delivery_mode,
443 vector, level, trig_mode);
444 }
445}
446
447static u32 apic_get_tmcct(struct kvm_lapic *apic)
448{
449 u32 counter_passed;
450 ktime_t passed, now = apic->timer.dev.base->get_time();
451 u32 tmcct = apic_get_reg(apic, APIC_TMICT);
452
453 ASSERT(apic != NULL);
454
455 if (unlikely(ktime_to_ns(now) <=
456 ktime_to_ns(apic->timer.last_update))) {
457 /* Wrap around */
458 passed = ktime_add(( {
459 (ktime_t) {
460 .tv64 = KTIME_MAX -
461 (apic->timer.last_update).tv64}; }
462 ), now);
463 apic_debug("time elapsed\n");
464 } else
465 passed = ktime_sub(now, apic->timer.last_update);
466
467 counter_passed = div64_64(ktime_to_ns(passed),
468 (APIC_BUS_CYCLE_NS * apic->timer.divide_count));
469 tmcct -= counter_passed;
470
471 if (tmcct <= 0) {
472 if (unlikely(!apic_lvtt_period(apic)))
473 tmcct = 0;
474 else
475 do {
476 tmcct += apic_get_reg(apic, APIC_TMICT);
477 } while (tmcct <= 0);
478 }
479
480 return tmcct;
481}
482
483static u32 __apic_read(struct kvm_lapic *apic, unsigned int offset)
484{
485 u32 val = 0;
486
487 if (offset >= LAPIC_MMIO_LENGTH)
488 return 0;
489
490 switch (offset) {
491 case APIC_ARBPRI:
492 printk(KERN_WARNING "Access APIC ARBPRI register "
493 "which is for P6\n");
494 break;
495
496 case APIC_TMCCT: /* Timer CCR */
497 val = apic_get_tmcct(apic);
498 break;
499
500 default:
6e5d865c 501 apic_update_ppr(apic);
97222cc8
ED		 502 val = apic_get_reg(apic, offset);
503 break;
504 }
505
506 return val;
507}
508
509static void apic_mmio_read(struct kvm_io_device *this,
510 gpa_t address, int len, void *data)
511{
512 struct kvm_lapic *apic = (struct kvm_lapic *)this->private;
513 unsigned int offset = address - apic->base_address;
514 unsigned char alignment = offset & 0xf;
515 u32 result;
516
517 if ((alignment + len) > 4) {
518 printk(KERN_ERR "KVM_APIC_READ: alignment error %lx %d",
519 (unsigned long)address, len);
520 return;
521 }
522 result = __apic_read(apic, offset & ~0xf);
523
524 switch (len) {
525 case 1:
526 case 2:
527 case 4:
528 memcpy(data, (char *)&result + alignment, len);
529 break;
530 default:
531 printk(KERN_ERR "Local APIC read with len = %x, "
532 "should be 1,2, or 4 instead\n", len);
533 break;
534 }
535}
536
537static void update_divide_count(struct kvm_lapic *apic)
538{
539 u32 tmp1, tmp2, tdcr;
540
541 tdcr = apic_get_reg(apic, APIC_TDCR);
542 tmp1 = tdcr & 0xf;
543 tmp2 = ((tmp1 & 0x3) | ((tmp1 & 0x8) >> 1)) + 1;
544 apic->timer.divide_count = 0x1 << (tmp2 & 0x7);
545
546 apic_debug("timer divide count is 0x%x\n",
547 apic->timer.divide_count);
548}
549
550static void start_apic_timer(struct kvm_lapic *apic)
551{
552 ktime_t now = apic->timer.dev.base->get_time();
553
554 apic->timer.last_update = now;
555
556 apic->timer.period = apic_get_reg(apic, APIC_TMICT) *
557 APIC_BUS_CYCLE_NS * apic->timer.divide_count;
558 atomic_set(&apic->timer.pending, 0);
559 hrtimer_start(&apic->timer.dev,
560 ktime_add_ns(now, apic->timer.period),
561 HRTIMER_MODE_ABS);
562
563 apic_debug("%s: bus cycle is %" PRId64 "ns, now 0x%016"
564 PRIx64 ", "
565 "timer initial count 0x%x, period %lldns, "
566 "expire @ 0x%016" PRIx64 ".\n", __FUNCTION__,
567 APIC_BUS_CYCLE_NS, ktime_to_ns(now),
568 apic_get_reg(apic, APIC_TMICT),
569 apic->timer.period,
570 ktime_to_ns(ktime_add_ns(now,
571 apic->timer.period)));
572}
573
574static void apic_mmio_write(struct kvm_io_device *this,
575 gpa_t address, int len, const void *data)
576{
577 struct kvm_lapic *apic = (struct kvm_lapic *)this->private;
578 unsigned int offset = address - apic->base_address;
579 unsigned char alignment = offset & 0xf;
580 u32 val;
581
582 /*
583 * APIC register must be aligned on 128-bits boundary.
584 * 32/64/128 bits registers must be accessed thru 32 bits.
585 * Refer SDM 8.4.1
586 */
587 if (len != 4 || alignment) {
588 if (printk_ratelimit())
589 printk(KERN_ERR "apic write: bad size=%d %lx\n",
590 len, (long)address);
591 return;
592 }
593
594 val = *(u32 *) data;
595
596 /* too common printing */
597 if (offset != APIC_EOI)
598 apic_debug("%s: offset 0x%x with length 0x%x, and value is "
599 "0x%x\n", __FUNCTION__, offset, len, val);
600
601 offset &= 0xff0;
602
603 switch (offset) {
604 case APIC_ID: /* Local APIC ID */
605 apic_set_reg(apic, APIC_ID, val);
606 break;
607
608 case APIC_TASKPRI:
609 apic_set_tpr(apic, val & 0xff);
610 break;
611
612 case APIC_EOI:
613 apic_set_eoi(apic);
614 break;
615
616 case APIC_LDR:
617 apic_set_reg(apic, APIC_LDR, val & APIC_LDR_MASK);
618 break;
619
620 case APIC_DFR:
621 apic_set_reg(apic, APIC_DFR, val | 0x0FFFFFFF);
622 break;
623
624 case APIC_SPIV:
625 apic_set_reg(apic, APIC_SPIV, val & 0x3ff);
626 if (!(val & APIC_SPIV_APIC_ENABLED)) {
627 int i;
628 u32 lvt_val;
629
630 for (i = 0; i < APIC_LVT_NUM; i++) {
631 lvt_val = apic_get_reg(apic,
632 APIC_LVTT + 0x10 * i);
633 apic_set_reg(apic, APIC_LVTT + 0x10 * i,
634 lvt_val | APIC_LVT_MASKED);
635 }
636 atomic_set(&apic->timer.pending, 0);
637
638 }
639 break;
640
641 case APIC_ICR:
642 /* No delay here, so we always clear the pending bit */
643 apic_set_reg(apic, APIC_ICR, val & ~(1 << 12));
644 apic_send_ipi(apic);
645 break;
646
647 case APIC_ICR2:
648 apic_set_reg(apic, APIC_ICR2, val & 0xff000000);
649 break;
650
651 case APIC_LVTT:
652 case APIC_LVTTHMR:
653 case APIC_LVTPC:
654 case APIC_LVT0:
655 case APIC_LVT1:
656 case APIC_LVTERR:
657 /* TODO: Check vector */
658 if (!apic_sw_enabled(apic))
659 val |= APIC_LVT_MASKED;
660
661 val &= apic_lvt_mask[(offset - APIC_LVTT) >> 4];
662 apic_set_reg(apic, offset, val);
663
664 break;
665
666 case APIC_TMICT:
667 hrtimer_cancel(&apic->timer.dev);
668 apic_set_reg(apic, APIC_TMICT, val);
669 start_apic_timer(apic);
670 return;
671
672 case APIC_TDCR:
673 if (val & 4)
674 printk(KERN_ERR "KVM_WRITE:TDCR %x\n", val);
675 apic_set_reg(apic, APIC_TDCR, val);
676 update_divide_count(apic);
677 break;
678
679 default:
680 apic_debug("Local APIC Write to read-only register %x\n",
681 offset);
682 break;
683 }
684
685}
686
687static int apic_mmio_range(struct kvm_io_device *this, gpa_t addr)
688{
689 struct kvm_lapic *apic = (struct kvm_lapic *)this->private;
690 int ret = 0;
691
692
693 if (apic_hw_enabled(apic) &&
694 (addr >= apic->base_address) &&
695 (addr < (apic->base_address + LAPIC_MMIO_LENGTH)))
696 ret = 1;
697
698 return ret;
699}
700
701void kvm_free_apic(struct kvm_lapic *apic)
702{
703 if (!apic)
704 return;
705
706 hrtimer_cancel(&apic->timer.dev);
707
708 if (apic->regs_page) {
709 __free_page(apic->regs_page);
710 apic->regs_page = 0;
711 }
712
713 kfree(apic);
714}
715
716/*
717 *----------------------------------------------------------------------
718 * LAPIC interface
719 *----------------------------------------------------------------------
720 */
721
722void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8)
723{
724 struct kvm_lapic *apic = (struct kvm_lapic *)vcpu->apic;
725
726 if (!apic)
727 return;
728 apic_set_tpr(apic, ((cr8 & 0x0f) << 4));
729}
730
731u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu)
732{
733 struct kvm_lapic *apic = (struct kvm_lapic *)vcpu->apic;
734 u64 tpr;
735
736 if (!apic)
737 return 0;
738 tpr = (u64) apic_get_reg(apic, APIC_TASKPRI);
739
740 return (tpr & 0xf0) >> 4;
741}
6e5d865c 742EXPORT_SYMBOL_GPL(kvm_lapic_get_cr8);
97222cc8
ED		 743
744void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value)
745{
746 struct kvm_lapic *apic = (struct kvm_lapic *)vcpu->apic;
747
748 if (!apic) {
749 value |= MSR_IA32_APICBASE_BSP;
750 vcpu->apic_base = value;
751 return;
752 }
753 if (apic->vcpu->vcpu_id)
754 value &= ~MSR_IA32_APICBASE_BSP;
755
756 vcpu->apic_base = value;
757 apic->base_address = apic->vcpu->apic_base &
758 MSR_IA32_APICBASE_BASE;
759
760 /* with FSB delivery interrupt, we can restart APIC functionality */
761 apic_debug("apic base msr is 0x%016" PRIx64 ", and base address is "
762 "0x%lx.\n", apic->apic_base, apic->base_address);
763
764}
765
766u64 kvm_lapic_get_base(struct kvm_vcpu *vcpu)
767{
768 return vcpu->apic_base;
769}
770EXPORT_SYMBOL_GPL(kvm_lapic_get_base);
771
772static void lapic_reset(struct kvm_vcpu *vcpu)
773{
774 struct kvm_lapic *apic;
775 int i;
776
777 apic_debug("%s\n", __FUNCTION__);
778
779 ASSERT(vcpu);
780 apic = vcpu->apic;
781 ASSERT(apic != NULL);
782
783 /* Stop the timer in case it's a reset to an active apic */
784 hrtimer_cancel(&apic->timer.dev);
785
786 apic_set_reg(apic, APIC_ID, vcpu->vcpu_id << 24);
787 apic_set_reg(apic, APIC_LVR, APIC_VERSION);
788
789 for (i = 0; i < APIC_LVT_NUM; i++)
790 apic_set_reg(apic, APIC_LVTT + 0x10 * i, APIC_LVT_MASKED);
791
792 apic_set_reg(apic, APIC_DFR, 0xffffffffU);
793 apic_set_reg(apic, APIC_SPIV, 0xff);
794 apic_set_reg(apic, APIC_TASKPRI, 0);
795 apic_set_reg(apic, APIC_LDR, 0);
796 apic_set_reg(apic, APIC_ESR, 0);
797 apic_set_reg(apic, APIC_ICR, 0);
798 apic_set_reg(apic, APIC_ICR2, 0);
799 apic_set_reg(apic, APIC_TDCR, 0);
800 apic_set_reg(apic, APIC_TMICT, 0);
801 for (i = 0; i < 8; i++) {
802 apic_set_reg(apic, APIC_IRR + 0x10 * i, 0);
803 apic_set_reg(apic, APIC_ISR + 0x10 * i, 0);
804 apic_set_reg(apic, APIC_TMR + 0x10 * i, 0);
805 }
806 apic->timer.divide_count = 0;
807 atomic_set(&apic->timer.pending, 0);
808 if (vcpu->vcpu_id == 0)
809 vcpu->apic_base |= MSR_IA32_APICBASE_BSP;
810 apic_update_ppr(apic);
811
812 apic_debug(KERN_INFO "%s: vcpu=%p, id=%d, base_msr="
813 "0x%016" PRIx64 ", base_address=0x%0lx.\n", __FUNCTION__,
814 vcpu, kvm_apic_id(apic),
815 vcpu->apic_base, apic->base_address);
816}
817
818int kvm_lapic_enabled(struct kvm_vcpu *vcpu)
819{
820 struct kvm_lapic *apic = (struct kvm_lapic *)vcpu->apic;
821 int ret = 0;
822
823 if (!apic)
824 return 0;
825 ret = apic_enabled(apic);
826
827 return ret;
828}
6e5d865c 829EXPORT_SYMBOL_GPL(kvm_lapic_enabled);
97222cc8
ED		 830
831/*
832 *----------------------------------------------------------------------
833 * timer interface
834 *----------------------------------------------------------------------
835 */
1b9778da
ED		 836
837/* TODO: make sure __apic_timer_fn runs in current pCPU */
97222cc8
ED		 838static int __apic_timer_fn(struct kvm_lapic *apic)
839{
97222cc8 840 int result = 0;
1b9778da 841 wait_queue_head_t *q = &apic->vcpu->wq;
97222cc8 842
97222cc8 843 atomic_inc(&apic->timer.pending);
1b9778da
ED		 844 if (waitqueue_active(q))
845 wake_up_interruptible(q);
97222cc8 846 if (apic_lvtt_period(apic)) {
97222cc8
ED		 847 result = 1;
848 apic->timer.dev.expires = ktime_add_ns(
849 apic->timer.dev.expires,
850 apic->timer.period);
851 }
97222cc8
ED		 852 return result;
853}
854
1b9778da
ED		 855static int __inject_apic_timer_irq(struct kvm_lapic *apic)
856{
857 int vector;
858
859 vector = apic_lvt_vector(apic, APIC_LVTT);
860 return __apic_accept_irq(apic, APIC_DM_FIXED, vector, 1, 0);
861}
862
97222cc8
ED		 863static enum hrtimer_restart apic_timer_fn(struct hrtimer *data)
864{
865 struct kvm_lapic *apic;
866 int restart_timer = 0;
867
868 apic = container_of(data, struct kvm_lapic, timer.dev);
869
870 restart_timer = __apic_timer_fn(apic);
871
872 if (restart_timer)
873 return HRTIMER_RESTART;
874 else
875 return HRTIMER_NORESTART;
876}
877
878int kvm_create_lapic(struct kvm_vcpu *vcpu)
879{
880 struct kvm_lapic *apic;
881
882 ASSERT(vcpu != NULL);
883 apic_debug("apic_init %d\n", vcpu->vcpu_id);
884
885 apic = kzalloc(sizeof(*apic), GFP_KERNEL);
886 if (!apic)
887 goto nomem;
888
889 vcpu->apic = apic;
890
891 apic->regs_page = alloc_page(GFP_KERNEL);
892 if (apic->regs_page == NULL) {
893 printk(KERN_ERR "malloc apic regs error for vcpu %x\n",
894 vcpu->vcpu_id);
895 goto nomem;
896 }
897 apic->regs = page_address(apic->regs_page);
898 memset(apic->regs, 0, PAGE_SIZE);
899 apic->vcpu = vcpu;
900
901 hrtimer_init(&apic->timer.dev, CLOCK_MONOTONIC, HRTIMER_MODE_ABS);
902 apic->timer.dev.function = apic_timer_fn;
903 apic->base_address = APIC_DEFAULT_PHYS_BASE;
904 vcpu->apic_base = APIC_DEFAULT_PHYS_BASE;
905
906 lapic_reset(vcpu);
907 apic->dev.read = apic_mmio_read;
908 apic->dev.write = apic_mmio_write;
909 apic->dev.in_range = apic_mmio_range;
910 apic->dev.private = apic;
911
912 return 0;
913nomem:
914 kvm_free_apic(apic);
915 return -ENOMEM;
916}
917EXPORT_SYMBOL_GPL(kvm_create_lapic);
918
919int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu)
920{
921 struct kvm_lapic *apic = vcpu->apic;
922 int highest_irr;
923
924 if (!apic || !apic_enabled(apic))
925 return -1;
926
6e5d865c 927 apic_update_ppr(apic);
97222cc8
ED		 928 highest_irr = apic_find_highest_irr(apic);
929 if ((highest_irr == -1) ||
930 ((highest_irr & 0xF0) <= apic_get_reg(apic, APIC_PROCPRI)))
931 return -1;
932 return highest_irr;
933}
934
1b9778da
ED		 935void kvm_inject_apic_timer_irqs(struct kvm_vcpu *vcpu)
936{
937 struct kvm_lapic *apic = vcpu->apic;
938
939 if (apic && apic_lvt_enabled(apic, APIC_LVTT) &&
940 atomic_read(&apic->timer.pending) > 0) {
941 if (__inject_apic_timer_irq(apic))
942 atomic_dec(&apic->timer.pending);
943 }
944}
945
946void kvm_apic_timer_intr_post(struct kvm_vcpu *vcpu, int vec)
947{
948 struct kvm_lapic *apic = vcpu->apic;
949
950 if (apic && apic_lvt_vector(apic, APIC_LVTT) == vec)
951 apic->timer.last_update = ktime_add_ns(
952 apic->timer.last_update,
953 apic->timer.period);
954}
955
97222cc8
ED		 956int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu)
957{
958 int vector = kvm_apic_has_interrupt(vcpu);
959 struct kvm_lapic *apic = vcpu->apic;
960
961 if (vector == -1)
962 return -1;
963
964 apic_set_vector(vector, apic->regs + APIC_ISR);
965 apic_update_ppr(apic);
966 apic_clear_irr(vector, apic);
967 return vector;
968}
96ad2cc6
ED		 969
970void kvm_apic_post_state_restore(struct kvm_vcpu *vcpu)
971{
972 struct kvm_lapic *apic = vcpu->apic;
973
974 apic->base_address = vcpu->apic_base &
975 MSR_IA32_APICBASE_BASE;
976 apic_set_reg(apic, APIC_LVR, APIC_VERSION);
977 apic_update_ppr(apic);
978 hrtimer_cancel(&apic->timer.dev);
979 update_divide_count(apic);
980 start_apic_timer(apic);
981}
Linux 6.x block layer and io_uring tree(s)