[linux-2.6-block.git] / drivers / isdn / hisax / icc.c

/* $Id: icc.c,v 1.8.2.3 2004/01/13 14:31:25 keil Exp $
 *
 * ICC specific routines
 *
 * Author       Matt Henderson & Guy Ellis
 * Copyright    by Traverse Technologies Pty Ltd, www.travers.com.au
 *
 * This software may be used and distributed according to the terms
 * of the GNU General Public License, incorporated herein by reference.
 *
 * 1999.6.25 Initial implementation of routines for Siemens ISDN
 * Communication Controller PEB 2070 based on the ISAC routines
 * written by Karsten Keil.
 *
 */

#include <linux/init.h>
#include "hisax.h"
#include "icc.h"
// #include "arcofi.h"
#include "isdnl1.h"
#include <linux/interrupt.h>
#include <linux/slab.h>

#define DBUSY_TIMER_VALUE 80
#define ARCOFI_USE 0

static char *ICCVer[] =
{"2070 A1/A3", "2070 B1", "2070 B2/B3", "2070 V2.4"};

void
ICCVersion(struct IsdnCardState *cs, char *s)
{
	int val;

	val = cs->readisac(cs, ICC_RBCH);
	printk(KERN_INFO "%s ICC version (%x): %s\n", s, val, ICCVer[(val >> 5) & 3]);
}

static void
ph_command(struct IsdnCardState *cs, unsigned int command)
{
	if (cs->debug & L1_DEB_ISAC)
		debugl1(cs, "ph_command %x", command);
	cs->writeisac(cs, ICC_CIX0, (command << 2) | 3);
}


static void
icc_new_ph(struct IsdnCardState *cs)
{
	switch (cs->dc.icc.ph_state) {
	case (ICC_IND_EI1):
		ph_command(cs, ICC_CMD_DI);
		l1_msg(cs, HW_RESET | INDICATION, NULL);
		break;
	case (ICC_IND_DC):
		l1_msg(cs, HW_DEACTIVATE | CONFIRM, NULL);
		break;
	case (ICC_IND_DR):
		l1_msg(cs, HW_DEACTIVATE | INDICATION, NULL);
		break;
	case (ICC_IND_PU):
		l1_msg(cs, HW_POWERUP | CONFIRM, NULL);
		break;
	case (ICC_IND_FJ):
		l1_msg(cs, HW_RSYNC | INDICATION, NULL);
		break;
	case (ICC_IND_AR):
		l1_msg(cs, HW_INFO2 | INDICATION, NULL);
		break;
	case (ICC_IND_AI):
		l1_msg(cs, HW_INFO4 | INDICATION, NULL);
		break;
	default:
		break;
	}
}

static void
icc_bh(struct work_struct *work)
{
	struct IsdnCardState *cs =
		container_of(work, struct IsdnCardState, tqueue);
	struct PStack *stptr;

	if (test_and_clear_bit(D_CLEARBUSY, &cs->event)) {
		if (cs->debug)
			debugl1(cs, "D-Channel Busy cleared");
		stptr = cs->stlist;
		while (stptr != NULL) {
			stptr->l1.l1l2(stptr, PH_PAUSE | CONFIRM, NULL);
			stptr = stptr->next;
		}
	}
	if (test_and_clear_bit(D_L1STATECHANGE, &cs->event))
		icc_new_ph(cs);
	if (test_and_clear_bit(D_RCVBUFREADY, &cs->event))
		DChannel_proc_rcv(cs);
	if (test_and_clear_bit(D_XMTBUFREADY, &cs->event))
		DChannel_proc_xmt(cs);
#if ARCOFI_USE
	if (!test_bit(HW_ARCOFI, &cs->HW_Flags))
		return;
	if (test_and_clear_bit(D_RX_MON1, &cs->event))
		arcofi_fsm(cs, ARCOFI_RX_END, NULL);
	if (test_and_clear_bit(D_TX_MON1, &cs->event))
		arcofi_fsm(cs, ARCOFI_TX_END, NULL);
#endif
}

static void
icc_empty_fifo(struct IsdnCardState *cs, int count)
{
	u_char *ptr;

	if ((cs->debug & L1_DEB_ISAC) && !(cs->debug & L1_DEB_ISAC_FIFO))
		debugl1(cs, "icc_empty_fifo");

	if ((cs->rcvidx + count) >= MAX_DFRAME_LEN_L1) {
		if (cs->debug & L1_DEB_WARN)
			debugl1(cs, "icc_empty_fifo overrun %d",
				cs->rcvidx + count);
		cs->writeisac(cs, ICC_CMDR, 0x80);
		cs->rcvidx = 0;
		return;
	}
	ptr = cs->rcvbuf + cs->rcvidx;
	cs->rcvidx += count;
	cs->readisacfifo(cs, ptr, count);
	cs->writeisac(cs, ICC_CMDR, 0x80);
	if (cs->debug & L1_DEB_ISAC_FIFO) {
		char *t = cs->dlog;

		t += sprintf(t, "icc_empty_fifo cnt %d", count);
		QuickHex(t, ptr, count);
		debugl1(cs, cs->dlog);
	}
}

static void
icc_fill_fifo(struct IsdnCardState *cs)
{
	int count, more;
	u_char *ptr;

	if ((cs->debug & L1_DEB_ISAC) && !(cs->debug & L1_DEB_ISAC_FIFO))
		debugl1(cs, "icc_fill_fifo");

	if (!cs->tx_skb)
		return;

	count = cs->tx_skb->len;
	if (count <= 0)
		return;

	more = 0;
	if (count > 32) {
		more = !0;
		count = 32;
	}
	ptr = cs->tx_skb->data;
	skb_pull(cs->tx_skb, count);
	cs->tx_cnt += count;
	cs->writeisacfifo(cs, ptr, count);
	cs->writeisac(cs, ICC_CMDR, more ? 0x8 : 0xa);
	if (test_and_set_bit(FLG_DBUSY_TIMER, &cs->HW_Flags)) {
		debugl1(cs, "icc_fill_fifo dbusytimer running");
		del_timer(&cs->dbusytimer);
	}
	init_timer(&cs->dbusytimer);
	cs->dbusytimer.expires = jiffies + ((DBUSY_TIMER_VALUE * HZ)/1000);
	add_timer(&cs->dbusytimer);
	if (cs->debug & L1_DEB_ISAC_FIFO) {
		char *t = cs->dlog;

		t += sprintf(t, "icc_fill_fifo cnt %d", count);
		QuickHex(t, ptr, count);
		debugl1(cs, cs->dlog);
	}
}

void
icc_interrupt(struct IsdnCardState *cs, u_char val)
{
	u_char exval, v1;
	struct sk_buff *skb;
	unsigned int count;

	if (cs->debug & L1_DEB_ISAC)
		debugl1(cs, "ICC interrupt %x", val);
	if (val & 0x80) {	/* RME */
		exval = cs->readisac(cs, ICC_RSTA);
		if ((exval & 0x70) != 0x20) {
			if (exval & 0x40) {
				if (cs->debug & L1_DEB_WARN)
					debugl1(cs, "ICC RDO");
#ifdef ERROR_STATISTIC
				cs->err_rx++;
#endif
			}
			if (!(exval & 0x20)) {
				if (cs->debug & L1_DEB_WARN)
					debugl1(cs, "ICC CRC error");
#ifdef ERROR_STATISTIC
				cs->err_crc++;
#endif
			}
			cs->writeisac(cs, ICC_CMDR, 0x80);
		} else {
			count = cs->readisac(cs, ICC_RBCL) & 0x1f;
			if (count == 0)
				count = 32;
			icc_empty_fifo(cs, count);
			if ((count = cs->rcvidx) > 0) {
				cs->rcvidx = 0;
				if (!(skb = alloc_skb(count, GFP_ATOMIC)))
					printk(KERN_WARNING "HiSax: D receive out of memory\n");
				else {
					memcpy(skb_put(skb, count), cs->rcvbuf, count);
					skb_queue_tail(&cs->rq, skb);
				}
			}
		}
		cs->rcvidx = 0;
		schedule_event(cs, D_RCVBUFREADY);
	}
	if (val & 0x40) {	/* RPF */
		icc_empty_fifo(cs, 32);
	}
	if (val & 0x20) {	/* RSC */
		/* never */
		if (cs->debug & L1_DEB_WARN)
			debugl1(cs, "ICC RSC interrupt");
	}
	if (val & 0x10) {	/* XPR */
		if (test_and_clear_bit(FLG_DBUSY_TIMER, &cs->HW_Flags))
			del_timer(&cs->dbusytimer);
		if (test_and_clear_bit(FLG_L1_DBUSY, &cs->HW_Flags))
			schedule_event(cs, D_CLEARBUSY);
		if (cs->tx_skb) {
			if (cs->tx_skb->len) {
				icc_fill_fifo(cs);
				goto afterXPR;
			} else {
				dev_kfree_skb_irq(cs->tx_skb);
				cs->tx_cnt = 0;
				cs->tx_skb = NULL;
			}
		}
		if ((cs->tx_skb = skb_dequeue(&cs->sq))) {
			cs->tx_cnt = 0;
			icc_fill_fifo(cs);
		} else
			schedule_event(cs, D_XMTBUFREADY);
	}
afterXPR:
	if (val & 0x04) {	/* CISQ */
		exval = cs->readisac(cs, ICC_CIR0);
		if (cs->debug & L1_DEB_ISAC)
			debugl1(cs, "ICC CIR0 %02X", exval);
		if (exval & 2) {
			cs->dc.icc.ph_state = (exval >> 2) & 0xf;
			if (cs->debug & L1_DEB_ISAC)
				debugl1(cs, "ph_state change %x", cs->dc.icc.ph_state);
			schedule_event(cs, D_L1STATECHANGE);
		}
		if (exval & 1) {
			exval = cs->readisac(cs, ICC_CIR1);
			if (cs->debug & L1_DEB_ISAC)
				debugl1(cs, "ICC CIR1 %02X", exval);
		}
	}
	if (val & 0x02) {	/* SIN */
		/* never */
		if (cs->debug & L1_DEB_WARN)
			debugl1(cs, "ICC SIN interrupt");
	}
	if (val & 0x01) {	/* EXI */
		exval = cs->readisac(cs, ICC_EXIR);
		if (cs->debug & L1_DEB_WARN)
			debugl1(cs, "ICC EXIR %02x", exval);
		if (exval & 0x80) {  /* XMR */
			debugl1(cs, "ICC XMR");
			printk(KERN_WARNING "HiSax: ICC XMR\n");
		}
		if (exval & 0x40) {  /* XDU */
			debugl1(cs, "ICC XDU");
			printk(KERN_WARNING "HiSax: ICC XDU\n");
#ifdef ERROR_STATISTIC
			cs->err_tx++;
#endif
			if (test_and_clear_bit(FLG_DBUSY_TIMER, &cs->HW_Flags))
				del_timer(&cs->dbusytimer);
			if (test_and_clear_bit(FLG_L1_DBUSY, &cs->HW_Flags))
				schedule_event(cs, D_CLEARBUSY);
			if (cs->tx_skb) { /* Restart frame */
				skb_push(cs->tx_skb, cs->tx_cnt);
				cs->tx_cnt = 0;
				icc_fill_fifo(cs);
			} else {
				printk(KERN_WARNING "HiSax: ICC XDU no skb\n");
				debugl1(cs, "ICC XDU no skb");
			}
		}
		if (exval & 0x04) {  /* MOS */
			v1 = cs->readisac(cs, ICC_MOSR);
			if (cs->debug & L1_DEB_MONITOR)
				debugl1(cs, "ICC MOSR %02x", v1);
#if ARCOFI_USE
			if (v1 & 0x08) {
				if (!cs->dc.icc.mon_rx) {
					if (!(cs->dc.icc.mon_rx = kmalloc(MAX_MON_FRAME, GFP_ATOMIC))) {
						if (cs->debug & L1_DEB_WARN)
							debugl1(cs, "ICC MON RX out of memory!");
						cs->dc.icc.mocr &= 0xf0;
						cs->dc.icc.mocr |= 0x0a;
						cs->writeisac(cs, ICC_MOCR, cs->dc.icc.mocr);
						goto afterMONR0;
					} else
						cs->dc.icc.mon_rxp = 0;
				}
				if (cs->dc.icc.mon_rxp >= MAX_MON_FRAME) {
					cs->dc.icc.mocr &= 0xf0;
					cs->dc.icc.mocr |= 0x0a;
					cs->writeisac(cs, ICC_MOCR, cs->dc.icc.mocr);
					cs->dc.icc.mon_rxp = 0;
					if (cs->debug & L1_DEB_WARN)
						debugl1(cs, "ICC MON RX overflow!");
					goto afterMONR0;
				}
				cs->dc.icc.mon_rx[cs->dc.icc.mon_rxp++] = cs->readisac(cs, ICC_MOR0);
				if (cs->debug & L1_DEB_MONITOR)
					debugl1(cs, "ICC MOR0 %02x", cs->dc.icc.mon_rx[cs->dc.icc.mon_rxp - 1]);
				if (cs->dc.icc.mon_rxp == 1) {
					cs->dc.icc.mocr |= 0x04;
					cs->writeisac(cs, ICC_MOCR, cs->dc.icc.mocr);
				}
			}
		afterMONR0:
			if (v1 & 0x80) {
				if (!cs->dc.icc.mon_rx) {
					if (!(cs->dc.icc.mon_rx = kmalloc(MAX_MON_FRAME, GFP_ATOMIC))) {
						if (cs->debug & L1_DEB_WARN)
							debugl1(cs, "ICC MON RX out of memory!");
						cs->dc.icc.mocr &= 0x0f;
						cs->dc.icc.mocr |= 0xa0;
						cs->writeisac(cs, ICC_MOCR, cs->dc.icc.mocr);
						goto afterMONR1;
					} else
						cs->dc.icc.mon_rxp = 0;
				}
				if (cs->dc.icc.mon_rxp >= MAX_MON_FRAME) {
					cs->dc.icc.mocr &= 0x0f;
					cs->dc.icc.mocr |= 0xa0;
					cs->writeisac(cs, ICC_MOCR, cs->dc.icc.mocr);
					cs->dc.icc.mon_rxp = 0;
					if (cs->debug & L1_DEB_WARN)
						debugl1(cs, "ICC MON RX overflow!");
					goto afterMONR1;
				}
				cs->dc.icc.mon_rx[cs->dc.icc.mon_rxp++] = cs->readisac(cs, ICC_MOR1);
				if (cs->debug & L1_DEB_MONITOR)
					debugl1(cs, "ICC MOR1 %02x", cs->dc.icc.mon_rx[cs->dc.icc.mon_rxp - 1]);
				cs->dc.icc.mocr |= 0x40;
				cs->writeisac(cs, ICC_MOCR, cs->dc.icc.mocr);
			}
		afterMONR1:
			if (v1 & 0x04) {
				cs->dc.icc.mocr &= 0xf0;
				cs->writeisac(cs, ICC_MOCR, cs->dc.icc.mocr);
				cs->dc.icc.mocr |= 0x0a;
				cs->writeisac(cs, ICC_MOCR, cs->dc.icc.mocr);
				schedule_event(cs, D_RX_MON0);
			}
			if (v1 & 0x40) {
				cs->dc.icc.mocr &= 0x0f;
				cs->writeisac(cs, ICC_MOCR, cs->dc.icc.mocr);
				cs->dc.icc.mocr |= 0xa0;
				cs->writeisac(cs, ICC_MOCR, cs->dc.icc.mocr);
				schedule_event(cs, D_RX_MON1);
			}
			if (v1 & 0x02) {
				if ((!cs->dc.icc.mon_tx) || (cs->dc.icc.mon_txc &&
							     (cs->dc.icc.mon_txp >= cs->dc.icc.mon_txc) &&
							     !(v1 & 0x08))) {
					cs->dc.icc.mocr &= 0xf0;
					cs->writeisac(cs, ICC_MOCR, cs->dc.icc.mocr);
					cs->dc.icc.mocr |= 0x0a;
					cs->writeisac(cs, ICC_MOCR, cs->dc.icc.mocr);
					if (cs->dc.icc.mon_txc &&
					    (cs->dc.icc.mon_txp >= cs->dc.icc.mon_txc))
						schedule_event(cs, D_TX_MON0);
					goto AfterMOX0;
				}
				if (cs->dc.icc.mon_txc && (cs->dc.icc.mon_txp >= cs->dc.icc.mon_txc)) {
					schedule_event(cs, D_TX_MON0);
					goto AfterMOX0;
				}
				cs->writeisac(cs, ICC_MOX0,
					      cs->dc.icc.mon_tx[cs->dc.icc.mon_txp++]);
				if (cs->debug & L1_DEB_MONITOR)
					debugl1(cs, "ICC %02x -> MOX0", cs->dc.icc.mon_tx[cs->dc.icc.mon_txp - 1]);
			}
		AfterMOX0:
			if (v1 & 0x20) {
				if ((!cs->dc.icc.mon_tx) || (cs->dc.icc.mon_txc &&
							     (cs->dc.icc.mon_txp >= cs->dc.icc.mon_txc) &&
							     !(v1 & 0x80))) {
					cs->dc.icc.mocr &= 0x0f;
					cs->writeisac(cs, ICC_MOCR, cs->dc.icc.mocr);
					cs->dc.icc.mocr |= 0xa0;
					cs->writeisac(cs, ICC_MOCR, cs->dc.icc.mocr);
					if (cs->dc.icc.mon_txc &&
					    (cs->dc.icc.mon_txp >= cs->dc.icc.mon_txc))
						schedule_event(cs, D_TX_MON1);
					goto AfterMOX1;
				}
				if (cs->dc.icc.mon_txc && (cs->dc.icc.mon_txp >= cs->dc.icc.mon_txc)) {
					schedule_event(cs, D_TX_MON1);
					goto AfterMOX1;
				}
				cs->writeisac(cs, ICC_MOX1,
					      cs->dc.icc.mon_tx[cs->dc.icc.mon_txp++]);
				if (cs->debug & L1_DEB_MONITOR)
					debugl1(cs, "ICC %02x -> MOX1", cs->dc.icc.mon_tx[cs->dc.icc.mon_txp - 1]);
			}
		AfterMOX1:
#endif
		}
	}
}

static void
ICC_l1hw(struct PStack *st, int pr, void *arg)
{
	struct IsdnCardState *cs = (struct IsdnCardState *) st->l1.hardware;
	struct sk_buff *skb = arg;
	u_long flags;
	int  val;

	switch (pr) {
	case (PH_DATA | REQUEST):
		if (cs->debug & DEB_DLOG_HEX)
			LogFrame(cs, skb->data, skb->len);
		if (cs->debug & DEB_DLOG_VERBOSE)
			dlogframe(cs, skb, 0);
		spin_lock_irqsave(&cs->lock, flags);
		if (cs->tx_skb) {
			skb_queue_tail(&cs->sq, skb);
#ifdef L2FRAME_DEBUG		/* psa */
			if (cs->debug & L1_DEB_LAPD)
				Logl2Frame(cs, skb, "PH_DATA Queued", 0);
#endif
		} else {
			cs->tx_skb = skb;
			cs->tx_cnt = 0;
#ifdef L2FRAME_DEBUG		/* psa */
			if (cs->debug & L1_DEB_LAPD)
				Logl2Frame(cs, skb, "PH_DATA", 0);
#endif
			icc_fill_fifo(cs);
		}
		spin_unlock_irqrestore(&cs->lock, flags);
		break;
	case (PH_PULL | INDICATION):
		spin_lock_irqsave(&cs->lock, flags);
		if (cs->tx_skb) {
			if (cs->debug & L1_DEB_WARN)
				debugl1(cs, " l2l1 tx_skb exist this shouldn't happen");
			skb_queue_tail(&cs->sq, skb);
			spin_unlock_irqrestore(&cs->lock, flags);
			break;
		}
		if (cs->debug & DEB_DLOG_HEX)
			LogFrame(cs, skb->data, skb->len);
		if (cs->debug & DEB_DLOG_VERBOSE)
			dlogframe(cs, skb, 0);
		cs->tx_skb = skb;
		cs->tx_cnt = 0;
#ifdef L2FRAME_DEBUG		/* psa */
		if (cs->debug & L1_DEB_LAPD)
			Logl2Frame(cs, skb, "PH_DATA_PULLED", 0);
#endif
		icc_fill_fifo(cs);
		spin_unlock_irqrestore(&cs->lock, flags);
		break;
	case (PH_PULL | REQUEST):
#ifdef L2FRAME_DEBUG		/* psa */
		if (cs->debug & L1_DEB_LAPD)
			debugl1(cs, "-> PH_REQUEST_PULL");
#endif
		if (!cs->tx_skb) {
			test_and_clear_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
			st->l1.l1l2(st, PH_PULL | CONFIRM, NULL);
		} else
			test_and_set_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
		break;
	case (HW_RESET | REQUEST):
		spin_lock_irqsave(&cs->lock, flags);
		if ((cs->dc.icc.ph_state == ICC_IND_EI1) ||
		    (cs->dc.icc.ph_state == ICC_IND_DR))
			ph_command(cs, ICC_CMD_DI);
		else
			ph_command(cs, ICC_CMD_RES);
		spin_unlock_irqrestore(&cs->lock, flags);
		break;
	case (HW_ENABLE | REQUEST):
		spin_lock_irqsave(&cs->lock, flags);
		ph_command(cs, ICC_CMD_DI);
		spin_unlock_irqrestore(&cs->lock, flags);
		break;
	case (HW_INFO1 | REQUEST):
		spin_lock_irqsave(&cs->lock, flags);
		ph_command(cs, ICC_CMD_AR);
		spin_unlock_irqrestore(&cs->lock, flags);
		break;
	case (HW_INFO3 | REQUEST):
		spin_lock_irqsave(&cs->lock, flags);
		ph_command(cs, ICC_CMD_AI);
		spin_unlock_irqrestore(&cs->lock, flags);
		break;
	case (HW_TESTLOOP | REQUEST):
		spin_lock_irqsave(&cs->lock, flags);
		val = 0;
		if (1 & (long) arg)
			val |= 0x0c;
		if (2 & (long) arg)
			val |= 0x3;
		if (test_bit(HW_IOM1, &cs->HW_Flags)) {
			/* IOM 1 Mode */
			if (!val) {
				cs->writeisac(cs, ICC_SPCR, 0xa);
				cs->writeisac(cs, ICC_ADF1, 0x2);
			} else {
				cs->writeisac(cs, ICC_SPCR, val);
				cs->writeisac(cs, ICC_ADF1, 0xa);
			}
		} else {
			/* IOM 2 Mode */
			cs->writeisac(cs, ICC_SPCR, val);
			if (val)
				cs->writeisac(cs, ICC_ADF1, 0x8);
			else
				cs->writeisac(cs, ICC_ADF1, 0x0);
		}
		spin_unlock_irqrestore(&cs->lock, flags);
		break;
	case (HW_DEACTIVATE | RESPONSE):
		skb_queue_purge(&cs->rq);
		skb_queue_purge(&cs->sq);
		if (cs->tx_skb) {
			dev_kfree_skb_any(cs->tx_skb);
			cs->tx_skb = NULL;
		}
		if (test_and_clear_bit(FLG_DBUSY_TIMER, &cs->HW_Flags))
			del_timer(&cs->dbusytimer);
		if (test_and_clear_bit(FLG_L1_DBUSY, &cs->HW_Flags))
			schedule_event(cs, D_CLEARBUSY);
		break;
	default:
		if (cs->debug & L1_DEB_WARN)
			debugl1(cs, "icc_l1hw unknown %04x", pr);
		break;
	}
}

static void
setstack_icc(struct PStack *st, struct IsdnCardState *cs)
{
	st->l1.l1hw = ICC_l1hw;
}

static void
DC_Close_icc(struct IsdnCardState *cs) {
	kfree(cs->dc.icc.mon_rx);
	cs->dc.icc.mon_rx = NULL;
	kfree(cs->dc.icc.mon_tx);
	cs->dc.icc.mon_tx = NULL;
}

static void
dbusy_timer_handler(struct IsdnCardState *cs)
{
	struct PStack *stptr;
	int	rbch, star;

	if (test_bit(FLG_DBUSY_TIMER, &cs->HW_Flags)) {
		rbch = cs->readisac(cs, ICC_RBCH);
		star = cs->readisac(cs, ICC_STAR);
		if (cs->debug)
			debugl1(cs, "D-Channel Busy RBCH %02x STAR %02x",
				rbch, star);
		if (rbch & ICC_RBCH_XAC) { /* D-Channel Busy */
			test_and_set_bit(FLG_L1_DBUSY, &cs->HW_Flags);
			stptr = cs->stlist;
			while (stptr != NULL) {
				stptr->l1.l1l2(stptr, PH_PAUSE | INDICATION, NULL);
				stptr = stptr->next;
			}
		} else {
			/* discard frame; reset transceiver */
			test_and_clear_bit(FLG_DBUSY_TIMER, &cs->HW_Flags);
			if (cs->tx_skb) {
				dev_kfree_skb_any(cs->tx_skb);
				cs->tx_cnt = 0;
				cs->tx_skb = NULL;
			} else {
				printk(KERN_WARNING "HiSax: ICC D-Channel Busy no skb\n");
				debugl1(cs, "D-Channel Busy no skb");
			}
			cs->writeisac(cs, ICC_CMDR, 0x01); /* Transmitter reset */
			cs->irq_func(cs->irq, cs);
		}
	}
}

void
initicc(struct IsdnCardState *cs)
{
	cs->setstack_d = setstack_icc;
	cs->DC_Close = DC_Close_icc;
	cs->dc.icc.mon_tx = NULL;
	cs->dc.icc.mon_rx = NULL;
	cs->writeisac(cs, ICC_MASK, 0xff);
	cs->dc.icc.mocr = 0xaa;
	if (test_bit(HW_IOM1, &cs->HW_Flags)) {
		/* IOM 1 Mode */
		cs->writeisac(cs, ICC_ADF2, 0x0);
		cs->writeisac(cs, ICC_SPCR, 0xa);
		cs->writeisac(cs, ICC_ADF1, 0x2);
		cs->writeisac(cs, ICC_STCR, 0x70);
		cs->writeisac(cs, ICC_MODE, 0xc9);
	} else {
		/* IOM 2 Mode */
		if (!cs->dc.icc.adf2)
			cs->dc.icc.adf2 = 0x80;
		cs->writeisac(cs, ICC_ADF2, cs->dc.icc.adf2);
		cs->writeisac(cs, ICC_SQXR, 0xa0);
		cs->writeisac(cs, ICC_SPCR, 0x20);
		cs->writeisac(cs, ICC_STCR, 0x70);
		cs->writeisac(cs, ICC_MODE, 0xca);
		cs->writeisac(cs, ICC_TIMR, 0x00);
		cs->writeisac(cs, ICC_ADF1, 0x20);
	}
	ph_command(cs, ICC_CMD_RES);
	cs->writeisac(cs, ICC_MASK, 0x0);
	ph_command(cs, ICC_CMD_DI);
}

void
clear_pending_icc_ints(struct IsdnCardState *cs)
{
	int val, eval;

	val = cs->readisac(cs, ICC_STAR);
	debugl1(cs, "ICC STAR %x", val);
	val = cs->readisac(cs, ICC_MODE);
	debugl1(cs, "ICC MODE %x", val);
	val = cs->readisac(cs, ICC_ADF2);
	debugl1(cs, "ICC ADF2 %x", val);
	val = cs->readisac(cs, ICC_ISTA);
	debugl1(cs, "ICC ISTA %x", val);
	if (val & 0x01) {
		eval = cs->readisac(cs, ICC_EXIR);
		debugl1(cs, "ICC EXIR %x", eval);
	}
	val = cs->readisac(cs, ICC_CIR0);
	debugl1(cs, "ICC CIR0 %x", val);
	cs->dc.icc.ph_state = (val >> 2) & 0xf;
	schedule_event(cs, D_L1STATECHANGE);
	/* Disable all IRQ */
	cs->writeisac(cs, ICC_MASK, 0xFF);
}

void setup_icc(struct IsdnCardState *cs)
{
	INIT_WORK(&cs->tqueue, icc_bh);
	cs->dbusytimer.function = (void *) dbusy_timer_handler;
	cs->dbusytimer.data = (long) cs;
	init_timer(&cs->dbusytimer);
}
Commit	Line	Data
1da177e4 LT	1	/* $Id: icc.c,v 1.8.2.3 2004/01/13 14:31:25 keil Exp $
	2	*
	3	* ICC specific routines
	4	*
	5	* Author Matt Henderson & Guy Ellis
	6	* Copyright by Traverse Technologies Pty Ltd, www.travers.com.au
475be4d8	7	*
1da177e4 LT	8	* This software may be used and distributed according to the terms
	9	* of the GNU General Public License, incorporated herein by reference.
	10	*
	11	* 1999.6.25 Initial implementation of routines for Siemens ISDN
	12	* Communication Controller PEB 2070 based on the ISAC routines
	13	* written by Karsten Keil.
	14	*
	15	*/
	16
	17	#include <linux/init.h>
	18	#include "hisax.h"
	19	#include "icc.h"
	20	// #include "arcofi.h"
	21	#include "isdnl1.h"
	22	#include <linux/interrupt.h>
5a0e3ad6	23	#include <linux/slab.h>
1da177e4 LT	24
	25	#define DBUSY_TIMER_VALUE 80
	26	#define ARCOFI_USE 0
	27
67eb5db5	28	static char *ICCVer[] =
1da177e4 LT	29	{"2070 A1/A3", "2070 B1", "2070 B2/B3", "2070 V2.4"};
1da177e4 LT	30
67eb5db5	31	void
1da177e4 LT	32	ICCVersion(struct IsdnCardState cs, char s)
	33	{
	34	int val;
	35
	36	val = cs->readisac(cs, ICC_RBCH);
	37	printk(KERN_INFO "%s ICC version (%x): %s\n", s, val, ICCVer[(val >> 5) & 3]);
	38	}
	39
	40	static void
	41	ph_command(struct IsdnCardState *cs, unsigned int command)
	42	{
	43	if (cs->debug & L1_DEB_ISAC)
	44	debugl1(cs, "ph_command %x", command);
	45	cs->writeisac(cs, ICC_CIX0, (command << 2) \| 3);
	46	}
	47
	48
	49	static void
	50	icc_new_ph(struct IsdnCardState *cs)
	51	{
	52	switch (cs->dc.icc.ph_state) {
475be4d8 JP	53	case (ICC_IND_EI1):
	54	ph_command(cs, ICC_CMD_DI);
	55	l1_msg(cs, HW_RESET \| INDICATION, NULL);
	56	break;
	57	case (ICC_IND_DC):
	58	l1_msg(cs, HW_DEACTIVATE \| CONFIRM, NULL);
	59	break;
	60	case (ICC_IND_DR):
	61	l1_msg(cs, HW_DEACTIVATE \| INDICATION, NULL);
	62	break;
	63	case (ICC_IND_PU):
	64	l1_msg(cs, HW_POWERUP \| CONFIRM, NULL);
	65	break;
	66	case (ICC_IND_FJ):
	67	l1_msg(cs, HW_RSYNC \| INDICATION, NULL);
	68	break;
	69	case (ICC_IND_AR):
	70	l1_msg(cs, HW_INFO2 \| INDICATION, NULL);
	71	break;
	72	case (ICC_IND_AI):
	73	l1_msg(cs, HW_INFO4 \| INDICATION, NULL);
	74	break;
	75	default:
	76	break;
1da177e4 LT	77	}
	78	}
	79
	80	static void
c4028958	81	icc_bh(struct work_struct *work)
1da177e4	82	{
c4028958 DH	83	struct IsdnCardState *cs =
c4028958 DH	84	container_of(work, struct IsdnCardState, tqueue);
1da177e4	85	struct PStack *stptr;
475be4d8	86
1da177e4 LT	87	if (test_and_clear_bit(D_CLEARBUSY, &cs->event)) {
	88	if (cs->debug)
	89	debugl1(cs, "D-Channel Busy cleared");
	90	stptr = cs->stlist;
	91	while (stptr != NULL) {
	92	stptr->l1.l1l2(stptr, PH_PAUSE \| CONFIRM, NULL);
	93	stptr = stptr->next;
	94	}
	95	}
	96	if (test_and_clear_bit(D_L1STATECHANGE, &cs->event))
475be4d8	97	icc_new_ph(cs);
1da177e4 LT	98	if (test_and_clear_bit(D_RCVBUFREADY, &cs->event))
	99	DChannel_proc_rcv(cs);
	100	if (test_and_clear_bit(D_XMTBUFREADY, &cs->event))
	101	DChannel_proc_xmt(cs);
	102	#if ARCOFI_USE
	103	if (!test_bit(HW_ARCOFI, &cs->HW_Flags))
	104	return;
	105	if (test_and_clear_bit(D_RX_MON1, &cs->event))
	106	arcofi_fsm(cs, ARCOFI_RX_END, NULL);
	107	if (test_and_clear_bit(D_TX_MON1, &cs->event))
	108	arcofi_fsm(cs, ARCOFI_TX_END, NULL);
	109	#endif
	110	}
	111
672c3fd9	112	static void
1da177e4 LT	113	icc_empty_fifo(struct IsdnCardState *cs, int count)
	114	{
	115	u_char *ptr;
	116
	117	if ((cs->debug & L1_DEB_ISAC) && !(cs->debug & L1_DEB_ISAC_FIFO))
	118	debugl1(cs, "icc_empty_fifo");
	119
	120	if ((cs->rcvidx + count) >= MAX_DFRAME_LEN_L1) {
	121	if (cs->debug & L1_DEB_WARN)
	122	debugl1(cs, "icc_empty_fifo overrun %d",
	123	cs->rcvidx + count);
	124	cs->writeisac(cs, ICC_CMDR, 0x80);
	125	cs->rcvidx = 0;
	126	return;
	127	}
	128	ptr = cs->rcvbuf + cs->rcvidx;
	129	cs->rcvidx += count;
	130	cs->readisacfifo(cs, ptr, count);
	131	cs->writeisac(cs, ICC_CMDR, 0x80);
	132	if (cs->debug & L1_DEB_ISAC_FIFO) {
	133	char *t = cs->dlog;
	134
	135	t += sprintf(t, "icc_empty_fifo cnt %d", count);
	136	QuickHex(t, ptr, count);
	137	debugl1(cs, cs->dlog);
	138	}
	139	}
	140
	141	static void
	142	icc_fill_fifo(struct IsdnCardState *cs)
	143	{
	144	int count, more;
	145	u_char *ptr;
	146
	147	if ((cs->debug & L1_DEB_ISAC) && !(cs->debug & L1_DEB_ISAC_FIFO))
	148	debugl1(cs, "icc_fill_fifo");
	149
	150	if (!cs->tx_skb)
	151	return;
	152
	153	count = cs->tx_skb->len;
	154	if (count <= 0)
	155	return;
	156
	157	more = 0;
	158	if (count > 32) {
	159	more = !0;
	160	count = 32;
	161	}
	162	ptr = cs->tx_skb->data;
	163	skb_pull(cs->tx_skb, count);
	164	cs->tx_cnt += count;
	165	cs->writeisacfifo(cs, ptr, count);
	166	cs->writeisac(cs, ICC_CMDR, more ? 0x8 : 0xa);
	167	if (test_and_set_bit(FLG_DBUSY_TIMER, &cs->HW_Flags)) {
	168	debugl1(cs, "icc_fill_fifo dbusytimer running");
	169	del_timer(&cs->dbusytimer);
	170	}
	171	init_timer(&cs->dbusytimer);
	172	cs->dbusytimer.expires = jiffies + ((DBUSY_TIMER_VALUE * HZ)/1000);
	173	add_timer(&cs->dbusytimer);
	174	if (cs->debug & L1_DEB_ISAC_FIFO) {
	175	char *t = cs->dlog;
	176
177	t += sprintf(t, "icc_fill_fifo cnt %d", count);
178	QuickHex(t, ptr, count);
179	debugl1(cs, cs->dlog);
180	}
181	}
182
183	void
184	icc_interrupt(struct IsdnCardState *cs, u_char val)
185	{
186	u_char exval, v1;
187	struct sk_buff *skb;
188	unsigned int count;
189
190	if (cs->debug & L1_DEB_ISAC)
191	debugl1(cs, "ICC interrupt %x", val);
192	if (val & 0x80) { /* RME */
193	exval = cs->readisac(cs, ICC_RSTA);
194	if ((exval & 0x70) != 0x20) {
195	if (exval & 0x40) {
196	if (cs->debug & L1_DEB_WARN)
197	debugl1(cs, "ICC RDO");
198	#ifdef ERROR_STATISTIC
199	cs->err_rx++;
200	#endif
201	}
202	if (!(exval & 0x20)) {
203	if (cs->debug & L1_DEB_WARN)
204	debugl1(cs, "ICC CRC error");
205	#ifdef ERROR_STATISTIC
206	cs->err_crc++;
207	#endif
208	}
209	cs->writeisac(cs, ICC_CMDR, 0x80);
210	} else {
211	count = cs->readisac(cs, ICC_RBCL) & 0x1f;
212	if (count == 0)
213	count = 32;
214	icc_empty_fifo(cs, count);
215	if ((count = cs->rcvidx) > 0) {
216	cs->rcvidx = 0;
217	if (!(skb = alloc_skb(count, GFP_ATOMIC)))
218	printk(KERN_WARNING "HiSax: D receive out of memory\n");
219	else {
220	memcpy(skb_put(skb, count), cs->rcvbuf, count);
221	skb_queue_tail(&cs->rq, skb);
222	}
223	}
224	}
225	cs->rcvidx = 0;
226	schedule_event(cs, D_RCVBUFREADY);
227	}
228	if (val & 0x40) { /* RPF */
229	icc_empty_fifo(cs, 32);
230	}
231	if (val & 0x20) { /* RSC */
232	/* never */
233	if (cs->debug & L1_DEB_WARN)
234	debugl1(cs, "ICC RSC interrupt");
235	}
236	if (val & 0x10) { /* XPR */
237	if (test_and_clear_bit(FLG_DBUSY_TIMER, &cs->HW_Flags))
238	del_timer(&cs->dbusytimer);
239	if (test_and_clear_bit(FLG_L1_DBUSY, &cs->HW_Flags))
240	schedule_event(cs, D_CLEARBUSY);
241	if (cs->tx_skb) {
242	if (cs->tx_skb->len) {
243	icc_fill_fifo(cs);
244	goto afterXPR;
245	} else {
246	dev_kfree_skb_irq(cs->tx_skb);
247	cs->tx_cnt = 0;
248	cs->tx_skb = NULL;
249	}
250	}
251	if ((cs->tx_skb = skb_dequeue(&cs->sq))) {
252	cs->tx_cnt = 0;
253	icc_fill_fifo(cs);
254	} else
255	schedule_event(cs, D_XMTBUFREADY);
256	}
475be4d8	257	afterXPR:
1da177e4 LT	258	if (val & 0x04) { /* CISQ */
	259	exval = cs->readisac(cs, ICC_CIR0);
	260	if (cs->debug & L1_DEB_ISAC)
475be4d8	261	debugl1(cs, "ICC CIR0 %02X", exval);
1da177e4 LT	262	if (exval & 2) {
	263	cs->dc.icc.ph_state = (exval >> 2) & 0xf;
	264	if (cs->debug & L1_DEB_ISAC)
	265	debugl1(cs, "ph_state change %x", cs->dc.icc.ph_state);
	266	schedule_event(cs, D_L1STATECHANGE);
	267	}
	268	if (exval & 1) {
	269	exval = cs->readisac(cs, ICC_CIR1);
	270	if (cs->debug & L1_DEB_ISAC)
475be4d8	271	debugl1(cs, "ICC CIR1 %02X", exval);
1da177e4 LT	272	}
	273	}
	274	if (val & 0x02) { /* SIN */
	275	/* never */
	276	if (cs->debug & L1_DEB_WARN)
	277	debugl1(cs, "ICC SIN interrupt");
	278	}
	279	if (val & 0x01) { /* EXI */
	280	exval = cs->readisac(cs, ICC_EXIR);
	281	if (cs->debug & L1_DEB_WARN)
	282	debugl1(cs, "ICC EXIR %02x", exval);
	283	if (exval & 0x80) { /* XMR */
	284	debugl1(cs, "ICC XMR");
	285	printk(KERN_WARNING "HiSax: ICC XMR\n");
	286	}
	287	if (exval & 0x40) { /* XDU */
	288	debugl1(cs, "ICC XDU");
	289	printk(KERN_WARNING "HiSax: ICC XDU\n");
	290	#ifdef ERROR_STATISTIC
	291	cs->err_tx++;
	292	#endif
	293	if (test_and_clear_bit(FLG_DBUSY_TIMER, &cs->HW_Flags))
	294	del_timer(&cs->dbusytimer);
	295	if (test_and_clear_bit(FLG_L1_DBUSY, &cs->HW_Flags))
	296	schedule_event(cs, D_CLEARBUSY);
	297	if (cs->tx_skb) { /* Restart frame */
	298	skb_push(cs->tx_skb, cs->tx_cnt);
	299	cs->tx_cnt = 0;
	300	icc_fill_fifo(cs);
	301	} else {
	302	printk(KERN_WARNING "HiSax: ICC XDU no skb\n");
	303	debugl1(cs, "ICC XDU no skb");
	304	}
	305	}
	306	if (exval & 0x04) { /* MOS */
	307	v1 = cs->readisac(cs, ICC_MOSR);
	308	if (cs->debug & L1_DEB_MONITOR)
	309	debugl1(cs, "ICC MOSR %02x", v1);
	310	#if ARCOFI_USE
	311	if (v1 & 0x08) {
	312	if (!cs->dc.icc.mon_rx) {
	313	if (!(cs->dc.icc.mon_rx = kmalloc(MAX_MON_FRAME, GFP_ATOMIC))) {
	314	if (cs->debug & L1_DEB_WARN)
	315	debugl1(cs, "ICC MON RX out of memory!");
	316	cs->dc.icc.mocr &= 0xf0;
	317	cs->dc.icc.mocr \|= 0x0a;
	318	cs->writeisac(cs, ICC_MOCR, cs->dc.icc.mocr);
	319	goto afterMONR0;
	320	} else
	321	cs->dc.icc.mon_rxp = 0;
	322	}
	323	if (cs->dc.icc.mon_rxp >= MAX_MON_FRAME) {
	324	cs->dc.icc.mocr &= 0xf0;
	325	cs->dc.icc.mocr \|= 0x0a;
	326	cs->writeisac(cs, ICC_MOCR, cs->dc.icc.mocr);
	327	cs->dc.icc.mon_rxp = 0;
	328	if (cs->debug & L1_DEB_WARN)
	329	debugl1(cs, "ICC MON RX overflow!");
	330	goto afterMONR0;
	331	}
	332	cs->dc.icc.mon_rx[cs->dc.icc.mon_rxp++] = cs->readisac(cs, ICC_MOR0);
	333	if (cs->debug & L1_DEB_MONITOR)
475be4d8	334	debugl1(cs, "ICC MOR0 %02x", cs->dc.icc.mon_rx[cs->dc.icc.mon_rxp - 1]);
1da177e4 LT	335	if (cs->dc.icc.mon_rxp == 1) {
	336	cs->dc.icc.mocr \|= 0x04;
	337	cs->writeisac(cs, ICC_MOCR, cs->dc.icc.mocr);
	338	}
	339	}
475be4d8	340	afterMONR0:
1da177e4 LT	341	if (v1 & 0x80) {
	342	if (!cs->dc.icc.mon_rx) {
	343	if (!(cs->dc.icc.mon_rx = kmalloc(MAX_MON_FRAME, GFP_ATOMIC))) {
	344	if (cs->debug & L1_DEB_WARN)
	345	debugl1(cs, "ICC MON RX out of memory!");
	346	cs->dc.icc.mocr &= 0x0f;
	347	cs->dc.icc.mocr \|= 0xa0;
	348	cs->writeisac(cs, ICC_MOCR, cs->dc.icc.mocr);
	349	goto afterMONR1;
	350	} else
	351	cs->dc.icc.mon_rxp = 0;
	352	}
	353	if (cs->dc.icc.mon_rxp >= MAX_MON_FRAME) {
	354	cs->dc.icc.mocr &= 0x0f;
	355	cs->dc.icc.mocr \|= 0xa0;
	356	cs->writeisac(cs, ICC_MOCR, cs->dc.icc.mocr);
	357	cs->dc.icc.mon_rxp = 0;
	358	if (cs->debug & L1_DEB_WARN)
	359	debugl1(cs, "ICC MON RX overflow!");
	360	goto afterMONR1;
	361	}
	362	cs->dc.icc.mon_rx[cs->dc.icc.mon_rxp++] = cs->readisac(cs, ICC_MOR1);
	363	if (cs->debug & L1_DEB_MONITOR)
475be4d8	364	debugl1(cs, "ICC MOR1 %02x", cs->dc.icc.mon_rx[cs->dc.icc.mon_rxp - 1]);
1da177e4 LT	365	cs->dc.icc.mocr \|= 0x40;
	366	cs->writeisac(cs, ICC_MOCR, cs->dc.icc.mocr);
	367	}
475be4d8	368	afterMONR1:
1da177e4 LT	369	if (v1 & 0x04) {
	370	cs->dc.icc.mocr &= 0xf0;
	371	cs->writeisac(cs, ICC_MOCR, cs->dc.icc.mocr);
	372	cs->dc.icc.mocr \|= 0x0a;
	373	cs->writeisac(cs, ICC_MOCR, cs->dc.icc.mocr);
	374	schedule_event(cs, D_RX_MON0);
	375	}
	376	if (v1 & 0x40) {
	377	cs->dc.icc.mocr &= 0x0f;
	378	cs->writeisac(cs, ICC_MOCR, cs->dc.icc.mocr);
	379	cs->dc.icc.mocr \|= 0xa0;
	380	cs->writeisac(cs, ICC_MOCR, cs->dc.icc.mocr);
	381	schedule_event(cs, D_RX_MON1);
	382	}
	383	if (v1 & 0x02) {
475be4d8 JP	384	if ((!cs->dc.icc.mon_tx) \|\| (cs->dc.icc.mon_txc &&
	385	(cs->dc.icc.mon_txp >= cs->dc.icc.mon_txc) &&
	386	!(v1 & 0x08))) {
1da177e4 LT	387	cs->dc.icc.mocr &= 0xf0;
	388	cs->writeisac(cs, ICC_MOCR, cs->dc.icc.mocr);
	389	cs->dc.icc.mocr \|= 0x0a;
	390	cs->writeisac(cs, ICC_MOCR, cs->dc.icc.mocr);
	391	if (cs->dc.icc.mon_txc &&
475be4d8	392	(cs->dc.icc.mon_txp >= cs->dc.icc.mon_txc))
1da177e4 LT	393	schedule_event(cs, D_TX_MON0);
	394	goto AfterMOX0;
	395	}
	396	if (cs->dc.icc.mon_txc && (cs->dc.icc.mon_txp >= cs->dc.icc.mon_txc)) {
	397	schedule_event(cs, D_TX_MON0);
	398	goto AfterMOX0;
	399	}
	400	cs->writeisac(cs, ICC_MOX0,
475be4d8	401	cs->dc.icc.mon_tx[cs->dc.icc.mon_txp++]);
1da177e4	402	if (cs->debug & L1_DEB_MONITOR)
475be4d8	403	debugl1(cs, "ICC %02x -> MOX0", cs->dc.icc.mon_tx[cs->dc.icc.mon_txp - 1]);
1da177e4	404	}
475be4d8	405	AfterMOX0:
1da177e4	406	if (v1 & 0x20) {
475be4d8 JP	407	if ((!cs->dc.icc.mon_tx) \|\| (cs->dc.icc.mon_txc &&
	408	(cs->dc.icc.mon_txp >= cs->dc.icc.mon_txc) &&
	409	!(v1 & 0x80))) {
1da177e4 LT	410	cs->dc.icc.mocr &= 0x0f;
	411	cs->writeisac(cs, ICC_MOCR, cs->dc.icc.mocr);
	412	cs->dc.icc.mocr \|= 0xa0;
	413	cs->writeisac(cs, ICC_MOCR, cs->dc.icc.mocr);
	414	if (cs->dc.icc.mon_txc &&
475be4d8	415	(cs->dc.icc.mon_txp >= cs->dc.icc.mon_txc))
1da177e4 LT	416	schedule_event(cs, D_TX_MON1);
	417	goto AfterMOX1;
	418	}
	419	if (cs->dc.icc.mon_txc && (cs->dc.icc.mon_txp >= cs->dc.icc.mon_txc)) {
	420	schedule_event(cs, D_TX_MON1);
	421	goto AfterMOX1;
	422	}
	423	cs->writeisac(cs, ICC_MOX1,
475be4d8	424	cs->dc.icc.mon_tx[cs->dc.icc.mon_txp++]);
1da177e4	425	if (cs->debug & L1_DEB_MONITOR)
475be4d8	426	debugl1(cs, "ICC %02x -> MOX1", cs->dc.icc.mon_tx[cs->dc.icc.mon_txp - 1]);
1da177e4	427	}
475be4d8	428	AfterMOX1:
1da177e4 LT	429	#endif
	430	}
	431	}
	432	}
	433
	434	static void
	435	ICC_l1hw(struct PStack st, int pr, void arg)
	436	{
	437	struct IsdnCardState cs = (struct IsdnCardState ) st->l1.hardware;
	438	struct sk_buff *skb = arg;
	439	u_long flags;
	440	int val;
	441
	442	switch (pr) {
475be4d8 JP	443	case (PH_DATA \| REQUEST):
	444	if (cs->debug & DEB_DLOG_HEX)
	445	LogFrame(cs, skb->data, skb->len);
	446	if (cs->debug & DEB_DLOG_VERBOSE)
	447	dlogframe(cs, skb, 0);
	448	spin_lock_irqsave(&cs->lock, flags);
	449	if (cs->tx_skb) {
	450	skb_queue_tail(&cs->sq, skb);
1da177e4	451	#ifdef L2FRAME_DEBUG /* psa */
475be4d8 JP	452	if (cs->debug & L1_DEB_LAPD)
475be4d8 JP	453	Logl2Frame(cs, skb, "PH_DATA Queued", 0);
1da177e4	454	#endif
475be4d8	455	} else {
1da177e4 LT	456	cs->tx_skb = skb;
	457	cs->tx_cnt = 0;
	458	#ifdef L2FRAME_DEBUG /* psa */
	459	if (cs->debug & L1_DEB_LAPD)
475be4d8	460	Logl2Frame(cs, skb, "PH_DATA", 0);
1da177e4 LT	461	#endif
1da177e4 LT	462	icc_fill_fifo(cs);
475be4d8 JP	463	}
	464	spin_unlock_irqrestore(&cs->lock, flags);
	465	break;
	466	case (PH_PULL \| INDICATION):
	467	spin_lock_irqsave(&cs->lock, flags);
	468	if (cs->tx_skb) {
	469	if (cs->debug & L1_DEB_WARN)
	470	debugl1(cs, " l2l1 tx_skb exist this shouldn't happen");
	471	skb_queue_tail(&cs->sq, skb);
1da177e4 LT	472	spin_unlock_irqrestore(&cs->lock, flags);
1da177e4 LT	473	break;
475be4d8 JP	474	}
	475	if (cs->debug & DEB_DLOG_HEX)
	476	LogFrame(cs, skb->data, skb->len);
	477	if (cs->debug & DEB_DLOG_VERBOSE)
	478	dlogframe(cs, skb, 0);
	479	cs->tx_skb = skb;
	480	cs->tx_cnt = 0;
1da177e4	481	#ifdef L2FRAME_DEBUG /* psa */
475be4d8 JP	482	if (cs->debug & L1_DEB_LAPD)
475be4d8 JP	483	Logl2Frame(cs, skb, "PH_DATA_PULLED", 0);
1da177e4	484	#endif
475be4d8 JP	485	icc_fill_fifo(cs);
	486	spin_unlock_irqrestore(&cs->lock, flags);
	487	break;
	488	case (PH_PULL \| REQUEST):
	489	#ifdef L2FRAME_DEBUG /* psa */
	490	if (cs->debug & L1_DEB_LAPD)
	491	debugl1(cs, "-> PH_REQUEST_PULL");
	492	#endif
	493	if (!cs->tx_skb) {
	494	test_and_clear_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
	495	st->l1.l1l2(st, PH_PULL \| CONFIRM, NULL);
	496	} else
	497	test_and_set_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
	498	break;
	499	case (HW_RESET \| REQUEST):
	500	spin_lock_irqsave(&cs->lock, flags);
	501	if ((cs->dc.icc.ph_state == ICC_IND_EI1) \|\|
	502	(cs->dc.icc.ph_state == ICC_IND_DR))
1da177e4	503	ph_command(cs, ICC_CMD_DI);
475be4d8 JP	504	else
	505	ph_command(cs, ICC_CMD_RES);
	506	spin_unlock_irqrestore(&cs->lock, flags);
	507	break;
	508	case (HW_ENABLE \| REQUEST):
	509	spin_lock_irqsave(&cs->lock, flags);
	510	ph_command(cs, ICC_CMD_DI);
	511	spin_unlock_irqrestore(&cs->lock, flags);
	512	break;
	513	case (HW_INFO1 \| REQUEST):
	514	spin_lock_irqsave(&cs->lock, flags);
	515	ph_command(cs, ICC_CMD_AR);
	516	spin_unlock_irqrestore(&cs->lock, flags);
	517	break;
	518	case (HW_INFO3 \| REQUEST):
	519	spin_lock_irqsave(&cs->lock, flags);
	520	ph_command(cs, ICC_CMD_AI);
	521	spin_unlock_irqrestore(&cs->lock, flags);
	522	break;
	523	case (HW_TESTLOOP \| REQUEST):
	524	spin_lock_irqsave(&cs->lock, flags);
	525	val = 0;
	526	if (1 & (long) arg)
	527	val \|= 0x0c;
	528	if (2 & (long) arg)
	529	val \|= 0x3;
	530	if (test_bit(HW_IOM1, &cs->HW_Flags)) {
	531	/* IOM 1 Mode */
	532	if (!val) {
	533	cs->writeisac(cs, ICC_SPCR, 0xa);
	534	cs->writeisac(cs, ICC_ADF1, 0x2);
1da177e4	535	} else {
1da177e4	536	cs->writeisac(cs, ICC_SPCR, val);
475be4d8	537	cs->writeisac(cs, ICC_ADF1, 0xa);
1da177e4	538	}
475be4d8 JP	539	} else {
	540	/* IOM 2 Mode */
	541	cs->writeisac(cs, ICC_SPCR, val);
	542	if (val)
	543	cs->writeisac(cs, ICC_ADF1, 0x8);
	544	else
	545	cs->writeisac(cs, ICC_ADF1, 0x0);
	546	}
	547	spin_unlock_irqrestore(&cs->lock, flags);
	548	break;
	549	case (HW_DEACTIVATE \| RESPONSE):
	550	skb_queue_purge(&cs->rq);
	551	skb_queue_purge(&cs->sq);
	552	if (cs->tx_skb) {
	553	dev_kfree_skb_any(cs->tx_skb);
	554	cs->tx_skb = NULL;
	555	}
	556	if (test_and_clear_bit(FLG_DBUSY_TIMER, &cs->HW_Flags))
	557	del_timer(&cs->dbusytimer);
	558	if (test_and_clear_bit(FLG_L1_DBUSY, &cs->HW_Flags))
	559	schedule_event(cs, D_CLEARBUSY);
	560	break;
	561	default:
	562	if (cs->debug & L1_DEB_WARN)
	563	debugl1(cs, "icc_l1hw unknown %04x", pr);
	564	break;
1da177e4 LT	565	}
	566	}
	567
672c3fd9	568	static void
1da177e4 LT	569	setstack_icc(struct PStack st, struct IsdnCardState cs)
	570	{
	571	st->l1.l1hw = ICC_l1hw;
	572	}
	573
672c3fd9	574	static void
1da177e4	575	DC_Close_icc(struct IsdnCardState *cs) {
3c7208f2 JJ	576	kfree(cs->dc.icc.mon_rx);
	577	cs->dc.icc.mon_rx = NULL;
	578	kfree(cs->dc.icc.mon_tx);
	579	cs->dc.icc.mon_tx = NULL;
1da177e4 LT	580	}
	581
	582	static void
	583	dbusy_timer_handler(struct IsdnCardState *cs)
	584	{
	585	struct PStack *stptr;
	586	int rbch, star;
	587
	588	if (test_bit(FLG_DBUSY_TIMER, &cs->HW_Flags)) {
	589	rbch = cs->readisac(cs, ICC_RBCH);
	590	star = cs->readisac(cs, ICC_STAR);
475be4d8	591	if (cs->debug)
1da177e4 LT	592	debugl1(cs, "D-Channel Busy RBCH %02x STAR %02x",
	593	rbch, star);
	594	if (rbch & ICC_RBCH_XAC) { /* D-Channel Busy */
	595	test_and_set_bit(FLG_L1_DBUSY, &cs->HW_Flags);
	596	stptr = cs->stlist;
	597	while (stptr != NULL) {
	598	stptr->l1.l1l2(stptr, PH_PAUSE \| INDICATION, NULL);
	599	stptr = stptr->next;
	600	}
	601	} else {
	602	/* discard frame; reset transceiver */
	603	test_and_clear_bit(FLG_DBUSY_TIMER, &cs->HW_Flags);
	604	if (cs->tx_skb) {
	605	dev_kfree_skb_any(cs->tx_skb);
	606	cs->tx_cnt = 0;
	607	cs->tx_skb = NULL;
	608	} else {
	609	printk(KERN_WARNING "HiSax: ICC D-Channel Busy no skb\n");
	610	debugl1(cs, "D-Channel Busy no skb");
	611	}
	612	cs->writeisac(cs, ICC_CMDR, 0x01); /* Transmitter reset */
7d12e780	613	cs->irq_func(cs->irq, cs);
1da177e4 LT	614	}
	615	}
	616	}
	617
67eb5db5	618	void
1da177e4 LT	619	initicc(struct IsdnCardState *cs)
	620	{
	621	cs->setstack_d = setstack_icc;
	622	cs->DC_Close = DC_Close_icc;
	623	cs->dc.icc.mon_tx = NULL;
	624	cs->dc.icc.mon_rx = NULL;
475be4d8 JP	625	cs->writeisac(cs, ICC_MASK, 0xff);
475be4d8 JP	626	cs->dc.icc.mocr = 0xaa;
1da177e4 LT	627	if (test_bit(HW_IOM1, &cs->HW_Flags)) {
	628	/* IOM 1 Mode */
	629	cs->writeisac(cs, ICC_ADF2, 0x0);
	630	cs->writeisac(cs, ICC_SPCR, 0xa);
	631	cs->writeisac(cs, ICC_ADF1, 0x2);
	632	cs->writeisac(cs, ICC_STCR, 0x70);
	633	cs->writeisac(cs, ICC_MODE, 0xc9);
	634	} else {
	635	/* IOM 2 Mode */
	636	if (!cs->dc.icc.adf2)
	637	cs->dc.icc.adf2 = 0x80;
	638	cs->writeisac(cs, ICC_ADF2, cs->dc.icc.adf2);
	639	cs->writeisac(cs, ICC_SQXR, 0xa0);
	640	cs->writeisac(cs, ICC_SPCR, 0x20);
	641	cs->writeisac(cs, ICC_STCR, 0x70);
	642	cs->writeisac(cs, ICC_MODE, 0xca);
	643	cs->writeisac(cs, ICC_TIMR, 0x00);
	644	cs->writeisac(cs, ICC_ADF1, 0x20);
	645	}
	646	ph_command(cs, ICC_CMD_RES);
	647	cs->writeisac(cs, ICC_MASK, 0x0);
	648	ph_command(cs, ICC_CMD_DI);
	649	}
	650
67eb5db5	651	void
1da177e4 LT	652	clear_pending_icc_ints(struct IsdnCardState *cs)
	653	{
	654	int val, eval;
	655
	656	val = cs->readisac(cs, ICC_STAR);
	657	debugl1(cs, "ICC STAR %x", val);
	658	val = cs->readisac(cs, ICC_MODE);
	659	debugl1(cs, "ICC MODE %x", val);
	660	val = cs->readisac(cs, ICC_ADF2);
	661	debugl1(cs, "ICC ADF2 %x", val);
	662	val = cs->readisac(cs, ICC_ISTA);
	663	debugl1(cs, "ICC ISTA %x", val);
	664	if (val & 0x01) {
	665	eval = cs->readisac(cs, ICC_EXIR);
	666	debugl1(cs, "ICC EXIR %x", eval);
	667	}
	668	val = cs->readisac(cs, ICC_CIR0);
	669	debugl1(cs, "ICC CIR0 %x", val);
	670	cs->dc.icc.ph_state = (val >> 2) & 0xf;
	671	schedule_event(cs, D_L1STATECHANGE);
	672	/* Disable all IRQ */
	673	cs->writeisac(cs, ICC_MASK, 0xFF);
	674	}
	675
ed5a84cd	676	void setup_icc(struct IsdnCardState *cs)
1da177e4	677	{
c4028958	678	INIT_WORK(&cs->tqueue, icc_bh);
1da177e4 LT	679	cs->dbusytimer.function = (void *) dbusy_timer_handler;
	680	cs->dbusytimer.data = (long) cs;
	681	init_timer(&cs->dbusytimer);
	682	}