[linux-block.git] / drivers / isdn / hisax / hfc_pci.h

/* $Id: hfc_pci.h,v 1.10.2.2 2004/01/12 22:52:26 keil Exp $
 *
 * specific defines for CCD's HFC 2BDS0 PCI chips
 *
 * Author       Werner Cornelius
 * Copyright    by Werner Cornelius  <werner@isdn4linux.de>
 * 
 * This software may be used and distributed according to the terms
 * of the GNU General Public License, incorporated herein by reference.
 *
 */

/*********************************************/
/* thresholds for transparent B-channel mode */
/* change mask and threshold simultaneously  */
/*********************************************/
#define HFCPCI_BTRANS_THRESHOLD 128
#define HFCPCI_BTRANS_THRESMASK 0x00


/* defines for PCI config */

#define PCI_ENA_MEMIO    0x02
#define PCI_ENA_MASTER   0x04


/* GCI/IOM bus monitor registers */

#define HCFPCI_C_I       0x08
#define HFCPCI_TRxR      0x0C
#define HFCPCI_MON1_D    0x28
#define HFCPCI_MON2_D    0x2C


/* GCI/IOM bus timeslot registers */

#define HFCPCI_B1_SSL    0x80
#define HFCPCI_B2_SSL    0x84
#define HFCPCI_AUX1_SSL  0x88
#define HFCPCI_AUX2_SSL  0x8C
#define HFCPCI_B1_RSL    0x90
#define HFCPCI_B2_RSL    0x94
#define HFCPCI_AUX1_RSL  0x98
#define HFCPCI_AUX2_RSL  0x9C

/* GCI/IOM bus data registers */

#define HFCPCI_B1_D      0xA0
#define HFCPCI_B2_D      0xA4
#define HFCPCI_AUX1_D    0xA8
#define HFCPCI_AUX2_D    0xAC

/* GCI/IOM bus configuration registers */

#define HFCPCI_MST_EMOD  0xB4
#define HFCPCI_MST_MODE	 0xB8
#define HFCPCI_CONNECT 	 0xBC


/* Interrupt and status registers */

#define HFCPCI_FIFO_EN   0x44
#define HFCPCI_TRM       0x48
#define HFCPCI_B_MODE    0x4C
#define HFCPCI_CHIP_ID   0x58
#define HFCPCI_CIRM  	 0x60
#define HFCPCI_CTMT	 0x64
#define HFCPCI_INT_M1  	 0x68
#define HFCPCI_INT_M2  	 0x6C
#define HFCPCI_INT_S1  	 0x78
#define HFCPCI_INT_S2  	 0x7C
#define HFCPCI_STATUS  	 0x70

/* S/T section registers */

#define HFCPCI_STATES  	 0xC0
#define HFCPCI_SCTRL  	 0xC4
#define HFCPCI_SCTRL_E   0xC8
#define HFCPCI_SCTRL_R   0xCC
#define HFCPCI_SQ  	 0xD0
#define HFCPCI_CLKDEL  	 0xDC
#define HFCPCI_B1_REC    0xF0
#define HFCPCI_B1_SEND   0xF0
#define HFCPCI_B2_REC    0xF4
#define HFCPCI_B2_SEND   0xF4
#define HFCPCI_D_REC     0xF8
#define HFCPCI_D_SEND    0xF8
#define HFCPCI_E_REC     0xFC


/* bits in status register (READ) */
#define HFCPCI_PCI_PROC   0x02
#define HFCPCI_NBUSY	  0x04 
#define HFCPCI_TIMER_ELAP 0x10
#define HFCPCI_STATINT	  0x20
#define HFCPCI_FRAMEINT	  0x40
#define HFCPCI_ANYINT	  0x80

/* bits in CTMT (Write) */
#define HFCPCI_CLTIMER    0x80
#define HFCPCI_TIM3_125   0x04
#define HFCPCI_TIM25      0x10
#define HFCPCI_TIM50      0x14
#define HFCPCI_TIM400     0x18
#define HFCPCI_TIM800     0x1C
#define HFCPCI_AUTO_TIMER 0x20
#define HFCPCI_TRANSB2    0x02
#define HFCPCI_TRANSB1    0x01

/* bits in CIRM (Write) */
#define HFCPCI_AUX_MSK    0x07
#define HFCPCI_RESET  	  0x08
#define HFCPCI_B1_REV     0x40
#define HFCPCI_B2_REV     0x80

/* bits in INT_M1 and INT_S1 */
#define HFCPCI_INTS_B1TRANS  0x01
#define HFCPCI_INTS_B2TRANS  0x02
#define HFCPCI_INTS_DTRANS   0x04
#define HFCPCI_INTS_B1REC    0x08
#define HFCPCI_INTS_B2REC    0x10
#define HFCPCI_INTS_DREC     0x20
#define HFCPCI_INTS_L1STATE  0x40
#define HFCPCI_INTS_TIMER    0x80

/* bits in INT_M2 */
#define HFCPCI_PROC_TRANS    0x01
#define HFCPCI_GCI_I_CHG     0x02
#define HFCPCI_GCI_MON_REC   0x04
#define HFCPCI_IRQ_ENABLE    0x08
#define HFCPCI_PMESEL        0x80

/* bits in STATES */
#define HFCPCI_STATE_MSK     0x0F
#define HFCPCI_LOAD_STATE    0x10
#define HFCPCI_ACTIVATE	     0x20
#define HFCPCI_DO_ACTION     0x40
#define HFCPCI_NT_G2_G3      0x80

/* bits in HFCD_MST_MODE */
#define HFCPCI_MASTER	     0x01
#define HFCPCI_SLAVE         0x00
/* remaining bits are for codecs control */

/* bits in HFCD_SCTRL */
#define SCTRL_B1_ENA	     0x01
#define SCTRL_B2_ENA	     0x02
#define SCTRL_MODE_TE        0x00
#define SCTRL_MODE_NT        0x04
#define SCTRL_LOW_PRIO	     0x08
#define SCTRL_SQ_ENA	     0x10
#define SCTRL_TEST	     0x20
#define SCTRL_NONE_CAP	     0x40
#define SCTRL_PWR_DOWN	     0x80

/* bits in SCTRL_E  */
#define HFCPCI_AUTO_AWAKE    0x01
#define HFCPCI_DBIT_1        0x04
#define HFCPCI_IGNORE_COL    0x08
#define HFCPCI_CHG_B1_B2     0x80

/****************************/
/* bits in FIFO_EN register */
/****************************/
#define HFCPCI_FIFOEN_B1     0x03
#define HFCPCI_FIFOEN_B2     0x0C
#define HFCPCI_FIFOEN_DTX    0x10
#define HFCPCI_FIFOEN_B1TX   0x01
#define HFCPCI_FIFOEN_B1RX   0x02
#define HFCPCI_FIFOEN_B2TX   0x04
#define HFCPCI_FIFOEN_B2RX   0x08


/***********************************/
/* definitions of fifo memory area */
/***********************************/
#define MAX_D_FRAMES 15
#define MAX_B_FRAMES 31
#define B_SUB_VAL    0x200
#define B_FIFO_SIZE  (0x2000 - B_SUB_VAL)
#define D_FIFO_SIZE  512
#define D_FREG_MASK  0xF

typedef struct {
    unsigned short z1;  /* Z1 pointer 16 Bit */
    unsigned short z2;  /* Z2 pointer 16 Bit */
  } z_type;

typedef struct {
    u_char data[D_FIFO_SIZE]; /* FIFO data space */
    u_char fill1[0x20A0-D_FIFO_SIZE]; /* reserved, do not use */
    u_char f1,f2; /* f pointers */
    u_char fill2[0x20C0-0x20A2]; /* reserved, do not use */
    z_type za[MAX_D_FRAMES+1]; /* mask index with D_FREG_MASK for access */
    u_char fill3[0x4000-0x2100]; /* align 16K */  
  } dfifo_type;

typedef struct {
    z_type za[MAX_B_FRAMES+1]; /* only range 0x0..0x1F allowed */ 
    u_char f1,f2; /* f pointers */
    u_char fill[0x2100-0x2082]; /* alignment */
  } bzfifo_type;


typedef union {
    struct { 
      dfifo_type d_tx; /* D-send channel */
      dfifo_type d_rx; /* D-receive channel */
    } d_chan; 
    struct {
      u_char fill1[0x200];
      u_char txdat_b1[B_FIFO_SIZE];
      bzfifo_type txbz_b1;

      bzfifo_type txbz_b2;
      u_char txdat_b2[B_FIFO_SIZE];

      u_char fill2[D_FIFO_SIZE];

      u_char rxdat_b1[B_FIFO_SIZE];
      bzfifo_type rxbz_b1;

      bzfifo_type rxbz_b2;
      u_char rxdat_b2[B_FIFO_SIZE];
    } b_chans;  
    u_char fill[32768]; 
  } fifo_area;


#define Write_hfc(a,b,c) (*(((u_char *)a->hw.hfcpci.pci_io)+b) = c) 
#define Read_hfc(a,b) (*(((u_char *)a->hw.hfcpci.pci_io)+b))

extern void main_irq_hcpci(struct BCState *bcs);
extern void releasehfcpci(struct IsdnCardState *cs);
Commit	Line	Data
1da177e4 LT	1	/* $Id: hfc_pci.h,v 1.10.2.2 2004/01/12 22:52:26 keil Exp $
	2	*
	3	* specific defines for CCD's HFC 2BDS0 PCI chips
	4	*
	5	* Author Werner Cornelius
	6	* Copyright by Werner Cornelius <werner@isdn4linux.de>
	7	*
	8	* This software may be used and distributed according to the terms
	9	* of the GNU General Public License, incorporated herein by reference.
	10	*
	11	*/
	12
	13	/*********************************************/
	14	/* thresholds for transparent B-channel mode */
	15	/* change mask and threshold simultaneously */
	16	/*********************************************/
	17	#define HFCPCI_BTRANS_THRESHOLD 128
	18	#define HFCPCI_BTRANS_THRESMASK 0x00
	19
	20
	21
	22	/* defines for PCI config */
	23
	24	#define PCI_ENA_MEMIO 0x02
	25	#define PCI_ENA_MASTER 0x04
	26
	27
	28	/* GCI/IOM bus monitor registers */
	29
	30	#define HCFPCI_C_I 0x08
	31	#define HFCPCI_TRxR 0x0C
	32	#define HFCPCI_MON1_D 0x28
	33	#define HFCPCI_MON2_D 0x2C
	34
	35
	36	/* GCI/IOM bus timeslot registers */
	37
	38	#define HFCPCI_B1_SSL 0x80
	39	#define HFCPCI_B2_SSL 0x84
	40	#define HFCPCI_AUX1_SSL 0x88
	41	#define HFCPCI_AUX2_SSL 0x8C
	42	#define HFCPCI_B1_RSL 0x90
	43	#define HFCPCI_B2_RSL 0x94
	44	#define HFCPCI_AUX1_RSL 0x98
	45	#define HFCPCI_AUX2_RSL 0x9C
	46
	47	/* GCI/IOM bus data registers */
	48
	49	#define HFCPCI_B1_D 0xA0
	50	#define HFCPCI_B2_D 0xA4
	51	#define HFCPCI_AUX1_D 0xA8
	52	#define HFCPCI_AUX2_D 0xAC
	53
	54	/* GCI/IOM bus configuration registers */
	55
	56	#define HFCPCI_MST_EMOD 0xB4
	57	#define HFCPCI_MST_MODE 0xB8
	58	#define HFCPCI_CONNECT 0xBC
	59
	60
	61	/* Interrupt and status registers */
	62
	63	#define HFCPCI_FIFO_EN 0x44
	64	#define HFCPCI_TRM 0x48
65	#define HFCPCI_B_MODE 0x4C
66	#define HFCPCI_CHIP_ID 0x58
67	#define HFCPCI_CIRM 0x60
68	#define HFCPCI_CTMT 0x64
69	#define HFCPCI_INT_M1 0x68
70	#define HFCPCI_INT_M2 0x6C
71	#define HFCPCI_INT_S1 0x78
72	#define HFCPCI_INT_S2 0x7C
73	#define HFCPCI_STATUS 0x70
74
75	/* S/T section registers */
76
77	#define HFCPCI_STATES 0xC0
78	#define HFCPCI_SCTRL 0xC4
79	#define HFCPCI_SCTRL_E 0xC8
80	#define HFCPCI_SCTRL_R 0xCC
81	#define HFCPCI_SQ 0xD0
82	#define HFCPCI_CLKDEL 0xDC
83	#define HFCPCI_B1_REC 0xF0
84	#define HFCPCI_B1_SEND 0xF0
85	#define HFCPCI_B2_REC 0xF4
86	#define HFCPCI_B2_SEND 0xF4
87	#define HFCPCI_D_REC 0xF8
88	#define HFCPCI_D_SEND 0xF8
89	#define HFCPCI_E_REC 0xFC
90
91
92	/* bits in status register (READ) */
93	#define HFCPCI_PCI_PROC 0x02
94	#define HFCPCI_NBUSY 0x04
95	#define HFCPCI_TIMER_ELAP 0x10
96	#define HFCPCI_STATINT 0x20
97	#define HFCPCI_FRAMEINT 0x40
98	#define HFCPCI_ANYINT 0x80
99
100	/* bits in CTMT (Write) */
101	#define HFCPCI_CLTIMER 0x80
102	#define HFCPCI_TIM3_125 0x04
103	#define HFCPCI_TIM25 0x10
104	#define HFCPCI_TIM50 0x14
105	#define HFCPCI_TIM400 0x18
106	#define HFCPCI_TIM800 0x1C
107	#define HFCPCI_AUTO_TIMER 0x20
108	#define HFCPCI_TRANSB2 0x02
109	#define HFCPCI_TRANSB1 0x01
110
111	/* bits in CIRM (Write) */
112	#define HFCPCI_AUX_MSK 0x07
113	#define HFCPCI_RESET 0x08
114	#define HFCPCI_B1_REV 0x40
115	#define HFCPCI_B2_REV 0x80
116
117	/* bits in INT_M1 and INT_S1 */
118	#define HFCPCI_INTS_B1TRANS 0x01
119	#define HFCPCI_INTS_B2TRANS 0x02
120	#define HFCPCI_INTS_DTRANS 0x04
121	#define HFCPCI_INTS_B1REC 0x08
122	#define HFCPCI_INTS_B2REC 0x10
123	#define HFCPCI_INTS_DREC 0x20
124	#define HFCPCI_INTS_L1STATE 0x40
125	#define HFCPCI_INTS_TIMER 0x80
126
127	/* bits in INT_M2 */
128	#define HFCPCI_PROC_TRANS 0x01
129	#define HFCPCI_GCI_I_CHG 0x02
130	#define HFCPCI_GCI_MON_REC 0x04
131	#define HFCPCI_IRQ_ENABLE 0x08
132	#define HFCPCI_PMESEL 0x80
133
134	/* bits in STATES */
135	#define HFCPCI_STATE_MSK 0x0F
136	#define HFCPCI_LOAD_STATE 0x10
137	#define HFCPCI_ACTIVATE 0x20
138	#define HFCPCI_DO_ACTION 0x40
139	#define HFCPCI_NT_G2_G3 0x80
140
141	/* bits in HFCD_MST_MODE */
142	#define HFCPCI_MASTER 0x01
143	#define HFCPCI_SLAVE 0x00
144	/* remaining bits are for codecs control */
145
146	/* bits in HFCD_SCTRL */
147	#define SCTRL_B1_ENA 0x01
148	#define SCTRL_B2_ENA 0x02
149	#define SCTRL_MODE_TE 0x00
150	#define SCTRL_MODE_NT 0x04
151	#define SCTRL_LOW_PRIO 0x08
152	#define SCTRL_SQ_ENA 0x10
153	#define SCTRL_TEST 0x20
154	#define SCTRL_NONE_CAP 0x40
155	#define SCTRL_PWR_DOWN 0x80
156
157	/* bits in SCTRL_E */
158	#define HFCPCI_AUTO_AWAKE 0x01
159	#define HFCPCI_DBIT_1 0x04
160	#define HFCPCI_IGNORE_COL 0x08
161	#define HFCPCI_CHG_B1_B2 0x80
162
163	/****************************/
164	/* bits in FIFO_EN register */
165	/****************************/
166	#define HFCPCI_FIFOEN_B1 0x03
167	#define HFCPCI_FIFOEN_B2 0x0C
168	#define HFCPCI_FIFOEN_DTX 0x10
169	#define HFCPCI_FIFOEN_B1TX 0x01
170	#define HFCPCI_FIFOEN_B1RX 0x02
171	#define HFCPCI_FIFOEN_B2TX 0x04
172	#define HFCPCI_FIFOEN_B2RX 0x08
173
174
175	/***********************************/
176	/* definitions of fifo memory area */
177	/***********************************/
178	#define MAX_D_FRAMES 15
179	#define MAX_B_FRAMES 31
180	#define B_SUB_VAL 0x200
181	#define B_FIFO_SIZE (0x2000 - B_SUB_VAL)
182	#define D_FIFO_SIZE 512
183	#define D_FREG_MASK 0xF
184
185	typedef struct {
186	unsigned short z1; /* Z1 pointer 16 Bit */
187	unsigned short z2; /* Z2 pointer 16 Bit */
188	} z_type;
189
190	typedef struct {
191	u_char data[D_FIFO_SIZE]; /* FIFO data space */
192	u_char fill1[0x20A0-D_FIFO_SIZE]; /* reserved, do not use */
193	u_char f1,f2; /* f pointers */
194	u_char fill2[0x20C0-0x20A2]; /* reserved, do not use */
195	z_type za[MAX_D_FRAMES+1]; /* mask index with D_FREG_MASK for access */
196	u_char fill3[0x4000-0x2100]; /* align 16K */
197	} dfifo_type;
198
199	typedef struct {
200	z_type za[MAX_B_FRAMES+1]; /* only range 0x0..0x1F allowed */
201	u_char f1,f2; /* f pointers */
202	u_char fill[0x2100-0x2082]; /* alignment */
203	} bzfifo_type;
204
205
206	typedef union {
207	struct {
208	dfifo_type d_tx; /* D-send channel */
209	dfifo_type d_rx; /* D-receive channel */
210	} d_chan;
211	struct {
212	u_char fill1[0x200];
213	u_char txdat_b1[B_FIFO_SIZE];
214	bzfifo_type txbz_b1;
215
216	bzfifo_type txbz_b2;
217	u_char txdat_b2[B_FIFO_SIZE];
218
219	u_char fill2[D_FIFO_SIZE];
220
221	u_char rxdat_b1[B_FIFO_SIZE];
222	bzfifo_type rxbz_b1;
223
224	bzfifo_type rxbz_b2;
225	u_char rxdat_b2[B_FIFO_SIZE];
226	} b_chans;
227	u_char fill[32768];
228	} fifo_area;
229
230
231	#define Write_hfc(a,b,c) ((((u_char )a->hw.hfcpci.pci_io)+b) = c)
232	#define Read_hfc(a,b) ((((u_char )a->hw.hfcpci.pci_io)+b))
233
234	extern void main_irq_hcpci(struct BCState *bcs);
1da177e4	235	extern void releasehfcpci(struct IsdnCardState *cs);