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1da177e4 LT |
1 | /*************************************************************************/ |
2 | /* $Id: hfc4s8s_l1.c,v 1.10 2005/02/09 16:31:09 martinb1 Exp $ */ | |
3 | /* HFC-4S/8S low layer interface for Cologne Chip HFC-4S/8S isdn chips */ | |
4 | /* The low layer (L1) is implemented as a loadable module for usage with */ | |
5 | /* the HiSax isdn driver for passive cards. */ | |
6 | /* */ | |
7 | /* Author: Werner Cornelius */ | |
8 | /* (C) 2003 Cornelius Consult (werner@cornelius-consult.de) */ | |
9 | /* */ | |
10 | /* Driver maintained by Cologne Chip */ | |
11 | /* - Martin Bachem, support@colognechip.com */ | |
12 | /* */ | |
13 | /* This driver only works with chip revisions >= 1, older revision 0 */ | |
14 | /* engineering samples (only first manufacturer sample cards) will not */ | |
15 | /* work and are rejected by the driver. */ | |
16 | /* */ | |
17 | /* This file distributed under the GNU GPL. */ | |
18 | /* */ | |
19 | /* See Version History at the end of this file */ | |
20 | /* */ | |
21 | /*************************************************************************/ | |
22 | ||
23 | #include <linux/module.h> | |
24 | #include <linux/init.h> | |
1da177e4 LT |
25 | #include <linux/pci.h> |
26 | #include <linux/interrupt.h> | |
27 | #include <linux/delay.h> | |
28 | #include <linux/timer.h> | |
29 | #include <linux/skbuff.h> | |
30 | #include <linux/wait.h> | |
a62e7cef | 31 | #include <asm/io.h> |
1da177e4 LT |
32 | #include "hisax_if.h" |
33 | #include "hfc4s8s_l1.h" | |
34 | ||
35 | static const char hfc4s8s_rev[] = "Revision: 1.10"; | |
36 | ||
37 | /***************************************************************/ | |
38 | /* adjustable transparent mode fifo threshold */ | |
39 | /* The value defines the used fifo threshold with the equation */ | |
40 | /* */ | |
41 | /* notify number of bytes = 2 * 2 ^ TRANS_FIFO_THRES */ | |
42 | /* */ | |
43 | /* The default value is 5 which results in a buffer size of 64 */ | |
44 | /* and an interrupt rate of 8ms. */ | |
45 | /* The maximum value is 7 due to fifo size restrictions. */ | |
46 | /* Values below 3-4 are not recommended due to high interrupt */ | |
47 | /* load of the processor. For non critical applications the */ | |
48 | /* value should be raised to 7 to reduce any interrupt overhead*/ | |
49 | /***************************************************************/ | |
50 | #define TRANS_FIFO_THRES 5 | |
51 | ||
52 | /*************/ | |
53 | /* constants */ | |
54 | /*************/ | |
55 | #define CLOCKMODE_0 0 /* ext. 24.576 MhZ clk freq, int. single clock mode */ | |
56 | #define CLOCKMODE_1 1 /* ext. 49.576 MhZ clk freq, int. single clock mode */ | |
57 | #define CHIP_ID_SHIFT 4 | |
58 | #define HFC_MAX_ST 8 | |
59 | #define MAX_D_FRAME_SIZE 270 | |
60 | #define MAX_B_FRAME_SIZE 1536 | |
61 | #define TRANS_TIMER_MODE (TRANS_FIFO_THRES & 0xf) | |
62 | #define TRANS_FIFO_BYTES (2 << TRANS_FIFO_THRES) | |
63 | #define MAX_F_CNT 0x0f | |
64 | ||
65 | #define CLKDEL_NT 0x6c | |
66 | #define CLKDEL_TE 0xf | |
67 | #define CTRL0_NT 4 | |
68 | #define CTRL0_TE 0 | |
69 | ||
70 | #define L1_TIMER_T4 2 /* minimum in jiffies */ | |
71 | #define L1_TIMER_T3 (7 * HZ) /* activation timeout */ | |
72 | #define L1_TIMER_T1 ((120 * HZ) / 1000) /* NT mode deactivation timeout */ | |
73 | ||
74 | ||
75 | /******************/ | |
76 | /* types and vars */ | |
77 | /******************/ | |
78 | static int card_cnt; | |
79 | ||
80 | /* private driver_data */ | |
81 | typedef struct { | |
82 | int chip_id; | |
83 | int clock_mode; | |
84 | int max_st_ports; | |
85 | char *device_name; | |
86 | } hfc4s8s_param; | |
87 | ||
88 | static struct pci_device_id hfc4s8s_ids[] = { | |
89 | {.vendor = PCI_VENDOR_ID_CCD, | |
90 | .device = PCI_DEVICE_ID_4S, | |
91 | .subvendor = 0x1397, | |
92 | .subdevice = 0x08b4, | |
93 | .driver_data = | |
94 | (unsigned long) &((hfc4s8s_param) {CHIP_ID_4S, CLOCKMODE_0, 4, | |
95 | "HFC-4S Evaluation Board"}), | |
96 | }, | |
97 | {.vendor = PCI_VENDOR_ID_CCD, | |
98 | .device = PCI_DEVICE_ID_8S, | |
99 | .subvendor = 0x1397, | |
100 | .subdevice = 0x16b8, | |
101 | .driver_data = | |
102 | (unsigned long) &((hfc4s8s_param) {CHIP_ID_8S, CLOCKMODE_0, 8, | |
103 | "HFC-8S Evaluation Board"}), | |
104 | }, | |
105 | {.vendor = PCI_VENDOR_ID_CCD, | |
106 | .device = PCI_DEVICE_ID_4S, | |
107 | .subvendor = 0x1397, | |
108 | .subdevice = 0xb520, | |
109 | .driver_data = | |
110 | (unsigned long) &((hfc4s8s_param) {CHIP_ID_4S, CLOCKMODE_1, 4, | |
111 | "IOB4ST"}), | |
112 | }, | |
113 | {.vendor = PCI_VENDOR_ID_CCD, | |
114 | .device = PCI_DEVICE_ID_8S, | |
115 | .subvendor = 0x1397, | |
116 | .subdevice = 0xb522, | |
117 | .driver_data = | |
118 | (unsigned long) &((hfc4s8s_param) {CHIP_ID_8S, CLOCKMODE_1, 8, | |
119 | "IOB8ST"}), | |
120 | }, | |
121 | {} | |
122 | }; | |
123 | ||
124 | MODULE_DEVICE_TABLE(pci, hfc4s8s_ids); | |
125 | ||
126 | MODULE_AUTHOR("Werner Cornelius, werner@cornelius-consult.de"); | |
127 | MODULE_DESCRIPTION("ISDN layer 1 for Cologne Chip HFC-4S/8S chips"); | |
128 | MODULE_LICENSE("GPL"); | |
129 | ||
130 | /***********/ | |
131 | /* layer 1 */ | |
132 | /***********/ | |
133 | struct hfc4s8s_btype { | |
134 | spinlock_t lock; | |
135 | struct hisax_b_if b_if; | |
136 | struct hfc4s8s_l1 *l1p; | |
137 | struct sk_buff_head tx_queue; | |
138 | struct sk_buff *tx_skb; | |
139 | struct sk_buff *rx_skb; | |
140 | __u8 *rx_ptr; | |
141 | int tx_cnt; | |
142 | int bchan; | |
143 | int mode; | |
144 | }; | |
145 | ||
146 | struct _hfc4s8s_hw; | |
147 | ||
148 | struct hfc4s8s_l1 { | |
149 | spinlock_t lock; | |
150 | struct _hfc4s8s_hw *hw; /* pointer to hardware area */ | |
151 | int l1_state; /* actual l1 state */ | |
152 | struct timer_list l1_timer; /* layer 1 timer structure */ | |
153 | int nt_mode; /* set to nt mode */ | |
154 | int st_num; /* own index */ | |
155 | int enabled; /* interface is enabled */ | |
156 | struct sk_buff_head d_tx_queue; /* send queue */ | |
157 | int tx_cnt; /* bytes to send */ | |
158 | struct hisax_d_if d_if; /* D-channel interface */ | |
159 | struct hfc4s8s_btype b_ch[2]; /* B-channel data */ | |
160 | struct hisax_b_if *b_table[2]; | |
161 | }; | |
162 | ||
163 | /**********************/ | |
164 | /* hardware structure */ | |
165 | /**********************/ | |
166 | typedef struct _hfc4s8s_hw { | |
167 | spinlock_t lock; | |
168 | ||
169 | int cardnum; | |
170 | int ifnum; | |
171 | int iobase; | |
172 | int nt_mode; | |
173 | u_char *membase; | |
174 | u_char *hw_membase; | |
175 | void *pdev; | |
176 | int max_fifo; | |
177 | hfc4s8s_param driver_data; | |
178 | int irq; | |
179 | int fifo_sched_cnt; | |
180 | struct work_struct tqueue; | |
181 | struct hfc4s8s_l1 l1[HFC_MAX_ST]; | |
182 | char card_name[60]; | |
183 | struct { | |
184 | u_char r_irq_ctrl; | |
185 | u_char r_ctrl0; | |
186 | volatile u_char r_irq_statech; /* active isdn l1 status */ | |
187 | u_char r_irqmsk_statchg; /* enabled isdn status ints */ | |
188 | u_char r_irq_fifo_blx[8]; /* fifo status registers */ | |
189 | u_char fifo_rx_trans_enables[8]; /* mask for enabled transparent rx fifos */ | |
190 | u_char fifo_slow_timer_service[8]; /* mask for fifos needing slower timer service */ | |
191 | volatile u_char r_irq_oview; /* contents of overview register */ | |
192 | volatile u_char timer_irq; | |
193 | int timer_usg_cnt; /* number of channels using timer */ | |
194 | } mr; | |
195 | } hfc4s8s_hw; | |
196 | ||
197 | ||
198 | ||
199 | /***************************/ | |
200 | /* inline function defines */ | |
201 | /***************************/ | |
202 | #ifdef CONFIG_HISAX_HFC4S8S_PCIMEM /* inline functions mempry mapped */ | |
203 | ||
204 | /* memory write and dummy IO read to avoid PCI byte merge problems */ | |
205 | #define Write_hfc8(a,b,c) {(*((volatile u_char *)(a->membase+b)) = c); inb(a->iobase+4);} | |
206 | /* memory write without dummy IO access for fifo data access */ | |
207 | #define fWrite_hfc8(a,b,c) (*((volatile u_char *)(a->membase+b)) = c) | |
208 | #define Read_hfc8(a,b) (*((volatile u_char *)(a->membase+b))) | |
209 | #define Write_hfc16(a,b,c) (*((volatile unsigned short *)(a->membase+b)) = c) | |
210 | #define Read_hfc16(a,b) (*((volatile unsigned short *)(a->membase+b))) | |
211 | #define Write_hfc32(a,b,c) (*((volatile unsigned long *)(a->membase+b)) = c) | |
212 | #define Read_hfc32(a,b) (*((volatile unsigned long *)(a->membase+b))) | |
213 | #define wait_busy(a) {while ((Read_hfc8(a, R_STATUS) & M_BUSY));} | |
214 | #define PCI_ENA_MEMIO 0x03 | |
215 | ||
216 | #else | |
217 | ||
218 | /* inline functions io mapped */ | |
219 | static inline void | |
220 | SetRegAddr(hfc4s8s_hw * a, u_char b) | |
221 | { | |
222 | outb(b, (a->iobase) + 4); | |
223 | } | |
224 | ||
225 | static inline u_char | |
226 | GetRegAddr(hfc4s8s_hw * a) | |
227 | { | |
228 | return (inb((volatile u_int) (a->iobase + 4))); | |
229 | } | |
230 | ||
231 | ||
232 | static inline void | |
233 | Write_hfc8(hfc4s8s_hw * a, u_char b, u_char c) | |
234 | { | |
235 | SetRegAddr(a, b); | |
236 | outb(c, a->iobase); | |
237 | } | |
238 | ||
239 | static inline void | |
240 | fWrite_hfc8(hfc4s8s_hw * a, u_char c) | |
241 | { | |
242 | outb(c, a->iobase); | |
243 | } | |
244 | ||
245 | static inline void | |
246 | Write_hfc16(hfc4s8s_hw * a, u_char b, u_short c) | |
247 | { | |
248 | SetRegAddr(a, b); | |
249 | outw(c, a->iobase); | |
250 | } | |
251 | ||
252 | static inline void | |
253 | Write_hfc32(hfc4s8s_hw * a, u_char b, u_long c) | |
254 | { | |
255 | SetRegAddr(a, b); | |
256 | outl(c, a->iobase); | |
257 | } | |
258 | ||
259 | static inline void | |
260 | fWrite_hfc32(hfc4s8s_hw * a, u_long c) | |
261 | { | |
262 | outl(c, a->iobase); | |
263 | } | |
264 | ||
265 | static inline u_char | |
266 | Read_hfc8(hfc4s8s_hw * a, u_char b) | |
267 | { | |
268 | SetRegAddr(a, b); | |
269 | return (inb((volatile u_int) a->iobase)); | |
270 | } | |
271 | ||
272 | static inline u_char | |
273 | fRead_hfc8(hfc4s8s_hw * a) | |
274 | { | |
275 | return (inb((volatile u_int) a->iobase)); | |
276 | } | |
277 | ||
278 | ||
279 | static inline u_short | |
280 | Read_hfc16(hfc4s8s_hw * a, u_char b) | |
281 | { | |
282 | SetRegAddr(a, b); | |
283 | return (inw((volatile u_int) a->iobase)); | |
284 | } | |
285 | ||
286 | static inline u_long | |
287 | Read_hfc32(hfc4s8s_hw * a, u_char b) | |
288 | { | |
289 | SetRegAddr(a, b); | |
290 | return (inl((volatile u_int) a->iobase)); | |
291 | } | |
292 | ||
293 | static inline u_long | |
294 | fRead_hfc32(hfc4s8s_hw * a) | |
295 | { | |
296 | return (inl((volatile u_int) a->iobase)); | |
297 | } | |
298 | ||
299 | static inline void | |
300 | wait_busy(hfc4s8s_hw * a) | |
301 | { | |
302 | SetRegAddr(a, R_STATUS); | |
303 | while (inb((volatile u_int) a->iobase) & M_BUSY); | |
304 | } | |
305 | ||
306 | #define PCI_ENA_REGIO 0x01 | |
307 | ||
308 | #endif /* CONFIG_HISAX_HFC4S8S_PCIMEM */ | |
309 | ||
310 | /******************************************************/ | |
311 | /* function to read critical counter registers that */ | |
312 | /* may be udpated by the chip during read */ | |
313 | /******************************************************/ | |
b79646e3 | 314 | static u_char |
1da177e4 LT |
315 | Read_hfc8_stable(hfc4s8s_hw * hw, int reg) |
316 | { | |
317 | u_char ref8; | |
318 | u_char in8; | |
319 | ref8 = Read_hfc8(hw, reg); | |
320 | while (((in8 = Read_hfc8(hw, reg)) != ref8)) { | |
321 | ref8 = in8; | |
322 | } | |
323 | return in8; | |
324 | } | |
325 | ||
b79646e3 | 326 | static int |
1da177e4 LT |
327 | Read_hfc16_stable(hfc4s8s_hw * hw, int reg) |
328 | { | |
329 | int ref16; | |
330 | int in16; | |
331 | ||
332 | ref16 = Read_hfc16(hw, reg); | |
333 | while (((in16 = Read_hfc16(hw, reg)) != ref16)) { | |
334 | ref16 = in16; | |
335 | } | |
336 | return in16; | |
337 | } | |
338 | ||
339 | /*****************************/ | |
340 | /* D-channel call from HiSax */ | |
341 | /*****************************/ | |
342 | static void | |
343 | dch_l2l1(struct hisax_d_if *iface, int pr, void *arg) | |
344 | { | |
345 | struct hfc4s8s_l1 *l1 = iface->ifc.priv; | |
346 | struct sk_buff *skb = (struct sk_buff *) arg; | |
347 | u_long flags; | |
348 | ||
349 | switch (pr) { | |
350 | ||
351 | case (PH_DATA | REQUEST): | |
352 | if (!l1->enabled) { | |
353 | dev_kfree_skb(skb); | |
354 | break; | |
355 | } | |
356 | spin_lock_irqsave(&l1->lock, flags); | |
357 | skb_queue_tail(&l1->d_tx_queue, skb); | |
358 | if ((skb_queue_len(&l1->d_tx_queue) == 1) && | |
359 | (l1->tx_cnt <= 0)) { | |
360 | l1->hw->mr.r_irq_fifo_blx[l1->st_num] |= | |
361 | 0x10; | |
362 | spin_unlock_irqrestore(&l1->lock, flags); | |
363 | schedule_work(&l1->hw->tqueue); | |
364 | } else | |
365 | spin_unlock_irqrestore(&l1->lock, flags); | |
366 | break; | |
367 | ||
368 | case (PH_ACTIVATE | REQUEST): | |
369 | if (!l1->enabled) | |
370 | break; | |
371 | if (!l1->nt_mode) { | |
372 | if (l1->l1_state < 6) { | |
373 | spin_lock_irqsave(&l1->lock, | |
374 | flags); | |
375 | ||
376 | Write_hfc8(l1->hw, R_ST_SEL, | |
377 | l1->st_num); | |
378 | Write_hfc8(l1->hw, A_ST_WR_STA, | |
379 | 0x60); | |
380 | mod_timer(&l1->l1_timer, | |
381 | jiffies + L1_TIMER_T3); | |
382 | spin_unlock_irqrestore(&l1->lock, | |
383 | flags); | |
384 | } else if (l1->l1_state == 7) | |
385 | l1->d_if.ifc.l1l2(&l1->d_if.ifc, | |
386 | PH_ACTIVATE | | |
387 | INDICATION, | |
388 | NULL); | |
389 | } else { | |
390 | if (l1->l1_state != 3) { | |
391 | spin_lock_irqsave(&l1->lock, | |
392 | flags); | |
393 | Write_hfc8(l1->hw, R_ST_SEL, | |
394 | l1->st_num); | |
395 | Write_hfc8(l1->hw, A_ST_WR_STA, | |
396 | 0x60); | |
397 | spin_unlock_irqrestore(&l1->lock, | |
398 | flags); | |
399 | } else if (l1->l1_state == 3) | |
400 | l1->d_if.ifc.l1l2(&l1->d_if.ifc, | |
401 | PH_ACTIVATE | | |
402 | INDICATION, | |
403 | NULL); | |
404 | } | |
405 | break; | |
406 | ||
407 | default: | |
408 | printk(KERN_INFO | |
409 | "HFC-4S/8S: Unknown D-chan cmd 0x%x received, ignored\n", | |
410 | pr); | |
411 | break; | |
412 | } | |
413 | if (!l1->enabled) | |
414 | l1->d_if.ifc.l1l2(&l1->d_if.ifc, | |
415 | PH_DEACTIVATE | INDICATION, NULL); | |
416 | } /* dch_l2l1 */ | |
417 | ||
418 | /*****************************/ | |
419 | /* B-channel call from HiSax */ | |
420 | /*****************************/ | |
421 | static void | |
422 | bch_l2l1(struct hisax_if *ifc, int pr, void *arg) | |
423 | { | |
424 | struct hfc4s8s_btype *bch = ifc->priv; | |
425 | struct hfc4s8s_l1 *l1 = bch->l1p; | |
426 | struct sk_buff *skb = (struct sk_buff *) arg; | |
427 | int mode = (int) arg; | |
428 | u_long flags; | |
429 | ||
430 | switch (pr) { | |
431 | ||
432 | case (PH_DATA | REQUEST): | |
433 | if (!l1->enabled || (bch->mode == L1_MODE_NULL)) { | |
434 | dev_kfree_skb(skb); | |
435 | break; | |
436 | } | |
437 | spin_lock_irqsave(&l1->lock, flags); | |
438 | skb_queue_tail(&bch->tx_queue, skb); | |
439 | if (!bch->tx_skb && (bch->tx_cnt <= 0)) { | |
440 | l1->hw->mr.r_irq_fifo_blx[l1->st_num] |= | |
441 | ((bch->bchan == 1) ? 1 : 4); | |
442 | spin_unlock_irqrestore(&l1->lock, flags); | |
443 | schedule_work(&l1->hw->tqueue); | |
444 | } else | |
445 | spin_unlock_irqrestore(&l1->lock, flags); | |
446 | break; | |
447 | ||
448 | case (PH_ACTIVATE | REQUEST): | |
449 | case (PH_DEACTIVATE | REQUEST): | |
450 | if (!l1->enabled) | |
451 | break; | |
452 | if (pr == (PH_DEACTIVATE | REQUEST)) | |
453 | mode = L1_MODE_NULL; | |
454 | ||
455 | switch (mode) { | |
456 | case L1_MODE_HDLC: | |
457 | spin_lock_irqsave(&l1->lock, | |
458 | flags); | |
459 | l1->hw->mr.timer_usg_cnt++; | |
460 | l1->hw->mr. | |
461 | fifo_slow_timer_service[l1-> | |
462 | st_num] | |
463 | |= | |
464 | ((bch->bchan == | |
465 | 1) ? 0x2 : 0x8); | |
466 | Write_hfc8(l1->hw, R_FIFO, | |
467 | (l1->st_num * 8 + | |
468 | ((bch->bchan == | |
469 | 1) ? 0 : 2))); | |
470 | wait_busy(l1->hw); | |
471 | Write_hfc8(l1->hw, A_CON_HDLC, 0xc); /* HDLC mode, flag fill, connect ST */ | |
472 | Write_hfc8(l1->hw, A_SUBCH_CFG, 0); /* 8 bits */ | |
473 | Write_hfc8(l1->hw, A_IRQ_MSK, 1); /* enable TX interrupts for hdlc */ | |
474 | Write_hfc8(l1->hw, A_INC_RES_FIFO, 2); /* reset fifo */ | |
475 | wait_busy(l1->hw); | |
476 | ||
477 | Write_hfc8(l1->hw, R_FIFO, | |
478 | (l1->st_num * 8 + | |
479 | ((bch->bchan == | |
480 | 1) ? 1 : 3))); | |
481 | wait_busy(l1->hw); | |
482 | Write_hfc8(l1->hw, A_CON_HDLC, 0xc); /* HDLC mode, flag fill, connect ST */ | |
483 | Write_hfc8(l1->hw, A_SUBCH_CFG, 0); /* 8 bits */ | |
484 | Write_hfc8(l1->hw, A_IRQ_MSK, 1); /* enable RX interrupts for hdlc */ | |
485 | Write_hfc8(l1->hw, A_INC_RES_FIFO, 2); /* reset fifo */ | |
486 | ||
487 | Write_hfc8(l1->hw, R_ST_SEL, | |
488 | l1->st_num); | |
489 | l1->hw->mr.r_ctrl0 |= | |
490 | (bch->bchan & 3); | |
491 | Write_hfc8(l1->hw, A_ST_CTRL0, | |
492 | l1->hw->mr.r_ctrl0); | |
493 | bch->mode = L1_MODE_HDLC; | |
494 | spin_unlock_irqrestore(&l1->lock, | |
495 | flags); | |
496 | ||
497 | bch->b_if.ifc.l1l2(&bch->b_if.ifc, | |
498 | PH_ACTIVATE | | |
499 | INDICATION, | |
500 | NULL); | |
501 | break; | |
502 | ||
503 | case L1_MODE_TRANS: | |
504 | spin_lock_irqsave(&l1->lock, | |
505 | flags); | |
506 | l1->hw->mr. | |
507 | fifo_rx_trans_enables[l1-> | |
508 | st_num] | |
509 | |= | |
510 | ((bch->bchan == | |
511 | 1) ? 0x2 : 0x8); | |
512 | l1->hw->mr.timer_usg_cnt++; | |
513 | Write_hfc8(l1->hw, R_FIFO, | |
514 | (l1->st_num * 8 + | |
515 | ((bch->bchan == | |
516 | 1) ? 0 : 2))); | |
517 | wait_busy(l1->hw); | |
518 | Write_hfc8(l1->hw, A_CON_HDLC, 0xf); /* Transparent mode, 1 fill, connect ST */ | |
519 | Write_hfc8(l1->hw, A_SUBCH_CFG, 0); /* 8 bits */ | |
520 | Write_hfc8(l1->hw, A_IRQ_MSK, 0); /* disable TX interrupts */ | |
521 | Write_hfc8(l1->hw, A_INC_RES_FIFO, 2); /* reset fifo */ | |
522 | wait_busy(l1->hw); | |
523 | ||
524 | Write_hfc8(l1->hw, R_FIFO, | |
525 | (l1->st_num * 8 + | |
526 | ((bch->bchan == | |
527 | 1) ? 1 : 3))); | |
528 | wait_busy(l1->hw); | |
529 | Write_hfc8(l1->hw, A_CON_HDLC, 0xf); /* Transparent mode, 1 fill, connect ST */ | |
530 | Write_hfc8(l1->hw, A_SUBCH_CFG, 0); /* 8 bits */ | |
531 | Write_hfc8(l1->hw, A_IRQ_MSK, 0); /* disable RX interrupts */ | |
532 | Write_hfc8(l1->hw, A_INC_RES_FIFO, 2); /* reset fifo */ | |
533 | ||
534 | Write_hfc8(l1->hw, R_ST_SEL, | |
535 | l1->st_num); | |
536 | l1->hw->mr.r_ctrl0 |= | |
537 | (bch->bchan & 3); | |
538 | Write_hfc8(l1->hw, A_ST_CTRL0, | |
539 | l1->hw->mr.r_ctrl0); | |
540 | bch->mode = L1_MODE_TRANS; | |
541 | spin_unlock_irqrestore(&l1->lock, | |
542 | flags); | |
543 | ||
544 | bch->b_if.ifc.l1l2(&bch->b_if.ifc, | |
545 | PH_ACTIVATE | | |
546 | INDICATION, | |
547 | NULL); | |
548 | break; | |
549 | ||
550 | default: | |
551 | if (bch->mode == L1_MODE_NULL) | |
552 | break; | |
553 | spin_lock_irqsave(&l1->lock, | |
554 | flags); | |
555 | l1->hw->mr. | |
556 | fifo_slow_timer_service[l1-> | |
557 | st_num] | |
558 | &= | |
559 | ~((bch->bchan == | |
560 | 1) ? 0x3 : 0xc); | |
561 | l1->hw->mr. | |
562 | fifo_rx_trans_enables[l1-> | |
563 | st_num] | |
564 | &= | |
565 | ~((bch->bchan == | |
566 | 1) ? 0x3 : 0xc); | |
567 | l1->hw->mr.timer_usg_cnt--; | |
568 | Write_hfc8(l1->hw, R_FIFO, | |
569 | (l1->st_num * 8 + | |
570 | ((bch->bchan == | |
571 | 1) ? 0 : 2))); | |
572 | wait_busy(l1->hw); | |
573 | Write_hfc8(l1->hw, A_IRQ_MSK, 0); /* disable TX interrupts */ | |
574 | wait_busy(l1->hw); | |
575 | Write_hfc8(l1->hw, R_FIFO, | |
576 | (l1->st_num * 8 + | |
577 | ((bch->bchan == | |
578 | 1) ? 1 : 3))); | |
579 | wait_busy(l1->hw); | |
580 | Write_hfc8(l1->hw, A_IRQ_MSK, 0); /* disable RX interrupts */ | |
581 | Write_hfc8(l1->hw, R_ST_SEL, | |
582 | l1->st_num); | |
583 | l1->hw->mr.r_ctrl0 &= | |
584 | ~(bch->bchan & 3); | |
585 | Write_hfc8(l1->hw, A_ST_CTRL0, | |
586 | l1->hw->mr.r_ctrl0); | |
587 | spin_unlock_irqrestore(&l1->lock, | |
588 | flags); | |
589 | ||
590 | bch->mode = L1_MODE_NULL; | |
591 | bch->b_if.ifc.l1l2(&bch->b_if.ifc, | |
592 | PH_DEACTIVATE | | |
593 | INDICATION, | |
594 | NULL); | |
595 | if (bch->tx_skb) { | |
596 | dev_kfree_skb(bch->tx_skb); | |
597 | bch->tx_skb = NULL; | |
598 | } | |
599 | if (bch->rx_skb) { | |
600 | dev_kfree_skb(bch->rx_skb); | |
601 | bch->rx_skb = NULL; | |
602 | } | |
603 | skb_queue_purge(&bch->tx_queue); | |
604 | bch->tx_cnt = 0; | |
605 | bch->rx_ptr = NULL; | |
606 | break; | |
607 | } | |
608 | ||
609 | /* timer is only used when at least one b channel */ | |
610 | /* is set up to transparent mode */ | |
611 | if (l1->hw->mr.timer_usg_cnt) { | |
612 | Write_hfc8(l1->hw, R_IRQMSK_MISC, | |
613 | M_TI_IRQMSK); | |
614 | } else { | |
615 | Write_hfc8(l1->hw, R_IRQMSK_MISC, 0); | |
616 | } | |
617 | ||
618 | break; | |
619 | ||
620 | default: | |
621 | printk(KERN_INFO | |
622 | "HFC-4S/8S: Unknown B-chan cmd 0x%x received, ignored\n", | |
623 | pr); | |
624 | break; | |
625 | } | |
626 | if (!l1->enabled) | |
627 | bch->b_if.ifc.l1l2(&bch->b_if.ifc, | |
628 | PH_DEACTIVATE | INDICATION, NULL); | |
629 | } /* bch_l2l1 */ | |
630 | ||
631 | /**************************/ | |
632 | /* layer 1 timer function */ | |
633 | /**************************/ | |
634 | static void | |
635 | hfc_l1_timer(struct hfc4s8s_l1 *l1) | |
636 | { | |
637 | u_long flags; | |
638 | ||
639 | if (!l1->enabled) | |
640 | return; | |
641 | ||
642 | spin_lock_irqsave(&l1->lock, flags); | |
643 | if (l1->nt_mode) { | |
644 | l1->l1_state = 1; | |
645 | Write_hfc8(l1->hw, R_ST_SEL, l1->st_num); | |
646 | Write_hfc8(l1->hw, A_ST_WR_STA, 0x11); | |
647 | spin_unlock_irqrestore(&l1->lock, flags); | |
648 | l1->d_if.ifc.l1l2(&l1->d_if.ifc, | |
649 | PH_DEACTIVATE | INDICATION, NULL); | |
650 | spin_lock_irqsave(&l1->lock, flags); | |
651 | l1->l1_state = 1; | |
652 | Write_hfc8(l1->hw, A_ST_WR_STA, 0x1); | |
653 | spin_unlock_irqrestore(&l1->lock, flags); | |
654 | } else { | |
655 | /* activation timed out */ | |
656 | Write_hfc8(l1->hw, R_ST_SEL, l1->st_num); | |
657 | Write_hfc8(l1->hw, A_ST_WR_STA, 0x13); | |
658 | spin_unlock_irqrestore(&l1->lock, flags); | |
659 | l1->d_if.ifc.l1l2(&l1->d_if.ifc, | |
660 | PH_DEACTIVATE | INDICATION, NULL); | |
661 | spin_lock_irqsave(&l1->lock, flags); | |
662 | Write_hfc8(l1->hw, R_ST_SEL, l1->st_num); | |
663 | Write_hfc8(l1->hw, A_ST_WR_STA, 0x3); | |
664 | spin_unlock_irqrestore(&l1->lock, flags); | |
665 | } | |
666 | } /* hfc_l1_timer */ | |
667 | ||
668 | /****************************************/ | |
669 | /* a complete D-frame has been received */ | |
670 | /****************************************/ | |
671 | static void | |
672 | rx_d_frame(struct hfc4s8s_l1 *l1p, int ech) | |
673 | { | |
674 | int z1, z2; | |
675 | u_char f1, f2, df; | |
676 | struct sk_buff *skb; | |
677 | u_char *cp; | |
678 | ||
679 | ||
680 | if (!l1p->enabled) | |
681 | return; | |
682 | do { | |
683 | /* E/D RX fifo */ | |
684 | Write_hfc8(l1p->hw, R_FIFO, | |
685 | (l1p->st_num * 8 + ((ech) ? 7 : 5))); | |
686 | wait_busy(l1p->hw); | |
687 | ||
688 | f1 = Read_hfc8_stable(l1p->hw, A_F1); | |
689 | f2 = Read_hfc8(l1p->hw, A_F2); | |
690 | df = f1 - f2; | |
691 | if ((f1 - f2) < 0) | |
692 | df = f1 - f2 + MAX_F_CNT + 1; | |
693 | ||
694 | ||
695 | if (!df) { | |
696 | return; /* no complete frame in fifo */ | |
697 | } | |
698 | ||
699 | z1 = Read_hfc16_stable(l1p->hw, A_Z1); | |
700 | z2 = Read_hfc16(l1p->hw, A_Z2); | |
701 | ||
702 | z1 = z1 - z2 + 1; | |
703 | if (z1 < 0) | |
704 | z1 += 384; | |
705 | ||
706 | if (!(skb = dev_alloc_skb(MAX_D_FRAME_SIZE))) { | |
707 | printk(KERN_INFO | |
708 | "HFC-4S/8S: Could not allocate D/E " | |
709 | "channel receive buffer"); | |
710 | Write_hfc8(l1p->hw, A_INC_RES_FIFO, 2); | |
711 | wait_busy(l1p->hw); | |
712 | return; | |
713 | } | |
714 | ||
715 | if (((z1 < 4) || (z1 > MAX_D_FRAME_SIZE))) { | |
716 | if (skb) | |
717 | dev_kfree_skb(skb); | |
718 | /* remove errornous D frame */ | |
719 | if (df == 1) { | |
720 | /* reset fifo */ | |
721 | Write_hfc8(l1p->hw, A_INC_RES_FIFO, 2); | |
722 | wait_busy(l1p->hw); | |
723 | return; | |
724 | } else { | |
725 | /* read errornous D frame */ | |
726 | ||
727 | #ifndef CONFIG_HISAX_HFC4S8S_PCIMEM | |
728 | SetRegAddr(l1p->hw, A_FIFO_DATA0); | |
729 | #endif | |
730 | ||
731 | while (z1 >= 4) { | |
732 | #ifdef CONFIG_HISAX_HFC4S8S_PCIMEM | |
733 | Read_hfc32(l1p->hw, A_FIFO_DATA0); | |
734 | #else | |
735 | fRead_hfc32(l1p->hw); | |
736 | #endif | |
737 | z1 -= 4; | |
738 | } | |
739 | ||
740 | while (z1--) | |
741 | #ifdef CONFIG_HISAX_HFC4S8S_PCIMEM | |
742 | Read_hfc8(l1p->hw, A_FIFO_DATA0); | |
743 | #else | |
744 | fRead_hfc8(l1p->hw); | |
745 | #endif | |
746 | ||
747 | Write_hfc8(l1p->hw, A_INC_RES_FIFO, 1); | |
748 | wait_busy(l1p->hw); | |
749 | return; | |
750 | } | |
751 | } | |
752 | ||
753 | cp = skb->data; | |
754 | ||
755 | #ifndef CONFIG_HISAX_HFC4S8S_PCIMEM | |
756 | SetRegAddr(l1p->hw, A_FIFO_DATA0); | |
757 | #endif | |
758 | ||
759 | while (z1 >= 4) { | |
760 | #ifdef CONFIG_HISAX_HFC4S8S_PCIMEM | |
761 | *((unsigned long *) cp) = | |
762 | Read_hfc32(l1p->hw, A_FIFO_DATA0); | |
763 | #else | |
764 | *((unsigned long *) cp) = fRead_hfc32(l1p->hw); | |
765 | #endif | |
766 | cp += 4; | |
767 | z1 -= 4; | |
768 | } | |
769 | ||
770 | while (z1--) | |
771 | #ifdef CONFIG_HISAX_HFC4S8S_PCIMEM | |
772 | *cp++ = Read_hfc8(l1p->hw, A_FIFO_DATA0); | |
773 | #else | |
774 | *cp++ = fRead_hfc8(l1p->hw); | |
775 | #endif | |
776 | ||
777 | Write_hfc8(l1p->hw, A_INC_RES_FIFO, 1); /* increment f counter */ | |
778 | wait_busy(l1p->hw); | |
779 | ||
780 | if (*(--cp)) { | |
781 | dev_kfree_skb(skb); | |
782 | } else { | |
783 | skb->len = (cp - skb->data) - 2; | |
784 | if (ech) | |
785 | l1p->d_if.ifc.l1l2(&l1p->d_if.ifc, | |
786 | PH_DATA_E | INDICATION, | |
787 | skb); | |
788 | else | |
789 | l1p->d_if.ifc.l1l2(&l1p->d_if.ifc, | |
790 | PH_DATA | INDICATION, | |
791 | skb); | |
792 | } | |
793 | } while (1); | |
794 | } /* rx_d_frame */ | |
795 | ||
796 | /*************************************************************/ | |
797 | /* a B-frame has been received (perhaps not fully completed) */ | |
798 | /*************************************************************/ | |
799 | static void | |
800 | rx_b_frame(struct hfc4s8s_btype *bch) | |
801 | { | |
802 | int z1, z2, hdlc_complete; | |
803 | u_char f1, f2; | |
804 | struct hfc4s8s_l1 *l1 = bch->l1p; | |
805 | struct sk_buff *skb; | |
806 | ||
807 | if (!l1->enabled || (bch->mode == L1_MODE_NULL)) | |
808 | return; | |
809 | ||
810 | do { | |
811 | /* RX Fifo */ | |
812 | Write_hfc8(l1->hw, R_FIFO, | |
813 | (l1->st_num * 8 + ((bch->bchan == 1) ? 1 : 3))); | |
814 | wait_busy(l1->hw); | |
815 | ||
816 | if (bch->mode == L1_MODE_HDLC) { | |
817 | f1 = Read_hfc8_stable(l1->hw, A_F1); | |
818 | f2 = Read_hfc8(l1->hw, A_F2); | |
819 | hdlc_complete = ((f1 ^ f2) & MAX_F_CNT); | |
820 | } else | |
821 | hdlc_complete = 0; | |
822 | z1 = Read_hfc16_stable(l1->hw, A_Z1); | |
823 | z2 = Read_hfc16(l1->hw, A_Z2); | |
824 | z1 = (z1 - z2); | |
825 | if (hdlc_complete) | |
826 | z1++; | |
827 | if (z1 < 0) | |
828 | z1 += 384; | |
829 | ||
830 | if (!z1) | |
831 | break; | |
832 | ||
833 | if (!(skb = bch->rx_skb)) { | |
834 | if (! | |
835 | (skb = | |
836 | dev_alloc_skb((bch->mode == | |
837 | L1_MODE_TRANS) ? z1 | |
838 | : (MAX_B_FRAME_SIZE + 3)))) { | |
839 | printk(KERN_ERR | |
840 | "HFC-4S/8S: Could not allocate B " | |
841 | "channel receive buffer"); | |
842 | return; | |
843 | } | |
844 | bch->rx_ptr = skb->data; | |
845 | bch->rx_skb = skb; | |
846 | } | |
847 | ||
848 | skb->len = (bch->rx_ptr - skb->data) + z1; | |
849 | ||
850 | /* HDLC length check */ | |
851 | if ((bch->mode == L1_MODE_HDLC) && | |
852 | ((hdlc_complete && (skb->len < 4)) || | |
853 | (skb->len > (MAX_B_FRAME_SIZE + 3)))) { | |
854 | ||
855 | skb->len = 0; | |
856 | bch->rx_ptr = skb->data; | |
857 | Write_hfc8(l1->hw, A_INC_RES_FIFO, 2); /* reset fifo */ | |
858 | wait_busy(l1->hw); | |
859 | return; | |
860 | } | |
861 | #ifndef CONFIG_HISAX_HFC4S8S_PCIMEM | |
862 | SetRegAddr(l1->hw, A_FIFO_DATA0); | |
863 | #endif | |
864 | ||
865 | while (z1 >= 4) { | |
866 | #ifdef CONFIG_HISAX_HFC4S8S_PCIMEM | |
867 | *((unsigned long *) bch->rx_ptr) = | |
868 | Read_hfc32(l1->hw, A_FIFO_DATA0); | |
869 | #else | |
870 | *((unsigned long *) bch->rx_ptr) = | |
871 | fRead_hfc32(l1->hw); | |
872 | #endif | |
873 | bch->rx_ptr += 4; | |
874 | z1 -= 4; | |
875 | } | |
876 | ||
877 | while (z1--) | |
878 | #ifdef CONFIG_HISAX_HFC4S8S_PCIMEM | |
879 | *(bch->rx_ptr++) = Read_hfc8(l1->hw, A_FIFO_DATA0); | |
880 | #else | |
881 | *(bch->rx_ptr++) = fRead_hfc8(l1->hw); | |
882 | #endif | |
883 | ||
884 | if (hdlc_complete) { | |
885 | /* increment f counter */ | |
886 | Write_hfc8(l1->hw, A_INC_RES_FIFO, 1); | |
887 | wait_busy(l1->hw); | |
888 | ||
889 | /* hdlc crc check */ | |
890 | bch->rx_ptr--; | |
891 | if (*bch->rx_ptr) { | |
892 | skb->len = 0; | |
893 | bch->rx_ptr = skb->data; | |
894 | continue; | |
895 | } | |
896 | skb->len -= 3; | |
897 | } | |
898 | if (hdlc_complete || (bch->mode == L1_MODE_TRANS)) { | |
899 | bch->rx_skb = NULL; | |
900 | bch->rx_ptr = NULL; | |
901 | bch->b_if.ifc.l1l2(&bch->b_if.ifc, | |
902 | PH_DATA | INDICATION, skb); | |
903 | } | |
904 | ||
905 | } while (1); | |
906 | } /* rx_b_frame */ | |
907 | ||
908 | /********************************************/ | |
909 | /* a D-frame has been/should be transmitted */ | |
910 | /********************************************/ | |
911 | static void | |
912 | tx_d_frame(struct hfc4s8s_l1 *l1p) | |
913 | { | |
914 | struct sk_buff *skb; | |
915 | u_char f1, f2; | |
916 | u_char *cp; | |
917 | int cnt; | |
918 | ||
919 | if (l1p->l1_state != 7) | |
920 | return; | |
921 | ||
922 | /* TX fifo */ | |
923 | Write_hfc8(l1p->hw, R_FIFO, (l1p->st_num * 8 + 4)); | |
924 | wait_busy(l1p->hw); | |
925 | ||
926 | f1 = Read_hfc8(l1p->hw, A_F1); | |
927 | f2 = Read_hfc8_stable(l1p->hw, A_F2); | |
928 | ||
929 | if ((f1 ^ f2) & MAX_F_CNT) | |
930 | return; /* fifo is still filled */ | |
931 | ||
932 | if (l1p->tx_cnt > 0) { | |
933 | cnt = l1p->tx_cnt; | |
934 | l1p->tx_cnt = 0; | |
935 | l1p->d_if.ifc.l1l2(&l1p->d_if.ifc, PH_DATA | CONFIRM, | |
936 | (void *) cnt); | |
937 | } | |
938 | ||
939 | if ((skb = skb_dequeue(&l1p->d_tx_queue))) { | |
940 | cp = skb->data; | |
941 | cnt = skb->len; | |
942 | #ifndef CONFIG_HISAX_HFC4S8S_PCIMEM | |
943 | SetRegAddr(l1p->hw, A_FIFO_DATA0); | |
944 | #endif | |
945 | ||
946 | while (cnt >= 4) { | |
947 | #ifdef CONFIG_HISAX_HFC4S8S_PCIMEM | |
948 | fWrite_hfc32(l1p->hw, A_FIFO_DATA0, | |
949 | *(unsigned long *) cp); | |
950 | #else | |
951 | SetRegAddr(l1p->hw, A_FIFO_DATA0); | |
952 | fWrite_hfc32(l1p->hw, *(unsigned long *) cp); | |
953 | #endif | |
954 | cp += 4; | |
955 | cnt -= 4; | |
956 | } | |
957 | ||
958 | #ifdef CONFIG_HISAX_HFC4S8S_PCIMEM | |
959 | while (cnt--) | |
960 | fWrite_hfc8(l1p->hw, A_FIFO_DATA0, *cp++); | |
961 | #else | |
962 | while (cnt--) | |
963 | fWrite_hfc8(l1p->hw, *cp++); | |
964 | #endif | |
965 | ||
966 | l1p->tx_cnt = skb->truesize; | |
967 | Write_hfc8(l1p->hw, A_INC_RES_FIFO, 1); /* increment f counter */ | |
968 | wait_busy(l1p->hw); | |
969 | ||
970 | dev_kfree_skb(skb); | |
971 | } | |
972 | } /* tx_d_frame */ | |
973 | ||
974 | /******************************************************/ | |
975 | /* a B-frame may be transmitted (or is not completed) */ | |
976 | /******************************************************/ | |
977 | static void | |
978 | tx_b_frame(struct hfc4s8s_btype *bch) | |
979 | { | |
980 | struct sk_buff *skb; | |
981 | struct hfc4s8s_l1 *l1 = bch->l1p; | |
982 | u_char *cp; | |
983 | int cnt, max, hdlc_num, ack_len = 0; | |
984 | ||
985 | if (!l1->enabled || (bch->mode == L1_MODE_NULL)) | |
986 | return; | |
987 | ||
988 | /* TX fifo */ | |
989 | Write_hfc8(l1->hw, R_FIFO, | |
990 | (l1->st_num * 8 + ((bch->bchan == 1) ? 0 : 2))); | |
991 | wait_busy(l1->hw); | |
992 | do { | |
993 | ||
994 | if (bch->mode == L1_MODE_HDLC) { | |
995 | hdlc_num = Read_hfc8(l1->hw, A_F1) & MAX_F_CNT; | |
996 | hdlc_num -= | |
997 | (Read_hfc8_stable(l1->hw, A_F2) & MAX_F_CNT); | |
998 | if (hdlc_num < 0) | |
999 | hdlc_num += 16; | |
1000 | if (hdlc_num >= 15) | |
1001 | break; /* fifo still filled up with hdlc frames */ | |
1002 | } else | |
1003 | hdlc_num = 0; | |
1004 | ||
1005 | if (!(skb = bch->tx_skb)) { | |
1006 | if (!(skb = skb_dequeue(&bch->tx_queue))) { | |
1007 | l1->hw->mr.fifo_slow_timer_service[l1-> | |
1008 | st_num] | |
1009 | &= ~((bch->bchan == 1) ? 1 : 4); | |
1010 | break; /* list empty */ | |
1011 | } | |
1012 | bch->tx_skb = skb; | |
1013 | bch->tx_cnt = 0; | |
1014 | } | |
1015 | ||
1016 | if (!hdlc_num) | |
1017 | l1->hw->mr.fifo_slow_timer_service[l1->st_num] |= | |
1018 | ((bch->bchan == 1) ? 1 : 4); | |
1019 | else | |
1020 | l1->hw->mr.fifo_slow_timer_service[l1->st_num] &= | |
1021 | ~((bch->bchan == 1) ? 1 : 4); | |
1022 | ||
1023 | max = Read_hfc16_stable(l1->hw, A_Z2); | |
1024 | max -= Read_hfc16(l1->hw, A_Z1); | |
1025 | if (max <= 0) | |
1026 | max += 384; | |
1027 | max--; | |
1028 | ||
1029 | if (max < 16) | |
1030 | break; /* don't write to small amounts of bytes */ | |
1031 | ||
1032 | cnt = skb->len - bch->tx_cnt; | |
1033 | if (cnt > max) | |
1034 | cnt = max; | |
1035 | cp = skb->data + bch->tx_cnt; | |
1036 | bch->tx_cnt += cnt; | |
1037 | ||
1038 | #ifndef CONFIG_HISAX_HFC4S8S_PCIMEM | |
1039 | SetRegAddr(l1->hw, A_FIFO_DATA0); | |
1040 | #endif | |
1041 | while (cnt >= 4) { | |
1042 | #ifdef CONFIG_HISAX_HFC4S8S_PCIMEM | |
1043 | fWrite_hfc32(l1->hw, A_FIFO_DATA0, | |
1044 | *(unsigned long *) cp); | |
1045 | #else | |
1046 | fWrite_hfc32(l1->hw, *(unsigned long *) cp); | |
1047 | #endif | |
1048 | cp += 4; | |
1049 | cnt -= 4; | |
1050 | } | |
1051 | ||
1052 | while (cnt--) | |
1053 | #ifdef CONFIG_HISAX_HFC4S8S_PCIMEM | |
1054 | fWrite_hfc8(l1->hw, A_FIFO_DATA0, *cp++); | |
1055 | #else | |
1056 | fWrite_hfc8(l1->hw, *cp++); | |
1057 | #endif | |
1058 | ||
1059 | if (bch->tx_cnt >= skb->len) { | |
1060 | if (bch->mode == L1_MODE_HDLC) { | |
1061 | /* increment f counter */ | |
1062 | Write_hfc8(l1->hw, A_INC_RES_FIFO, 1); | |
1063 | } | |
1064 | ack_len += skb->truesize; | |
874ec33f | 1065 | bch->tx_skb = NULL; |
1da177e4 LT |
1066 | bch->tx_cnt = 0; |
1067 | dev_kfree_skb(skb); | |
1068 | } else | |
1069 | /* Re-Select */ | |
1070 | Write_hfc8(l1->hw, R_FIFO, | |
1071 | (l1->st_num * 8 + | |
1072 | ((bch->bchan == 1) ? 0 : 2))); | |
1073 | wait_busy(l1->hw); | |
1074 | } while (1); | |
1075 | ||
1076 | if (ack_len) | |
1077 | bch->b_if.ifc.l1l2((struct hisax_if *) &bch->b_if, | |
1078 | PH_DATA | CONFIRM, (void *) ack_len); | |
1079 | } /* tx_b_frame */ | |
1080 | ||
1081 | /*************************************/ | |
1082 | /* bottom half handler for interrupt */ | |
1083 | /*************************************/ | |
1084 | static void | |
1085 | hfc4s8s_bh(hfc4s8s_hw * hw) | |
1086 | { | |
1087 | u_char b; | |
1088 | struct hfc4s8s_l1 *l1p; | |
1089 | volatile u_char *fifo_stat; | |
1090 | int idx; | |
1091 | ||
1092 | /* handle layer 1 state changes */ | |
1093 | b = 1; | |
1094 | l1p = hw->l1; | |
1095 | while (b) { | |
1096 | if ((b & hw->mr.r_irq_statech)) { | |
1097 | /* reset l1 event */ | |
1098 | hw->mr.r_irq_statech &= ~b; | |
1099 | if (l1p->enabled) { | |
1100 | if (l1p->nt_mode) { | |
1101 | u_char oldstate = l1p->l1_state; | |
1102 | ||
1103 | Write_hfc8(l1p->hw, R_ST_SEL, | |
1104 | l1p->st_num); | |
1105 | l1p->l1_state = | |
1106 | Read_hfc8(l1p->hw, | |
1107 | A_ST_RD_STA) & 0xf; | |
1108 | ||
1109 | if ((oldstate == 3) | |
1110 | && (l1p->l1_state != 3)) | |
1111 | l1p->d_if.ifc.l1l2(&l1p-> | |
1112 | d_if. | |
1113 | ifc, | |
1114 | PH_DEACTIVATE | |
1115 | | | |
1116 | INDICATION, | |
1117 | NULL); | |
1118 | ||
1119 | if (l1p->l1_state != 2) { | |
1120 | del_timer(&l1p->l1_timer); | |
1121 | if (l1p->l1_state == 3) { | |
1122 | l1p->d_if.ifc. | |
1123 | l1l2(&l1p-> | |
1124 | d_if.ifc, | |
1125 | PH_ACTIVATE | |
1126 | | | |
1127 | INDICATION, | |
1128 | NULL); | |
1129 | } | |
1130 | } else { | |
1131 | /* allow transition */ | |
1132 | Write_hfc8(hw, A_ST_WR_STA, | |
1133 | M_SET_G2_G3); | |
1134 | mod_timer(&l1p->l1_timer, | |
1135 | jiffies + | |
1136 | L1_TIMER_T1); | |
1137 | } | |
1138 | printk(KERN_INFO | |
1139 | "HFC-4S/8S: NT ch %d l1 state %d -> %d\n", | |
1140 | l1p->st_num, oldstate, | |
1141 | l1p->l1_state); | |
1142 | } else { | |
1143 | u_char oldstate = l1p->l1_state; | |
1144 | ||
1145 | Write_hfc8(l1p->hw, R_ST_SEL, | |
1146 | l1p->st_num); | |
1147 | l1p->l1_state = | |
1148 | Read_hfc8(l1p->hw, | |
1149 | A_ST_RD_STA) & 0xf; | |
1150 | ||
1151 | if (((l1p->l1_state == 3) && | |
1152 | ((oldstate == 7) || | |
1153 | (oldstate == 8))) || | |
1154 | ((timer_pending | |
1155 | (&l1p->l1_timer)) | |
1156 | && (l1p->l1_state == 8))) { | |
1157 | mod_timer(&l1p->l1_timer, | |
1158 | L1_TIMER_T4 + | |
1159 | jiffies); | |
1160 | } else { | |
1161 | if (l1p->l1_state == 7) { | |
1162 | del_timer(&l1p-> | |
1163 | l1_timer); | |
1164 | l1p->d_if.ifc. | |
1165 | l1l2(&l1p-> | |
1166 | d_if.ifc, | |
1167 | PH_ACTIVATE | |
1168 | | | |
1169 | INDICATION, | |
1170 | NULL); | |
1171 | tx_d_frame(l1p); | |
1172 | } | |
1173 | if (l1p->l1_state == 3) { | |
1174 | if (oldstate != 3) | |
1175 | l1p->d_if. | |
1176 | ifc. | |
1177 | l1l2 | |
1178 | (&l1p-> | |
1179 | d_if. | |
1180 | ifc, | |
1181 | PH_DEACTIVATE | |
1182 | | | |
1183 | INDICATION, | |
1184 | NULL); | |
1185 | } | |
1186 | } | |
1187 | printk(KERN_INFO | |
1188 | "HFC-4S/8S: TE %d ch %d l1 state %d -> %d\n", | |
1189 | l1p->hw->cardnum, | |
1190 | l1p->st_num, oldstate, | |
1191 | l1p->l1_state); | |
1192 | } | |
1193 | } | |
1194 | } | |
1195 | b <<= 1; | |
1196 | l1p++; | |
1197 | } | |
1198 | ||
1199 | /* now handle the fifos */ | |
1200 | idx = 0; | |
1201 | fifo_stat = hw->mr.r_irq_fifo_blx; | |
1202 | l1p = hw->l1; | |
1203 | while (idx < hw->driver_data.max_st_ports) { | |
1204 | ||
1205 | if (hw->mr.timer_irq) { | |
1206 | *fifo_stat |= hw->mr.fifo_rx_trans_enables[idx]; | |
1207 | if (hw->fifo_sched_cnt <= 0) { | |
1208 | *fifo_stat |= | |
1209 | hw->mr.fifo_slow_timer_service[l1p-> | |
1210 | st_num]; | |
1211 | } | |
1212 | } | |
1213 | /* ignore fifo 6 (TX E fifo) */ | |
1214 | *fifo_stat &= 0xff - 0x40; | |
1215 | ||
1216 | while (*fifo_stat) { | |
1217 | ||
1218 | if (!l1p->nt_mode) { | |
1219 | /* RX Fifo has data to read */ | |
1220 | if ((*fifo_stat & 0x20)) { | |
1221 | *fifo_stat &= ~0x20; | |
1222 | rx_d_frame(l1p, 0); | |
1223 | } | |
1224 | /* E Fifo has data to read */ | |
1225 | if ((*fifo_stat & 0x80)) { | |
1226 | *fifo_stat &= ~0x80; | |
1227 | rx_d_frame(l1p, 1); | |
1228 | } | |
1229 | /* TX Fifo completed send */ | |
1230 | if ((*fifo_stat & 0x10)) { | |
1231 | *fifo_stat &= ~0x10; | |
1232 | tx_d_frame(l1p); | |
1233 | } | |
1234 | } | |
1235 | /* B1 RX Fifo has data to read */ | |
1236 | if ((*fifo_stat & 0x2)) { | |
1237 | *fifo_stat &= ~0x2; | |
1238 | rx_b_frame(l1p->b_ch); | |
1239 | } | |
1240 | /* B1 TX Fifo has send completed */ | |
1241 | if ((*fifo_stat & 0x1)) { | |
1242 | *fifo_stat &= ~0x1; | |
1243 | tx_b_frame(l1p->b_ch); | |
1244 | } | |
1245 | /* B2 RX Fifo has data to read */ | |
1246 | if ((*fifo_stat & 0x8)) { | |
1247 | *fifo_stat &= ~0x8; | |
1248 | rx_b_frame(l1p->b_ch + 1); | |
1249 | } | |
1250 | /* B2 TX Fifo has send completed */ | |
1251 | if ((*fifo_stat & 0x4)) { | |
1252 | *fifo_stat &= ~0x4; | |
1253 | tx_b_frame(l1p->b_ch + 1); | |
1254 | } | |
1255 | } | |
1256 | fifo_stat++; | |
1257 | l1p++; | |
1258 | idx++; | |
1259 | } | |
1260 | ||
1261 | if (hw->fifo_sched_cnt <= 0) | |
1262 | hw->fifo_sched_cnt += (1 << (7 - TRANS_TIMER_MODE)); | |
1263 | hw->mr.timer_irq = 0; /* clear requested timer irq */ | |
1264 | } /* hfc4s8s_bh */ | |
1265 | ||
1266 | /*********************/ | |
1267 | /* interrupt handler */ | |
1268 | /*********************/ | |
1269 | static irqreturn_t | |
1270 | hfc4s8s_interrupt(int intno, void *dev_id, struct pt_regs *regs) | |
1271 | { | |
1272 | hfc4s8s_hw *hw = dev_id; | |
1273 | u_char b, ovr; | |
1274 | volatile u_char *ovp; | |
1275 | int idx; | |
1276 | u_char old_ioreg; | |
1277 | ||
1278 | if (!hw || !(hw->mr.r_irq_ctrl & M_GLOB_IRQ_EN)) | |
1279 | return IRQ_NONE; | |
1280 | ||
1281 | #ifndef CONFIG_HISAX_HFC4S8S_PCIMEM | |
1282 | /* read current selected regsister */ | |
1283 | old_ioreg = GetRegAddr(hw); | |
1284 | #endif | |
1285 | ||
1286 | /* Layer 1 State change */ | |
1287 | hw->mr.r_irq_statech |= | |
1288 | (Read_hfc8(hw, R_SCI) & hw->mr.r_irqmsk_statchg); | |
1289 | if (! | |
1290 | (b = (Read_hfc8(hw, R_STATUS) & (M_MISC_IRQSTA | M_FR_IRQSTA))) | |
1291 | && !hw->mr.r_irq_statech) { | |
1292 | #ifndef CONFIG_HISAX_HFC4S8S_PCIMEM | |
1293 | SetRegAddr(hw, old_ioreg); | |
1294 | #endif | |
1295 | return IRQ_NONE; | |
1296 | } | |
1297 | ||
1298 | /* timer event */ | |
1299 | if (Read_hfc8(hw, R_IRQ_MISC) & M_TI_IRQ) { | |
1300 | hw->mr.timer_irq = 1; | |
1301 | hw->fifo_sched_cnt--; | |
1302 | } | |
1303 | ||
1304 | /* FIFO event */ | |
1305 | if ((ovr = Read_hfc8(hw, R_IRQ_OVIEW))) { | |
1306 | hw->mr.r_irq_oview |= ovr; | |
1307 | idx = R_IRQ_FIFO_BL0; | |
1308 | ovp = hw->mr.r_irq_fifo_blx; | |
1309 | while (ovr) { | |
1310 | if ((ovr & 1)) { | |
1311 | *ovp |= Read_hfc8(hw, idx); | |
1312 | } | |
1313 | ovp++; | |
1314 | idx++; | |
1315 | ovr >>= 1; | |
1316 | } | |
1317 | } | |
1318 | ||
1319 | /* queue the request to allow other cards to interrupt */ | |
1320 | schedule_work(&hw->tqueue); | |
1321 | ||
1322 | #ifndef CONFIG_HISAX_HFC4S8S_PCIMEM | |
1323 | SetRegAddr(hw, old_ioreg); | |
1324 | #endif | |
1325 | return IRQ_HANDLED; | |
1326 | } /* hfc4s8s_interrupt */ | |
1327 | ||
1328 | /***********************************************************************/ | |
1329 | /* reset the complete chip, don't release the chips irq but disable it */ | |
1330 | /***********************************************************************/ | |
1331 | static void | |
1332 | chipreset(hfc4s8s_hw * hw) | |
1333 | { | |
1334 | u_long flags; | |
1335 | ||
1336 | spin_lock_irqsave(&hw->lock, flags); | |
1337 | Write_hfc8(hw, R_CTRL, 0); /* use internal RAM */ | |
1338 | Write_hfc8(hw, R_RAM_MISC, 0); /* 32k*8 RAM */ | |
1339 | Write_hfc8(hw, R_FIFO_MD, 0); /* fifo mode 386 byte/fifo simple mode */ | |
1340 | Write_hfc8(hw, R_CIRM, M_SRES); /* reset chip */ | |
1341 | hw->mr.r_irq_ctrl = 0; /* interrupt is inactive */ | |
1342 | spin_unlock_irqrestore(&hw->lock, flags); | |
1343 | ||
1344 | udelay(3); | |
1345 | Write_hfc8(hw, R_CIRM, 0); /* disable reset */ | |
1346 | wait_busy(hw); | |
1347 | ||
1348 | Write_hfc8(hw, R_PCM_MD0, M_PCM_MD); /* master mode */ | |
1349 | Write_hfc8(hw, R_RAM_MISC, M_FZ_MD); /* transmit fifo option */ | |
1350 | if (hw->driver_data.clock_mode == 1) | |
1351 | Write_hfc8(hw, R_BRG_PCM_CFG, M_PCM_CLK); /* PCM clk / 2 */ | |
1352 | Write_hfc8(hw, R_TI_WD, TRANS_TIMER_MODE); /* timer interval */ | |
1353 | ||
1354 | memset(&hw->mr, 0, sizeof(hw->mr)); | |
1355 | } /* chipreset */ | |
1356 | ||
1357 | /********************************************/ | |
1358 | /* disable/enable hardware in nt or te mode */ | |
1359 | /********************************************/ | |
672c3fd9 | 1360 | static void |
1da177e4 LT |
1361 | hfc_hardware_enable(hfc4s8s_hw * hw, int enable, int nt_mode) |
1362 | { | |
1363 | u_long flags; | |
1364 | char if_name[40]; | |
1365 | int i; | |
1366 | ||
1367 | if (enable) { | |
1368 | /* save system vars */ | |
1369 | hw->nt_mode = nt_mode; | |
1370 | ||
1371 | /* enable fifo and state irqs, but not global irq enable */ | |
1372 | hw->mr.r_irq_ctrl = M_FIFO_IRQ; | |
1373 | Write_hfc8(hw, R_IRQ_CTRL, hw->mr.r_irq_ctrl); | |
1374 | hw->mr.r_irqmsk_statchg = 0; | |
1375 | Write_hfc8(hw, R_SCI_MSK, hw->mr.r_irqmsk_statchg); | |
1376 | Write_hfc8(hw, R_PWM_MD, 0x80); | |
1377 | Write_hfc8(hw, R_PWM1, 26); | |
1378 | if (!nt_mode) | |
1379 | Write_hfc8(hw, R_ST_SYNC, M_AUTO_SYNC); | |
1380 | ||
1381 | /* enable the line interfaces and fifos */ | |
1382 | for (i = 0; i < hw->driver_data.max_st_ports; i++) { | |
1383 | hw->mr.r_irqmsk_statchg |= (1 << i); | |
1384 | Write_hfc8(hw, R_SCI_MSK, hw->mr.r_irqmsk_statchg); | |
1385 | Write_hfc8(hw, R_ST_SEL, i); | |
1386 | Write_hfc8(hw, A_ST_CLK_DLY, | |
1387 | ((nt_mode) ? CLKDEL_NT : CLKDEL_TE)); | |
1388 | hw->mr.r_ctrl0 = ((nt_mode) ? CTRL0_NT : CTRL0_TE); | |
1389 | Write_hfc8(hw, A_ST_CTRL0, hw->mr.r_ctrl0); | |
1390 | Write_hfc8(hw, A_ST_CTRL2, 3); | |
1391 | Write_hfc8(hw, A_ST_WR_STA, 0); /* enable state machine */ | |
1392 | ||
1393 | hw->l1[i].enabled = 1; | |
1394 | hw->l1[i].nt_mode = nt_mode; | |
1395 | ||
1396 | if (!nt_mode) { | |
1397 | /* setup E-fifo */ | |
1398 | Write_hfc8(hw, R_FIFO, i * 8 + 7); /* E fifo */ | |
1399 | wait_busy(hw); | |
1400 | Write_hfc8(hw, A_CON_HDLC, 0x11); /* HDLC mode, 1 fill, connect ST */ | |
1401 | Write_hfc8(hw, A_SUBCH_CFG, 2); /* only 2 bits */ | |
1402 | Write_hfc8(hw, A_IRQ_MSK, 1); /* enable interrupt */ | |
1403 | Write_hfc8(hw, A_INC_RES_FIFO, 2); /* reset fifo */ | |
1404 | wait_busy(hw); | |
1405 | ||
1406 | /* setup D RX-fifo */ | |
1407 | Write_hfc8(hw, R_FIFO, i * 8 + 5); /* RX fifo */ | |
1408 | wait_busy(hw); | |
1409 | Write_hfc8(hw, A_CON_HDLC, 0x11); /* HDLC mode, 1 fill, connect ST */ | |
1410 | Write_hfc8(hw, A_SUBCH_CFG, 2); /* only 2 bits */ | |
1411 | Write_hfc8(hw, A_IRQ_MSK, 1); /* enable interrupt */ | |
1412 | Write_hfc8(hw, A_INC_RES_FIFO, 2); /* reset fifo */ | |
1413 | wait_busy(hw); | |
1414 | ||
1415 | /* setup D TX-fifo */ | |
1416 | Write_hfc8(hw, R_FIFO, i * 8 + 4); /* TX fifo */ | |
1417 | wait_busy(hw); | |
1418 | Write_hfc8(hw, A_CON_HDLC, 0x11); /* HDLC mode, 1 fill, connect ST */ | |
1419 | Write_hfc8(hw, A_SUBCH_CFG, 2); /* only 2 bits */ | |
1420 | Write_hfc8(hw, A_IRQ_MSK, 1); /* enable interrupt */ | |
1421 | Write_hfc8(hw, A_INC_RES_FIFO, 2); /* reset fifo */ | |
1422 | wait_busy(hw); | |
1423 | } | |
1424 | ||
1425 | sprintf(if_name, "hfc4s8s_%d%d_", hw->cardnum, i); | |
1426 | ||
1427 | if (hisax_register | |
1428 | (&hw->l1[i].d_if, hw->l1[i].b_table, if_name, | |
1429 | ((nt_mode) ? 3 : 2))) { | |
1430 | ||
1431 | hw->l1[i].enabled = 0; | |
1432 | hw->mr.r_irqmsk_statchg &= ~(1 << i); | |
1433 | Write_hfc8(hw, R_SCI_MSK, | |
1434 | hw->mr.r_irqmsk_statchg); | |
1435 | printk(KERN_INFO | |
1436 | "HFC-4S/8S: Unable to register S/T device %s, break\n", | |
1437 | if_name); | |
1438 | break; | |
1439 | } | |
1440 | } | |
1441 | spin_lock_irqsave(&hw->lock, flags); | |
1442 | hw->mr.r_irq_ctrl |= M_GLOB_IRQ_EN; | |
1443 | Write_hfc8(hw, R_IRQ_CTRL, hw->mr.r_irq_ctrl); | |
1444 | spin_unlock_irqrestore(&hw->lock, flags); | |
1445 | } else { | |
1446 | /* disable hardware */ | |
1447 | spin_lock_irqsave(&hw->lock, flags); | |
1448 | hw->mr.r_irq_ctrl &= ~M_GLOB_IRQ_EN; | |
1449 | Write_hfc8(hw, R_IRQ_CTRL, hw->mr.r_irq_ctrl); | |
1450 | spin_unlock_irqrestore(&hw->lock, flags); | |
1451 | ||
1452 | for (i = hw->driver_data.max_st_ports - 1; i >= 0; i--) { | |
1453 | hw->l1[i].enabled = 0; | |
1454 | hisax_unregister(&hw->l1[i].d_if); | |
1455 | del_timer(&hw->l1[i].l1_timer); | |
1456 | skb_queue_purge(&hw->l1[i].d_tx_queue); | |
1457 | skb_queue_purge(&hw->l1[i].b_ch[0].tx_queue); | |
1458 | skb_queue_purge(&hw->l1[i].b_ch[1].tx_queue); | |
1459 | } | |
1460 | chipreset(hw); | |
1461 | } | |
1462 | } /* hfc_hardware_enable */ | |
1463 | ||
1464 | /******************************************/ | |
1465 | /* disable memory mapped ports / io ports */ | |
1466 | /******************************************/ | |
aade0e82 | 1467 | static void |
1da177e4 LT |
1468 | release_pci_ports(hfc4s8s_hw * hw) |
1469 | { | |
1470 | pci_write_config_word(hw->pdev, PCI_COMMAND, 0); | |
1471 | #ifdef CONFIG_HISAX_HFC4S8S_PCIMEM | |
1472 | if (hw->membase) | |
1473 | iounmap((void *) hw->membase); | |
1474 | #else | |
1475 | if (hw->iobase) | |
1476 | release_region(hw->iobase, 8); | |
1477 | #endif | |
1478 | } | |
1479 | ||
1480 | /*****************************************/ | |
1481 | /* enable memory mapped ports / io ports */ | |
1482 | /*****************************************/ | |
aade0e82 | 1483 | static void |
1da177e4 LT |
1484 | enable_pci_ports(hfc4s8s_hw * hw) |
1485 | { | |
1486 | #ifdef CONFIG_HISAX_HFC4S8S_PCIMEM | |
1487 | pci_write_config_word(hw->pdev, PCI_COMMAND, PCI_ENA_MEMIO); | |
1488 | #else | |
1489 | pci_write_config_word(hw->pdev, PCI_COMMAND, PCI_ENA_REGIO); | |
1490 | #endif | |
1491 | } | |
1492 | ||
1493 | /*************************************/ | |
1494 | /* initialise the HFC-4s/8s hardware */ | |
1495 | /* return 0 on success. */ | |
1496 | /*************************************/ | |
1497 | static int __devinit | |
1498 | setup_instance(hfc4s8s_hw * hw) | |
1499 | { | |
1500 | int err = -EIO; | |
1501 | int i; | |
1502 | ||
1503 | for (i = 0; i < HFC_MAX_ST; i++) { | |
1504 | struct hfc4s8s_l1 *l1p; | |
1505 | ||
1506 | l1p = hw->l1 + i; | |
1507 | spin_lock_init(&l1p->lock); | |
1508 | l1p->hw = hw; | |
1509 | l1p->l1_timer.function = (void *) hfc_l1_timer; | |
1510 | l1p->l1_timer.data = (long) (l1p); | |
1511 | init_timer(&l1p->l1_timer); | |
1512 | l1p->st_num = i; | |
1513 | skb_queue_head_init(&l1p->d_tx_queue); | |
1514 | l1p->d_if.ifc.priv = hw->l1 + i; | |
1515 | l1p->d_if.ifc.l2l1 = (void *) dch_l2l1; | |
1516 | ||
1517 | spin_lock_init(&l1p->b_ch[0].lock); | |
1518 | l1p->b_ch[0].b_if.ifc.l2l1 = (void *) bch_l2l1; | |
1519 | l1p->b_ch[0].b_if.ifc.priv = (void *) &l1p->b_ch[0]; | |
1520 | l1p->b_ch[0].l1p = hw->l1 + i; | |
1521 | l1p->b_ch[0].bchan = 1; | |
1522 | l1p->b_table[0] = &l1p->b_ch[0].b_if; | |
1523 | skb_queue_head_init(&l1p->b_ch[0].tx_queue); | |
1524 | ||
1525 | spin_lock_init(&l1p->b_ch[1].lock); | |
1526 | l1p->b_ch[1].b_if.ifc.l2l1 = (void *) bch_l2l1; | |
1527 | l1p->b_ch[1].b_if.ifc.priv = (void *) &l1p->b_ch[1]; | |
1528 | l1p->b_ch[1].l1p = hw->l1 + i; | |
1529 | l1p->b_ch[1].bchan = 2; | |
1530 | l1p->b_table[1] = &l1p->b_ch[1].b_if; | |
1531 | skb_queue_head_init(&l1p->b_ch[1].tx_queue); | |
1532 | } | |
1533 | ||
1534 | enable_pci_ports(hw); | |
1535 | chipreset(hw); | |
1536 | ||
1537 | i = Read_hfc8(hw, R_CHIP_ID) >> CHIP_ID_SHIFT; | |
1538 | if (i != hw->driver_data.chip_id) { | |
1539 | printk(KERN_INFO | |
1540 | "HFC-4S/8S: invalid chip id 0x%x instead of 0x%x, card ignored\n", | |
1541 | i, hw->driver_data.chip_id); | |
1542 | goto out; | |
1543 | } | |
1544 | ||
1545 | i = Read_hfc8(hw, R_CHIP_RV) & 0xf; | |
1546 | if (!i) { | |
1547 | printk(KERN_INFO | |
1548 | "HFC-4S/8S: chip revision 0 not supported, card ignored\n"); | |
1549 | goto out; | |
1550 | } | |
1551 | ||
1552 | INIT_WORK(&hw->tqueue, (void *) (void *) hfc4s8s_bh, hw); | |
1553 | ||
1554 | if (request_irq | |
1555 | (hw->irq, hfc4s8s_interrupt, SA_SHIRQ, hw->card_name, hw)) { | |
1556 | printk(KERN_INFO | |
1557 | "HFC-4S/8S: unable to alloc irq %d, card ignored\n", | |
1558 | hw->irq); | |
1559 | goto out; | |
1560 | } | |
1561 | #ifdef CONFIG_HISAX_HFC4S8S_PCIMEM | |
1562 | printk(KERN_INFO | |
1563 | "HFC-4S/8S: found PCI card at membase 0x%p, irq %d\n", | |
1564 | hw->hw_membase, hw->irq); | |
1565 | #else | |
1566 | printk(KERN_INFO | |
1567 | "HFC-4S/8S: found PCI card at iobase 0x%x, irq %d\n", | |
1568 | hw->iobase, hw->irq); | |
1569 | #endif | |
1570 | ||
1571 | hfc_hardware_enable(hw, 1, 0); | |
1572 | ||
1573 | return (0); | |
1574 | ||
1575 | out: | |
1576 | hw->irq = 0; | |
1577 | release_pci_ports(hw); | |
1578 | kfree(hw); | |
1579 | return (err); | |
1580 | } | |
1581 | ||
1582 | /*****************************************/ | |
1583 | /* PCI hotplug interface: probe new card */ | |
1584 | /*****************************************/ | |
1585 | static int __devinit | |
1586 | hfc4s8s_probe(struct pci_dev *pdev, const struct pci_device_id *ent) | |
1587 | { | |
1588 | int err = -ENOMEM; | |
1589 | hfc4s8s_param *driver_data = (hfc4s8s_param *) ent->driver_data; | |
1590 | hfc4s8s_hw *hw; | |
1591 | ||
1592 | if (!(hw = kmalloc(sizeof(hfc4s8s_hw), GFP_ATOMIC))) { | |
1593 | printk(KERN_ERR "No kmem for HFC-4S/8S card\n"); | |
1594 | return (err); | |
1595 | } | |
1596 | memset(hw, 0, sizeof(hfc4s8s_hw)); | |
1597 | ||
1598 | hw->pdev = pdev; | |
1599 | err = pci_enable_device(pdev); | |
1600 | ||
1601 | if (err) | |
1602 | goto out; | |
1603 | ||
1604 | hw->cardnum = card_cnt; | |
1605 | sprintf(hw->card_name, "hfc4s8s_%d", hw->cardnum); | |
1606 | printk(KERN_INFO "HFC-4S/8S: found adapter %s (%s) at %s\n", | |
1607 | driver_data->device_name, hw->card_name, pci_name(pdev)); | |
1608 | ||
1609 | spin_lock_init(&hw->lock); | |
1610 | ||
1611 | hw->driver_data = *driver_data; | |
1612 | hw->irq = pdev->irq; | |
1613 | hw->iobase = pci_resource_start(pdev, 0); | |
1614 | ||
1615 | #ifdef CONFIG_HISAX_HFC4S8S_PCIMEM | |
1616 | hw->hw_membase = (u_char *) pci_resource_start(pdev, 1); | |
1617 | hw->membase = ioremap((ulong) hw->hw_membase, 256); | |
1618 | #else | |
1619 | if (!request_region(hw->iobase, 8, hw->card_name)) { | |
1620 | printk(KERN_INFO | |
1621 | "HFC-4S/8S: failed to rquest address space at 0x%04x\n", | |
1622 | hw->iobase); | |
1623 | goto out; | |
1624 | } | |
1625 | #endif | |
1626 | ||
1627 | pci_set_drvdata(pdev, hw); | |
1628 | err = setup_instance(hw); | |
1629 | if (!err) | |
1630 | card_cnt++; | |
1631 | return (err); | |
1632 | ||
1633 | out: | |
1634 | kfree(hw); | |
1635 | return (err); | |
1636 | } | |
1637 | ||
1638 | /**************************************/ | |
1639 | /* PCI hotplug interface: remove card */ | |
1640 | /**************************************/ | |
1641 | static void __devexit | |
1642 | hfc4s8s_remove(struct pci_dev *pdev) | |
1643 | { | |
1644 | hfc4s8s_hw *hw = pci_get_drvdata(pdev); | |
1645 | ||
1646 | printk(KERN_INFO "HFC-4S/8S: removing card %d\n", hw->cardnum); | |
1647 | hfc_hardware_enable(hw, 0, 0); | |
1648 | ||
1649 | if (hw->irq) | |
1650 | free_irq(hw->irq, hw); | |
1651 | hw->irq = 0; | |
1652 | release_pci_ports(hw); | |
1653 | ||
1654 | card_cnt--; | |
1655 | pci_disable_device(pdev); | |
1656 | kfree(hw); | |
1657 | return; | |
1658 | } | |
1659 | ||
1660 | static struct pci_driver hfc4s8s_driver = { | |
874ec33f RD |
1661 | .name = "hfc4s8s_l1", |
1662 | .probe = hfc4s8s_probe, | |
1663 | .remove = __devexit_p(hfc4s8s_remove), | |
1664 | .id_table = hfc4s8s_ids, | |
1da177e4 LT |
1665 | }; |
1666 | ||
1667 | /**********************/ | |
1668 | /* driver Module init */ | |
1669 | /**********************/ | |
1670 | static int __init | |
1671 | hfc4s8s_module_init(void) | |
1672 | { | |
1673 | int err; | |
1674 | ||
1675 | printk(KERN_INFO | |
1676 | "HFC-4S/8S: Layer 1 driver module for HFC-4S/8S isdn chips, %s\n", | |
1677 | hfc4s8s_rev); | |
1678 | printk(KERN_INFO | |
1679 | "HFC-4S/8S: (C) 2003 Cornelius Consult, www.cornelius-consult.de\n"); | |
1680 | ||
1681 | card_cnt = 0; | |
1682 | ||
1683 | err = pci_register_driver(&hfc4s8s_driver); | |
1684 | if (err < 0) { | |
1685 | goto out; | |
1686 | } | |
1687 | printk(KERN_INFO "HFC-4S/8S: found %d cards\n", card_cnt); | |
1688 | ||
1689 | #if !defined(CONFIG_HOTPLUG) | |
1690 | if (err == 0) { | |
1691 | err = -ENODEV; | |
1692 | pci_unregister_driver(&hfc4s8s_driver); | |
1693 | goto out; | |
1694 | } | |
1695 | #endif | |
1696 | ||
1697 | return 0; | |
1698 | out: | |
1699 | return (err); | |
1700 | } /* hfc4s8s_init_hw */ | |
1701 | ||
1702 | /*************************************/ | |
1703 | /* driver module exit : */ | |
1704 | /* release the HFC-4s/8s hardware */ | |
1705 | /*************************************/ | |
1706 | static void | |
1707 | hfc4s8s_module_exit(void) | |
1708 | { | |
1709 | pci_unregister_driver(&hfc4s8s_driver); | |
1710 | printk(KERN_INFO "HFC-4S/8S: module removed\n"); | |
1711 | } /* hfc4s8s_release_hw */ | |
1712 | ||
1713 | module_init(hfc4s8s_module_init); | |
1714 | module_exit(hfc4s8s_module_exit); |