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1da177e4 LT |
1 | /*************************************************************************/ |
2 | /* $Id: hfc4s8s_l1.c,v 1.10 2005/02/09 16:31:09 martinb1 Exp $ */ | |
3 | /* HFC-4S/8S low layer interface for Cologne Chip HFC-4S/8S isdn chips */ | |
4 | /* The low layer (L1) is implemented as a loadable module for usage with */ | |
5 | /* the HiSax isdn driver for passive cards. */ | |
6 | /* */ | |
7 | /* Author: Werner Cornelius */ | |
8 | /* (C) 2003 Cornelius Consult (werner@cornelius-consult.de) */ | |
9 | /* */ | |
10 | /* Driver maintained by Cologne Chip */ | |
11 | /* - Martin Bachem, support@colognechip.com */ | |
12 | /* */ | |
13 | /* This driver only works with chip revisions >= 1, older revision 0 */ | |
14 | /* engineering samples (only first manufacturer sample cards) will not */ | |
15 | /* work and are rejected by the driver. */ | |
16 | /* */ | |
17 | /* This file distributed under the GNU GPL. */ | |
18 | /* */ | |
19 | /* See Version History at the end of this file */ | |
20 | /* */ | |
21 | /*************************************************************************/ | |
22 | ||
23 | #include <linux/module.h> | |
24 | #include <linux/init.h> | |
1da177e4 LT |
25 | #include <linux/pci.h> |
26 | #include <linux/interrupt.h> | |
27 | #include <linux/delay.h> | |
5a0e3ad6 | 28 | #include <linux/slab.h> |
1da177e4 LT |
29 | #include <linux/timer.h> |
30 | #include <linux/skbuff.h> | |
31 | #include <linux/wait.h> | |
a62e7cef | 32 | #include <asm/io.h> |
1da177e4 LT |
33 | #include "hisax_if.h" |
34 | #include "hfc4s8s_l1.h" | |
35 | ||
36 | static const char hfc4s8s_rev[] = "Revision: 1.10"; | |
37 | ||
38 | /***************************************************************/ | |
39 | /* adjustable transparent mode fifo threshold */ | |
40 | /* The value defines the used fifo threshold with the equation */ | |
41 | /* */ | |
42 | /* notify number of bytes = 2 * 2 ^ TRANS_FIFO_THRES */ | |
43 | /* */ | |
44 | /* The default value is 5 which results in a buffer size of 64 */ | |
45 | /* and an interrupt rate of 8ms. */ | |
46 | /* The maximum value is 7 due to fifo size restrictions. */ | |
47 | /* Values below 3-4 are not recommended due to high interrupt */ | |
48 | /* load of the processor. For non critical applications the */ | |
49 | /* value should be raised to 7 to reduce any interrupt overhead*/ | |
50 | /***************************************************************/ | |
51 | #define TRANS_FIFO_THRES 5 | |
52 | ||
53 | /*************/ | |
54 | /* constants */ | |
55 | /*************/ | |
56 | #define CLOCKMODE_0 0 /* ext. 24.576 MhZ clk freq, int. single clock mode */ | |
57 | #define CLOCKMODE_1 1 /* ext. 49.576 MhZ clk freq, int. single clock mode */ | |
58 | #define CHIP_ID_SHIFT 4 | |
59 | #define HFC_MAX_ST 8 | |
60 | #define MAX_D_FRAME_SIZE 270 | |
61 | #define MAX_B_FRAME_SIZE 1536 | |
62 | #define TRANS_TIMER_MODE (TRANS_FIFO_THRES & 0xf) | |
63 | #define TRANS_FIFO_BYTES (2 << TRANS_FIFO_THRES) | |
64 | #define MAX_F_CNT 0x0f | |
65 | ||
66 | #define CLKDEL_NT 0x6c | |
67 | #define CLKDEL_TE 0xf | |
68 | #define CTRL0_NT 4 | |
69 | #define CTRL0_TE 0 | |
70 | ||
71 | #define L1_TIMER_T4 2 /* minimum in jiffies */ | |
72 | #define L1_TIMER_T3 (7 * HZ) /* activation timeout */ | |
73 | #define L1_TIMER_T1 ((120 * HZ) / 1000) /* NT mode deactivation timeout */ | |
74 | ||
75 | ||
76 | /******************/ | |
77 | /* types and vars */ | |
78 | /******************/ | |
79 | static int card_cnt; | |
80 | ||
81 | /* private driver_data */ | |
82 | typedef struct { | |
83 | int chip_id; | |
84 | int clock_mode; | |
85 | int max_st_ports; | |
86 | char *device_name; | |
87 | } hfc4s8s_param; | |
88 | ||
89 | static struct pci_device_id hfc4s8s_ids[] = { | |
90 | {.vendor = PCI_VENDOR_ID_CCD, | |
91 | .device = PCI_DEVICE_ID_4S, | |
92 | .subvendor = 0x1397, | |
93 | .subdevice = 0x08b4, | |
94 | .driver_data = | |
95 | (unsigned long) &((hfc4s8s_param) {CHIP_ID_4S, CLOCKMODE_0, 4, | |
475be4d8 JP |
96 | "HFC-4S Evaluation Board"}), |
97 | }, | |
1da177e4 LT |
98 | {.vendor = PCI_VENDOR_ID_CCD, |
99 | .device = PCI_DEVICE_ID_8S, | |
100 | .subvendor = 0x1397, | |
101 | .subdevice = 0x16b8, | |
102 | .driver_data = | |
103 | (unsigned long) &((hfc4s8s_param) {CHIP_ID_8S, CLOCKMODE_0, 8, | |
475be4d8 JP |
104 | "HFC-8S Evaluation Board"}), |
105 | }, | |
1da177e4 LT |
106 | {.vendor = PCI_VENDOR_ID_CCD, |
107 | .device = PCI_DEVICE_ID_4S, | |
108 | .subvendor = 0x1397, | |
109 | .subdevice = 0xb520, | |
110 | .driver_data = | |
111 | (unsigned long) &((hfc4s8s_param) {CHIP_ID_4S, CLOCKMODE_1, 4, | |
475be4d8 JP |
112 | "IOB4ST"}), |
113 | }, | |
1da177e4 LT |
114 | {.vendor = PCI_VENDOR_ID_CCD, |
115 | .device = PCI_DEVICE_ID_8S, | |
116 | .subvendor = 0x1397, | |
117 | .subdevice = 0xb522, | |
118 | .driver_data = | |
119 | (unsigned long) &((hfc4s8s_param) {CHIP_ID_8S, CLOCKMODE_1, 8, | |
475be4d8 JP |
120 | "IOB8ST"}), |
121 | }, | |
1da177e4 LT |
122 | {} |
123 | }; | |
124 | ||
125 | MODULE_DEVICE_TABLE(pci, hfc4s8s_ids); | |
126 | ||
127 | MODULE_AUTHOR("Werner Cornelius, werner@cornelius-consult.de"); | |
128 | MODULE_DESCRIPTION("ISDN layer 1 for Cologne Chip HFC-4S/8S chips"); | |
129 | MODULE_LICENSE("GPL"); | |
130 | ||
131 | /***********/ | |
132 | /* layer 1 */ | |
133 | /***********/ | |
134 | struct hfc4s8s_btype { | |
135 | spinlock_t lock; | |
136 | struct hisax_b_if b_if; | |
137 | struct hfc4s8s_l1 *l1p; | |
138 | struct sk_buff_head tx_queue; | |
139 | struct sk_buff *tx_skb; | |
140 | struct sk_buff *rx_skb; | |
141 | __u8 *rx_ptr; | |
142 | int tx_cnt; | |
143 | int bchan; | |
144 | int mode; | |
145 | }; | |
146 | ||
147 | struct _hfc4s8s_hw; | |
148 | ||
149 | struct hfc4s8s_l1 { | |
150 | spinlock_t lock; | |
151 | struct _hfc4s8s_hw *hw; /* pointer to hardware area */ | |
152 | int l1_state; /* actual l1 state */ | |
153 | struct timer_list l1_timer; /* layer 1 timer structure */ | |
154 | int nt_mode; /* set to nt mode */ | |
155 | int st_num; /* own index */ | |
156 | int enabled; /* interface is enabled */ | |
157 | struct sk_buff_head d_tx_queue; /* send queue */ | |
158 | int tx_cnt; /* bytes to send */ | |
159 | struct hisax_d_if d_if; /* D-channel interface */ | |
160 | struct hfc4s8s_btype b_ch[2]; /* B-channel data */ | |
161 | struct hisax_b_if *b_table[2]; | |
162 | }; | |
163 | ||
164 | /**********************/ | |
165 | /* hardware structure */ | |
166 | /**********************/ | |
167 | typedef struct _hfc4s8s_hw { | |
168 | spinlock_t lock; | |
169 | ||
170 | int cardnum; | |
171 | int ifnum; | |
172 | int iobase; | |
173 | int nt_mode; | |
174 | u_char *membase; | |
175 | u_char *hw_membase; | |
176 | void *pdev; | |
177 | int max_fifo; | |
178 | hfc4s8s_param driver_data; | |
179 | int irq; | |
180 | int fifo_sched_cnt; | |
181 | struct work_struct tqueue; | |
182 | struct hfc4s8s_l1 l1[HFC_MAX_ST]; | |
183 | char card_name[60]; | |
184 | struct { | |
185 | u_char r_irq_ctrl; | |
186 | u_char r_ctrl0; | |
187 | volatile u_char r_irq_statech; /* active isdn l1 status */ | |
188 | u_char r_irqmsk_statchg; /* enabled isdn status ints */ | |
189 | u_char r_irq_fifo_blx[8]; /* fifo status registers */ | |
190 | u_char fifo_rx_trans_enables[8]; /* mask for enabled transparent rx fifos */ | |
191 | u_char fifo_slow_timer_service[8]; /* mask for fifos needing slower timer service */ | |
192 | volatile u_char r_irq_oview; /* contents of overview register */ | |
193 | volatile u_char timer_irq; | |
194 | int timer_usg_cnt; /* number of channels using timer */ | |
195 | } mr; | |
196 | } hfc4s8s_hw; | |
197 | ||
198 | ||
199 | ||
1da177e4 LT |
200 | /* inline functions io mapped */ |
201 | static inline void | |
475be4d8 | 202 | SetRegAddr(hfc4s8s_hw *a, u_char b) |
1da177e4 LT |
203 | { |
204 | outb(b, (a->iobase) + 4); | |
205 | } | |
206 | ||
207 | static inline u_char | |
475be4d8 | 208 | GetRegAddr(hfc4s8s_hw *a) |
1da177e4 LT |
209 | { |
210 | return (inb((volatile u_int) (a->iobase + 4))); | |
211 | } | |
212 | ||
213 | ||
214 | static inline void | |
475be4d8 | 215 | Write_hfc8(hfc4s8s_hw *a, u_char b, u_char c) |
1da177e4 LT |
216 | { |
217 | SetRegAddr(a, b); | |
218 | outb(c, a->iobase); | |
219 | } | |
220 | ||
221 | static inline void | |
475be4d8 | 222 | fWrite_hfc8(hfc4s8s_hw *a, u_char c) |
1da177e4 LT |
223 | { |
224 | outb(c, a->iobase); | |
225 | } | |
226 | ||
1da177e4 | 227 | static inline void |
475be4d8 | 228 | fWrite_hfc32(hfc4s8s_hw *a, u_long c) |
1da177e4 LT |
229 | { |
230 | outl(c, a->iobase); | |
231 | } | |
232 | ||
233 | static inline u_char | |
475be4d8 | 234 | Read_hfc8(hfc4s8s_hw *a, u_char b) |
1da177e4 LT |
235 | { |
236 | SetRegAddr(a, b); | |
237 | return (inb((volatile u_int) a->iobase)); | |
238 | } | |
239 | ||
240 | static inline u_char | |
475be4d8 | 241 | fRead_hfc8(hfc4s8s_hw *a) |
1da177e4 LT |
242 | { |
243 | return (inb((volatile u_int) a->iobase)); | |
244 | } | |
245 | ||
246 | ||
247 | static inline u_short | |
475be4d8 | 248 | Read_hfc16(hfc4s8s_hw *a, u_char b) |
1da177e4 LT |
249 | { |
250 | SetRegAddr(a, b); | |
251 | return (inw((volatile u_int) a->iobase)); | |
252 | } | |
253 | ||
1da177e4 | 254 | static inline u_long |
475be4d8 | 255 | fRead_hfc32(hfc4s8s_hw *a) |
1da177e4 LT |
256 | { |
257 | return (inl((volatile u_int) a->iobase)); | |
258 | } | |
259 | ||
260 | static inline void | |
475be4d8 | 261 | wait_busy(hfc4s8s_hw *a) |
1da177e4 LT |
262 | { |
263 | SetRegAddr(a, R_STATUS); | |
264 | while (inb((volatile u_int) a->iobase) & M_BUSY); | |
265 | } | |
266 | ||
267 | #define PCI_ENA_REGIO 0x01 | |
268 | ||
1da177e4 LT |
269 | /******************************************************/ |
270 | /* function to read critical counter registers that */ | |
88393161 | 271 | /* may be updated by the chip during read */ |
1da177e4 | 272 | /******************************************************/ |
b79646e3 | 273 | static u_char |
475be4d8 | 274 | Read_hfc8_stable(hfc4s8s_hw *hw, int reg) |
1da177e4 LT |
275 | { |
276 | u_char ref8; | |
277 | u_char in8; | |
278 | ref8 = Read_hfc8(hw, reg); | |
279 | while (((in8 = Read_hfc8(hw, reg)) != ref8)) { | |
280 | ref8 = in8; | |
281 | } | |
282 | return in8; | |
283 | } | |
284 | ||
b79646e3 | 285 | static int |
475be4d8 | 286 | Read_hfc16_stable(hfc4s8s_hw *hw, int reg) |
1da177e4 LT |
287 | { |
288 | int ref16; | |
289 | int in16; | |
290 | ||
291 | ref16 = Read_hfc16(hw, reg); | |
292 | while (((in16 = Read_hfc16(hw, reg)) != ref16)) { | |
293 | ref16 = in16; | |
294 | } | |
295 | return in16; | |
296 | } | |
297 | ||
298 | /*****************************/ | |
299 | /* D-channel call from HiSax */ | |
300 | /*****************************/ | |
301 | static void | |
302 | dch_l2l1(struct hisax_d_if *iface, int pr, void *arg) | |
303 | { | |
304 | struct hfc4s8s_l1 *l1 = iface->ifc.priv; | |
305 | struct sk_buff *skb = (struct sk_buff *) arg; | |
306 | u_long flags; | |
307 | ||
308 | switch (pr) { | |
309 | ||
475be4d8 JP |
310 | case (PH_DATA | REQUEST): |
311 | if (!l1->enabled) { | |
312 | dev_kfree_skb(skb); | |
1da177e4 | 313 | break; |
475be4d8 JP |
314 | } |
315 | spin_lock_irqsave(&l1->lock, flags); | |
316 | skb_queue_tail(&l1->d_tx_queue, skb); | |
317 | if ((skb_queue_len(&l1->d_tx_queue) == 1) && | |
318 | (l1->tx_cnt <= 0)) { | |
319 | l1->hw->mr.r_irq_fifo_blx[l1->st_num] |= | |
320 | 0x10; | |
321 | spin_unlock_irqrestore(&l1->lock, flags); | |
322 | schedule_work(&l1->hw->tqueue); | |
323 | } else | |
324 | spin_unlock_irqrestore(&l1->lock, flags); | |
325 | break; | |
1da177e4 | 326 | |
475be4d8 JP |
327 | case (PH_ACTIVATE | REQUEST): |
328 | if (!l1->enabled) | |
1da177e4 | 329 | break; |
475be4d8 JP |
330 | if (!l1->nt_mode) { |
331 | if (l1->l1_state < 6) { | |
332 | spin_lock_irqsave(&l1->lock, | |
333 | flags); | |
334 | ||
335 | Write_hfc8(l1->hw, R_ST_SEL, | |
336 | l1->st_num); | |
337 | Write_hfc8(l1->hw, A_ST_WR_STA, | |
338 | 0x60); | |
339 | mod_timer(&l1->l1_timer, | |
340 | jiffies + L1_TIMER_T3); | |
341 | spin_unlock_irqrestore(&l1->lock, | |
342 | flags); | |
343 | } else if (l1->l1_state == 7) | |
344 | l1->d_if.ifc.l1l2(&l1->d_if.ifc, | |
345 | PH_ACTIVATE | | |
346 | INDICATION, | |
347 | NULL); | |
348 | } else { | |
349 | if (l1->l1_state != 3) { | |
350 | spin_lock_irqsave(&l1->lock, | |
351 | flags); | |
352 | Write_hfc8(l1->hw, R_ST_SEL, | |
353 | l1->st_num); | |
354 | Write_hfc8(l1->hw, A_ST_WR_STA, | |
355 | 0x60); | |
356 | spin_unlock_irqrestore(&l1->lock, | |
357 | flags); | |
358 | } else if (l1->l1_state == 3) | |
359 | l1->d_if.ifc.l1l2(&l1->d_if.ifc, | |
360 | PH_ACTIVATE | | |
361 | INDICATION, | |
362 | NULL); | |
363 | } | |
364 | break; | |
1da177e4 | 365 | |
475be4d8 JP |
366 | default: |
367 | printk(KERN_INFO | |
368 | "HFC-4S/8S: Unknown D-chan cmd 0x%x received, ignored\n", | |
369 | pr); | |
370 | break; | |
1da177e4 LT |
371 | } |
372 | if (!l1->enabled) | |
373 | l1->d_if.ifc.l1l2(&l1->d_if.ifc, | |
374 | PH_DEACTIVATE | INDICATION, NULL); | |
375 | } /* dch_l2l1 */ | |
376 | ||
377 | /*****************************/ | |
378 | /* B-channel call from HiSax */ | |
379 | /*****************************/ | |
380 | static void | |
381 | bch_l2l1(struct hisax_if *ifc, int pr, void *arg) | |
382 | { | |
383 | struct hfc4s8s_btype *bch = ifc->priv; | |
384 | struct hfc4s8s_l1 *l1 = bch->l1p; | |
385 | struct sk_buff *skb = (struct sk_buff *) arg; | |
17a4506d | 386 | long mode = (long) arg; |
1da177e4 LT |
387 | u_long flags; |
388 | ||
389 | switch (pr) { | |
390 | ||
475be4d8 JP |
391 | case (PH_DATA | REQUEST): |
392 | if (!l1->enabled || (bch->mode == L1_MODE_NULL)) { | |
393 | dev_kfree_skb(skb); | |
1da177e4 | 394 | break; |
475be4d8 JP |
395 | } |
396 | spin_lock_irqsave(&l1->lock, flags); | |
397 | skb_queue_tail(&bch->tx_queue, skb); | |
398 | if (!bch->tx_skb && (bch->tx_cnt <= 0)) { | |
399 | l1->hw->mr.r_irq_fifo_blx[l1->st_num] |= | |
400 | ((bch->bchan == 1) ? 1 : 4); | |
401 | spin_unlock_irqrestore(&l1->lock, flags); | |
402 | schedule_work(&l1->hw->tqueue); | |
403 | } else | |
404 | spin_unlock_irqrestore(&l1->lock, flags); | |
405 | break; | |
1da177e4 | 406 | |
475be4d8 JP |
407 | case (PH_ACTIVATE | REQUEST): |
408 | case (PH_DEACTIVATE | REQUEST): | |
409 | if (!l1->enabled) | |
410 | break; | |
411 | if (pr == (PH_DEACTIVATE | REQUEST)) | |
412 | mode = L1_MODE_NULL; | |
413 | ||
414 | switch (mode) { | |
415 | case L1_MODE_HDLC: | |
416 | spin_lock_irqsave(&l1->lock, | |
417 | flags); | |
418 | l1->hw->mr.timer_usg_cnt++; | |
419 | l1->hw->mr. | |
420 | fifo_slow_timer_service[l1-> | |
421 | st_num] | |
422 | |= | |
423 | ((bch->bchan == | |
424 | 1) ? 0x2 : 0x8); | |
425 | Write_hfc8(l1->hw, R_FIFO, | |
426 | (l1->st_num * 8 + | |
427 | ((bch->bchan == | |
428 | 1) ? 0 : 2))); | |
429 | wait_busy(l1->hw); | |
430 | Write_hfc8(l1->hw, A_CON_HDLC, 0xc); /* HDLC mode, flag fill, connect ST */ | |
431 | Write_hfc8(l1->hw, A_SUBCH_CFG, 0); /* 8 bits */ | |
432 | Write_hfc8(l1->hw, A_IRQ_MSK, 1); /* enable TX interrupts for hdlc */ | |
433 | Write_hfc8(l1->hw, A_INC_RES_FIFO, 2); /* reset fifo */ | |
434 | wait_busy(l1->hw); | |
1da177e4 | 435 | |
475be4d8 JP |
436 | Write_hfc8(l1->hw, R_FIFO, |
437 | (l1->st_num * 8 + | |
438 | ((bch->bchan == | |
439 | 1) ? 1 : 3))); | |
440 | wait_busy(l1->hw); | |
441 | Write_hfc8(l1->hw, A_CON_HDLC, 0xc); /* HDLC mode, flag fill, connect ST */ | |
442 | Write_hfc8(l1->hw, A_SUBCH_CFG, 0); /* 8 bits */ | |
443 | Write_hfc8(l1->hw, A_IRQ_MSK, 1); /* enable RX interrupts for hdlc */ | |
444 | Write_hfc8(l1->hw, A_INC_RES_FIFO, 2); /* reset fifo */ | |
445 | ||
446 | Write_hfc8(l1->hw, R_ST_SEL, | |
447 | l1->st_num); | |
448 | l1->hw->mr.r_ctrl0 |= | |
449 | (bch->bchan & 3); | |
450 | Write_hfc8(l1->hw, A_ST_CTRL0, | |
451 | l1->hw->mr.r_ctrl0); | |
452 | bch->mode = L1_MODE_HDLC; | |
453 | spin_unlock_irqrestore(&l1->lock, | |
454 | flags); | |
455 | ||
456 | bch->b_if.ifc.l1l2(&bch->b_if.ifc, | |
457 | PH_ACTIVATE | | |
458 | INDICATION, | |
459 | NULL); | |
460 | break; | |
1da177e4 | 461 | |
475be4d8 JP |
462 | case L1_MODE_TRANS: |
463 | spin_lock_irqsave(&l1->lock, | |
464 | flags); | |
465 | l1->hw->mr. | |
466 | fifo_rx_trans_enables[l1-> | |
467 | st_num] | |
468 | |= | |
469 | ((bch->bchan == | |
470 | 1) ? 0x2 : 0x8); | |
471 | l1->hw->mr.timer_usg_cnt++; | |
472 | Write_hfc8(l1->hw, R_FIFO, | |
473 | (l1->st_num * 8 + | |
474 | ((bch->bchan == | |
475 | 1) ? 0 : 2))); | |
476 | wait_busy(l1->hw); | |
477 | Write_hfc8(l1->hw, A_CON_HDLC, 0xf); /* Transparent mode, 1 fill, connect ST */ | |
478 | Write_hfc8(l1->hw, A_SUBCH_CFG, 0); /* 8 bits */ | |
479 | Write_hfc8(l1->hw, A_IRQ_MSK, 0); /* disable TX interrupts */ | |
480 | Write_hfc8(l1->hw, A_INC_RES_FIFO, 2); /* reset fifo */ | |
481 | wait_busy(l1->hw); | |
482 | ||
483 | Write_hfc8(l1->hw, R_FIFO, | |
484 | (l1->st_num * 8 + | |
485 | ((bch->bchan == | |
486 | 1) ? 1 : 3))); | |
487 | wait_busy(l1->hw); | |
488 | Write_hfc8(l1->hw, A_CON_HDLC, 0xf); /* Transparent mode, 1 fill, connect ST */ | |
489 | Write_hfc8(l1->hw, A_SUBCH_CFG, 0); /* 8 bits */ | |
490 | Write_hfc8(l1->hw, A_IRQ_MSK, 0); /* disable RX interrupts */ | |
491 | Write_hfc8(l1->hw, A_INC_RES_FIFO, 2); /* reset fifo */ | |
492 | ||
493 | Write_hfc8(l1->hw, R_ST_SEL, | |
494 | l1->st_num); | |
495 | l1->hw->mr.r_ctrl0 |= | |
496 | (bch->bchan & 3); | |
497 | Write_hfc8(l1->hw, A_ST_CTRL0, | |
498 | l1->hw->mr.r_ctrl0); | |
499 | bch->mode = L1_MODE_TRANS; | |
500 | spin_unlock_irqrestore(&l1->lock, | |
501 | flags); | |
502 | ||
503 | bch->b_if.ifc.l1l2(&bch->b_if.ifc, | |
504 | PH_ACTIVATE | | |
505 | INDICATION, | |
506 | NULL); | |
1da177e4 LT |
507 | break; |
508 | ||
509 | default: | |
475be4d8 JP |
510 | if (bch->mode == L1_MODE_NULL) |
511 | break; | |
512 | spin_lock_irqsave(&l1->lock, | |
513 | flags); | |
514 | l1->hw->mr. | |
515 | fifo_slow_timer_service[l1-> | |
516 | st_num] | |
517 | &= | |
518 | ~((bch->bchan == | |
519 | 1) ? 0x3 : 0xc); | |
520 | l1->hw->mr. | |
521 | fifo_rx_trans_enables[l1-> | |
522 | st_num] | |
523 | &= | |
524 | ~((bch->bchan == | |
525 | 1) ? 0x3 : 0xc); | |
526 | l1->hw->mr.timer_usg_cnt--; | |
527 | Write_hfc8(l1->hw, R_FIFO, | |
528 | (l1->st_num * 8 + | |
529 | ((bch->bchan == | |
530 | 1) ? 0 : 2))); | |
531 | wait_busy(l1->hw); | |
532 | Write_hfc8(l1->hw, A_IRQ_MSK, 0); /* disable TX interrupts */ | |
533 | wait_busy(l1->hw); | |
534 | Write_hfc8(l1->hw, R_FIFO, | |
535 | (l1->st_num * 8 + | |
536 | ((bch->bchan == | |
537 | 1) ? 1 : 3))); | |
538 | wait_busy(l1->hw); | |
539 | Write_hfc8(l1->hw, A_IRQ_MSK, 0); /* disable RX interrupts */ | |
540 | Write_hfc8(l1->hw, R_ST_SEL, | |
541 | l1->st_num); | |
542 | l1->hw->mr.r_ctrl0 &= | |
543 | ~(bch->bchan & 3); | |
544 | Write_hfc8(l1->hw, A_ST_CTRL0, | |
545 | l1->hw->mr.r_ctrl0); | |
546 | spin_unlock_irqrestore(&l1->lock, | |
547 | flags); | |
548 | ||
549 | bch->mode = L1_MODE_NULL; | |
550 | bch->b_if.ifc.l1l2(&bch->b_if.ifc, | |
551 | PH_DEACTIVATE | | |
552 | INDICATION, | |
553 | NULL); | |
554 | if (bch->tx_skb) { | |
555 | dev_kfree_skb(bch->tx_skb); | |
556 | bch->tx_skb = NULL; | |
557 | } | |
558 | if (bch->rx_skb) { | |
559 | dev_kfree_skb(bch->rx_skb); | |
560 | bch->rx_skb = NULL; | |
561 | } | |
562 | skb_queue_purge(&bch->tx_queue); | |
563 | bch->tx_cnt = 0; | |
564 | bch->rx_ptr = NULL; | |
1da177e4 | 565 | break; |
475be4d8 JP |
566 | } |
567 | ||
568 | /* timer is only used when at least one b channel */ | |
569 | /* is set up to transparent mode */ | |
570 | if (l1->hw->mr.timer_usg_cnt) { | |
571 | Write_hfc8(l1->hw, R_IRQMSK_MISC, | |
572 | M_TI_IRQMSK); | |
573 | } else { | |
574 | Write_hfc8(l1->hw, R_IRQMSK_MISC, 0); | |
575 | } | |
576 | ||
577 | break; | |
578 | ||
579 | default: | |
580 | printk(KERN_INFO | |
581 | "HFC-4S/8S: Unknown B-chan cmd 0x%x received, ignored\n", | |
582 | pr); | |
583 | break; | |
1da177e4 LT |
584 | } |
585 | if (!l1->enabled) | |
586 | bch->b_if.ifc.l1l2(&bch->b_if.ifc, | |
587 | PH_DEACTIVATE | INDICATION, NULL); | |
588 | } /* bch_l2l1 */ | |
589 | ||
590 | /**************************/ | |
591 | /* layer 1 timer function */ | |
592 | /**************************/ | |
593 | static void | |
594 | hfc_l1_timer(struct hfc4s8s_l1 *l1) | |
595 | { | |
596 | u_long flags; | |
597 | ||
598 | if (!l1->enabled) | |
599 | return; | |
600 | ||
601 | spin_lock_irqsave(&l1->lock, flags); | |
602 | if (l1->nt_mode) { | |
603 | l1->l1_state = 1; | |
604 | Write_hfc8(l1->hw, R_ST_SEL, l1->st_num); | |
605 | Write_hfc8(l1->hw, A_ST_WR_STA, 0x11); | |
606 | spin_unlock_irqrestore(&l1->lock, flags); | |
607 | l1->d_if.ifc.l1l2(&l1->d_if.ifc, | |
608 | PH_DEACTIVATE | INDICATION, NULL); | |
609 | spin_lock_irqsave(&l1->lock, flags); | |
610 | l1->l1_state = 1; | |
611 | Write_hfc8(l1->hw, A_ST_WR_STA, 0x1); | |
612 | spin_unlock_irqrestore(&l1->lock, flags); | |
613 | } else { | |
614 | /* activation timed out */ | |
615 | Write_hfc8(l1->hw, R_ST_SEL, l1->st_num); | |
616 | Write_hfc8(l1->hw, A_ST_WR_STA, 0x13); | |
617 | spin_unlock_irqrestore(&l1->lock, flags); | |
618 | l1->d_if.ifc.l1l2(&l1->d_if.ifc, | |
619 | PH_DEACTIVATE | INDICATION, NULL); | |
620 | spin_lock_irqsave(&l1->lock, flags); | |
621 | Write_hfc8(l1->hw, R_ST_SEL, l1->st_num); | |
622 | Write_hfc8(l1->hw, A_ST_WR_STA, 0x3); | |
623 | spin_unlock_irqrestore(&l1->lock, flags); | |
624 | } | |
625 | } /* hfc_l1_timer */ | |
626 | ||
627 | /****************************************/ | |
628 | /* a complete D-frame has been received */ | |
629 | /****************************************/ | |
630 | static void | |
631 | rx_d_frame(struct hfc4s8s_l1 *l1p, int ech) | |
632 | { | |
633 | int z1, z2; | |
634 | u_char f1, f2, df; | |
635 | struct sk_buff *skb; | |
636 | u_char *cp; | |
637 | ||
638 | ||
639 | if (!l1p->enabled) | |
640 | return; | |
641 | do { | |
642 | /* E/D RX fifo */ | |
643 | Write_hfc8(l1p->hw, R_FIFO, | |
644 | (l1p->st_num * 8 + ((ech) ? 7 : 5))); | |
645 | wait_busy(l1p->hw); | |
646 | ||
647 | f1 = Read_hfc8_stable(l1p->hw, A_F1); | |
648 | f2 = Read_hfc8(l1p->hw, A_F2); | |
1da177e4 | 649 | |
8f89642f AH |
650 | if (f1 < f2) |
651 | df = MAX_F_CNT + 1 + f1 - f2; | |
652 | else | |
653 | df = f1 - f2; | |
1da177e4 | 654 | |
8f89642f | 655 | if (!df) |
1da177e4 | 656 | return; /* no complete frame in fifo */ |
1da177e4 LT |
657 | |
658 | z1 = Read_hfc16_stable(l1p->hw, A_Z1); | |
659 | z2 = Read_hfc16(l1p->hw, A_Z2); | |
660 | ||
661 | z1 = z1 - z2 + 1; | |
662 | if (z1 < 0) | |
663 | z1 += 384; | |
664 | ||
665 | if (!(skb = dev_alloc_skb(MAX_D_FRAME_SIZE))) { | |
666 | printk(KERN_INFO | |
667 | "HFC-4S/8S: Could not allocate D/E " | |
668 | "channel receive buffer"); | |
669 | Write_hfc8(l1p->hw, A_INC_RES_FIFO, 2); | |
670 | wait_busy(l1p->hw); | |
671 | return; | |
672 | } | |
673 | ||
674 | if (((z1 < 4) || (z1 > MAX_D_FRAME_SIZE))) { | |
675 | if (skb) | |
676 | dev_kfree_skb(skb); | |
677 | /* remove errornous D frame */ | |
678 | if (df == 1) { | |
679 | /* reset fifo */ | |
680 | Write_hfc8(l1p->hw, A_INC_RES_FIFO, 2); | |
681 | wait_busy(l1p->hw); | |
682 | return; | |
683 | } else { | |
684 | /* read errornous D frame */ | |
1da177e4 | 685 | SetRegAddr(l1p->hw, A_FIFO_DATA0); |
1da177e4 LT |
686 | |
687 | while (z1 >= 4) { | |
1da177e4 | 688 | fRead_hfc32(l1p->hw); |
1da177e4 LT |
689 | z1 -= 4; |
690 | } | |
691 | ||
692 | while (z1--) | |
d1f88a66 | 693 | fRead_hfc8(l1p->hw); |
1da177e4 LT |
694 | |
695 | Write_hfc8(l1p->hw, A_INC_RES_FIFO, 1); | |
696 | wait_busy(l1p->hw); | |
697 | return; | |
698 | } | |
699 | } | |
700 | ||
701 | cp = skb->data; | |
702 | ||
1da177e4 | 703 | SetRegAddr(l1p->hw, A_FIFO_DATA0); |
1da177e4 LT |
704 | |
705 | while (z1 >= 4) { | |
1da177e4 | 706 | *((unsigned long *) cp) = fRead_hfc32(l1p->hw); |
1da177e4 LT |
707 | cp += 4; |
708 | z1 -= 4; | |
709 | } | |
710 | ||
711 | while (z1--) | |
d1f88a66 | 712 | *cp++ = fRead_hfc8(l1p->hw); |
1da177e4 LT |
713 | |
714 | Write_hfc8(l1p->hw, A_INC_RES_FIFO, 1); /* increment f counter */ | |
715 | wait_busy(l1p->hw); | |
716 | ||
717 | if (*(--cp)) { | |
718 | dev_kfree_skb(skb); | |
719 | } else { | |
720 | skb->len = (cp - skb->data) - 2; | |
721 | if (ech) | |
722 | l1p->d_if.ifc.l1l2(&l1p->d_if.ifc, | |
723 | PH_DATA_E | INDICATION, | |
724 | skb); | |
725 | else | |
726 | l1p->d_if.ifc.l1l2(&l1p->d_if.ifc, | |
727 | PH_DATA | INDICATION, | |
728 | skb); | |
729 | } | |
730 | } while (1); | |
731 | } /* rx_d_frame */ | |
732 | ||
733 | /*************************************************************/ | |
734 | /* a B-frame has been received (perhaps not fully completed) */ | |
735 | /*************************************************************/ | |
736 | static void | |
737 | rx_b_frame(struct hfc4s8s_btype *bch) | |
738 | { | |
739 | int z1, z2, hdlc_complete; | |
740 | u_char f1, f2; | |
741 | struct hfc4s8s_l1 *l1 = bch->l1p; | |
742 | struct sk_buff *skb; | |
743 | ||
744 | if (!l1->enabled || (bch->mode == L1_MODE_NULL)) | |
745 | return; | |
746 | ||
747 | do { | |
748 | /* RX Fifo */ | |
749 | Write_hfc8(l1->hw, R_FIFO, | |
750 | (l1->st_num * 8 + ((bch->bchan == 1) ? 1 : 3))); | |
751 | wait_busy(l1->hw); | |
752 | ||
753 | if (bch->mode == L1_MODE_HDLC) { | |
754 | f1 = Read_hfc8_stable(l1->hw, A_F1); | |
755 | f2 = Read_hfc8(l1->hw, A_F2); | |
756 | hdlc_complete = ((f1 ^ f2) & MAX_F_CNT); | |
757 | } else | |
758 | hdlc_complete = 0; | |
759 | z1 = Read_hfc16_stable(l1->hw, A_Z1); | |
760 | z2 = Read_hfc16(l1->hw, A_Z2); | |
761 | z1 = (z1 - z2); | |
762 | if (hdlc_complete) | |
763 | z1++; | |
764 | if (z1 < 0) | |
765 | z1 += 384; | |
766 | ||
767 | if (!z1) | |
768 | break; | |
769 | ||
770 | if (!(skb = bch->rx_skb)) { | |
771 | if (! | |
772 | (skb = | |
773 | dev_alloc_skb((bch->mode == | |
774 | L1_MODE_TRANS) ? z1 | |
775 | : (MAX_B_FRAME_SIZE + 3)))) { | |
776 | printk(KERN_ERR | |
777 | "HFC-4S/8S: Could not allocate B " | |
778 | "channel receive buffer"); | |
779 | return; | |
780 | } | |
781 | bch->rx_ptr = skb->data; | |
782 | bch->rx_skb = skb; | |
783 | } | |
784 | ||
785 | skb->len = (bch->rx_ptr - skb->data) + z1; | |
786 | ||
787 | /* HDLC length check */ | |
788 | if ((bch->mode == L1_MODE_HDLC) && | |
789 | ((hdlc_complete && (skb->len < 4)) || | |
790 | (skb->len > (MAX_B_FRAME_SIZE + 3)))) { | |
791 | ||
792 | skb->len = 0; | |
793 | bch->rx_ptr = skb->data; | |
794 | Write_hfc8(l1->hw, A_INC_RES_FIFO, 2); /* reset fifo */ | |
795 | wait_busy(l1->hw); | |
796 | return; | |
797 | } | |
1da177e4 | 798 | SetRegAddr(l1->hw, A_FIFO_DATA0); |
1da177e4 LT |
799 | |
800 | while (z1 >= 4) { | |
1da177e4 | 801 | *((unsigned long *) bch->rx_ptr) = |
475be4d8 | 802 | fRead_hfc32(l1->hw); |
1da177e4 LT |
803 | bch->rx_ptr += 4; |
804 | z1 -= 4; | |
805 | } | |
806 | ||
807 | while (z1--) | |
d1f88a66 | 808 | *(bch->rx_ptr++) = fRead_hfc8(l1->hw); |
1da177e4 LT |
809 | |
810 | if (hdlc_complete) { | |
811 | /* increment f counter */ | |
812 | Write_hfc8(l1->hw, A_INC_RES_FIFO, 1); | |
813 | wait_busy(l1->hw); | |
814 | ||
815 | /* hdlc crc check */ | |
816 | bch->rx_ptr--; | |
817 | if (*bch->rx_ptr) { | |
818 | skb->len = 0; | |
819 | bch->rx_ptr = skb->data; | |
820 | continue; | |
821 | } | |
822 | skb->len -= 3; | |
823 | } | |
824 | if (hdlc_complete || (bch->mode == L1_MODE_TRANS)) { | |
825 | bch->rx_skb = NULL; | |
826 | bch->rx_ptr = NULL; | |
827 | bch->b_if.ifc.l1l2(&bch->b_if.ifc, | |
828 | PH_DATA | INDICATION, skb); | |
829 | } | |
830 | ||
831 | } while (1); | |
832 | } /* rx_b_frame */ | |
833 | ||
834 | /********************************************/ | |
835 | /* a D-frame has been/should be transmitted */ | |
836 | /********************************************/ | |
837 | static void | |
838 | tx_d_frame(struct hfc4s8s_l1 *l1p) | |
839 | { | |
840 | struct sk_buff *skb; | |
841 | u_char f1, f2; | |
842 | u_char *cp; | |
17a4506d | 843 | long cnt; |
1da177e4 LT |
844 | |
845 | if (l1p->l1_state != 7) | |
846 | return; | |
847 | ||
848 | /* TX fifo */ | |
849 | Write_hfc8(l1p->hw, R_FIFO, (l1p->st_num * 8 + 4)); | |
850 | wait_busy(l1p->hw); | |
851 | ||
852 | f1 = Read_hfc8(l1p->hw, A_F1); | |
853 | f2 = Read_hfc8_stable(l1p->hw, A_F2); | |
854 | ||
855 | if ((f1 ^ f2) & MAX_F_CNT) | |
856 | return; /* fifo is still filled */ | |
857 | ||
858 | if (l1p->tx_cnt > 0) { | |
859 | cnt = l1p->tx_cnt; | |
860 | l1p->tx_cnt = 0; | |
861 | l1p->d_if.ifc.l1l2(&l1p->d_if.ifc, PH_DATA | CONFIRM, | |
862 | (void *) cnt); | |
863 | } | |
864 | ||
865 | if ((skb = skb_dequeue(&l1p->d_tx_queue))) { | |
866 | cp = skb->data; | |
867 | cnt = skb->len; | |
1da177e4 | 868 | SetRegAddr(l1p->hw, A_FIFO_DATA0); |
1da177e4 LT |
869 | |
870 | while (cnt >= 4) { | |
1da177e4 LT |
871 | SetRegAddr(l1p->hw, A_FIFO_DATA0); |
872 | fWrite_hfc32(l1p->hw, *(unsigned long *) cp); | |
1da177e4 LT |
873 | cp += 4; |
874 | cnt -= 4; | |
875 | } | |
876 | ||
1da177e4 LT |
877 | while (cnt--) |
878 | fWrite_hfc8(l1p->hw, *cp++); | |
1da177e4 LT |
879 | |
880 | l1p->tx_cnt = skb->truesize; | |
881 | Write_hfc8(l1p->hw, A_INC_RES_FIFO, 1); /* increment f counter */ | |
882 | wait_busy(l1p->hw); | |
883 | ||
884 | dev_kfree_skb(skb); | |
885 | } | |
886 | } /* tx_d_frame */ | |
887 | ||
888 | /******************************************************/ | |
889 | /* a B-frame may be transmitted (or is not completed) */ | |
890 | /******************************************************/ | |
891 | static void | |
892 | tx_b_frame(struct hfc4s8s_btype *bch) | |
893 | { | |
894 | struct sk_buff *skb; | |
895 | struct hfc4s8s_l1 *l1 = bch->l1p; | |
896 | u_char *cp; | |
17a4506d AC |
897 | int cnt, max, hdlc_num; |
898 | long ack_len = 0; | |
1da177e4 LT |
899 | |
900 | if (!l1->enabled || (bch->mode == L1_MODE_NULL)) | |
901 | return; | |
902 | ||
903 | /* TX fifo */ | |
904 | Write_hfc8(l1->hw, R_FIFO, | |
905 | (l1->st_num * 8 + ((bch->bchan == 1) ? 0 : 2))); | |
906 | wait_busy(l1->hw); | |
907 | do { | |
908 | ||
909 | if (bch->mode == L1_MODE_HDLC) { | |
910 | hdlc_num = Read_hfc8(l1->hw, A_F1) & MAX_F_CNT; | |
911 | hdlc_num -= | |
475be4d8 | 912 | (Read_hfc8_stable(l1->hw, A_F2) & MAX_F_CNT); |
1da177e4 LT |
913 | if (hdlc_num < 0) |
914 | hdlc_num += 16; | |
915 | if (hdlc_num >= 15) | |
916 | break; /* fifo still filled up with hdlc frames */ | |
917 | } else | |
918 | hdlc_num = 0; | |
919 | ||
920 | if (!(skb = bch->tx_skb)) { | |
921 | if (!(skb = skb_dequeue(&bch->tx_queue))) { | |
922 | l1->hw->mr.fifo_slow_timer_service[l1-> | |
923 | st_num] | |
475be4d8 | 924 | &= ~((bch->bchan == 1) ? 1 : 4); |
1da177e4 LT |
925 | break; /* list empty */ |
926 | } | |
927 | bch->tx_skb = skb; | |
928 | bch->tx_cnt = 0; | |
929 | } | |
930 | ||
931 | if (!hdlc_num) | |
932 | l1->hw->mr.fifo_slow_timer_service[l1->st_num] |= | |
475be4d8 | 933 | ((bch->bchan == 1) ? 1 : 4); |
1da177e4 LT |
934 | else |
935 | l1->hw->mr.fifo_slow_timer_service[l1->st_num] &= | |
475be4d8 | 936 | ~((bch->bchan == 1) ? 1 : 4); |
1da177e4 LT |
937 | |
938 | max = Read_hfc16_stable(l1->hw, A_Z2); | |
939 | max -= Read_hfc16(l1->hw, A_Z1); | |
940 | if (max <= 0) | |
941 | max += 384; | |
942 | max--; | |
943 | ||
944 | if (max < 16) | |
945 | break; /* don't write to small amounts of bytes */ | |
946 | ||
947 | cnt = skb->len - bch->tx_cnt; | |
948 | if (cnt > max) | |
949 | cnt = max; | |
950 | cp = skb->data + bch->tx_cnt; | |
951 | bch->tx_cnt += cnt; | |
952 | ||
1da177e4 | 953 | SetRegAddr(l1->hw, A_FIFO_DATA0); |
1da177e4 | 954 | while (cnt >= 4) { |
1da177e4 | 955 | fWrite_hfc32(l1->hw, *(unsigned long *) cp); |
1da177e4 LT |
956 | cp += 4; |
957 | cnt -= 4; | |
958 | } | |
959 | ||
960 | while (cnt--) | |
d1f88a66 | 961 | fWrite_hfc8(l1->hw, *cp++); |
1da177e4 LT |
962 | |
963 | if (bch->tx_cnt >= skb->len) { | |
964 | if (bch->mode == L1_MODE_HDLC) { | |
965 | /* increment f counter */ | |
966 | Write_hfc8(l1->hw, A_INC_RES_FIFO, 1); | |
967 | } | |
968 | ack_len += skb->truesize; | |
874ec33f | 969 | bch->tx_skb = NULL; |
1da177e4 LT |
970 | bch->tx_cnt = 0; |
971 | dev_kfree_skb(skb); | |
972 | } else | |
973 | /* Re-Select */ | |
974 | Write_hfc8(l1->hw, R_FIFO, | |
975 | (l1->st_num * 8 + | |
976 | ((bch->bchan == 1) ? 0 : 2))); | |
977 | wait_busy(l1->hw); | |
978 | } while (1); | |
979 | ||
980 | if (ack_len) | |
981 | bch->b_if.ifc.l1l2((struct hisax_if *) &bch->b_if, | |
982 | PH_DATA | CONFIRM, (void *) ack_len); | |
983 | } /* tx_b_frame */ | |
984 | ||
985 | /*************************************/ | |
986 | /* bottom half handler for interrupt */ | |
987 | /*************************************/ | |
988 | static void | |
c4028958 | 989 | hfc4s8s_bh(struct work_struct *work) |
1da177e4 | 990 | { |
c4028958 | 991 | hfc4s8s_hw *hw = container_of(work, hfc4s8s_hw, tqueue); |
1da177e4 LT |
992 | u_char b; |
993 | struct hfc4s8s_l1 *l1p; | |
994 | volatile u_char *fifo_stat; | |
995 | int idx; | |
996 | ||
997 | /* handle layer 1 state changes */ | |
998 | b = 1; | |
999 | l1p = hw->l1; | |
1000 | while (b) { | |
1001 | if ((b & hw->mr.r_irq_statech)) { | |
1002 | /* reset l1 event */ | |
1003 | hw->mr.r_irq_statech &= ~b; | |
1004 | if (l1p->enabled) { | |
1005 | if (l1p->nt_mode) { | |
1006 | u_char oldstate = l1p->l1_state; | |
1007 | ||
1008 | Write_hfc8(l1p->hw, R_ST_SEL, | |
1009 | l1p->st_num); | |
1010 | l1p->l1_state = | |
475be4d8 JP |
1011 | Read_hfc8(l1p->hw, |
1012 | A_ST_RD_STA) & 0xf; | |
1da177e4 LT |
1013 | |
1014 | if ((oldstate == 3) | |
1015 | && (l1p->l1_state != 3)) | |
1016 | l1p->d_if.ifc.l1l2(&l1p-> | |
1017 | d_if. | |
1018 | ifc, | |
1019 | PH_DEACTIVATE | |
1020 | | | |
1021 | INDICATION, | |
1022 | NULL); | |
1023 | ||
1024 | if (l1p->l1_state != 2) { | |
1025 | del_timer(&l1p->l1_timer); | |
1026 | if (l1p->l1_state == 3) { | |
1027 | l1p->d_if.ifc. | |
475be4d8 JP |
1028 | l1l2(&l1p-> |
1029 | d_if.ifc, | |
1030 | PH_ACTIVATE | |
1031 | | | |
1032 | INDICATION, | |
1033 | NULL); | |
1da177e4 LT |
1034 | } |
1035 | } else { | |
1036 | /* allow transition */ | |
1037 | Write_hfc8(hw, A_ST_WR_STA, | |
1038 | M_SET_G2_G3); | |
1039 | mod_timer(&l1p->l1_timer, | |
1040 | jiffies + | |
1041 | L1_TIMER_T1); | |
1042 | } | |
1043 | printk(KERN_INFO | |
1044 | "HFC-4S/8S: NT ch %d l1 state %d -> %d\n", | |
1045 | l1p->st_num, oldstate, | |
1046 | l1p->l1_state); | |
1047 | } else { | |
1048 | u_char oldstate = l1p->l1_state; | |
1049 | ||
1050 | Write_hfc8(l1p->hw, R_ST_SEL, | |
1051 | l1p->st_num); | |
1052 | l1p->l1_state = | |
475be4d8 JP |
1053 | Read_hfc8(l1p->hw, |
1054 | A_ST_RD_STA) & 0xf; | |
1da177e4 LT |
1055 | |
1056 | if (((l1p->l1_state == 3) && | |
1057 | ((oldstate == 7) || | |
1058 | (oldstate == 8))) || | |
1059 | ((timer_pending | |
1060 | (&l1p->l1_timer)) | |
1061 | && (l1p->l1_state == 8))) { | |
1062 | mod_timer(&l1p->l1_timer, | |
1063 | L1_TIMER_T4 + | |
1064 | jiffies); | |
1065 | } else { | |
1066 | if (l1p->l1_state == 7) { | |
1067 | del_timer(&l1p-> | |
1068 | l1_timer); | |
1069 | l1p->d_if.ifc. | |
475be4d8 JP |
1070 | l1l2(&l1p-> |
1071 | d_if.ifc, | |
1072 | PH_ACTIVATE | |
1073 | | | |
1074 | INDICATION, | |
1075 | NULL); | |
1da177e4 LT |
1076 | tx_d_frame(l1p); |
1077 | } | |
1078 | if (l1p->l1_state == 3) { | |
1079 | if (oldstate != 3) | |
1080 | l1p->d_if. | |
475be4d8 JP |
1081 | ifc. |
1082 | l1l2 | |
1083 | (&l1p-> | |
1084 | d_if. | |
1085 | ifc, | |
1086 | PH_DEACTIVATE | |
1087 | | | |
1088 | INDICATION, | |
1089 | NULL); | |
1da177e4 LT |
1090 | } |
1091 | } | |
1092 | printk(KERN_INFO | |
1093 | "HFC-4S/8S: TE %d ch %d l1 state %d -> %d\n", | |
1094 | l1p->hw->cardnum, | |
1095 | l1p->st_num, oldstate, | |
1096 | l1p->l1_state); | |
1097 | } | |
1098 | } | |
1099 | } | |
1100 | b <<= 1; | |
1101 | l1p++; | |
1102 | } | |
1103 | ||
1104 | /* now handle the fifos */ | |
1105 | idx = 0; | |
1106 | fifo_stat = hw->mr.r_irq_fifo_blx; | |
1107 | l1p = hw->l1; | |
1108 | while (idx < hw->driver_data.max_st_ports) { | |
1109 | ||
1110 | if (hw->mr.timer_irq) { | |
1111 | *fifo_stat |= hw->mr.fifo_rx_trans_enables[idx]; | |
1112 | if (hw->fifo_sched_cnt <= 0) { | |
1113 | *fifo_stat |= | |
475be4d8 JP |
1114 | hw->mr.fifo_slow_timer_service[l1p-> |
1115 | st_num]; | |
1da177e4 LT |
1116 | } |
1117 | } | |
1118 | /* ignore fifo 6 (TX E fifo) */ | |
1119 | *fifo_stat &= 0xff - 0x40; | |
1120 | ||
1121 | while (*fifo_stat) { | |
1122 | ||
1123 | if (!l1p->nt_mode) { | |
1124 | /* RX Fifo has data to read */ | |
1125 | if ((*fifo_stat & 0x20)) { | |
1126 | *fifo_stat &= ~0x20; | |
1127 | rx_d_frame(l1p, 0); | |
1128 | } | |
1129 | /* E Fifo has data to read */ | |
1130 | if ((*fifo_stat & 0x80)) { | |
1131 | *fifo_stat &= ~0x80; | |
1132 | rx_d_frame(l1p, 1); | |
1133 | } | |
1134 | /* TX Fifo completed send */ | |
1135 | if ((*fifo_stat & 0x10)) { | |
1136 | *fifo_stat &= ~0x10; | |
1137 | tx_d_frame(l1p); | |
1138 | } | |
1139 | } | |
1140 | /* B1 RX Fifo has data to read */ | |
1141 | if ((*fifo_stat & 0x2)) { | |
1142 | *fifo_stat &= ~0x2; | |
1143 | rx_b_frame(l1p->b_ch); | |
1144 | } | |
1145 | /* B1 TX Fifo has send completed */ | |
1146 | if ((*fifo_stat & 0x1)) { | |
1147 | *fifo_stat &= ~0x1; | |
1148 | tx_b_frame(l1p->b_ch); | |
1149 | } | |
1150 | /* B2 RX Fifo has data to read */ | |
1151 | if ((*fifo_stat & 0x8)) { | |
1152 | *fifo_stat &= ~0x8; | |
1153 | rx_b_frame(l1p->b_ch + 1); | |
1154 | } | |
1155 | /* B2 TX Fifo has send completed */ | |
1156 | if ((*fifo_stat & 0x4)) { | |
1157 | *fifo_stat &= ~0x4; | |
1158 | tx_b_frame(l1p->b_ch + 1); | |
1159 | } | |
1160 | } | |
1161 | fifo_stat++; | |
1162 | l1p++; | |
1163 | idx++; | |
1164 | } | |
1165 | ||
1166 | if (hw->fifo_sched_cnt <= 0) | |
1167 | hw->fifo_sched_cnt += (1 << (7 - TRANS_TIMER_MODE)); | |
1168 | hw->mr.timer_irq = 0; /* clear requested timer irq */ | |
1169 | } /* hfc4s8s_bh */ | |
1170 | ||
1171 | /*********************/ | |
1172 | /* interrupt handler */ | |
1173 | /*********************/ | |
1174 | static irqreturn_t | |
7d12e780 | 1175 | hfc4s8s_interrupt(int intno, void *dev_id) |
1da177e4 LT |
1176 | { |
1177 | hfc4s8s_hw *hw = dev_id; | |
1178 | u_char b, ovr; | |
1179 | volatile u_char *ovp; | |
1180 | int idx; | |
1181 | u_char old_ioreg; | |
1182 | ||
1183 | if (!hw || !(hw->mr.r_irq_ctrl & M_GLOB_IRQ_EN)) | |
1184 | return IRQ_NONE; | |
1185 | ||
1da177e4 LT |
1186 | /* read current selected regsister */ |
1187 | old_ioreg = GetRegAddr(hw); | |
1da177e4 LT |
1188 | |
1189 | /* Layer 1 State change */ | |
1190 | hw->mr.r_irq_statech |= | |
475be4d8 | 1191 | (Read_hfc8(hw, R_SCI) & hw->mr.r_irqmsk_statchg); |
1da177e4 LT |
1192 | if (! |
1193 | (b = (Read_hfc8(hw, R_STATUS) & (M_MISC_IRQSTA | M_FR_IRQSTA))) | |
475be4d8 | 1194 | && !hw->mr.r_irq_statech) { |
1da177e4 | 1195 | SetRegAddr(hw, old_ioreg); |
1da177e4 LT |
1196 | return IRQ_NONE; |
1197 | } | |
1198 | ||
1199 | /* timer event */ | |
1200 | if (Read_hfc8(hw, R_IRQ_MISC) & M_TI_IRQ) { | |
1201 | hw->mr.timer_irq = 1; | |
1202 | hw->fifo_sched_cnt--; | |
1203 | } | |
1204 | ||
1205 | /* FIFO event */ | |
1206 | if ((ovr = Read_hfc8(hw, R_IRQ_OVIEW))) { | |
1207 | hw->mr.r_irq_oview |= ovr; | |
1208 | idx = R_IRQ_FIFO_BL0; | |
1209 | ovp = hw->mr.r_irq_fifo_blx; | |
1210 | while (ovr) { | |
1211 | if ((ovr & 1)) { | |
1212 | *ovp |= Read_hfc8(hw, idx); | |
1213 | } | |
1214 | ovp++; | |
1215 | idx++; | |
1216 | ovr >>= 1; | |
1217 | } | |
1218 | } | |
1219 | ||
1220 | /* queue the request to allow other cards to interrupt */ | |
1221 | schedule_work(&hw->tqueue); | |
1222 | ||
1da177e4 | 1223 | SetRegAddr(hw, old_ioreg); |
1da177e4 LT |
1224 | return IRQ_HANDLED; |
1225 | } /* hfc4s8s_interrupt */ | |
1226 | ||
1227 | /***********************************************************************/ | |
1228 | /* reset the complete chip, don't release the chips irq but disable it */ | |
1229 | /***********************************************************************/ | |
1230 | static void | |
475be4d8 | 1231 | chipreset(hfc4s8s_hw *hw) |
1da177e4 LT |
1232 | { |
1233 | u_long flags; | |
1234 | ||
1235 | spin_lock_irqsave(&hw->lock, flags); | |
1236 | Write_hfc8(hw, R_CTRL, 0); /* use internal RAM */ | |
1237 | Write_hfc8(hw, R_RAM_MISC, 0); /* 32k*8 RAM */ | |
1238 | Write_hfc8(hw, R_FIFO_MD, 0); /* fifo mode 386 byte/fifo simple mode */ | |
1239 | Write_hfc8(hw, R_CIRM, M_SRES); /* reset chip */ | |
1240 | hw->mr.r_irq_ctrl = 0; /* interrupt is inactive */ | |
1241 | spin_unlock_irqrestore(&hw->lock, flags); | |
1242 | ||
1243 | udelay(3); | |
1244 | Write_hfc8(hw, R_CIRM, 0); /* disable reset */ | |
1245 | wait_busy(hw); | |
1246 | ||
1247 | Write_hfc8(hw, R_PCM_MD0, M_PCM_MD); /* master mode */ | |
1248 | Write_hfc8(hw, R_RAM_MISC, M_FZ_MD); /* transmit fifo option */ | |
1249 | if (hw->driver_data.clock_mode == 1) | |
1250 | Write_hfc8(hw, R_BRG_PCM_CFG, M_PCM_CLK); /* PCM clk / 2 */ | |
1251 | Write_hfc8(hw, R_TI_WD, TRANS_TIMER_MODE); /* timer interval */ | |
1252 | ||
1253 | memset(&hw->mr, 0, sizeof(hw->mr)); | |
1254 | } /* chipreset */ | |
1255 | ||
1256 | /********************************************/ | |
1257 | /* disable/enable hardware in nt or te mode */ | |
1258 | /********************************************/ | |
672c3fd9 | 1259 | static void |
475be4d8 | 1260 | hfc_hardware_enable(hfc4s8s_hw *hw, int enable, int nt_mode) |
1da177e4 LT |
1261 | { |
1262 | u_long flags; | |
1263 | char if_name[40]; | |
1264 | int i; | |
1265 | ||
1266 | if (enable) { | |
1267 | /* save system vars */ | |
1268 | hw->nt_mode = nt_mode; | |
1269 | ||
1270 | /* enable fifo and state irqs, but not global irq enable */ | |
1271 | hw->mr.r_irq_ctrl = M_FIFO_IRQ; | |
1272 | Write_hfc8(hw, R_IRQ_CTRL, hw->mr.r_irq_ctrl); | |
1273 | hw->mr.r_irqmsk_statchg = 0; | |
1274 | Write_hfc8(hw, R_SCI_MSK, hw->mr.r_irqmsk_statchg); | |
1275 | Write_hfc8(hw, R_PWM_MD, 0x80); | |
1276 | Write_hfc8(hw, R_PWM1, 26); | |
1277 | if (!nt_mode) | |
1278 | Write_hfc8(hw, R_ST_SYNC, M_AUTO_SYNC); | |
1279 | ||
1280 | /* enable the line interfaces and fifos */ | |
1281 | for (i = 0; i < hw->driver_data.max_st_ports; i++) { | |
1282 | hw->mr.r_irqmsk_statchg |= (1 << i); | |
1283 | Write_hfc8(hw, R_SCI_MSK, hw->mr.r_irqmsk_statchg); | |
1284 | Write_hfc8(hw, R_ST_SEL, i); | |
1285 | Write_hfc8(hw, A_ST_CLK_DLY, | |
1286 | ((nt_mode) ? CLKDEL_NT : CLKDEL_TE)); | |
1287 | hw->mr.r_ctrl0 = ((nt_mode) ? CTRL0_NT : CTRL0_TE); | |
1288 | Write_hfc8(hw, A_ST_CTRL0, hw->mr.r_ctrl0); | |
1289 | Write_hfc8(hw, A_ST_CTRL2, 3); | |
1290 | Write_hfc8(hw, A_ST_WR_STA, 0); /* enable state machine */ | |
1291 | ||
1292 | hw->l1[i].enabled = 1; | |
1293 | hw->l1[i].nt_mode = nt_mode; | |
1294 | ||
1295 | if (!nt_mode) { | |
1296 | /* setup E-fifo */ | |
1297 | Write_hfc8(hw, R_FIFO, i * 8 + 7); /* E fifo */ | |
1298 | wait_busy(hw); | |
1299 | Write_hfc8(hw, A_CON_HDLC, 0x11); /* HDLC mode, 1 fill, connect ST */ | |
1300 | Write_hfc8(hw, A_SUBCH_CFG, 2); /* only 2 bits */ | |
1301 | Write_hfc8(hw, A_IRQ_MSK, 1); /* enable interrupt */ | |
1302 | Write_hfc8(hw, A_INC_RES_FIFO, 2); /* reset fifo */ | |
1303 | wait_busy(hw); | |
1304 | ||
1305 | /* setup D RX-fifo */ | |
1306 | Write_hfc8(hw, R_FIFO, i * 8 + 5); /* RX fifo */ | |
1307 | wait_busy(hw); | |
1308 | Write_hfc8(hw, A_CON_HDLC, 0x11); /* HDLC mode, 1 fill, connect ST */ | |
1309 | Write_hfc8(hw, A_SUBCH_CFG, 2); /* only 2 bits */ | |
1310 | Write_hfc8(hw, A_IRQ_MSK, 1); /* enable interrupt */ | |
1311 | Write_hfc8(hw, A_INC_RES_FIFO, 2); /* reset fifo */ | |
1312 | wait_busy(hw); | |
1313 | ||
1314 | /* setup D TX-fifo */ | |
1315 | Write_hfc8(hw, R_FIFO, i * 8 + 4); /* TX fifo */ | |
1316 | wait_busy(hw); | |
1317 | Write_hfc8(hw, A_CON_HDLC, 0x11); /* HDLC mode, 1 fill, connect ST */ | |
1318 | Write_hfc8(hw, A_SUBCH_CFG, 2); /* only 2 bits */ | |
1319 | Write_hfc8(hw, A_IRQ_MSK, 1); /* enable interrupt */ | |
1320 | Write_hfc8(hw, A_INC_RES_FIFO, 2); /* reset fifo */ | |
1321 | wait_busy(hw); | |
1322 | } | |
1323 | ||
1324 | sprintf(if_name, "hfc4s8s_%d%d_", hw->cardnum, i); | |
1325 | ||
1326 | if (hisax_register | |
1327 | (&hw->l1[i].d_if, hw->l1[i].b_table, if_name, | |
1328 | ((nt_mode) ? 3 : 2))) { | |
1329 | ||
1330 | hw->l1[i].enabled = 0; | |
1331 | hw->mr.r_irqmsk_statchg &= ~(1 << i); | |
1332 | Write_hfc8(hw, R_SCI_MSK, | |
1333 | hw->mr.r_irqmsk_statchg); | |
1334 | printk(KERN_INFO | |
1335 | "HFC-4S/8S: Unable to register S/T device %s, break\n", | |
1336 | if_name); | |
1337 | break; | |
1338 | } | |
1339 | } | |
1340 | spin_lock_irqsave(&hw->lock, flags); | |
1341 | hw->mr.r_irq_ctrl |= M_GLOB_IRQ_EN; | |
1342 | Write_hfc8(hw, R_IRQ_CTRL, hw->mr.r_irq_ctrl); | |
1343 | spin_unlock_irqrestore(&hw->lock, flags); | |
1344 | } else { | |
1345 | /* disable hardware */ | |
1346 | spin_lock_irqsave(&hw->lock, flags); | |
1347 | hw->mr.r_irq_ctrl &= ~M_GLOB_IRQ_EN; | |
1348 | Write_hfc8(hw, R_IRQ_CTRL, hw->mr.r_irq_ctrl); | |
1349 | spin_unlock_irqrestore(&hw->lock, flags); | |
1350 | ||
1351 | for (i = hw->driver_data.max_st_ports - 1; i >= 0; i--) { | |
1352 | hw->l1[i].enabled = 0; | |
1353 | hisax_unregister(&hw->l1[i].d_if); | |
1354 | del_timer(&hw->l1[i].l1_timer); | |
1355 | skb_queue_purge(&hw->l1[i].d_tx_queue); | |
1356 | skb_queue_purge(&hw->l1[i].b_ch[0].tx_queue); | |
1357 | skb_queue_purge(&hw->l1[i].b_ch[1].tx_queue); | |
1358 | } | |
1359 | chipreset(hw); | |
1360 | } | |
1361 | } /* hfc_hardware_enable */ | |
1362 | ||
1363 | /******************************************/ | |
1364 | /* disable memory mapped ports / io ports */ | |
1365 | /******************************************/ | |
aade0e82 | 1366 | static void |
475be4d8 | 1367 | release_pci_ports(hfc4s8s_hw *hw) |
1da177e4 LT |
1368 | { |
1369 | pci_write_config_word(hw->pdev, PCI_COMMAND, 0); | |
1da177e4 LT |
1370 | if (hw->iobase) |
1371 | release_region(hw->iobase, 8); | |
1da177e4 LT |
1372 | } |
1373 | ||
1374 | /*****************************************/ | |
1375 | /* enable memory mapped ports / io ports */ | |
1376 | /*****************************************/ | |
aade0e82 | 1377 | static void |
475be4d8 | 1378 | enable_pci_ports(hfc4s8s_hw *hw) |
1da177e4 | 1379 | { |
1da177e4 | 1380 | pci_write_config_word(hw->pdev, PCI_COMMAND, PCI_ENA_REGIO); |
1da177e4 LT |
1381 | } |
1382 | ||
1383 | /*************************************/ | |
1384 | /* initialise the HFC-4s/8s hardware */ | |
1385 | /* return 0 on success. */ | |
1386 | /*************************************/ | |
ed5a84cd | 1387 | static int |
475be4d8 | 1388 | setup_instance(hfc4s8s_hw *hw) |
1da177e4 LT |
1389 | { |
1390 | int err = -EIO; | |
1391 | int i; | |
1392 | ||
1393 | for (i = 0; i < HFC_MAX_ST; i++) { | |
1394 | struct hfc4s8s_l1 *l1p; | |
1395 | ||
1396 | l1p = hw->l1 + i; | |
1397 | spin_lock_init(&l1p->lock); | |
1398 | l1p->hw = hw; | |
1399 | l1p->l1_timer.function = (void *) hfc_l1_timer; | |
1400 | l1p->l1_timer.data = (long) (l1p); | |
1401 | init_timer(&l1p->l1_timer); | |
1402 | l1p->st_num = i; | |
1403 | skb_queue_head_init(&l1p->d_tx_queue); | |
1404 | l1p->d_if.ifc.priv = hw->l1 + i; | |
1405 | l1p->d_if.ifc.l2l1 = (void *) dch_l2l1; | |
1406 | ||
1407 | spin_lock_init(&l1p->b_ch[0].lock); | |
1408 | l1p->b_ch[0].b_if.ifc.l2l1 = (void *) bch_l2l1; | |
1409 | l1p->b_ch[0].b_if.ifc.priv = (void *) &l1p->b_ch[0]; | |
1410 | l1p->b_ch[0].l1p = hw->l1 + i; | |
1411 | l1p->b_ch[0].bchan = 1; | |
1412 | l1p->b_table[0] = &l1p->b_ch[0].b_if; | |
1413 | skb_queue_head_init(&l1p->b_ch[0].tx_queue); | |
1414 | ||
1415 | spin_lock_init(&l1p->b_ch[1].lock); | |
1416 | l1p->b_ch[1].b_if.ifc.l2l1 = (void *) bch_l2l1; | |
1417 | l1p->b_ch[1].b_if.ifc.priv = (void *) &l1p->b_ch[1]; | |
1418 | l1p->b_ch[1].l1p = hw->l1 + i; | |
1419 | l1p->b_ch[1].bchan = 2; | |
1420 | l1p->b_table[1] = &l1p->b_ch[1].b_if; | |
1421 | skb_queue_head_init(&l1p->b_ch[1].tx_queue); | |
1422 | } | |
1423 | ||
1424 | enable_pci_ports(hw); | |
1425 | chipreset(hw); | |
1426 | ||
1427 | i = Read_hfc8(hw, R_CHIP_ID) >> CHIP_ID_SHIFT; | |
1428 | if (i != hw->driver_data.chip_id) { | |
1429 | printk(KERN_INFO | |
1430 | "HFC-4S/8S: invalid chip id 0x%x instead of 0x%x, card ignored\n", | |
1431 | i, hw->driver_data.chip_id); | |
1432 | goto out; | |
1433 | } | |
1434 | ||
1435 | i = Read_hfc8(hw, R_CHIP_RV) & 0xf; | |
1436 | if (!i) { | |
1437 | printk(KERN_INFO | |
1438 | "HFC-4S/8S: chip revision 0 not supported, card ignored\n"); | |
1439 | goto out; | |
1440 | } | |
1441 | ||
c4028958 | 1442 | INIT_WORK(&hw->tqueue, hfc4s8s_bh); |
1da177e4 LT |
1443 | |
1444 | if (request_irq | |
9ba02bec | 1445 | (hw->irq, hfc4s8s_interrupt, IRQF_SHARED, hw->card_name, hw)) { |
1da177e4 LT |
1446 | printk(KERN_INFO |
1447 | "HFC-4S/8S: unable to alloc irq %d, card ignored\n", | |
1448 | hw->irq); | |
1449 | goto out; | |
1450 | } | |
1da177e4 LT |
1451 | printk(KERN_INFO |
1452 | "HFC-4S/8S: found PCI card at iobase 0x%x, irq %d\n", | |
1453 | hw->iobase, hw->irq); | |
1da177e4 LT |
1454 | |
1455 | hfc_hardware_enable(hw, 1, 0); | |
1456 | ||
1457 | return (0); | |
1458 | ||
475be4d8 | 1459 | out: |
1da177e4 LT |
1460 | hw->irq = 0; |
1461 | release_pci_ports(hw); | |
1462 | kfree(hw); | |
1463 | return (err); | |
1464 | } | |
1465 | ||
1466 | /*****************************************/ | |
1467 | /* PCI hotplug interface: probe new card */ | |
1468 | /*****************************************/ | |
ed5a84cd | 1469 | static int |
1da177e4 LT |
1470 | hfc4s8s_probe(struct pci_dev *pdev, const struct pci_device_id *ent) |
1471 | { | |
1472 | int err = -ENOMEM; | |
1473 | hfc4s8s_param *driver_data = (hfc4s8s_param *) ent->driver_data; | |
1474 | hfc4s8s_hw *hw; | |
1475 | ||
41f96935 | 1476 | if (!(hw = kzalloc(sizeof(hfc4s8s_hw), GFP_ATOMIC))) { |
1da177e4 LT |
1477 | printk(KERN_ERR "No kmem for HFC-4S/8S card\n"); |
1478 | return (err); | |
1479 | } | |
1da177e4 LT |
1480 | |
1481 | hw->pdev = pdev; | |
1482 | err = pci_enable_device(pdev); | |
1483 | ||
1484 | if (err) | |
1485 | goto out; | |
1486 | ||
1487 | hw->cardnum = card_cnt; | |
1488 | sprintf(hw->card_name, "hfc4s8s_%d", hw->cardnum); | |
1489 | printk(KERN_INFO "HFC-4S/8S: found adapter %s (%s) at %s\n", | |
1490 | driver_data->device_name, hw->card_name, pci_name(pdev)); | |
1491 | ||
1492 | spin_lock_init(&hw->lock); | |
1493 | ||
1494 | hw->driver_data = *driver_data; | |
1495 | hw->irq = pdev->irq; | |
1496 | hw->iobase = pci_resource_start(pdev, 0); | |
1497 | ||
1da177e4 LT |
1498 | if (!request_region(hw->iobase, 8, hw->card_name)) { |
1499 | printk(KERN_INFO | |
77d84ff8 | 1500 | "HFC-4S/8S: failed to request address space at 0x%04x\n", |
1da177e4 LT |
1501 | hw->iobase); |
1502 | goto out; | |
1503 | } | |
1da177e4 LT |
1504 | |
1505 | pci_set_drvdata(pdev, hw); | |
1506 | err = setup_instance(hw); | |
1507 | if (!err) | |
1508 | card_cnt++; | |
1509 | return (err); | |
1510 | ||
475be4d8 | 1511 | out: |
1da177e4 LT |
1512 | kfree(hw); |
1513 | return (err); | |
1514 | } | |
1515 | ||
1516 | /**************************************/ | |
1517 | /* PCI hotplug interface: remove card */ | |
1518 | /**************************************/ | |
ed5a84cd | 1519 | static void |
1da177e4 LT |
1520 | hfc4s8s_remove(struct pci_dev *pdev) |
1521 | { | |
1522 | hfc4s8s_hw *hw = pci_get_drvdata(pdev); | |
1523 | ||
1524 | printk(KERN_INFO "HFC-4S/8S: removing card %d\n", hw->cardnum); | |
1525 | hfc_hardware_enable(hw, 0, 0); | |
1526 | ||
1527 | if (hw->irq) | |
1528 | free_irq(hw->irq, hw); | |
1529 | hw->irq = 0; | |
1530 | release_pci_ports(hw); | |
1531 | ||
1532 | card_cnt--; | |
1533 | pci_disable_device(pdev); | |
1534 | kfree(hw); | |
1535 | return; | |
1536 | } | |
1537 | ||
1538 | static struct pci_driver hfc4s8s_driver = { | |
475be4d8 JP |
1539 | .name = "hfc4s8s_l1", |
1540 | .probe = hfc4s8s_probe, | |
ed5a84cd | 1541 | .remove = hfc4s8s_remove, |
475be4d8 | 1542 | .id_table = hfc4s8s_ids, |
1da177e4 LT |
1543 | }; |
1544 | ||
1545 | /**********************/ | |
1546 | /* driver Module init */ | |
1547 | /**********************/ | |
1548 | static int __init | |
1549 | hfc4s8s_module_init(void) | |
1550 | { | |
1551 | int err; | |
1552 | ||
1553 | printk(KERN_INFO | |
1554 | "HFC-4S/8S: Layer 1 driver module for HFC-4S/8S isdn chips, %s\n", | |
1555 | hfc4s8s_rev); | |
1556 | printk(KERN_INFO | |
1557 | "HFC-4S/8S: (C) 2003 Cornelius Consult, www.cornelius-consult.de\n"); | |
1558 | ||
1559 | card_cnt = 0; | |
1560 | ||
1561 | err = pci_register_driver(&hfc4s8s_driver); | |
1562 | if (err < 0) { | |
1563 | goto out; | |
1564 | } | |
1565 | printk(KERN_INFO "HFC-4S/8S: found %d cards\n", card_cnt); | |
1566 | ||
1da177e4 | 1567 | return 0; |
475be4d8 | 1568 | out: |
1da177e4 LT |
1569 | return (err); |
1570 | } /* hfc4s8s_init_hw */ | |
1571 | ||
1572 | /*************************************/ | |
1573 | /* driver module exit : */ | |
1574 | /* release the HFC-4s/8s hardware */ | |
1575 | /*************************************/ | |
67eb5db5 | 1576 | static void __exit |
1da177e4 LT |
1577 | hfc4s8s_module_exit(void) |
1578 | { | |
1579 | pci_unregister_driver(&hfc4s8s_driver); | |
1580 | printk(KERN_INFO "HFC-4S/8S: module removed\n"); | |
1581 | } /* hfc4s8s_release_hw */ | |
1582 | ||
1583 | module_init(hfc4s8s_module_init); | |
1584 | module_exit(hfc4s8s_module_exit); |