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cae86d4a KK |
1 | /* |
2 | * isac.c ISAC specific routines | |
3 | * | |
4 | * Author Karsten Keil <keil@isdn4linux.de> | |
5 | * | |
6 | * Copyright 2009 by Karsten Keil <keil@isdn4linux.de> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
20 | * | |
21 | */ | |
22 | ||
a6b7a407 | 23 | #include <linux/irqreturn.h> |
5a0e3ad6 | 24 | #include <linux/slab.h> |
cae86d4a KK |
25 | #include <linux/module.h> |
26 | #include <linux/mISDNhw.h> | |
27 | #include "ipac.h" | |
28 | ||
29 | ||
30 | #define DBUSY_TIMER_VALUE 80 | |
31 | #define ARCOFI_USE 1 | |
32 | ||
33 | #define ISAC_REV "2.0" | |
34 | ||
35 | MODULE_AUTHOR("Karsten Keil"); | |
36 | MODULE_VERSION(ISAC_REV); | |
37 | MODULE_LICENSE("GPL v2"); | |
38 | ||
39 | #define ReadISAC(is, o) (is->read_reg(is->dch.hw, o + is->off)) | |
40 | #define WriteISAC(is, o, v) (is->write_reg(is->dch.hw, o + is->off, v)) | |
41 | #define ReadHSCX(h, o) (h->ip->read_reg(h->ip->hw, h->off + o)) | |
42 | #define WriteHSCX(h, o, v) (h->ip->write_reg(h->ip->hw, h->off + o, v)) | |
43 | #define ReadIPAC(ip, o) (ip->read_reg(ip->hw, o)) | |
44 | #define WriteIPAC(ip, o, v) (ip->write_reg(ip->hw, o, v)) | |
45 | ||
46 | static inline void | |
47 | ph_command(struct isac_hw *isac, u8 command) | |
48 | { | |
49 | pr_debug("%s: ph_command %x\n", isac->name, command); | |
50 | if (isac->type & IPAC_TYPE_ISACX) | |
51 | WriteISAC(isac, ISACX_CIX0, (command << 4) | 0xE); | |
52 | else | |
53 | WriteISAC(isac, ISAC_CIX0, (command << 2) | 3); | |
54 | } | |
55 | ||
56 | static void | |
57 | isac_ph_state_change(struct isac_hw *isac) | |
58 | { | |
59 | switch (isac->state) { | |
60 | case (ISAC_IND_RS): | |
61 | case (ISAC_IND_EI): | |
62 | ph_command(isac, ISAC_CMD_DUI); | |
63 | } | |
64 | schedule_event(&isac->dch, FLG_PHCHANGE); | |
65 | } | |
66 | ||
67 | static void | |
68 | isac_ph_state_bh(struct dchannel *dch) | |
69 | { | |
70 | struct isac_hw *isac = container_of(dch, struct isac_hw, dch); | |
71 | ||
72 | switch (isac->state) { | |
73 | case ISAC_IND_RS: | |
74 | case ISAC_IND_EI: | |
75 | dch->state = 0; | |
76 | l1_event(dch->l1, HW_RESET_IND); | |
77 | break; | |
78 | case ISAC_IND_DID: | |
79 | dch->state = 3; | |
80 | l1_event(dch->l1, HW_DEACT_CNF); | |
81 | break; | |
82 | case ISAC_IND_DR: | |
83 | dch->state = 3; | |
84 | l1_event(dch->l1, HW_DEACT_IND); | |
85 | break; | |
86 | case ISAC_IND_PU: | |
87 | dch->state = 4; | |
88 | l1_event(dch->l1, HW_POWERUP_IND); | |
89 | break; | |
90 | case ISAC_IND_RSY: | |
91 | if (dch->state <= 5) { | |
92 | dch->state = 5; | |
93 | l1_event(dch->l1, ANYSIGNAL); | |
94 | } else { | |
95 | dch->state = 8; | |
96 | l1_event(dch->l1, LOSTFRAMING); | |
97 | } | |
98 | break; | |
99 | case ISAC_IND_ARD: | |
100 | dch->state = 6; | |
101 | l1_event(dch->l1, INFO2); | |
102 | break; | |
103 | case ISAC_IND_AI8: | |
104 | dch->state = 7; | |
105 | l1_event(dch->l1, INFO4_P8); | |
106 | break; | |
107 | case ISAC_IND_AI10: | |
108 | dch->state = 7; | |
109 | l1_event(dch->l1, INFO4_P10); | |
110 | break; | |
111 | } | |
112 | pr_debug("%s: TE newstate %x\n", isac->name, dch->state); | |
113 | } | |
114 | ||
115 | void | |
116 | isac_empty_fifo(struct isac_hw *isac, int count) | |
117 | { | |
118 | u8 *ptr; | |
119 | ||
120 | pr_debug("%s: %s %d\n", isac->name, __func__, count); | |
121 | ||
122 | if (!isac->dch.rx_skb) { | |
123 | isac->dch.rx_skb = mI_alloc_skb(isac->dch.maxlen, GFP_ATOMIC); | |
124 | if (!isac->dch.rx_skb) { | |
125 | pr_info("%s: D receive out of memory\n", isac->name); | |
126 | WriteISAC(isac, ISAC_CMDR, 0x80); | |
127 | return; | |
128 | } | |
129 | } | |
130 | if ((isac->dch.rx_skb->len + count) >= isac->dch.maxlen) { | |
131 | pr_debug("%s: %s overrun %d\n", isac->name, __func__, | |
475be4d8 | 132 | isac->dch.rx_skb->len + count); |
cae86d4a KK |
133 | WriteISAC(isac, ISAC_CMDR, 0x80); |
134 | return; | |
135 | } | |
136 | ptr = skb_put(isac->dch.rx_skb, count); | |
137 | isac->read_fifo(isac->dch.hw, isac->off, ptr, count); | |
138 | WriteISAC(isac, ISAC_CMDR, 0x80); | |
139 | if (isac->dch.debug & DEBUG_HW_DFIFO) { | |
140 | char pfx[MISDN_MAX_IDLEN + 16]; | |
141 | ||
142 | snprintf(pfx, MISDN_MAX_IDLEN + 15, "D-recv %s %d ", | |
475be4d8 | 143 | isac->name, count); |
cae86d4a KK |
144 | print_hex_dump_bytes(pfx, DUMP_PREFIX_OFFSET, ptr, count); |
145 | } | |
146 | } | |
147 | ||
148 | static void | |
149 | isac_fill_fifo(struct isac_hw *isac) | |
150 | { | |
151 | int count, more; | |
152 | u8 *ptr; | |
153 | ||
154 | if (!isac->dch.tx_skb) | |
155 | return; | |
156 | count = isac->dch.tx_skb->len - isac->dch.tx_idx; | |
157 | if (count <= 0) | |
158 | return; | |
159 | ||
160 | more = 0; | |
161 | if (count > 32) { | |
162 | more = !0; | |
163 | count = 32; | |
164 | } | |
165 | pr_debug("%s: %s %d\n", isac->name, __func__, count); | |
166 | ptr = isac->dch.tx_skb->data + isac->dch.tx_idx; | |
167 | isac->dch.tx_idx += count; | |
168 | isac->write_fifo(isac->dch.hw, isac->off, ptr, count); | |
169 | WriteISAC(isac, ISAC_CMDR, more ? 0x8 : 0xa); | |
170 | if (test_and_set_bit(FLG_BUSY_TIMER, &isac->dch.Flags)) { | |
171 | pr_debug("%s: %s dbusytimer running\n", isac->name, __func__); | |
172 | del_timer(&isac->dch.timer); | |
173 | } | |
174 | init_timer(&isac->dch.timer); | |
175 | isac->dch.timer.expires = jiffies + ((DBUSY_TIMER_VALUE * HZ)/1000); | |
176 | add_timer(&isac->dch.timer); | |
177 | if (isac->dch.debug & DEBUG_HW_DFIFO) { | |
178 | char pfx[MISDN_MAX_IDLEN + 16]; | |
179 | ||
180 | snprintf(pfx, MISDN_MAX_IDLEN + 15, "D-send %s %d ", | |
475be4d8 | 181 | isac->name, count); |
cae86d4a KK |
182 | print_hex_dump_bytes(pfx, DUMP_PREFIX_OFFSET, ptr, count); |
183 | } | |
184 | } | |
185 | ||
186 | static void | |
187 | isac_rme_irq(struct isac_hw *isac) | |
188 | { | |
189 | u8 val, count; | |
190 | ||
191 | val = ReadISAC(isac, ISAC_RSTA); | |
192 | if ((val & 0x70) != 0x20) { | |
193 | if (val & 0x40) { | |
194 | pr_debug("%s: ISAC RDO\n", isac->name); | |
195 | #ifdef ERROR_STATISTIC | |
196 | isac->dch.err_rx++; | |
197 | #endif | |
198 | } | |
199 | if (!(val & 0x20)) { | |
200 | pr_debug("%s: ISAC CRC error\n", isac->name); | |
201 | #ifdef ERROR_STATISTIC | |
202 | isac->dch.err_crc++; | |
203 | #endif | |
204 | } | |
205 | WriteISAC(isac, ISAC_CMDR, 0x80); | |
206 | if (isac->dch.rx_skb) | |
207 | dev_kfree_skb(isac->dch.rx_skb); | |
208 | isac->dch.rx_skb = NULL; | |
209 | } else { | |
210 | count = ReadISAC(isac, ISAC_RBCL) & 0x1f; | |
211 | if (count == 0) | |
212 | count = 32; | |
213 | isac_empty_fifo(isac, count); | |
214 | recv_Dchannel(&isac->dch); | |
215 | } | |
216 | } | |
217 | ||
218 | static void | |
219 | isac_xpr_irq(struct isac_hw *isac) | |
220 | { | |
221 | if (test_and_clear_bit(FLG_BUSY_TIMER, &isac->dch.Flags)) | |
222 | del_timer(&isac->dch.timer); | |
223 | if (isac->dch.tx_skb && isac->dch.tx_idx < isac->dch.tx_skb->len) { | |
224 | isac_fill_fifo(isac); | |
225 | } else { | |
226 | if (isac->dch.tx_skb) | |
227 | dev_kfree_skb(isac->dch.tx_skb); | |
228 | if (get_next_dframe(&isac->dch)) | |
229 | isac_fill_fifo(isac); | |
230 | } | |
231 | } | |
232 | ||
233 | static void | |
234 | isac_retransmit(struct isac_hw *isac) | |
235 | { | |
236 | if (test_and_clear_bit(FLG_BUSY_TIMER, &isac->dch.Flags)) | |
237 | del_timer(&isac->dch.timer); | |
238 | if (test_bit(FLG_TX_BUSY, &isac->dch.Flags)) { | |
239 | /* Restart frame */ | |
240 | isac->dch.tx_idx = 0; | |
241 | isac_fill_fifo(isac); | |
242 | } else if (isac->dch.tx_skb) { /* should not happen */ | |
243 | pr_info("%s: tx_skb exist but not busy\n", isac->name); | |
244 | test_and_set_bit(FLG_TX_BUSY, &isac->dch.Flags); | |
245 | isac->dch.tx_idx = 0; | |
246 | isac_fill_fifo(isac); | |
247 | } else { | |
248 | pr_info("%s: ISAC XDU no TX_BUSY\n", isac->name); | |
249 | if (get_next_dframe(&isac->dch)) | |
250 | isac_fill_fifo(isac); | |
251 | } | |
252 | } | |
253 | ||
254 | static void | |
255 | isac_mos_irq(struct isac_hw *isac) | |
256 | { | |
257 | u8 val; | |
258 | int ret; | |
259 | ||
260 | val = ReadISAC(isac, ISAC_MOSR); | |
261 | pr_debug("%s: ISAC MOSR %02x\n", isac->name, val); | |
262 | #if ARCOFI_USE | |
263 | if (val & 0x08) { | |
264 | if (!isac->mon_rx) { | |
265 | isac->mon_rx = kmalloc(MAX_MON_FRAME, GFP_ATOMIC); | |
266 | if (!isac->mon_rx) { | |
267 | pr_info("%s: ISAC MON RX out of memory!\n", | |
268 | isac->name); | |
269 | isac->mocr &= 0xf0; | |
270 | isac->mocr |= 0x0a; | |
271 | WriteISAC(isac, ISAC_MOCR, isac->mocr); | |
272 | goto afterMONR0; | |
273 | } else | |
274 | isac->mon_rxp = 0; | |
275 | } | |
276 | if (isac->mon_rxp >= MAX_MON_FRAME) { | |
277 | isac->mocr &= 0xf0; | |
278 | isac->mocr |= 0x0a; | |
279 | WriteISAC(isac, ISAC_MOCR, isac->mocr); | |
280 | isac->mon_rxp = 0; | |
281 | pr_debug("%s: ISAC MON RX overflow!\n", isac->name); | |
282 | goto afterMONR0; | |
283 | } | |
284 | isac->mon_rx[isac->mon_rxp++] = ReadISAC(isac, ISAC_MOR0); | |
285 | pr_debug("%s: ISAC MOR0 %02x\n", isac->name, | |
475be4d8 | 286 | isac->mon_rx[isac->mon_rxp - 1]); |
cae86d4a KK |
287 | if (isac->mon_rxp == 1) { |
288 | isac->mocr |= 0x04; | |
289 | WriteISAC(isac, ISAC_MOCR, isac->mocr); | |
290 | } | |
291 | } | |
292 | afterMONR0: | |
293 | if (val & 0x80) { | |
294 | if (!isac->mon_rx) { | |
295 | isac->mon_rx = kmalloc(MAX_MON_FRAME, GFP_ATOMIC); | |
296 | if (!isac->mon_rx) { | |
297 | pr_info("%s: ISAC MON RX out of memory!\n", | |
298 | isac->name); | |
299 | isac->mocr &= 0x0f; | |
300 | isac->mocr |= 0xa0; | |
301 | WriteISAC(isac, ISAC_MOCR, isac->mocr); | |
302 | goto afterMONR1; | |
303 | } else | |
304 | isac->mon_rxp = 0; | |
305 | } | |
306 | if (isac->mon_rxp >= MAX_MON_FRAME) { | |
307 | isac->mocr &= 0x0f; | |
308 | isac->mocr |= 0xa0; | |
309 | WriteISAC(isac, ISAC_MOCR, isac->mocr); | |
310 | isac->mon_rxp = 0; | |
311 | pr_debug("%s: ISAC MON RX overflow!\n", isac->name); | |
312 | goto afterMONR1; | |
313 | } | |
314 | isac->mon_rx[isac->mon_rxp++] = ReadISAC(isac, ISAC_MOR1); | |
315 | pr_debug("%s: ISAC MOR1 %02x\n", isac->name, | |
475be4d8 | 316 | isac->mon_rx[isac->mon_rxp - 1]); |
cae86d4a KK |
317 | isac->mocr |= 0x40; |
318 | WriteISAC(isac, ISAC_MOCR, isac->mocr); | |
319 | } | |
320 | afterMONR1: | |
321 | if (val & 0x04) { | |
322 | isac->mocr &= 0xf0; | |
323 | WriteISAC(isac, ISAC_MOCR, isac->mocr); | |
324 | isac->mocr |= 0x0a; | |
325 | WriteISAC(isac, ISAC_MOCR, isac->mocr); | |
326 | if (isac->monitor) { | |
327 | ret = isac->monitor(isac->dch.hw, MONITOR_RX_0, | |
475be4d8 | 328 | isac->mon_rx, isac->mon_rxp); |
cae86d4a KK |
329 | if (ret) |
330 | kfree(isac->mon_rx); | |
331 | } else { | |
332 | pr_info("%s: MONITOR 0 received %d but no user\n", | |
333 | isac->name, isac->mon_rxp); | |
334 | kfree(isac->mon_rx); | |
335 | } | |
336 | isac->mon_rx = NULL; | |
337 | isac->mon_rxp = 0; | |
338 | } | |
339 | if (val & 0x40) { | |
340 | isac->mocr &= 0x0f; | |
341 | WriteISAC(isac, ISAC_MOCR, isac->mocr); | |
342 | isac->mocr |= 0xa0; | |
343 | WriteISAC(isac, ISAC_MOCR, isac->mocr); | |
344 | if (isac->monitor) { | |
345 | ret = isac->monitor(isac->dch.hw, MONITOR_RX_1, | |
475be4d8 | 346 | isac->mon_rx, isac->mon_rxp); |
cae86d4a KK |
347 | if (ret) |
348 | kfree(isac->mon_rx); | |
349 | } else { | |
350 | pr_info("%s: MONITOR 1 received %d but no user\n", | |
351 | isac->name, isac->mon_rxp); | |
352 | kfree(isac->mon_rx); | |
353 | } | |
354 | isac->mon_rx = NULL; | |
355 | isac->mon_rxp = 0; | |
356 | } | |
357 | if (val & 0x02) { | |
358 | if ((!isac->mon_tx) || (isac->mon_txc && | |
475be4d8 | 359 | (isac->mon_txp >= isac->mon_txc) && !(val & 0x08))) { |
cae86d4a KK |
360 | isac->mocr &= 0xf0; |
361 | WriteISAC(isac, ISAC_MOCR, isac->mocr); | |
362 | isac->mocr |= 0x0a; | |
363 | WriteISAC(isac, ISAC_MOCR, isac->mocr); | |
364 | if (isac->mon_txc && (isac->mon_txp >= isac->mon_txc)) { | |
365 | if (isac->monitor) | |
366 | ret = isac->monitor(isac->dch.hw, | |
475be4d8 | 367 | MONITOR_TX_0, NULL, 0); |
cae86d4a KK |
368 | } |
369 | kfree(isac->mon_tx); | |
370 | isac->mon_tx = NULL; | |
371 | isac->mon_txc = 0; | |
372 | isac->mon_txp = 0; | |
373 | goto AfterMOX0; | |
374 | } | |
375 | if (isac->mon_txc && (isac->mon_txp >= isac->mon_txc)) { | |
376 | if (isac->monitor) | |
377 | ret = isac->monitor(isac->dch.hw, | |
475be4d8 | 378 | MONITOR_TX_0, NULL, 0); |
cae86d4a KK |
379 | kfree(isac->mon_tx); |
380 | isac->mon_tx = NULL; | |
381 | isac->mon_txc = 0; | |
382 | isac->mon_txp = 0; | |
383 | goto AfterMOX0; | |
384 | } | |
385 | WriteISAC(isac, ISAC_MOX0, isac->mon_tx[isac->mon_txp++]); | |
386 | pr_debug("%s: ISAC %02x -> MOX0\n", isac->name, | |
475be4d8 | 387 | isac->mon_tx[isac->mon_txp - 1]); |
cae86d4a KK |
388 | } |
389 | AfterMOX0: | |
390 | if (val & 0x20) { | |
391 | if ((!isac->mon_tx) || (isac->mon_txc && | |
475be4d8 | 392 | (isac->mon_txp >= isac->mon_txc) && !(val & 0x80))) { |
cae86d4a KK |
393 | isac->mocr &= 0x0f; |
394 | WriteISAC(isac, ISAC_MOCR, isac->mocr); | |
395 | isac->mocr |= 0xa0; | |
396 | WriteISAC(isac, ISAC_MOCR, isac->mocr); | |
397 | if (isac->mon_txc && (isac->mon_txp >= isac->mon_txc)) { | |
398 | if (isac->monitor) | |
399 | ret = isac->monitor(isac->dch.hw, | |
475be4d8 | 400 | MONITOR_TX_1, NULL, 0); |
cae86d4a KK |
401 | } |
402 | kfree(isac->mon_tx); | |
403 | isac->mon_tx = NULL; | |
404 | isac->mon_txc = 0; | |
405 | isac->mon_txp = 0; | |
406 | goto AfterMOX1; | |
407 | } | |
408 | if (isac->mon_txc && (isac->mon_txp >= isac->mon_txc)) { | |
409 | if (isac->monitor) | |
410 | ret = isac->monitor(isac->dch.hw, | |
475be4d8 | 411 | MONITOR_TX_1, NULL, 0); |
cae86d4a KK |
412 | kfree(isac->mon_tx); |
413 | isac->mon_tx = NULL; | |
414 | isac->mon_txc = 0; | |
415 | isac->mon_txp = 0; | |
416 | goto AfterMOX1; | |
417 | } | |
418 | WriteISAC(isac, ISAC_MOX1, isac->mon_tx[isac->mon_txp++]); | |
419 | pr_debug("%s: ISAC %02x -> MOX1\n", isac->name, | |
475be4d8 | 420 | isac->mon_tx[isac->mon_txp - 1]); |
cae86d4a KK |
421 | } |
422 | AfterMOX1: | |
423 | val = 0; /* dummy to avoid warning */ | |
424 | #endif | |
425 | } | |
426 | ||
427 | static void | |
428 | isac_cisq_irq(struct isac_hw *isac) { | |
429 | u8 val; | |
430 | ||
431 | val = ReadISAC(isac, ISAC_CIR0); | |
432 | pr_debug("%s: ISAC CIR0 %02X\n", isac->name, val); | |
433 | if (val & 2) { | |
434 | pr_debug("%s: ph_state change %x->%x\n", isac->name, | |
475be4d8 | 435 | isac->state, (val >> 2) & 0xf); |
cae86d4a KK |
436 | isac->state = (val >> 2) & 0xf; |
437 | isac_ph_state_change(isac); | |
438 | } | |
439 | if (val & 1) { | |
440 | val = ReadISAC(isac, ISAC_CIR1); | |
441 | pr_debug("%s: ISAC CIR1 %02X\n", isac->name, val); | |
442 | } | |
443 | } | |
444 | ||
445 | static void | |
446 | isacsx_cic_irq(struct isac_hw *isac) | |
447 | { | |
448 | u8 val; | |
449 | ||
450 | val = ReadISAC(isac, ISACX_CIR0); | |
451 | pr_debug("%s: ISACX CIR0 %02X\n", isac->name, val); | |
452 | if (val & ISACX_CIR0_CIC0) { | |
453 | pr_debug("%s: ph_state change %x->%x\n", isac->name, | |
475be4d8 | 454 | isac->state, val >> 4); |
cae86d4a KK |
455 | isac->state = val >> 4; |
456 | isac_ph_state_change(isac); | |
457 | } | |
458 | } | |
459 | ||
460 | static void | |
461 | isacsx_rme_irq(struct isac_hw *isac) | |
462 | { | |
463 | int count; | |
464 | u8 val; | |
465 | ||
466 | val = ReadISAC(isac, ISACX_RSTAD); | |
467 | if ((val & (ISACX_RSTAD_VFR | | |
468 | ISACX_RSTAD_RDO | | |
469 | ISACX_RSTAD_CRC | | |
470 | ISACX_RSTAD_RAB)) | |
471 | != (ISACX_RSTAD_VFR | ISACX_RSTAD_CRC)) { | |
472 | pr_debug("%s: RSTAD %#x, dropped\n", isac->name, val); | |
473 | #ifdef ERROR_STATISTIC | |
474 | if (val & ISACX_RSTAD_CRC) | |
475 | isac->dch.err_rx++; | |
476 | else | |
477 | isac->dch.err_crc++; | |
478 | #endif | |
479 | WriteISAC(isac, ISACX_CMDRD, ISACX_CMDRD_RMC); | |
480 | if (isac->dch.rx_skb) | |
481 | dev_kfree_skb(isac->dch.rx_skb); | |
482 | isac->dch.rx_skb = NULL; | |
483 | } else { | |
484 | count = ReadISAC(isac, ISACX_RBCLD) & 0x1f; | |
485 | if (count == 0) | |
486 | count = 32; | |
487 | isac_empty_fifo(isac, count); | |
488 | if (isac->dch.rx_skb) { | |
489 | skb_trim(isac->dch.rx_skb, isac->dch.rx_skb->len - 1); | |
490 | pr_debug("%s: dchannel received %d\n", isac->name, | |
475be4d8 | 491 | isac->dch.rx_skb->len); |
cae86d4a KK |
492 | recv_Dchannel(&isac->dch); |
493 | } | |
494 | } | |
495 | } | |
496 | ||
497 | irqreturn_t | |
498 | mISDNisac_irq(struct isac_hw *isac, u8 val) | |
499 | { | |
500 | if (unlikely(!val)) | |
501 | return IRQ_NONE; | |
502 | pr_debug("%s: ISAC interrupt %02x\n", isac->name, val); | |
503 | if (isac->type & IPAC_TYPE_ISACX) { | |
504 | if (val & ISACX__CIC) | |
505 | isacsx_cic_irq(isac); | |
506 | if (val & ISACX__ICD) { | |
507 | val = ReadISAC(isac, ISACX_ISTAD); | |
508 | pr_debug("%s: ISTAD %02x\n", isac->name, val); | |
509 | if (val & ISACX_D_XDU) { | |
510 | pr_debug("%s: ISAC XDU\n", isac->name); | |
511 | #ifdef ERROR_STATISTIC | |
512 | isac->dch.err_tx++; | |
513 | #endif | |
514 | isac_retransmit(isac); | |
515 | } | |
516 | if (val & ISACX_D_XMR) { | |
517 | pr_debug("%s: ISAC XMR\n", isac->name); | |
518 | #ifdef ERROR_STATISTIC | |
519 | isac->dch.err_tx++; | |
520 | #endif | |
521 | isac_retransmit(isac); | |
522 | } | |
523 | if (val & ISACX_D_XPR) | |
524 | isac_xpr_irq(isac); | |
525 | if (val & ISACX_D_RFO) { | |
526 | pr_debug("%s: ISAC RFO\n", isac->name); | |
527 | WriteISAC(isac, ISACX_CMDRD, ISACX_CMDRD_RMC); | |
528 | } | |
529 | if (val & ISACX_D_RME) | |
530 | isacsx_rme_irq(isac); | |
531 | if (val & ISACX_D_RPF) | |
532 | isac_empty_fifo(isac, 0x20); | |
533 | } | |
534 | } else { | |
535 | if (val & 0x80) /* RME */ | |
536 | isac_rme_irq(isac); | |
537 | if (val & 0x40) /* RPF */ | |
538 | isac_empty_fifo(isac, 32); | |
539 | if (val & 0x10) /* XPR */ | |
540 | isac_xpr_irq(isac); | |
541 | if (val & 0x04) /* CISQ */ | |
542 | isac_cisq_irq(isac); | |
543 | if (val & 0x20) /* RSC - never */ | |
544 | pr_debug("%s: ISAC RSC interrupt\n", isac->name); | |
545 | if (val & 0x02) /* SIN - never */ | |
546 | pr_debug("%s: ISAC SIN interrupt\n", isac->name); | |
547 | if (val & 0x01) { /* EXI */ | |
548 | val = ReadISAC(isac, ISAC_EXIR); | |
549 | pr_debug("%s: ISAC EXIR %02x\n", isac->name, val); | |
550 | if (val & 0x80) /* XMR */ | |
551 | pr_debug("%s: ISAC XMR\n", isac->name); | |
552 | if (val & 0x40) { /* XDU */ | |
553 | pr_debug("%s: ISAC XDU\n", isac->name); | |
554 | #ifdef ERROR_STATISTIC | |
555 | isac->dch.err_tx++; | |
556 | #endif | |
557 | isac_retransmit(isac); | |
558 | } | |
559 | if (val & 0x04) /* MOS */ | |
560 | isac_mos_irq(isac); | |
561 | } | |
562 | } | |
563 | return IRQ_HANDLED; | |
564 | } | |
565 | EXPORT_SYMBOL(mISDNisac_irq); | |
566 | ||
567 | static int | |
568 | isac_l1hw(struct mISDNchannel *ch, struct sk_buff *skb) | |
569 | { | |
570 | struct mISDNdevice *dev = container_of(ch, struct mISDNdevice, D); | |
571 | struct dchannel *dch = container_of(dev, struct dchannel, dev); | |
572 | struct isac_hw *isac = container_of(dch, struct isac_hw, dch); | |
573 | int ret = -EINVAL; | |
574 | struct mISDNhead *hh = mISDN_HEAD_P(skb); | |
575 | u32 id; | |
576 | u_long flags; | |
577 | ||
578 | switch (hh->prim) { | |
579 | case PH_DATA_REQ: | |
580 | spin_lock_irqsave(isac->hwlock, flags); | |
581 | ret = dchannel_senddata(dch, skb); | |
582 | if (ret > 0) { /* direct TX */ | |
583 | id = hh->id; /* skb can be freed */ | |
584 | isac_fill_fifo(isac); | |
585 | ret = 0; | |
586 | spin_unlock_irqrestore(isac->hwlock, flags); | |
587 | queue_ch_frame(ch, PH_DATA_CNF, id, NULL); | |
588 | } else | |
589 | spin_unlock_irqrestore(isac->hwlock, flags); | |
590 | return ret; | |
591 | case PH_ACTIVATE_REQ: | |
592 | ret = l1_event(dch->l1, hh->prim); | |
593 | break; | |
594 | case PH_DEACTIVATE_REQ: | |
595 | test_and_clear_bit(FLG_L2_ACTIVATED, &dch->Flags); | |
596 | ret = l1_event(dch->l1, hh->prim); | |
597 | break; | |
598 | } | |
599 | ||
600 | if (!ret) | |
601 | dev_kfree_skb(skb); | |
602 | return ret; | |
603 | } | |
604 | ||
605 | static int | |
c626c127 | 606 | isac_ctrl(struct isac_hw *isac, u32 cmd, unsigned long para) |
cae86d4a KK |
607 | { |
608 | u8 tl = 0; | |
c626c127 KK |
609 | unsigned long flags; |
610 | int ret = 0; | |
cae86d4a KK |
611 | |
612 | switch (cmd) { | |
613 | case HW_TESTLOOP: | |
614 | spin_lock_irqsave(isac->hwlock, flags); | |
615 | if (!(isac->type & IPAC_TYPE_ISACX)) { | |
616 | /* TODO: implement for IPAC_TYPE_ISACX */ | |
617 | if (para & 1) /* B1 */ | |
618 | tl |= 0x0c; | |
619 | else if (para & 2) /* B2 */ | |
620 | tl |= 0x3; | |
621 | /* we only support IOM2 mode */ | |
622 | WriteISAC(isac, ISAC_SPCR, tl); | |
623 | if (tl) | |
624 | WriteISAC(isac, ISAC_ADF1, 0x8); | |
625 | else | |
626 | WriteISAC(isac, ISAC_ADF1, 0x0); | |
627 | } | |
628 | spin_unlock_irqrestore(isac->hwlock, flags); | |
629 | break; | |
c626c127 KK |
630 | case HW_TIMER3_VALUE: |
631 | ret = l1_event(isac->dch.l1, HW_TIMER3_VALUE | (para & 0xff)); | |
632 | break; | |
cae86d4a KK |
633 | default: |
634 | pr_debug("%s: %s unknown command %x %lx\n", isac->name, | |
475be4d8 | 635 | __func__, cmd, para); |
c626c127 | 636 | ret = -1; |
cae86d4a | 637 | } |
c626c127 | 638 | return ret; |
cae86d4a KK |
639 | } |
640 | ||
641 | static int | |
642 | isac_l1cmd(struct dchannel *dch, u32 cmd) | |
643 | { | |
644 | struct isac_hw *isac = container_of(dch, struct isac_hw, dch); | |
645 | u_long flags; | |
646 | ||
647 | pr_debug("%s: cmd(%x) state(%02x)\n", isac->name, cmd, isac->state); | |
648 | switch (cmd) { | |
649 | case INFO3_P8: | |
650 | spin_lock_irqsave(isac->hwlock, flags); | |
651 | ph_command(isac, ISAC_CMD_AR8); | |
652 | spin_unlock_irqrestore(isac->hwlock, flags); | |
653 | break; | |
654 | case INFO3_P10: | |
655 | spin_lock_irqsave(isac->hwlock, flags); | |
656 | ph_command(isac, ISAC_CMD_AR10); | |
657 | spin_unlock_irqrestore(isac->hwlock, flags); | |
658 | break; | |
659 | case HW_RESET_REQ: | |
660 | spin_lock_irqsave(isac->hwlock, flags); | |
661 | if ((isac->state == ISAC_IND_EI) || | |
662 | (isac->state == ISAC_IND_DR) || | |
663 | (isac->state == ISAC_IND_RS)) | |
664 | ph_command(isac, ISAC_CMD_TIM); | |
665 | else | |
666 | ph_command(isac, ISAC_CMD_RS); | |
667 | spin_unlock_irqrestore(isac->hwlock, flags); | |
668 | break; | |
669 | case HW_DEACT_REQ: | |
670 | skb_queue_purge(&dch->squeue); | |
671 | if (dch->tx_skb) { | |
672 | dev_kfree_skb(dch->tx_skb); | |
673 | dch->tx_skb = NULL; | |
674 | } | |
675 | dch->tx_idx = 0; | |
676 | if (dch->rx_skb) { | |
677 | dev_kfree_skb(dch->rx_skb); | |
678 | dch->rx_skb = NULL; | |
679 | } | |
680 | test_and_clear_bit(FLG_TX_BUSY, &dch->Flags); | |
681 | if (test_and_clear_bit(FLG_BUSY_TIMER, &dch->Flags)) | |
682 | del_timer(&dch->timer); | |
683 | break; | |
684 | case HW_POWERUP_REQ: | |
685 | spin_lock_irqsave(isac->hwlock, flags); | |
686 | ph_command(isac, ISAC_CMD_TIM); | |
687 | spin_unlock_irqrestore(isac->hwlock, flags); | |
688 | break; | |
689 | case PH_ACTIVATE_IND: | |
690 | test_and_set_bit(FLG_ACTIVE, &dch->Flags); | |
691 | _queue_data(&dch->dev.D, cmd, MISDN_ID_ANY, 0, NULL, | |
475be4d8 | 692 | GFP_ATOMIC); |
cae86d4a KK |
693 | break; |
694 | case PH_DEACTIVATE_IND: | |
695 | test_and_clear_bit(FLG_ACTIVE, &dch->Flags); | |
696 | _queue_data(&dch->dev.D, cmd, MISDN_ID_ANY, 0, NULL, | |
475be4d8 | 697 | GFP_ATOMIC); |
cae86d4a KK |
698 | break; |
699 | default: | |
700 | pr_debug("%s: %s unknown command %x\n", isac->name, | |
475be4d8 | 701 | __func__, cmd); |
cae86d4a KK |
702 | return -1; |
703 | } | |
704 | return 0; | |
705 | } | |
706 | ||
707 | static void | |
708 | isac_release(struct isac_hw *isac) | |
709 | { | |
710 | if (isac->type & IPAC_TYPE_ISACX) | |
711 | WriteISAC(isac, ISACX_MASK, 0xff); | |
712 | else | |
713 | WriteISAC(isac, ISAC_MASK, 0xff); | |
714 | if (isac->dch.timer.function != NULL) { | |
715 | del_timer(&isac->dch.timer); | |
716 | isac->dch.timer.function = NULL; | |
717 | } | |
718 | kfree(isac->mon_rx); | |
719 | isac->mon_rx = NULL; | |
720 | kfree(isac->mon_tx); | |
721 | isac->mon_tx = NULL; | |
722 | if (isac->dch.l1) | |
723 | l1_event(isac->dch.l1, CLOSE_CHANNEL); | |
724 | mISDN_freedchannel(&isac->dch); | |
725 | } | |
726 | ||
727 | static void | |
728 | dbusy_timer_handler(struct isac_hw *isac) | |
729 | { | |
730 | int rbch, star; | |
731 | u_long flags; | |
732 | ||
733 | if (test_bit(FLG_BUSY_TIMER, &isac->dch.Flags)) { | |
734 | spin_lock_irqsave(isac->hwlock, flags); | |
735 | rbch = ReadISAC(isac, ISAC_RBCH); | |
736 | star = ReadISAC(isac, ISAC_STAR); | |
737 | pr_debug("%s: D-Channel Busy RBCH %02x STAR %02x\n", | |
475be4d8 | 738 | isac->name, rbch, star); |
cae86d4a KK |
739 | if (rbch & ISAC_RBCH_XAC) /* D-Channel Busy */ |
740 | test_and_set_bit(FLG_L1_BUSY, &isac->dch.Flags); | |
741 | else { | |
742 | /* discard frame; reset transceiver */ | |
743 | test_and_clear_bit(FLG_BUSY_TIMER, &isac->dch.Flags); | |
744 | if (isac->dch.tx_idx) | |
745 | isac->dch.tx_idx = 0; | |
746 | else | |
747 | pr_info("%s: ISAC D-Channel Busy no tx_idx\n", | |
748 | isac->name); | |
749 | /* Transmitter reset */ | |
750 | WriteISAC(isac, ISAC_CMDR, 0x01); | |
751 | } | |
752 | spin_unlock_irqrestore(isac->hwlock, flags); | |
753 | } | |
754 | } | |
755 | ||
756 | static int | |
757 | open_dchannel(struct isac_hw *isac, struct channel_req *rq) | |
758 | { | |
759 | pr_debug("%s: %s dev(%d) open from %p\n", isac->name, __func__, | |
475be4d8 | 760 | isac->dch.dev.id, __builtin_return_address(1)); |
cae86d4a KK |
761 | if (rq->protocol != ISDN_P_TE_S0) |
762 | return -EINVAL; | |
763 | if (rq->adr.channel == 1) | |
764 | /* E-Channel not supported */ | |
765 | return -EINVAL; | |
766 | rq->ch = &isac->dch.dev.D; | |
767 | rq->ch->protocol = rq->protocol; | |
768 | if (isac->dch.state == 7) | |
769 | _queue_data(rq->ch, PH_ACTIVATE_IND, MISDN_ID_ANY, | |
475be4d8 | 770 | 0, NULL, GFP_KERNEL); |
cae86d4a KK |
771 | return 0; |
772 | } | |
773 | ||
774 | static const char *ISACVer[] = | |
775 | {"2086/2186 V1.1", "2085 B1", "2085 B2", | |
776 | "2085 V2.3"}; | |
777 | ||
778 | static int | |
779 | isac_init(struct isac_hw *isac) | |
780 | { | |
781 | u8 val; | |
782 | int err = 0; | |
783 | ||
784 | if (!isac->dch.l1) { | |
785 | err = create_l1(&isac->dch, isac_l1cmd); | |
786 | if (err) | |
787 | return err; | |
788 | } | |
789 | isac->mon_tx = NULL; | |
790 | isac->mon_rx = NULL; | |
791 | isac->dch.timer.function = (void *) dbusy_timer_handler; | |
792 | isac->dch.timer.data = (long)isac; | |
793 | init_timer(&isac->dch.timer); | |
794 | isac->mocr = 0xaa; | |
795 | if (isac->type & IPAC_TYPE_ISACX) { | |
796 | /* Disable all IRQ */ | |
797 | WriteISAC(isac, ISACX_MASK, 0xff); | |
798 | val = ReadISAC(isac, ISACX_STARD); | |
799 | pr_debug("%s: ISACX STARD %x\n", isac->name, val); | |
800 | val = ReadISAC(isac, ISACX_ISTAD); | |
801 | pr_debug("%s: ISACX ISTAD %x\n", isac->name, val); | |
802 | val = ReadISAC(isac, ISACX_ISTA); | |
803 | pr_debug("%s: ISACX ISTA %x\n", isac->name, val); | |
804 | /* clear LDD */ | |
805 | WriteISAC(isac, ISACX_TR_CONF0, 0x00); | |
806 | /* enable transmitter */ | |
807 | WriteISAC(isac, ISACX_TR_CONF2, 0x00); | |
808 | /* transparent mode 0, RAC, stop/go */ | |
809 | WriteISAC(isac, ISACX_MODED, 0xc9); | |
810 | /* all HDLC IRQ unmasked */ | |
811 | val = ReadISAC(isac, ISACX_ID); | |
812 | if (isac->dch.debug & DEBUG_HW) | |
813 | pr_notice("%s: ISACX Design ID %x\n", | |
475be4d8 | 814 | isac->name, val & 0x3f); |
cae86d4a KK |
815 | val = ReadISAC(isac, ISACX_CIR0); |
816 | pr_debug("%s: ISACX CIR0 %02X\n", isac->name, val); | |
817 | isac->state = val >> 4; | |
818 | isac_ph_state_change(isac); | |
819 | ph_command(isac, ISAC_CMD_RS); | |
820 | WriteISAC(isac, ISACX_MASK, IPACX__ON); | |
821 | WriteISAC(isac, ISACX_MASKD, 0x00); | |
822 | } else { /* old isac */ | |
823 | WriteISAC(isac, ISAC_MASK, 0xff); | |
824 | val = ReadISAC(isac, ISAC_STAR); | |
825 | pr_debug("%s: ISAC STAR %x\n", isac->name, val); | |
826 | val = ReadISAC(isac, ISAC_MODE); | |
827 | pr_debug("%s: ISAC MODE %x\n", isac->name, val); | |
828 | val = ReadISAC(isac, ISAC_ADF2); | |
829 | pr_debug("%s: ISAC ADF2 %x\n", isac->name, val); | |
830 | val = ReadISAC(isac, ISAC_ISTA); | |
831 | pr_debug("%s: ISAC ISTA %x\n", isac->name, val); | |
832 | if (val & 0x01) { | |
833 | val = ReadISAC(isac, ISAC_EXIR); | |
834 | pr_debug("%s: ISAC EXIR %x\n", isac->name, val); | |
835 | } | |
836 | val = ReadISAC(isac, ISAC_RBCH); | |
837 | if (isac->dch.debug & DEBUG_HW) | |
838 | pr_notice("%s: ISAC version (%x): %s\n", isac->name, | |
475be4d8 | 839 | val, ISACVer[(val >> 5) & 3]); |
cae86d4a KK |
840 | isac->type |= ((val >> 5) & 3); |
841 | if (!isac->adf2) | |
842 | isac->adf2 = 0x80; | |
843 | if (!(isac->adf2 & 0x80)) { /* only IOM 2 Mode */ | |
844 | pr_info("%s: only support IOM2 mode but adf2=%02x\n", | |
845 | isac->name, isac->adf2); | |
846 | isac_release(isac); | |
847 | return -EINVAL; | |
848 | } | |
849 | WriteISAC(isac, ISAC_ADF2, isac->adf2); | |
850 | WriteISAC(isac, ISAC_SQXR, 0x2f); | |
851 | WriteISAC(isac, ISAC_SPCR, 0x00); | |
852 | WriteISAC(isac, ISAC_STCR, 0x70); | |
853 | WriteISAC(isac, ISAC_MODE, 0xc9); | |
854 | WriteISAC(isac, ISAC_TIMR, 0x00); | |
855 | WriteISAC(isac, ISAC_ADF1, 0x00); | |
856 | val = ReadISAC(isac, ISAC_CIR0); | |
857 | pr_debug("%s: ISAC CIR0 %x\n", isac->name, val); | |
858 | isac->state = (val >> 2) & 0xf; | |
859 | isac_ph_state_change(isac); | |
860 | ph_command(isac, ISAC_CMD_RS); | |
861 | WriteISAC(isac, ISAC_MASK, 0); | |
862 | } | |
863 | return err; | |
864 | } | |
865 | ||
866 | int | |
867 | mISDNisac_init(struct isac_hw *isac, void *hw) | |
868 | { | |
869 | mISDN_initdchannel(&isac->dch, MAX_DFRAME_LEN_L1, isac_ph_state_bh); | |
870 | isac->dch.hw = hw; | |
871 | isac->dch.dev.D.send = isac_l1hw; | |
872 | isac->init = isac_init; | |
873 | isac->release = isac_release; | |
874 | isac->ctrl = isac_ctrl; | |
875 | isac->open = open_dchannel; | |
876 | isac->dch.dev.Dprotocols = (1 << ISDN_P_TE_S0); | |
877 | isac->dch.dev.nrbchan = 2; | |
878 | return 0; | |
879 | } | |
880 | EXPORT_SYMBOL(mISDNisac_init); | |
881 | ||
882 | static void | |
883 | waitforCEC(struct hscx_hw *hx) | |
884 | { | |
885 | u8 starb, to = 50; | |
886 | ||
887 | while (to) { | |
888 | starb = ReadHSCX(hx, IPAC_STARB); | |
889 | if (!(starb & 0x04)) | |
890 | break; | |
891 | udelay(1); | |
892 | to--; | |
893 | } | |
894 | if (to < 50) | |
895 | pr_debug("%s: B%1d CEC %d us\n", hx->ip->name, hx->bch.nr, | |
475be4d8 | 896 | 50 - to); |
cae86d4a KK |
897 | if (!to) |
898 | pr_info("%s: B%1d CEC timeout\n", hx->ip->name, hx->bch.nr); | |
899 | } | |
900 | ||
901 | ||
902 | static void | |
903 | waitforXFW(struct hscx_hw *hx) | |
904 | { | |
905 | u8 starb, to = 50; | |
906 | ||
907 | while (to) { | |
908 | starb = ReadHSCX(hx, IPAC_STARB); | |
909 | if ((starb & 0x44) == 0x40) | |
910 | break; | |
911 | udelay(1); | |
912 | to--; | |
913 | } | |
914 | if (to < 50) | |
915 | pr_debug("%s: B%1d XFW %d us\n", hx->ip->name, hx->bch.nr, | |
475be4d8 | 916 | 50 - to); |
cae86d4a KK |
917 | if (!to) |
918 | pr_info("%s: B%1d XFW timeout\n", hx->ip->name, hx->bch.nr); | |
919 | } | |
920 | ||
921 | static void | |
922 | hscx_cmdr(struct hscx_hw *hx, u8 cmd) | |
923 | { | |
924 | if (hx->ip->type & IPAC_TYPE_IPACX) | |
925 | WriteHSCX(hx, IPACX_CMDRB, cmd); | |
926 | else { | |
927 | waitforCEC(hx); | |
928 | WriteHSCX(hx, IPAC_CMDRB, cmd); | |
929 | } | |
930 | } | |
931 | ||
932 | static void | |
933 | hscx_empty_fifo(struct hscx_hw *hscx, u8 count) | |
934 | { | |
935 | u8 *p; | |
936 | ||
937 | pr_debug("%s: B%1d %d\n", hscx->ip->name, hscx->bch.nr, count); | |
938 | if (!hscx->bch.rx_skb) { | |
939 | hscx->bch.rx_skb = mI_alloc_skb(hscx->bch.maxlen, GFP_ATOMIC); | |
940 | if (!hscx->bch.rx_skb) { | |
941 | pr_info("%s: B receive out of memory\n", | |
942 | hscx->ip->name); | |
943 | hscx_cmdr(hscx, 0x80); /* RMC */ | |
944 | return; | |
945 | } | |
946 | } | |
947 | if ((hscx->bch.rx_skb->len + count) > hscx->bch.maxlen) { | |
948 | pr_debug("%s: overrun %d\n", hscx->ip->name, | |
475be4d8 | 949 | hscx->bch.rx_skb->len + count); |
cae86d4a KK |
950 | skb_trim(hscx->bch.rx_skb, 0); |
951 | hscx_cmdr(hscx, 0x80); /* RMC */ | |
952 | return; | |
953 | } | |
954 | p = skb_put(hscx->bch.rx_skb, count); | |
955 | ||
956 | if (hscx->ip->type & IPAC_TYPE_IPACX) | |
957 | hscx->ip->read_fifo(hscx->ip->hw, | |
475be4d8 | 958 | hscx->off + IPACX_RFIFOB, p, count); |
cae86d4a KK |
959 | else |
960 | hscx->ip->read_fifo(hscx->ip->hw, | |
475be4d8 | 961 | hscx->off, p, count); |
cae86d4a KK |
962 | |
963 | hscx_cmdr(hscx, 0x80); /* RMC */ | |
964 | ||
965 | if (hscx->bch.debug & DEBUG_HW_BFIFO) { | |
966 | snprintf(hscx->log, 64, "B%1d-recv %s %d ", | |
475be4d8 | 967 | hscx->bch.nr, hscx->ip->name, count); |
cae86d4a KK |
968 | print_hex_dump_bytes(hscx->log, DUMP_PREFIX_OFFSET, p, count); |
969 | } | |
970 | } | |
971 | ||
972 | static void | |
973 | hscx_fill_fifo(struct hscx_hw *hscx) | |
974 | { | |
975 | int count, more; | |
976 | u8 *p; | |
977 | ||
978 | if (!hscx->bch.tx_skb) | |
979 | return; | |
980 | count = hscx->bch.tx_skb->len - hscx->bch.tx_idx; | |
981 | if (count <= 0) | |
982 | return; | |
983 | p = hscx->bch.tx_skb->data + hscx->bch.tx_idx; | |
984 | ||
985 | more = test_bit(FLG_TRANSPARENT, &hscx->bch.Flags) ? 1 : 0; | |
986 | if (count > hscx->fifo_size) { | |
987 | count = hscx->fifo_size; | |
988 | more = 1; | |
989 | } | |
990 | pr_debug("%s: B%1d %d/%d/%d\n", hscx->ip->name, hscx->bch.nr, count, | |
475be4d8 | 991 | hscx->bch.tx_idx, hscx->bch.tx_skb->len); |
cae86d4a KK |
992 | hscx->bch.tx_idx += count; |
993 | ||
994 | if (hscx->ip->type & IPAC_TYPE_IPACX) | |
995 | hscx->ip->write_fifo(hscx->ip->hw, | |
475be4d8 | 996 | hscx->off + IPACX_XFIFOB, p, count); |
cae86d4a KK |
997 | else { |
998 | waitforXFW(hscx); | |
999 | hscx->ip->write_fifo(hscx->ip->hw, | |
475be4d8 | 1000 | hscx->off, p, count); |
cae86d4a KK |
1001 | } |
1002 | hscx_cmdr(hscx, more ? 0x08 : 0x0a); | |
1003 | ||
1004 | if (hscx->bch.debug & DEBUG_HW_BFIFO) { | |
1005 | snprintf(hscx->log, 64, "B%1d-send %s %d ", | |
475be4d8 | 1006 | hscx->bch.nr, hscx->ip->name, count); |
cae86d4a KK |
1007 | print_hex_dump_bytes(hscx->log, DUMP_PREFIX_OFFSET, p, count); |
1008 | } | |
1009 | } | |
1010 | ||
1011 | static void | |
1012 | hscx_xpr(struct hscx_hw *hx) | |
1013 | { | |
1014 | if (hx->bch.tx_skb && hx->bch.tx_idx < hx->bch.tx_skb->len) | |
1015 | hscx_fill_fifo(hx); | |
1016 | else { | |
1017 | if (hx->bch.tx_skb) { | |
1018 | /* send confirm, on trans, free on hdlc. */ | |
1019 | if (test_bit(FLG_TRANSPARENT, &hx->bch.Flags)) | |
1020 | confirm_Bsend(&hx->bch); | |
1021 | dev_kfree_skb(hx->bch.tx_skb); | |
1022 | } | |
1023 | if (get_next_bframe(&hx->bch)) | |
1024 | hscx_fill_fifo(hx); | |
1025 | } | |
1026 | } | |
1027 | ||
1028 | static void | |
1029 | ipac_rme(struct hscx_hw *hx) | |
1030 | { | |
1031 | int count; | |
1032 | u8 rstab; | |
1033 | ||
1034 | if (hx->ip->type & IPAC_TYPE_IPACX) | |
1035 | rstab = ReadHSCX(hx, IPACX_RSTAB); | |
1036 | else | |
1037 | rstab = ReadHSCX(hx, IPAC_RSTAB); | |
1038 | pr_debug("%s: B%1d RSTAB %02x\n", hx->ip->name, hx->bch.nr, rstab); | |
1039 | if ((rstab & 0xf0) != 0xa0) { | |
1040 | /* !(VFR && !RDO && CRC && !RAB) */ | |
1041 | if (!(rstab & 0x80)) { | |
1042 | if (hx->bch.debug & DEBUG_HW_BCHANNEL) | |
1043 | pr_notice("%s: B%1d invalid frame\n", | |
475be4d8 | 1044 | hx->ip->name, hx->bch.nr); |
cae86d4a KK |
1045 | } |
1046 | if (rstab & 0x40) { | |
1047 | if (hx->bch.debug & DEBUG_HW_BCHANNEL) | |
1048 | pr_notice("%s: B%1d RDO proto=%x\n", | |
475be4d8 JP |
1049 | hx->ip->name, hx->bch.nr, |
1050 | hx->bch.state); | |
cae86d4a KK |
1051 | } |
1052 | if (!(rstab & 0x20)) { | |
1053 | if (hx->bch.debug & DEBUG_HW_BCHANNEL) | |
1054 | pr_notice("%s: B%1d CRC error\n", | |
475be4d8 | 1055 | hx->ip->name, hx->bch.nr); |
cae86d4a KK |
1056 | } |
1057 | hscx_cmdr(hx, 0x80); /* Do RMC */ | |
1058 | return; | |
1059 | } | |
1060 | if (hx->ip->type & IPAC_TYPE_IPACX) | |
1061 | count = ReadHSCX(hx, IPACX_RBCLB); | |
1062 | else | |
1063 | count = ReadHSCX(hx, IPAC_RBCLB); | |
1064 | count &= (hx->fifo_size - 1); | |
1065 | if (count == 0) | |
1066 | count = hx->fifo_size; | |
1067 | hscx_empty_fifo(hx, count); | |
1068 | if (!hx->bch.rx_skb) | |
1069 | return; | |
1070 | if (hx->bch.rx_skb->len < 2) { | |
1071 | pr_debug("%s: B%1d frame to short %d\n", | |
475be4d8 | 1072 | hx->ip->name, hx->bch.nr, hx->bch.rx_skb->len); |
cae86d4a KK |
1073 | skb_trim(hx->bch.rx_skb, 0); |
1074 | } else { | |
1075 | skb_trim(hx->bch.rx_skb, hx->bch.rx_skb->len - 1); | |
1076 | recv_Bchannel(&hx->bch, 0); | |
1077 | } | |
1078 | } | |
1079 | ||
1080 | static void | |
1081 | ipac_irq(struct hscx_hw *hx, u8 ista) | |
1082 | { | |
1083 | u8 istab, m, exirb = 0; | |
1084 | ||
1085 | if (hx->ip->type & IPAC_TYPE_IPACX) | |
1086 | istab = ReadHSCX(hx, IPACX_ISTAB); | |
1087 | else if (hx->ip->type & IPAC_TYPE_IPAC) { | |
1088 | istab = ReadHSCX(hx, IPAC_ISTAB); | |
1089 | m = (hx->bch.nr & 1) ? IPAC__EXA : IPAC__EXB; | |
1090 | if (m & ista) { | |
1091 | exirb = ReadHSCX(hx, IPAC_EXIRB); | |
1092 | pr_debug("%s: B%1d EXIRB %02x\n", hx->ip->name, | |
475be4d8 | 1093 | hx->bch.nr, exirb); |
cae86d4a KK |
1094 | } |
1095 | } else if (hx->bch.nr & 2) { /* HSCX B */ | |
1096 | if (ista & (HSCX__EXA | HSCX__ICA)) | |
1097 | ipac_irq(&hx->ip->hscx[0], ista); | |
1098 | if (ista & HSCX__EXB) { | |
1099 | exirb = ReadHSCX(hx, IPAC_EXIRB); | |
1100 | pr_debug("%s: B%1d EXIRB %02x\n", hx->ip->name, | |
475be4d8 | 1101 | hx->bch.nr, exirb); |
cae86d4a KK |
1102 | } |
1103 | istab = ista & 0xF8; | |
1104 | } else { /* HSCX A */ | |
1105 | istab = ReadHSCX(hx, IPAC_ISTAB); | |
1106 | if (ista & HSCX__EXA) { | |
1107 | exirb = ReadHSCX(hx, IPAC_EXIRB); | |
1108 | pr_debug("%s: B%1d EXIRB %02x\n", hx->ip->name, | |
475be4d8 | 1109 | hx->bch.nr, exirb); |
cae86d4a KK |
1110 | } |
1111 | istab = istab & 0xF8; | |
1112 | } | |
1113 | if (exirb & IPAC_B_XDU) | |
1114 | istab |= IPACX_B_XDU; | |
1115 | if (exirb & IPAC_B_RFO) | |
1116 | istab |= IPACX_B_RFO; | |
1117 | pr_debug("%s: B%1d ISTAB %02x\n", hx->ip->name, hx->bch.nr, istab); | |
1118 | ||
1119 | if (!test_bit(FLG_ACTIVE, &hx->bch.Flags)) | |
1120 | return; | |
1121 | ||
1122 | if (istab & IPACX_B_RME) | |
1123 | ipac_rme(hx); | |
1124 | ||
1125 | if (istab & IPACX_B_RPF) { | |
1126 | hscx_empty_fifo(hx, hx->fifo_size); | |
1127 | if (test_bit(FLG_TRANSPARENT, &hx->bch.Flags)) { | |
1128 | /* receive transparent audio data */ | |
1129 | if (hx->bch.rx_skb) | |
1130 | recv_Bchannel(&hx->bch, 0); | |
1131 | } | |
1132 | } | |
1133 | ||
1134 | if (istab & IPACX_B_RFO) { | |
1135 | pr_debug("%s: B%1d RFO error\n", hx->ip->name, hx->bch.nr); | |
1136 | hscx_cmdr(hx, 0x40); /* RRES */ | |
1137 | } | |
1138 | ||
1139 | if (istab & IPACX_B_XPR) | |
1140 | hscx_xpr(hx); | |
1141 | ||
1142 | if (istab & IPACX_B_XDU) { | |
1143 | if (test_bit(FLG_TRANSPARENT, &hx->bch.Flags)) { | |
1144 | hscx_fill_fifo(hx); | |
1145 | return; | |
1146 | } | |
1147 | pr_debug("%s: B%1d XDU error at len %d\n", hx->ip->name, | |
475be4d8 | 1148 | hx->bch.nr, hx->bch.tx_idx); |
cae86d4a KK |
1149 | hx->bch.tx_idx = 0; |
1150 | hscx_cmdr(hx, 0x01); /* XRES */ | |
1151 | } | |
1152 | } | |
1153 | ||
1154 | irqreturn_t | |
1155 | mISDNipac_irq(struct ipac_hw *ipac, int maxloop) | |
1156 | { | |
1157 | int cnt = maxloop + 1; | |
1158 | u8 ista, istad; | |
1159 | struct isac_hw *isac = &ipac->isac; | |
1160 | ||
1161 | if (ipac->type & IPAC_TYPE_IPACX) { | |
1162 | ista = ReadIPAC(ipac, ISACX_ISTA); | |
1163 | while (ista && cnt--) { | |
1164 | pr_debug("%s: ISTA %02x\n", ipac->name, ista); | |
1165 | if (ista & IPACX__ICA) | |
1166 | ipac_irq(&ipac->hscx[0], ista); | |
1167 | if (ista & IPACX__ICB) | |
1168 | ipac_irq(&ipac->hscx[1], ista); | |
1169 | if (ista & (ISACX__ICD | ISACX__CIC)) | |
1170 | mISDNisac_irq(&ipac->isac, ista); | |
1171 | ista = ReadIPAC(ipac, ISACX_ISTA); | |
1172 | } | |
1173 | } else if (ipac->type & IPAC_TYPE_IPAC) { | |
1174 | ista = ReadIPAC(ipac, IPAC_ISTA); | |
1175 | while (ista && cnt--) { | |
1176 | pr_debug("%s: ISTA %02x\n", ipac->name, ista); | |
1177 | if (ista & (IPAC__ICD | IPAC__EXD)) { | |
1178 | istad = ReadISAC(isac, ISAC_ISTA); | |
1179 | pr_debug("%s: ISTAD %02x\n", ipac->name, istad); | |
1180 | if (istad & IPAC_D_TIN2) | |
1181 | pr_debug("%s TIN2 irq\n", ipac->name); | |
1182 | if (ista & IPAC__EXD) | |
1183 | istad |= 1; /* ISAC EXI */ | |
1184 | mISDNisac_irq(isac, istad); | |
1185 | } | |
1186 | if (ista & (IPAC__ICA | IPAC__EXA)) | |
1187 | ipac_irq(&ipac->hscx[0], ista); | |
1188 | if (ista & (IPAC__ICB | IPAC__EXB)) | |
1189 | ipac_irq(&ipac->hscx[1], ista); | |
1190 | ista = ReadIPAC(ipac, IPAC_ISTA); | |
1191 | } | |
1192 | } else if (ipac->type & IPAC_TYPE_HSCX) { | |
1193 | while (cnt) { | |
1194 | ista = ReadIPAC(ipac, IPAC_ISTAB + ipac->hscx[1].off); | |
1195 | pr_debug("%s: B2 ISTA %02x\n", ipac->name, ista); | |
1196 | if (ista) | |
1197 | ipac_irq(&ipac->hscx[1], ista); | |
1198 | istad = ReadISAC(isac, ISAC_ISTA); | |
1199 | pr_debug("%s: ISTAD %02x\n", ipac->name, istad); | |
1200 | if (istad) | |
1201 | mISDNisac_irq(isac, istad); | |
1202 | if (0 == (ista | istad)) | |
1203 | break; | |
1204 | cnt--; | |
1205 | } | |
1206 | } | |
1207 | if (cnt > maxloop) /* only for ISAC/HSCX without PCI IRQ test */ | |
1208 | return IRQ_NONE; | |
1209 | if (cnt < maxloop) | |
1210 | pr_debug("%s: %d irqloops cpu%d\n", ipac->name, | |
475be4d8 | 1211 | maxloop - cnt, smp_processor_id()); |
cae86d4a KK |
1212 | if (maxloop && !cnt) |
1213 | pr_notice("%s: %d IRQ LOOP cpu%d\n", ipac->name, | |
475be4d8 | 1214 | maxloop, smp_processor_id()); |
cae86d4a KK |
1215 | return IRQ_HANDLED; |
1216 | } | |
1217 | EXPORT_SYMBOL(mISDNipac_irq); | |
1218 | ||
1219 | static int | |
1220 | hscx_mode(struct hscx_hw *hscx, u32 bprotocol) | |
1221 | { | |
1222 | pr_debug("%s: HSCX %c protocol %x-->%x ch %d\n", hscx->ip->name, | |
475be4d8 | 1223 | '@' + hscx->bch.nr, hscx->bch.state, bprotocol, hscx->bch.nr); |
cae86d4a KK |
1224 | if (hscx->ip->type & IPAC_TYPE_IPACX) { |
1225 | if (hscx->bch.nr & 1) { /* B1 and ICA */ | |
1226 | WriteIPAC(hscx->ip, ISACX_BCHA_TSDP_BC1, 0x80); | |
1227 | WriteIPAC(hscx->ip, ISACX_BCHA_CR, 0x88); | |
1228 | } else { /* B2 and ICB */ | |
1229 | WriteIPAC(hscx->ip, ISACX_BCHB_TSDP_BC1, 0x81); | |
1230 | WriteIPAC(hscx->ip, ISACX_BCHB_CR, 0x88); | |
1231 | } | |
1232 | switch (bprotocol) { | |
1233 | case ISDN_P_NONE: /* init */ | |
1234 | WriteHSCX(hscx, IPACX_MODEB, 0xC0); /* rec off */ | |
1235 | WriteHSCX(hscx, IPACX_EXMB, 0x30); /* std adj. */ | |
1236 | WriteHSCX(hscx, IPACX_MASKB, 0xFF); /* ints off */ | |
1237 | hscx_cmdr(hscx, 0x41); | |
1238 | test_and_clear_bit(FLG_HDLC, &hscx->bch.Flags); | |
1239 | test_and_clear_bit(FLG_TRANSPARENT, &hscx->bch.Flags); | |
1240 | break; | |
1241 | case ISDN_P_B_RAW: | |
1242 | WriteHSCX(hscx, IPACX_MODEB, 0x88); /* ex trans */ | |
1243 | WriteHSCX(hscx, IPACX_EXMB, 0x00); /* trans */ | |
1244 | hscx_cmdr(hscx, 0x41); | |
1245 | WriteHSCX(hscx, IPACX_MASKB, IPACX_B_ON); | |
1246 | test_and_set_bit(FLG_TRANSPARENT, &hscx->bch.Flags); | |
1247 | break; | |
1248 | case ISDN_P_B_HDLC: | |
1249 | WriteHSCX(hscx, IPACX_MODEB, 0xC0); /* trans */ | |
1250 | WriteHSCX(hscx, IPACX_EXMB, 0x00); /* hdlc,crc */ | |
1251 | hscx_cmdr(hscx, 0x41); | |
1252 | WriteHSCX(hscx, IPACX_MASKB, IPACX_B_ON); | |
1253 | test_and_set_bit(FLG_HDLC, &hscx->bch.Flags); | |
1254 | break; | |
1255 | default: | |
1256 | pr_info("%s: protocol not known %x\n", hscx->ip->name, | |
1257 | bprotocol); | |
1258 | return -ENOPROTOOPT; | |
1259 | } | |
1260 | } else if (hscx->ip->type & IPAC_TYPE_IPAC) { /* IPAC */ | |
1261 | WriteHSCX(hscx, IPAC_CCR1, 0x82); | |
1262 | WriteHSCX(hscx, IPAC_CCR2, 0x30); | |
1263 | WriteHSCX(hscx, IPAC_XCCR, 0x07); | |
1264 | WriteHSCX(hscx, IPAC_RCCR, 0x07); | |
1265 | WriteHSCX(hscx, IPAC_TSAX, hscx->slot); | |
1266 | WriteHSCX(hscx, IPAC_TSAR, hscx->slot); | |
1267 | switch (bprotocol) { | |
1268 | case ISDN_P_NONE: | |
1269 | WriteHSCX(hscx, IPAC_TSAX, 0x1F); | |
1270 | WriteHSCX(hscx, IPAC_TSAR, 0x1F); | |
1271 | WriteHSCX(hscx, IPAC_MODEB, 0x84); | |
1272 | WriteHSCX(hscx, IPAC_CCR1, 0x82); | |
1273 | WriteHSCX(hscx, IPAC_MASKB, 0xFF); /* ints off */ | |
1274 | test_and_clear_bit(FLG_HDLC, &hscx->bch.Flags); | |
1275 | test_and_clear_bit(FLG_TRANSPARENT, &hscx->bch.Flags); | |
1276 | break; | |
1277 | case ISDN_P_B_RAW: | |
1278 | WriteHSCX(hscx, IPAC_MODEB, 0xe4); /* ex trans */ | |
1279 | WriteHSCX(hscx, IPAC_CCR1, 0x82); | |
1280 | hscx_cmdr(hscx, 0x41); | |
1281 | WriteHSCX(hscx, IPAC_MASKB, 0); | |
1282 | test_and_set_bit(FLG_TRANSPARENT, &hscx->bch.Flags); | |
1283 | break; | |
1284 | case ISDN_P_B_HDLC: | |
1285 | WriteHSCX(hscx, IPAC_MODEB, 0x8c); | |
1286 | WriteHSCX(hscx, IPAC_CCR1, 0x8a); | |
1287 | hscx_cmdr(hscx, 0x41); | |
1288 | WriteHSCX(hscx, IPAC_MASKB, 0); | |
1289 | test_and_set_bit(FLG_HDLC, &hscx->bch.Flags); | |
1290 | break; | |
1291 | default: | |
1292 | pr_info("%s: protocol not known %x\n", hscx->ip->name, | |
1293 | bprotocol); | |
1294 | return -ENOPROTOOPT; | |
1295 | } | |
1296 | } else if (hscx->ip->type & IPAC_TYPE_HSCX) { /* HSCX */ | |
1297 | WriteHSCX(hscx, IPAC_CCR1, 0x85); | |
1298 | WriteHSCX(hscx, IPAC_CCR2, 0x30); | |
1299 | WriteHSCX(hscx, IPAC_XCCR, 0x07); | |
1300 | WriteHSCX(hscx, IPAC_RCCR, 0x07); | |
1301 | WriteHSCX(hscx, IPAC_TSAX, hscx->slot); | |
1302 | WriteHSCX(hscx, IPAC_TSAR, hscx->slot); | |
1303 | switch (bprotocol) { | |
1304 | case ISDN_P_NONE: | |
1305 | WriteHSCX(hscx, IPAC_TSAX, 0x1F); | |
1306 | WriteHSCX(hscx, IPAC_TSAR, 0x1F); | |
1307 | WriteHSCX(hscx, IPAC_MODEB, 0x84); | |
1308 | WriteHSCX(hscx, IPAC_CCR1, 0x85); | |
1309 | WriteHSCX(hscx, IPAC_MASKB, 0xFF); /* ints off */ | |
1310 | test_and_clear_bit(FLG_HDLC, &hscx->bch.Flags); | |
1311 | test_and_clear_bit(FLG_TRANSPARENT, &hscx->bch.Flags); | |
1312 | break; | |
1313 | case ISDN_P_B_RAW: | |
1314 | WriteHSCX(hscx, IPAC_MODEB, 0xe4); /* ex trans */ | |
1315 | WriteHSCX(hscx, IPAC_CCR1, 0x85); | |
1316 | hscx_cmdr(hscx, 0x41); | |
1317 | WriteHSCX(hscx, IPAC_MASKB, 0); | |
1318 | test_and_set_bit(FLG_TRANSPARENT, &hscx->bch.Flags); | |
1319 | break; | |
1320 | case ISDN_P_B_HDLC: | |
1321 | WriteHSCX(hscx, IPAC_MODEB, 0x8c); | |
1322 | WriteHSCX(hscx, IPAC_CCR1, 0x8d); | |
1323 | hscx_cmdr(hscx, 0x41); | |
1324 | WriteHSCX(hscx, IPAC_MASKB, 0); | |
1325 | test_and_set_bit(FLG_HDLC, &hscx->bch.Flags); | |
1326 | break; | |
1327 | default: | |
1328 | pr_info("%s: protocol not known %x\n", hscx->ip->name, | |
1329 | bprotocol); | |
1330 | return -ENOPROTOOPT; | |
1331 | } | |
1332 | } else | |
1333 | return -EINVAL; | |
1334 | hscx->bch.state = bprotocol; | |
1335 | return 0; | |
1336 | } | |
1337 | ||
1338 | static int | |
1339 | hscx_l2l1(struct mISDNchannel *ch, struct sk_buff *skb) | |
1340 | { | |
1341 | struct bchannel *bch = container_of(ch, struct bchannel, ch); | |
1342 | struct hscx_hw *hx = container_of(bch, struct hscx_hw, bch); | |
1343 | int ret = -EINVAL; | |
1344 | struct mISDNhead *hh = mISDN_HEAD_P(skb); | |
1345 | u32 id; | |
1346 | u_long flags; | |
1347 | ||
1348 | switch (hh->prim) { | |
1349 | case PH_DATA_REQ: | |
1350 | spin_lock_irqsave(hx->ip->hwlock, flags); | |
1351 | ret = bchannel_senddata(bch, skb); | |
1352 | if (ret > 0) { /* direct TX */ | |
1353 | id = hh->id; /* skb can be freed */ | |
1354 | ret = 0; | |
1355 | hscx_fill_fifo(hx); | |
1356 | spin_unlock_irqrestore(hx->ip->hwlock, flags); | |
1357 | if (!test_bit(FLG_TRANSPARENT, &bch->Flags)) | |
1358 | queue_ch_frame(ch, PH_DATA_CNF, id, NULL); | |
1359 | } else | |
1360 | spin_unlock_irqrestore(hx->ip->hwlock, flags); | |
1361 | return ret; | |
1362 | case PH_ACTIVATE_REQ: | |
1363 | spin_lock_irqsave(hx->ip->hwlock, flags); | |
1364 | if (!test_and_set_bit(FLG_ACTIVE, &bch->Flags)) | |
1365 | ret = hscx_mode(hx, ch->protocol); | |
1366 | else | |
1367 | ret = 0; | |
1368 | spin_unlock_irqrestore(hx->ip->hwlock, flags); | |
1369 | if (!ret) | |
1370 | _queue_data(ch, PH_ACTIVATE_IND, MISDN_ID_ANY, 0, | |
475be4d8 | 1371 | NULL, GFP_KERNEL); |
cae86d4a KK |
1372 | break; |
1373 | case PH_DEACTIVATE_REQ: | |
1374 | spin_lock_irqsave(hx->ip->hwlock, flags); | |
1375 | mISDN_clear_bchannel(bch); | |
1376 | hscx_mode(hx, ISDN_P_NONE); | |
1377 | spin_unlock_irqrestore(hx->ip->hwlock, flags); | |
1378 | _queue_data(ch, PH_DEACTIVATE_IND, MISDN_ID_ANY, 0, | |
475be4d8 | 1379 | NULL, GFP_KERNEL); |
cae86d4a KK |
1380 | ret = 0; |
1381 | break; | |
1382 | default: | |
1383 | pr_info("%s: %s unknown prim(%x,%x)\n", | |
1384 | hx->ip->name, __func__, hh->prim, hh->id); | |
1385 | ret = -EINVAL; | |
1386 | } | |
1387 | if (!ret) | |
1388 | dev_kfree_skb(skb); | |
1389 | return ret; | |
1390 | } | |
1391 | ||
1392 | static int | |
1393 | channel_bctrl(struct bchannel *bch, struct mISDN_ctrl_req *cq) | |
1394 | { | |
1395 | int ret = 0; | |
1396 | ||
1397 | switch (cq->op) { | |
1398 | case MISDN_CTRL_GETOP: | |
1399 | cq->op = 0; | |
1400 | break; | |
475be4d8 | 1401 | /* Nothing implemented yet */ |
cae86d4a KK |
1402 | case MISDN_CTRL_FILL_EMPTY: |
1403 | default: | |
1404 | pr_info("%s: unknown Op %x\n", __func__, cq->op); | |
1405 | ret = -EINVAL; | |
1406 | break; | |
1407 | } | |
1408 | return ret; | |
1409 | } | |
1410 | ||
1411 | static int | |
1412 | hscx_bctrl(struct mISDNchannel *ch, u32 cmd, void *arg) | |
1413 | { | |
1414 | struct bchannel *bch = container_of(ch, struct bchannel, ch); | |
1415 | struct hscx_hw *hx = container_of(bch, struct hscx_hw, bch); | |
1416 | int ret = -EINVAL; | |
1417 | u_long flags; | |
1418 | ||
1419 | pr_debug("%s: %s cmd:%x %p\n", hx->ip->name, __func__, cmd, arg); | |
1420 | switch (cmd) { | |
1421 | case CLOSE_CHANNEL: | |
1422 | test_and_clear_bit(FLG_OPEN, &bch->Flags); | |
1368112c KK |
1423 | spin_lock_irqsave(hx->ip->hwlock, flags); |
1424 | mISDN_freebchannel(bch); | |
1425 | hscx_mode(hx, ISDN_P_NONE); | |
1426 | spin_unlock_irqrestore(hx->ip->hwlock, flags); | |
cae86d4a KK |
1427 | ch->protocol = ISDN_P_NONE; |
1428 | ch->peer = NULL; | |
1429 | module_put(hx->ip->owner); | |
1430 | ret = 0; | |
1431 | break; | |
1432 | case CONTROL_CHANNEL: | |
1433 | ret = channel_bctrl(bch, arg); | |
1434 | break; | |
1435 | default: | |
1436 | pr_info("%s: %s unknown prim(%x)\n", | |
1437 | hx->ip->name, __func__, cmd); | |
1438 | } | |
1439 | return ret; | |
1440 | } | |
1441 | ||
1442 | static void | |
1443 | free_ipac(struct ipac_hw *ipac) | |
1444 | { | |
1445 | isac_release(&ipac->isac); | |
1446 | } | |
1447 | ||
1448 | static const char *HSCXVer[] = | |
1449 | {"A1", "?1", "A2", "?3", "A3", "V2.1", "?6", "?7", | |
1450 | "?8", "?9", "?10", "?11", "?12", "?13", "?14", "???"}; | |
1451 | ||
1452 | ||
1453 | ||
1454 | static void | |
1455 | hscx_init(struct hscx_hw *hx) | |
1456 | { | |
1457 | u8 val; | |
1458 | ||
1459 | WriteHSCX(hx, IPAC_RAH2, 0xFF); | |
1460 | WriteHSCX(hx, IPAC_XBCH, 0x00); | |
1461 | WriteHSCX(hx, IPAC_RLCR, 0x00); | |
1462 | ||
1463 | if (hx->ip->type & IPAC_TYPE_HSCX) { | |
1464 | WriteHSCX(hx, IPAC_CCR1, 0x85); | |
1465 | val = ReadHSCX(hx, HSCX_VSTR); | |
1466 | pr_debug("%s: HSCX VSTR %02x\n", hx->ip->name, val); | |
1467 | if (hx->bch.debug & DEBUG_HW) | |
1468 | pr_notice("%s: HSCX version %s\n", hx->ip->name, | |
475be4d8 | 1469 | HSCXVer[val & 0x0f]); |
cae86d4a KK |
1470 | } else |
1471 | WriteHSCX(hx, IPAC_CCR1, 0x82); | |
1472 | WriteHSCX(hx, IPAC_CCR2, 0x30); | |
1473 | WriteHSCX(hx, IPAC_XCCR, 0x07); | |
1474 | WriteHSCX(hx, IPAC_RCCR, 0x07); | |
1475 | } | |
1476 | ||
1477 | static int | |
1478 | ipac_init(struct ipac_hw *ipac) | |
1479 | { | |
1480 | u8 val; | |
1481 | ||
1482 | if (ipac->type & IPAC_TYPE_HSCX) { | |
1483 | hscx_init(&ipac->hscx[0]); | |
1484 | hscx_init(&ipac->hscx[1]); | |
1485 | val = ReadIPAC(ipac, IPAC_ID); | |
1486 | } else if (ipac->type & IPAC_TYPE_IPAC) { | |
1487 | hscx_init(&ipac->hscx[0]); | |
1488 | hscx_init(&ipac->hscx[1]); | |
1489 | WriteIPAC(ipac, IPAC_MASK, IPAC__ON); | |
1490 | val = ReadIPAC(ipac, IPAC_CONF); | |
1491 | /* conf is default 0, but can be overwritten by card setup */ | |
1492 | pr_debug("%s: IPAC CONF %02x/%02x\n", ipac->name, | |
475be4d8 | 1493 | val, ipac->conf); |
cae86d4a KK |
1494 | WriteIPAC(ipac, IPAC_CONF, ipac->conf); |
1495 | val = ReadIPAC(ipac, IPAC_ID); | |
1496 | if (ipac->hscx[0].bch.debug & DEBUG_HW) | |
1497 | pr_notice("%s: IPAC Design ID %02x\n", ipac->name, val); | |
1498 | } | |
1499 | /* nothing special for IPACX to do here */ | |
1500 | return isac_init(&ipac->isac); | |
1501 | } | |
1502 | ||
1503 | static int | |
1504 | open_bchannel(struct ipac_hw *ipac, struct channel_req *rq) | |
1505 | { | |
1506 | struct bchannel *bch; | |
1507 | ||
819a1008 | 1508 | if (rq->adr.channel == 0 || rq->adr.channel > 2) |
cae86d4a KK |
1509 | return -EINVAL; |
1510 | if (rq->protocol == ISDN_P_NONE) | |
1511 | return -EINVAL; | |
1512 | bch = &ipac->hscx[rq->adr.channel - 1].bch; | |
1513 | if (test_and_set_bit(FLG_OPEN, &bch->Flags)) | |
1514 | return -EBUSY; /* b-channel can be only open once */ | |
1515 | test_and_clear_bit(FLG_FILLEMPTY, &bch->Flags); | |
1516 | bch->ch.protocol = rq->protocol; | |
1517 | rq->ch = &bch->ch; | |
1518 | return 0; | |
1519 | } | |
1520 | ||
1521 | static int | |
1522 | channel_ctrl(struct ipac_hw *ipac, struct mISDN_ctrl_req *cq) | |
1523 | { | |
1524 | int ret = 0; | |
1525 | ||
1526 | switch (cq->op) { | |
1527 | case MISDN_CTRL_GETOP: | |
c626c127 | 1528 | cq->op = MISDN_CTRL_LOOP | MISDN_CTRL_L1_TIMER3; |
cae86d4a KK |
1529 | break; |
1530 | case MISDN_CTRL_LOOP: | |
1531 | /* cq->channel: 0 disable, 1 B1 loop 2 B2 loop, 3 both */ | |
1532 | if (cq->channel < 0 || cq->channel > 3) { | |
1533 | ret = -EINVAL; | |
1534 | break; | |
1535 | } | |
1536 | ret = ipac->ctrl(ipac, HW_TESTLOOP, cq->channel); | |
1537 | break; | |
c626c127 KK |
1538 | case MISDN_CTRL_L1_TIMER3: |
1539 | ret = ipac->isac.ctrl(&ipac->isac, HW_TIMER3_VALUE, cq->p1); | |
1540 | break; | |
cae86d4a KK |
1541 | default: |
1542 | pr_info("%s: unknown CTRL OP %x\n", ipac->name, cq->op); | |
1543 | ret = -EINVAL; | |
1544 | break; | |
1545 | } | |
1546 | return ret; | |
1547 | } | |
1548 | ||
1549 | static int | |
1550 | ipac_dctrl(struct mISDNchannel *ch, u32 cmd, void *arg) | |
1551 | { | |
1552 | struct mISDNdevice *dev = container_of(ch, struct mISDNdevice, D); | |
1553 | struct dchannel *dch = container_of(dev, struct dchannel, dev); | |
1554 | struct isac_hw *isac = container_of(dch, struct isac_hw, dch); | |
1555 | struct ipac_hw *ipac = container_of(isac, struct ipac_hw, isac); | |
1556 | struct channel_req *rq; | |
1557 | int err = 0; | |
1558 | ||
1559 | pr_debug("%s: DCTRL: %x %p\n", ipac->name, cmd, arg); | |
1560 | switch (cmd) { | |
1561 | case OPEN_CHANNEL: | |
1562 | rq = arg; | |
1563 | if (rq->protocol == ISDN_P_TE_S0) | |
1564 | err = open_dchannel(isac, rq); | |
1565 | else | |
1566 | err = open_bchannel(ipac, rq); | |
1567 | if (err) | |
1568 | break; | |
1569 | if (!try_module_get(ipac->owner)) | |
1570 | pr_info("%s: cannot get module\n", ipac->name); | |
1571 | break; | |
1572 | case CLOSE_CHANNEL: | |
1573 | pr_debug("%s: dev(%d) close from %p\n", ipac->name, | |
475be4d8 | 1574 | dch->dev.id, __builtin_return_address(0)); |
cae86d4a KK |
1575 | module_put(ipac->owner); |
1576 | break; | |
1577 | case CONTROL_CHANNEL: | |
1578 | err = channel_ctrl(ipac, arg); | |
1579 | break; | |
1580 | default: | |
1581 | pr_debug("%s: unknown DCTRL command %x\n", ipac->name, cmd); | |
1582 | return -EINVAL; | |
1583 | } | |
1584 | return err; | |
1585 | } | |
1586 | ||
1587 | u32 | |
1588 | mISDNipac_init(struct ipac_hw *ipac, void *hw) | |
1589 | { | |
1590 | u32 ret; | |
1591 | u8 i; | |
1592 | ||
1593 | ipac->hw = hw; | |
1594 | if (ipac->isac.dch.debug & DEBUG_HW) | |
1595 | pr_notice("%s: ipac type %x\n", ipac->name, ipac->type); | |
1596 | if (ipac->type & IPAC_TYPE_HSCX) { | |
1597 | ipac->isac.type = IPAC_TYPE_ISAC; | |
1598 | ipac->hscx[0].off = 0; | |
1599 | ipac->hscx[1].off = 0x40; | |
1600 | ipac->hscx[0].fifo_size = 32; | |
1601 | ipac->hscx[1].fifo_size = 32; | |
1602 | } else if (ipac->type & IPAC_TYPE_IPAC) { | |
1603 | ipac->isac.type = IPAC_TYPE_IPAC | IPAC_TYPE_ISAC; | |
1604 | ipac->hscx[0].off = 0; | |
1605 | ipac->hscx[1].off = 0x40; | |
1606 | ipac->hscx[0].fifo_size = 64; | |
1607 | ipac->hscx[1].fifo_size = 64; | |
1608 | } else if (ipac->type & IPAC_TYPE_IPACX) { | |
1609 | ipac->isac.type = IPAC_TYPE_IPACX | IPAC_TYPE_ISACX; | |
1610 | ipac->hscx[0].off = IPACX_OFF_ICA; | |
1611 | ipac->hscx[1].off = IPACX_OFF_ICB; | |
1612 | ipac->hscx[0].fifo_size = 64; | |
1613 | ipac->hscx[1].fifo_size = 64; | |
1614 | } else | |
1615 | return 0; | |
1616 | ||
1617 | mISDNisac_init(&ipac->isac, hw); | |
1618 | ||
1619 | ipac->isac.dch.dev.D.ctrl = ipac_dctrl; | |
1620 | ||
1621 | for (i = 0; i < 2; i++) { | |
1622 | ipac->hscx[i].bch.nr = i + 1; | |
1623 | set_channelmap(i + 1, ipac->isac.dch.dev.channelmap); | |
1624 | list_add(&ipac->hscx[i].bch.ch.list, | |
475be4d8 | 1625 | &ipac->isac.dch.dev.bchannels); |
cae86d4a KK |
1626 | mISDN_initbchannel(&ipac->hscx[i].bch, MAX_DATA_MEM); |
1627 | ipac->hscx[i].bch.ch.nr = i + 1; | |
1628 | ipac->hscx[i].bch.ch.send = &hscx_l2l1; | |
1629 | ipac->hscx[i].bch.ch.ctrl = hscx_bctrl; | |
1630 | ipac->hscx[i].bch.hw = hw; | |
1631 | ipac->hscx[i].ip = ipac; | |
1632 | /* default values for IOM time slots | |
1633 | * can be overwriten by card */ | |
1634 | ipac->hscx[i].slot = (i == 0) ? 0x2f : 0x03; | |
1635 | } | |
1636 | ||
1637 | ipac->init = ipac_init; | |
1638 | ipac->release = free_ipac; | |
1639 | ||
1640 | ret = (1 << (ISDN_P_B_RAW & ISDN_P_B_MASK)) | | |
1641 | (1 << (ISDN_P_B_HDLC & ISDN_P_B_MASK)); | |
1642 | return ret; | |
1643 | } | |
1644 | EXPORT_SYMBOL(mISDNipac_init); | |
1645 | ||
1646 | static int __init | |
1647 | isac_mod_init(void) | |
1648 | { | |
1649 | pr_notice("mISDNipac module version %s\n", ISAC_REV); | |
1650 | return 0; | |
1651 | } | |
1652 | ||
1653 | static void __exit | |
1654 | isac_mod_cleanup(void) | |
1655 | { | |
1656 | pr_notice("mISDNipac module unloaded\n"); | |
1657 | } | |
1658 | module_init(isac_mod_init); | |
1659 | module_exit(isac_mod_cleanup); |