Commit | Line | Data |
---|---|---|
4c18e77f | 1 | /* |
4c18e77f | 2 | * SPEAr platform shared irq layer source file |
3 | * | |
df1590d9 | 4 | * Copyright (C) 2009-2012 ST Microelectronics |
10d8935f | 5 | * Viresh Kumar <viresh.linux@gmail.com> |
4c18e77f | 6 | * |
df1590d9 | 7 | * Copyright (C) 2012 ST Microelectronics |
9cc23682 | 8 | * Shiraz Hashim <shiraz.linux.kernel@gmail.com> |
df1590d9 | 9 | * |
4c18e77f | 10 | * This file is licensed under the terms of the GNU General Public |
11 | * License version 2. This program is licensed "as is" without any | |
12 | * warranty of any kind, whether express or implied. | |
13 | */ | |
80515a5a | 14 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
4c18e77f | 15 | |
16 | #include <linux/err.h> | |
80515a5a SH |
17 | #include <linux/export.h> |
18 | #include <linux/interrupt.h> | |
4c18e77f | 19 | #include <linux/io.h> |
20 | #include <linux/irq.h> | |
80515a5a SH |
21 | #include <linux/irqdomain.h> |
22 | #include <linux/of.h> | |
23 | #include <linux/of_address.h> | |
24 | #include <linux/of_irq.h> | |
4c18e77f | 25 | #include <linux/spinlock.h> |
4c18e77f | 26 | |
e9c51558 RH |
27 | #include "irqchip.h" |
28 | ||
078bc005 TG |
29 | /* |
30 | * struct shirq_regs: shared irq register configuration | |
31 | * | |
32 | * enb_reg: enable register offset | |
33 | * reset_to_enb: val 1 indicates, we need to clear bit for enabling interrupt | |
34 | * status_reg: status register offset | |
35 | * status_reg_mask: status register valid mask | |
36 | * clear_reg: clear register offset | |
37 | * reset_to_clear: val 1 indicates, we need to clear bit for clearing interrupt | |
38 | */ | |
39 | struct shirq_regs { | |
40 | u32 enb_reg; | |
41 | u32 reset_to_enb; | |
42 | u32 status_reg; | |
43 | u32 clear_reg; | |
44 | u32 reset_to_clear; | |
45 | }; | |
46 | ||
47 | /* | |
48 | * struct spear_shirq: shared irq structure | |
49 | * | |
078bc005 TG |
50 | * irq_base: base irq in linux domain |
51 | * irq_nr: no. of shared interrupts in a particular block | |
52 | * irq_bit_off: starting bit offset in the status register | |
53 | * invalid_irq: irq group is currently disabled | |
54 | * base: base address of shared irq register | |
55 | * regs: register configuration for shared irq block | |
56 | */ | |
57 | struct spear_shirq { | |
078bc005 TG |
58 | u32 irq_base; |
59 | u32 irq_nr; | |
60 | u32 irq_bit_off; | |
61 | int invalid_irq; | |
62 | void __iomem *base; | |
63 | struct shirq_regs regs; | |
64 | }; | |
65 | ||
4c18e77f | 66 | static DEFINE_SPINLOCK(lock); |
67 | ||
80515a5a SH |
68 | /* spear300 shared irq registers offsets and masks */ |
69 | #define SPEAR300_INT_ENB_MASK_REG 0x54 | |
70 | #define SPEAR300_INT_STS_MASK_REG 0x58 | |
71 | ||
72 | static struct spear_shirq spear300_shirq_ras1 = { | |
73 | .irq_nr = 9, | |
74 | .irq_bit_off = 0, | |
75 | .regs = { | |
76 | .enb_reg = SPEAR300_INT_ENB_MASK_REG, | |
77 | .status_reg = SPEAR300_INT_STS_MASK_REG, | |
78 | .clear_reg = -1, | |
79 | }, | |
80 | }; | |
81 | ||
82 | static struct spear_shirq *spear300_shirq_blocks[] = { | |
83 | &spear300_shirq_ras1, | |
84 | }; | |
85 | ||
86 | /* spear310 shared irq registers offsets and masks */ | |
87 | #define SPEAR310_INT_STS_MASK_REG 0x04 | |
88 | ||
89 | static struct spear_shirq spear310_shirq_ras1 = { | |
90 | .irq_nr = 8, | |
91 | .irq_bit_off = 0, | |
92 | .regs = { | |
93 | .enb_reg = -1, | |
94 | .status_reg = SPEAR310_INT_STS_MASK_REG, | |
95 | .clear_reg = -1, | |
96 | }, | |
97 | }; | |
98 | ||
99 | static struct spear_shirq spear310_shirq_ras2 = { | |
100 | .irq_nr = 5, | |
101 | .irq_bit_off = 8, | |
102 | .regs = { | |
103 | .enb_reg = -1, | |
104 | .status_reg = SPEAR310_INT_STS_MASK_REG, | |
105 | .clear_reg = -1, | |
106 | }, | |
107 | }; | |
108 | ||
109 | static struct spear_shirq spear310_shirq_ras3 = { | |
110 | .irq_nr = 1, | |
111 | .irq_bit_off = 13, | |
112 | .regs = { | |
113 | .enb_reg = -1, | |
114 | .status_reg = SPEAR310_INT_STS_MASK_REG, | |
115 | .clear_reg = -1, | |
116 | }, | |
117 | }; | |
118 | ||
119 | static struct spear_shirq spear310_shirq_intrcomm_ras = { | |
120 | .irq_nr = 3, | |
121 | .irq_bit_off = 14, | |
122 | .regs = { | |
123 | .enb_reg = -1, | |
124 | .status_reg = SPEAR310_INT_STS_MASK_REG, | |
125 | .clear_reg = -1, | |
126 | }, | |
127 | }; | |
128 | ||
129 | static struct spear_shirq *spear310_shirq_blocks[] = { | |
130 | &spear310_shirq_ras1, | |
131 | &spear310_shirq_ras2, | |
132 | &spear310_shirq_ras3, | |
133 | &spear310_shirq_intrcomm_ras, | |
134 | }; | |
135 | ||
136 | /* spear320 shared irq registers offsets and masks */ | |
137 | #define SPEAR320_INT_STS_MASK_REG 0x04 | |
138 | #define SPEAR320_INT_CLR_MASK_REG 0x04 | |
139 | #define SPEAR320_INT_ENB_MASK_REG 0x08 | |
140 | ||
141 | static struct spear_shirq spear320_shirq_ras1 = { | |
142 | .irq_nr = 3, | |
143 | .irq_bit_off = 7, | |
144 | .regs = { | |
145 | .enb_reg = -1, | |
146 | .status_reg = SPEAR320_INT_STS_MASK_REG, | |
147 | .clear_reg = SPEAR320_INT_CLR_MASK_REG, | |
148 | .reset_to_clear = 1, | |
149 | }, | |
150 | }; | |
151 | ||
152 | static struct spear_shirq spear320_shirq_ras2 = { | |
153 | .irq_nr = 1, | |
154 | .irq_bit_off = 10, | |
155 | .regs = { | |
156 | .enb_reg = -1, | |
157 | .status_reg = SPEAR320_INT_STS_MASK_REG, | |
158 | .clear_reg = SPEAR320_INT_CLR_MASK_REG, | |
159 | .reset_to_clear = 1, | |
160 | }, | |
161 | }; | |
162 | ||
163 | static struct spear_shirq spear320_shirq_ras3 = { | |
4f436603 | 164 | .irq_nr = 7, |
80515a5a SH |
165 | .irq_bit_off = 0, |
166 | .invalid_irq = 1, | |
167 | .regs = { | |
168 | .enb_reg = SPEAR320_INT_ENB_MASK_REG, | |
169 | .reset_to_enb = 1, | |
170 | .status_reg = SPEAR320_INT_STS_MASK_REG, | |
171 | .clear_reg = SPEAR320_INT_CLR_MASK_REG, | |
172 | .reset_to_clear = 1, | |
173 | }, | |
174 | }; | |
175 | ||
176 | static struct spear_shirq spear320_shirq_intrcomm_ras = { | |
177 | .irq_nr = 11, | |
178 | .irq_bit_off = 11, | |
179 | .regs = { | |
180 | .enb_reg = -1, | |
181 | .status_reg = SPEAR320_INT_STS_MASK_REG, | |
182 | .clear_reg = SPEAR320_INT_CLR_MASK_REG, | |
183 | .reset_to_clear = 1, | |
184 | }, | |
185 | }; | |
186 | ||
187 | static struct spear_shirq *spear320_shirq_blocks[] = { | |
188 | &spear320_shirq_ras3, | |
189 | &spear320_shirq_ras1, | |
190 | &spear320_shirq_ras2, | |
191 | &spear320_shirq_intrcomm_ras, | |
192 | }; | |
193 | ||
194 | static void shirq_irq_mask_unmask(struct irq_data *d, bool mask) | |
4c18e77f | 195 | { |
0e60e117 | 196 | struct spear_shirq *shirq = irq_data_get_irq_chip_data(d); |
80515a5a | 197 | u32 val, offset = d->irq - shirq->irq_base; |
4c18e77f | 198 | unsigned long flags; |
199 | ||
80515a5a | 200 | if (shirq->regs.enb_reg == -1) |
4c18e77f | 201 | return; |
202 | ||
203 | spin_lock_irqsave(&lock, flags); | |
80515a5a SH |
204 | val = readl(shirq->base + shirq->regs.enb_reg); |
205 | ||
206 | if (mask ^ shirq->regs.reset_to_enb) | |
207 | val &= ~(0x1 << shirq->irq_bit_off << offset); | |
4c18e77f | 208 | else |
80515a5a SH |
209 | val |= 0x1 << shirq->irq_bit_off << offset; |
210 | ||
211 | writel(val, shirq->base + shirq->regs.enb_reg); | |
4c18e77f | 212 | spin_unlock_irqrestore(&lock, flags); |
80515a5a | 213 | |
4c18e77f | 214 | } |
215 | ||
80515a5a | 216 | static void shirq_irq_mask(struct irq_data *d) |
4c18e77f | 217 | { |
80515a5a SH |
218 | shirq_irq_mask_unmask(d, 1); |
219 | } | |
4c18e77f | 220 | |
80515a5a SH |
221 | static void shirq_irq_unmask(struct irq_data *d) |
222 | { | |
223 | shirq_irq_mask_unmask(d, 0); | |
4c18e77f | 224 | } |
225 | ||
226 | static struct irq_chip shirq_chip = { | |
80515a5a | 227 | .name = "spear-shirq", |
0e60e117 LB |
228 | .irq_ack = shirq_irq_mask, |
229 | .irq_mask = shirq_irq_mask, | |
230 | .irq_unmask = shirq_irq_unmask, | |
4c18e77f | 231 | }; |
232 | ||
233 | static void shirq_handler(unsigned irq, struct irq_desc *desc) | |
234 | { | |
80515a5a SH |
235 | u32 i, j, val, mask, tmp; |
236 | struct irq_chip *chip; | |
6845664a | 237 | struct spear_shirq *shirq = irq_get_handler_data(irq); |
4c18e77f | 238 | |
80515a5a SH |
239 | chip = irq_get_chip(irq); |
240 | chip->irq_ack(&desc->irq_data); | |
241 | ||
242 | mask = ((0x1 << shirq->irq_nr) - 1) << shirq->irq_bit_off; | |
243 | while ((val = readl(shirq->base + shirq->regs.status_reg) & | |
244 | mask)) { | |
245 | ||
246 | val >>= shirq->irq_bit_off; | |
247 | for (i = 0, j = 1; i < shirq->irq_nr; i++, j <<= 1) { | |
248 | ||
249 | if (!(j & val)) | |
4c18e77f | 250 | continue; |
251 | ||
80515a5a | 252 | generic_handle_irq(shirq->irq_base + i); |
4c18e77f | 253 | |
254 | /* clear interrupt */ | |
80515a5a | 255 | if (shirq->regs.clear_reg == -1) |
4c18e77f | 256 | continue; |
80515a5a SH |
257 | |
258 | tmp = readl(shirq->base + shirq->regs.clear_reg); | |
4c18e77f | 259 | if (shirq->regs.reset_to_clear) |
80515a5a | 260 | tmp &= ~(j << shirq->irq_bit_off); |
4c18e77f | 261 | else |
80515a5a SH |
262 | tmp |= (j << shirq->irq_bit_off); |
263 | writel(tmp, shirq->base + shirq->regs.clear_reg); | |
4c18e77f | 264 | } |
265 | } | |
80515a5a | 266 | chip->irq_unmask(&desc->irq_data); |
4c18e77f | 267 | } |
268 | ||
f37ecbce TG |
269 | static void __init spear_shirq_register(struct spear_shirq *shirq, |
270 | int parent_irq) | |
4c18e77f | 271 | { |
272 | int i; | |
273 | ||
80515a5a SH |
274 | if (shirq->invalid_irq) |
275 | return; | |
4c18e77f | 276 | |
f37ecbce TG |
277 | irq_set_chained_handler(parent_irq, shirq_handler); |
278 | irq_set_handler_data(parent_irq, shirq); | |
279 | ||
80515a5a SH |
280 | for (i = 0; i < shirq->irq_nr; i++) { |
281 | irq_set_chip_and_handler(shirq->irq_base + i, | |
f38c02f3 | 282 | &shirq_chip, handle_simple_irq); |
80515a5a SH |
283 | set_irq_flags(shirq->irq_base + i, IRQF_VALID); |
284 | irq_set_chip_data(shirq->irq_base + i, shirq); | |
4c18e77f | 285 | } |
80515a5a SH |
286 | } |
287 | ||
288 | static int __init shirq_init(struct spear_shirq **shirq_blocks, int block_nr, | |
289 | struct device_node *np) | |
290 | { | |
f37ecbce | 291 | int i, parent_irq, irq_base, hwirq = 0, irq_nr = 0; |
a26c06f9 | 292 | struct irq_domain *shirq_domain; |
80515a5a SH |
293 | void __iomem *base; |
294 | ||
295 | base = of_iomap(np, 0); | |
296 | if (!base) { | |
297 | pr_err("%s: failed to map shirq registers\n", __func__); | |
298 | return -ENXIO; | |
299 | } | |
300 | ||
301 | for (i = 0; i < block_nr; i++) | |
302 | irq_nr += shirq_blocks[i]->irq_nr; | |
303 | ||
304 | irq_base = irq_alloc_descs(-1, 0, irq_nr, 0); | |
305 | if (IS_ERR_VALUE(irq_base)) { | |
306 | pr_err("%s: irq desc alloc failed\n", __func__); | |
307 | goto err_unmap; | |
308 | } | |
309 | ||
310 | shirq_domain = irq_domain_add_legacy(np, irq_nr, irq_base, 0, | |
311 | &irq_domain_simple_ops, NULL); | |
312 | if (WARN_ON(!shirq_domain)) { | |
313 | pr_warn("%s: irq domain init failed\n", __func__); | |
314 | goto err_free_desc; | |
315 | } | |
316 | ||
317 | for (i = 0; i < block_nr; i++) { | |
318 | shirq_blocks[i]->base = base; | |
319 | shirq_blocks[i]->irq_base = irq_find_mapping(shirq_domain, | |
320 | hwirq); | |
80515a5a | 321 | |
f37ecbce TG |
322 | parent_irq = irq_of_parse_and_map(np, i); |
323 | spear_shirq_register(shirq_blocks[i], parent_irq); | |
80515a5a SH |
324 | hwirq += shirq_blocks[i]->irq_nr; |
325 | } | |
326 | ||
4c18e77f | 327 | return 0; |
80515a5a SH |
328 | |
329 | err_free_desc: | |
330 | irq_free_descs(irq_base, irq_nr); | |
331 | err_unmap: | |
332 | iounmap(base); | |
333 | return -ENXIO; | |
334 | } | |
335 | ||
078bc005 TG |
336 | static int __init spear300_shirq_of_init(struct device_node *np, |
337 | struct device_node *parent) | |
80515a5a SH |
338 | { |
339 | return shirq_init(spear300_shirq_blocks, | |
340 | ARRAY_SIZE(spear300_shirq_blocks), np); | |
341 | } | |
e9c51558 | 342 | IRQCHIP_DECLARE(spear300_shirq, "st,spear300-shirq", spear300_shirq_of_init); |
80515a5a | 343 | |
078bc005 TG |
344 | static int __init spear310_shirq_of_init(struct device_node *np, |
345 | struct device_node *parent) | |
80515a5a SH |
346 | { |
347 | return shirq_init(spear310_shirq_blocks, | |
348 | ARRAY_SIZE(spear310_shirq_blocks), np); | |
349 | } | |
e9c51558 | 350 | IRQCHIP_DECLARE(spear310_shirq, "st,spear310-shirq", spear310_shirq_of_init); |
80515a5a | 351 | |
078bc005 TG |
352 | static int __init spear320_shirq_of_init(struct device_node *np, |
353 | struct device_node *parent) | |
80515a5a SH |
354 | { |
355 | return shirq_init(spear320_shirq_blocks, | |
356 | ARRAY_SIZE(spear320_shirq_blocks), np); | |
4c18e77f | 357 | } |
e9c51558 | 358 | IRQCHIP_DECLARE(spear320_shirq, "st,spear320-shirq", spear320_shirq_of_init); |