[linux-2.6-block.git] / drivers / irqchip / qcom-pdc.c

// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
 */

#include <linux/err.h>
#include <linux/init.h>
#include <linux/irq.h>
#include <linux/irqchip.h>
#include <linux/irqdomain.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_device.h>
#include <linux/spinlock.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/types.h>

#define PDC_MAX_IRQS		126

#define CLEAR_INTR(reg, intr)	(reg & ~(1 << intr))
#define ENABLE_INTR(reg, intr)	(reg | (1 << intr))

#define IRQ_ENABLE_BANK		0x10
#define IRQ_i_CFG		0x110

struct pdc_pin_region {
	u32 pin_base;
	u32 parent_base;
	u32 cnt;
};

static DEFINE_RAW_SPINLOCK(pdc_lock);
static void __iomem *pdc_base;
static struct pdc_pin_region *pdc_region;
static int pdc_region_cnt;

static void pdc_reg_write(int reg, u32 i, u32 val)
{
	writel_relaxed(val, pdc_base + reg + i * sizeof(u32));
}

static u32 pdc_reg_read(int reg, u32 i)
{
	return readl_relaxed(pdc_base + reg + i * sizeof(u32));
}

static void pdc_enable_intr(struct irq_data *d, bool on)
{
	int pin_out = d->hwirq;
	u32 index, mask;
	u32 enable;

	index = pin_out / 32;
	mask = pin_out % 32;

	raw_spin_lock(&pdc_lock);
	enable = pdc_reg_read(IRQ_ENABLE_BANK, index);
	enable = on ? ENABLE_INTR(enable, mask) : CLEAR_INTR(enable, mask);
	pdc_reg_write(IRQ_ENABLE_BANK, index, enable);
	raw_spin_unlock(&pdc_lock);
}

static void qcom_pdc_gic_mask(struct irq_data *d)
{
	pdc_enable_intr(d, false);
	irq_chip_mask_parent(d);
}

static void qcom_pdc_gic_unmask(struct irq_data *d)
{
	pdc_enable_intr(d, true);
	irq_chip_unmask_parent(d);
}

/*
 * GIC does not handle falling edge or active low. To allow falling edge and
 * active low interrupts to be handled at GIC, PDC has an inverter that inverts
 * falling edge into a rising edge and active low into an active high.
 * For the inverter to work, the polarity bit in the IRQ_CONFIG register has to
 * set as per the table below.
 * Level sensitive active low    LOW
 * Rising edge sensitive         NOT USED
 * Falling edge sensitive        LOW
 * Dual Edge sensitive           NOT USED
 * Level sensitive active High   HIGH
 * Falling Edge sensitive        NOT USED
 * Rising edge sensitive         HIGH
 * Dual Edge sensitive           HIGH
 */
enum pdc_irq_config_bits {
	PDC_LEVEL_LOW		= 0b000,
	PDC_EDGE_FALLING	= 0b010,
	PDC_LEVEL_HIGH		= 0b100,
	PDC_EDGE_RISING		= 0b110,
	PDC_EDGE_DUAL		= 0b111,
};

/**
 * qcom_pdc_gic_set_type: Configure PDC for the interrupt
 *
 * @d: the interrupt data
 * @type: the interrupt type
 *
 * If @type is edge triggered, forward that as Rising edge as PDC
 * takes care of converting falling edge to rising edge signal
 * If @type is level, then forward that as level high as PDC
 * takes care of converting falling edge to rising edge signal
 */
static int qcom_pdc_gic_set_type(struct irq_data *d, unsigned int type)
{
	int pin_out = d->hwirq;
	enum pdc_irq_config_bits pdc_type;

	switch (type) {
	case IRQ_TYPE_EDGE_RISING:
		pdc_type = PDC_EDGE_RISING;
		break;
	case IRQ_TYPE_EDGE_FALLING:
		pdc_type = PDC_EDGE_FALLING;
		type = IRQ_TYPE_EDGE_RISING;
		break;
	case IRQ_TYPE_EDGE_BOTH:
		pdc_type = PDC_EDGE_DUAL;
		break;
	case IRQ_TYPE_LEVEL_HIGH:
		pdc_type = PDC_LEVEL_HIGH;
		break;
	case IRQ_TYPE_LEVEL_LOW:
		pdc_type = PDC_LEVEL_LOW;
		type = IRQ_TYPE_LEVEL_HIGH;
		break;
	default:
		WARN_ON(1);
		return -EINVAL;
	}

	pdc_reg_write(IRQ_i_CFG, pin_out, pdc_type);

	return irq_chip_set_type_parent(d, type);
}

static struct irq_chip qcom_pdc_gic_chip = {
	.name			= "PDC",
	.irq_eoi		= irq_chip_eoi_parent,
	.irq_mask		= qcom_pdc_gic_mask,
	.irq_unmask		= qcom_pdc_gic_unmask,
	.irq_retrigger		= irq_chip_retrigger_hierarchy,
	.irq_set_type		= qcom_pdc_gic_set_type,
	.flags			= IRQCHIP_MASK_ON_SUSPEND |
				  IRQCHIP_SET_TYPE_MASKED |
				  IRQCHIP_SKIP_SET_WAKE,
	.irq_set_vcpu_affinity	= irq_chip_set_vcpu_affinity_parent,
	.irq_set_affinity	= irq_chip_set_affinity_parent,
};

static irq_hw_number_t get_parent_hwirq(int pin)
{
	int i;
	struct pdc_pin_region *region;

	for (i = 0; i < pdc_region_cnt; i++) {
		region = &pdc_region[i];
		if (pin >= region->pin_base &&
		    pin < region->pin_base + region->cnt)
			return (region->parent_base + pin - region->pin_base);
	}

	WARN_ON(1);
	return ~0UL;
}

static int qcom_pdc_translate(struct irq_domain *d, struct irq_fwspec *fwspec,
			      unsigned long *hwirq, unsigned int *type)
{
	if (is_of_node(fwspec->fwnode)) {
		if (fwspec->param_count != 2)
			return -EINVAL;

		*hwirq = fwspec->param[0];
		*type = fwspec->param[1] & IRQ_TYPE_SENSE_MASK;
		return 0;
	}

	return -EINVAL;
}

static int qcom_pdc_alloc(struct irq_domain *domain, unsigned int virq,
			  unsigned int nr_irqs, void *data)
{
	struct irq_fwspec *fwspec = data;
	struct irq_fwspec parent_fwspec;
	irq_hw_number_t hwirq, parent_hwirq;
	unsigned int type;
	int ret;

	ret = qcom_pdc_translate(domain, fwspec, &hwirq, &type);
	if (ret)
		return -EINVAL;

	parent_hwirq = get_parent_hwirq(hwirq);
	if (parent_hwirq == ~0UL)
		return -EINVAL;

	ret  = irq_domain_set_hwirq_and_chip(domain, virq, hwirq,
					     &qcom_pdc_gic_chip, NULL);
	if (ret)
		return ret;

	if (type & IRQ_TYPE_EDGE_BOTH)
		type = IRQ_TYPE_EDGE_RISING;

	if (type & IRQ_TYPE_LEVEL_MASK)
		type = IRQ_TYPE_LEVEL_HIGH;

	parent_fwspec.fwnode      = domain->parent->fwnode;
	parent_fwspec.param_count = 3;
	parent_fwspec.param[0]    = 0;
	parent_fwspec.param[1]    = parent_hwirq;
	parent_fwspec.param[2]    = type;

	return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs,
					    &parent_fwspec);
}

static const struct irq_domain_ops qcom_pdc_ops = {
	.translate	= qcom_pdc_translate,
	.alloc		= qcom_pdc_alloc,
	.free		= irq_domain_free_irqs_common,
};

static int pdc_setup_pin_mapping(struct device_node *np)
{
	int ret, n;

	n = of_property_count_elems_of_size(np, "qcom,pdc-ranges", sizeof(u32));
	if (n <= 0 || n % 3)
		return -EINVAL;

	pdc_region_cnt = n / 3;
	pdc_region = kcalloc(pdc_region_cnt, sizeof(*pdc_region), GFP_KERNEL);
	if (!pdc_region) {
		pdc_region_cnt = 0;
		return -ENOMEM;
	}

	for (n = 0; n < pdc_region_cnt; n++) {
		ret = of_property_read_u32_index(np, "qcom,pdc-ranges",
						 n * 3 + 0,
						 &pdc_region[n].pin_base);
		if (ret)
			return ret;
		ret = of_property_read_u32_index(np, "qcom,pdc-ranges",
						 n * 3 + 1,
						 &pdc_region[n].parent_base);
		if (ret)
			return ret;
		ret = of_property_read_u32_index(np, "qcom,pdc-ranges",
						 n * 3 + 2,
						 &pdc_region[n].cnt);
		if (ret)
			return ret;
	}

	return 0;
}

static int qcom_pdc_init(struct device_node *node, struct device_node *parent)
{
	struct irq_domain *parent_domain, *pdc_domain;
	int ret;

	pdc_base = of_iomap(node, 0);
	if (!pdc_base) {
		pr_err("%pOF: unable to map PDC registers\n", node);
		return -ENXIO;
	}

	parent_domain = irq_find_host(parent);
	if (!parent_domain) {
		pr_err("%pOF: unable to find PDC's parent domain\n", node);
		ret = -ENXIO;
		goto fail;
	}

	ret = pdc_setup_pin_mapping(node);
	if (ret) {
		pr_err("%pOF: failed to init PDC pin-hwirq mapping\n", node);
		goto fail;
	}

	pdc_domain = irq_domain_create_hierarchy(parent_domain, 0, PDC_MAX_IRQS,
						 of_fwnode_handle(node),
						 &qcom_pdc_ops, NULL);
	if (!pdc_domain) {
		pr_err("%pOF: GIC domain add failed\n", node);
		ret = -ENOMEM;
		goto fail;
	}

	return 0;

fail:
	kfree(pdc_region);
	iounmap(pdc_base);
	return ret;
}

IRQCHIP_DECLARE(pdc_sdm845, "qcom,sdm845-pdc", qcom_pdc_init);
Commit	Line	Data
f55c73ae AS	1	// SPDX-License-Identifier: GPL-2.0
	2	/*
	3	* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
	4	*/
	5
	6	#include <linux/err.h>
	7	#include <linux/init.h>
	8	#include <linux/irq.h>
	9	#include <linux/irqchip.h>
	10	#include <linux/irqdomain.h>
	11	#include <linux/io.h>
	12	#include <linux/kernel.h>
	13	#include <linux/of.h>
	14	#include <linux/of_address.h>
	15	#include <linux/of_device.h>
	16	#include <linux/spinlock.h>
	17	#include <linux/platform_device.h>
	18	#include <linux/slab.h>
	19	#include <linux/types.h>
	20
	21	#define PDC_MAX_IRQS 126
	22
	23	#define CLEAR_INTR(reg, intr) (reg & ~(1 << intr))
	24	#define ENABLE_INTR(reg, intr) (reg \| (1 << intr))
	25
	26	#define IRQ_ENABLE_BANK 0x10
	27	#define IRQ_i_CFG 0x110
	28
	29	struct pdc_pin_region {
	30	u32 pin_base;
	31	u32 parent_base;
	32	u32 cnt;
	33	};
	34
	35	static DEFINE_RAW_SPINLOCK(pdc_lock);
	36	static void __iomem *pdc_base;
	37	static struct pdc_pin_region *pdc_region;
	38	static int pdc_region_cnt;
	39
	40	static void pdc_reg_write(int reg, u32 i, u32 val)
	41	{
	42	writel_relaxed(val, pdc_base + reg + i * sizeof(u32));
	43	}
	44
	45	static u32 pdc_reg_read(int reg, u32 i)
	46	{
	47	return readl_relaxed(pdc_base + reg + i * sizeof(u32));
	48	}
	49
	50	static void pdc_enable_intr(struct irq_data *d, bool on)
	51	{
	52	int pin_out = d->hwirq;
	53	u32 index, mask;
	54	u32 enable;
	55
	56	index = pin_out / 32;
	57	mask = pin_out % 32;
	58
	59	raw_spin_lock(&pdc_lock);
	60	enable = pdc_reg_read(IRQ_ENABLE_BANK, index);
	61	enable = on ? ENABLE_INTR(enable, mask) : CLEAR_INTR(enable, mask);
	62	pdc_reg_write(IRQ_ENABLE_BANK, index, enable);
	63	raw_spin_unlock(&pdc_lock);
	64	}
65
66	static void qcom_pdc_gic_mask(struct irq_data *d)
67	{
68	pdc_enable_intr(d, false);
69	irq_chip_mask_parent(d);
70	}
71
72	static void qcom_pdc_gic_unmask(struct irq_data *d)
73	{
74	pdc_enable_intr(d, true);
75	irq_chip_unmask_parent(d);
76	}
77
78	/*
79	* GIC does not handle falling edge or active low. To allow falling edge and
80	* active low interrupts to be handled at GIC, PDC has an inverter that inverts
81	* falling edge into a rising edge and active low into an active high.
82	* For the inverter to work, the polarity bit in the IRQ_CONFIG register has to
83	* set as per the table below.
84	* Level sensitive active low LOW
85	* Rising edge sensitive NOT USED
86	* Falling edge sensitive LOW
87	* Dual Edge sensitive NOT USED
88	* Level sensitive active High HIGH
89	* Falling Edge sensitive NOT USED
90	* Rising edge sensitive HIGH
91	* Dual Edge sensitive HIGH
92	*/
93	enum pdc_irq_config_bits {
94	PDC_LEVEL_LOW = 0b000,
95	PDC_EDGE_FALLING = 0b010,
96	PDC_LEVEL_HIGH = 0b100,
97	PDC_EDGE_RISING = 0b110,
98	PDC_EDGE_DUAL = 0b111,
99	};
100
101	/**
102	* qcom_pdc_gic_set_type: Configure PDC for the interrupt
103	*
104	* @d: the interrupt data
105	* @type: the interrupt type
106	*
107	* If @type is edge triggered, forward that as Rising edge as PDC
108	* takes care of converting falling edge to rising edge signal
109	* If @type is level, then forward that as level high as PDC
110	* takes care of converting falling edge to rising edge signal
111	*/
112	static int qcom_pdc_gic_set_type(struct irq_data *d, unsigned int type)
113	{
114	int pin_out = d->hwirq;
115	enum pdc_irq_config_bits pdc_type;
116
117	switch (type) {
118	case IRQ_TYPE_EDGE_RISING:
119	pdc_type = PDC_EDGE_RISING;
120	break;
121	case IRQ_TYPE_EDGE_FALLING:
122	pdc_type = PDC_EDGE_FALLING;
123	type = IRQ_TYPE_EDGE_RISING;
124	break;
125	case IRQ_TYPE_EDGE_BOTH:
126	pdc_type = PDC_EDGE_DUAL;
127	break;
128	case IRQ_TYPE_LEVEL_HIGH:
129	pdc_type = PDC_LEVEL_HIGH;
130	break;
131	case IRQ_TYPE_LEVEL_LOW:
132	pdc_type = PDC_LEVEL_LOW;
133	type = IRQ_TYPE_LEVEL_HIGH;
134	break;
135	default:
136	WARN_ON(1);
137	return -EINVAL;
138	}
139
140	pdc_reg_write(IRQ_i_CFG, pin_out, pdc_type);
141
142	return irq_chip_set_type_parent(d, type);
143	}
144
145	static struct irq_chip qcom_pdc_gic_chip = {
146	.name = "PDC",
147	.irq_eoi = irq_chip_eoi_parent,
148	.irq_mask = qcom_pdc_gic_mask,
149	.irq_unmask = qcom_pdc_gic_unmask,
150	.irq_retrigger = irq_chip_retrigger_hierarchy,
151	.irq_set_type = qcom_pdc_gic_set_type,
152	.flags = IRQCHIP_MASK_ON_SUSPEND \|
153	IRQCHIP_SET_TYPE_MASKED \|
154	IRQCHIP_SKIP_SET_WAKE,
155	.irq_set_vcpu_affinity = irq_chip_set_vcpu_affinity_parent,
156	.irq_set_affinity = irq_chip_set_affinity_parent,
157	};
158
159	static irq_hw_number_t get_parent_hwirq(int pin)
160	{
161	int i;
162	struct pdc_pin_region *region;
163
164	for (i = 0; i < pdc_region_cnt; i++) {
165	region = &pdc_region[i];
166	if (pin >= region->pin_base &&
167	pin < region->pin_base + region->cnt)
168	return (region->parent_base + pin - region->pin_base);
169	}
170
171	WARN_ON(1);
172	return ~0UL;
173	}
174
175	static int qcom_pdc_translate(struct irq_domain d, struct irq_fwspec fwspec,
176	unsigned long hwirq, unsigned int type)
177	{
178	if (is_of_node(fwspec->fwnode)) {
179	if (fwspec->param_count != 2)
180	return -EINVAL;
181
182	*hwirq = fwspec->param[0];
183	*type = fwspec->param[1] & IRQ_TYPE_SENSE_MASK;
184	return 0;
185	}
186
187	return -EINVAL;
188	}
189
190	static int qcom_pdc_alloc(struct irq_domain *domain, unsigned int virq,
191	unsigned int nr_irqs, void *data)
192	{
193	struct irq_fwspec *fwspec = data;
194	struct irq_fwspec parent_fwspec;
195	irq_hw_number_t hwirq, parent_hwirq;
196	unsigned int type;
197	int ret;
198
199	ret = qcom_pdc_translate(domain, fwspec, &hwirq, &type);
200	if (ret)
201	return -EINVAL;
202
203	parent_hwirq = get_parent_hwirq(hwirq);
204	if (parent_hwirq == ~0UL)
205	return -EINVAL;
206
207	ret = irq_domain_set_hwirq_and_chip(domain, virq, hwirq,
208	&qcom_pdc_gic_chip, NULL);
209	if (ret)
210	return ret;
211
212	if (type & IRQ_TYPE_EDGE_BOTH)
213	type = IRQ_TYPE_EDGE_RISING;
214
215	if (type & IRQ_TYPE_LEVEL_MASK)
216	type = IRQ_TYPE_LEVEL_HIGH;
217
218	parent_fwspec.fwnode = domain->parent->fwnode;
219	parent_fwspec.param_count = 3;
220	parent_fwspec.param[0] = 0;
221	parent_fwspec.param[1] = parent_hwirq;
222	parent_fwspec.param[2] = type;
223
224	return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs,
225	&parent_fwspec);
226	}
227
228	static const struct irq_domain_ops qcom_pdc_ops = {
229	.translate = qcom_pdc_translate,
230	.alloc = qcom_pdc_alloc,
231	.free = irq_domain_free_irqs_common,
232	};
233
234	static int pdc_setup_pin_mapping(struct device_node *np)
235	{
236	int ret, n;
237
238	n = of_property_count_elems_of_size(np, "qcom,pdc-ranges", sizeof(u32));
239	if (n <= 0 \|\| n % 3)
240	return -EINVAL;
241
242	pdc_region_cnt = n / 3;
243	pdc_region = kcalloc(pdc_region_cnt, sizeof(*pdc_region), GFP_KERNEL);
244	if (!pdc_region) {
245	pdc_region_cnt = 0;
246	return -ENOMEM;
247	}
248
249	for (n = 0; n < pdc_region_cnt; n++) {
250	ret = of_property_read_u32_index(np, "qcom,pdc-ranges",
251	n * 3 + 0,
252	&pdc_region[n].pin_base);
253	if (ret)
254	return ret;
255	ret = of_property_read_u32_index(np, "qcom,pdc-ranges",
256	n * 3 + 1,
257	&pdc_region[n].parent_base);
258	if (ret)
259	return ret;
260	ret = of_property_read_u32_index(np, "qcom,pdc-ranges",
261	n * 3 + 2,
262	&pdc_region[n].cnt);
263	if (ret)
264	return ret;
265	}
266
267	return 0;
268	}
269
270	static int qcom_pdc_init(struct device_node node, struct device_node parent)
271	{
272	struct irq_domain parent_domain, pdc_domain;
273	int ret;
274
275	pdc_base = of_iomap(node, 0);
276	if (!pdc_base) {
277	pr_err("%pOF: unable to map PDC registers\n", node);
278	return -ENXIO;
279	}
280
281	parent_domain = irq_find_host(parent);
282	if (!parent_domain) {
283	pr_err("%pOF: unable to find PDC's parent domain\n", node);
284	ret = -ENXIO;
285	goto fail;
286	}
287
288	ret = pdc_setup_pin_mapping(node);
289	if (ret) {
290	pr_err("%pOF: failed to init PDC pin-hwirq mapping\n", node);
291	goto fail;
292	}
293
294	pdc_domain = irq_domain_create_hierarchy(parent_domain, 0, PDC_MAX_IRQS,
295	of_fwnode_handle(node),
296	&qcom_pdc_ops, NULL);
297	if (!pdc_domain) {
298	pr_err("%pOF: GIC domain add failed\n", node);
299	ret = -ENOMEM;
300	goto fail;
301	}
302
303	return 0;
304
305	fail:
306	kfree(pdc_region);
307	iounmap(pdc_base);
308	return ret;
309	}
310
311	IRQCHIP_DECLARE(pdc_sdm845, "qcom,sdm845-pdc", qcom_pdc_init);