[linux-2.6-block.git] / drivers / irqchip / irq-xtensa-pic.c

/*
 * Xtensa built-in interrupt controller
 *
 * Copyright (C) 2002 - 2013 Tensilica, Inc.
 * Copyright (C) 1992, 1998 Linus Torvalds, Ingo Molnar
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Chris Zankel <chris@zankel.net>
 * Kevin Chea
 */

#include <linux/interrupt.h>
#include <linux/irqdomain.h>
#include <linux/irq.h>
#include <linux/irqchip.h>
#include <linux/of.h>

unsigned int cached_irq_mask;

/*
 * Device Tree IRQ specifier translation function which works with one or
 * two cell bindings. First cell value maps directly to the hwirq number.
 * Second cell if present specifies whether hwirq number is external (1) or
 * internal (0).
 */
static int xtensa_pic_irq_domain_xlate(struct irq_domain *d,
		struct device_node *ctrlr,
		const u32 *intspec, unsigned int intsize,
		unsigned long *out_hwirq, unsigned int *out_type)
{
	return xtensa_irq_domain_xlate(intspec, intsize,
			intspec[0], intspec[0],
			out_hwirq, out_type);
}

static const struct irq_domain_ops xtensa_irq_domain_ops = {
	.xlate = xtensa_pic_irq_domain_xlate,
	.map = xtensa_irq_map,
};

static void xtensa_irq_mask(struct irq_data *d)
{
	cached_irq_mask &= ~(1 << d->hwirq);
	xtensa_set_sr(cached_irq_mask, intenable);
}

static void xtensa_irq_unmask(struct irq_data *d)
{
	cached_irq_mask |= 1 << d->hwirq;
	xtensa_set_sr(cached_irq_mask, intenable);
}

static void xtensa_irq_enable(struct irq_data *d)
{
	xtensa_irq_unmask(d);
}

static void xtensa_irq_disable(struct irq_data *d)
{
	xtensa_irq_mask(d);
}

static void xtensa_irq_ack(struct irq_data *d)
{
	xtensa_set_sr(1 << d->hwirq, intclear);
}

static int xtensa_irq_retrigger(struct irq_data *d)
{
	unsigned int mask = 1u << d->hwirq;

	if (WARN_ON(mask & ~XCHAL_INTTYPE_MASK_SOFTWARE))
		return 0;
	xtensa_set_sr(mask, intset);
	return 1;
}

static struct irq_chip xtensa_irq_chip = {
	.name		= "xtensa",
	.irq_enable	= xtensa_irq_enable,
	.irq_disable	= xtensa_irq_disable,
	.irq_mask	= xtensa_irq_mask,
	.irq_unmask	= xtensa_irq_unmask,
	.irq_ack	= xtensa_irq_ack,
	.irq_retrigger	= xtensa_irq_retrigger,
};

int __init xtensa_pic_init_legacy(struct device_node *interrupt_parent)
{
	struct irq_domain *root_domain =
		irq_domain_add_legacy(NULL, NR_IRQS - 1, 1, 0,
				&xtensa_irq_domain_ops, &xtensa_irq_chip);
	irq_set_default_host(root_domain);
	return 0;
}

static int __init xtensa_pic_init(struct device_node *np,
		struct device_node *interrupt_parent)
{
	struct irq_domain *root_domain =
		irq_domain_add_linear(np, NR_IRQS, &xtensa_irq_domain_ops,
				&xtensa_irq_chip);
	irq_set_default_host(root_domain);
	return 0;
}
IRQCHIP_DECLARE(xtensa_irq_chip, "cdns,xtensa-pic", xtensa_pic_init);
Commit	Line	Data
cbd1de2e MF	1	/*
	2	* Xtensa built-in interrupt controller
	3	*
	4	* Copyright (C) 2002 - 2013 Tensilica, Inc.
	5	* Copyright (C) 1992, 1998 Linus Torvalds, Ingo Molnar
	6	*
	7	* This file is subject to the terms and conditions of the GNU General Public
	8	* License. See the file "COPYING" in the main directory of this archive
	9	* for more details.
	10	*
	11	* Chris Zankel <chris@zankel.net>
	12	* Kevin Chea
	13	*/
	14
	15	#include <linux/interrupt.h>
	16	#include <linux/irqdomain.h>
	17	#include <linux/irq.h>
41a83e06	18	#include <linux/irqchip.h>
cbd1de2e MF	19	#include <linux/of.h>
cbd1de2e MF	20
cbd1de2e MF	21	unsigned int cached_irq_mask;
	22
	23	/*
	24	* Device Tree IRQ specifier translation function which works with one or
	25	* two cell bindings. First cell value maps directly to the hwirq number.
	26	* Second cell if present specifies whether hwirq number is external (1) or
	27	* internal (0).
	28	*/
	29	static int xtensa_pic_irq_domain_xlate(struct irq_domain *d,
	30	struct device_node *ctrlr,
	31	const u32 *intspec, unsigned int intsize,
	32	unsigned long out_hwirq, unsigned int out_type)
	33	{
	34	return xtensa_irq_domain_xlate(intspec, intsize,
	35	intspec[0], intspec[0],
	36	out_hwirq, out_type);
	37	}
	38
	39	static const struct irq_domain_ops xtensa_irq_domain_ops = {
	40	.xlate = xtensa_pic_irq_domain_xlate,
	41	.map = xtensa_irq_map,
	42	};
	43
	44	static void xtensa_irq_mask(struct irq_data *d)
	45	{
	46	cached_irq_mask &= ~(1 << d->hwirq);
cad6fade	47	xtensa_set_sr(cached_irq_mask, intenable);
cbd1de2e MF	48	}
	49
	50	static void xtensa_irq_unmask(struct irq_data *d)
	51	{
	52	cached_irq_mask \|= 1 << d->hwirq;
cad6fade	53	xtensa_set_sr(cached_irq_mask, intenable);
cbd1de2e MF	54	}
	55
	56	static void xtensa_irq_enable(struct irq_data *d)
	57	{
cbd1de2e MF	58	xtensa_irq_unmask(d);
	59	}
	60
	61	static void xtensa_irq_disable(struct irq_data *d)
	62	{
	63	xtensa_irq_mask(d);
cbd1de2e MF	64	}
	65
	66	static void xtensa_irq_ack(struct irq_data *d)
	67	{
cad6fade	68	xtensa_set_sr(1 << d->hwirq, intclear);
cbd1de2e MF	69	}
	70
	71	static int xtensa_irq_retrigger(struct irq_data *d)
	72	{
bb665236 MF	73	unsigned int mask = 1u << d->hwirq;
	74
	75	if (WARN_ON(mask & ~XCHAL_INTTYPE_MASK_SOFTWARE))
	76	return 0;
	77	xtensa_set_sr(mask, intset);
cbd1de2e MF	78	return 1;
	79	}
	80
	81	static struct irq_chip xtensa_irq_chip = {
	82	.name = "xtensa",
	83	.irq_enable = xtensa_irq_enable,
	84	.irq_disable = xtensa_irq_disable,
	85	.irq_mask = xtensa_irq_mask,
	86	.irq_unmask = xtensa_irq_unmask,
	87	.irq_ack = xtensa_irq_ack,
	88	.irq_retrigger = xtensa_irq_retrigger,
	89	};
	90
	91	int __init xtensa_pic_init_legacy(struct device_node *interrupt_parent)
	92	{
	93	struct irq_domain *root_domain =
e5c86679	94	irq_domain_add_legacy(NULL, NR_IRQS - 1, 1, 0,
cbd1de2e MF	95	&xtensa_irq_domain_ops, &xtensa_irq_chip);
	96	irq_set_default_host(root_domain);
	97	return 0;
	98	}
	99
	100	static int __init xtensa_pic_init(struct device_node *np,
	101	struct device_node *interrupt_parent)
	102	{
	103	struct irq_domain *root_domain =
	104	irq_domain_add_linear(np, NR_IRQS, &xtensa_irq_domain_ops,
	105	&xtensa_irq_chip);
	106	irq_set_default_host(root_domain);
	107	return 0;
	108	}
	109	IRQCHIP_DECLARE(xtensa_irq_chip, "cdns,xtensa-pic", xtensa_pic_init);