Commit | Line | Data |
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eedbdab9 | 1 | /* |
968674bd MS |
2 | * Copyright (C) 2007-2013 Michal Simek <monstr@monstr.eu> |
3 | * Copyright (C) 2012-2013 Xilinx, Inc. | |
eedbdab9 MS |
4 | * Copyright (C) 2007-2009 PetaLogix |
5 | * Copyright (C) 2006 Atmark Techno, Inc. | |
6 | * | |
7 | * This file is subject to the terms and conditions of the GNU General Public | |
8 | * License. See the file "COPYING" in the main directory of this archive | |
9 | * for more details. | |
10 | */ | |
11 | ||
2462bacd | 12 | #include <linux/irqdomain.h> |
eedbdab9 | 13 | #include <linux/irq.h> |
fd4b267b | 14 | #include <linux/irqchip.h> |
bcff661d | 15 | #include <linux/of_address.h> |
eedbdab9 | 16 | #include <linux/io.h> |
892ee92b | 17 | #include <linux/bug.h> |
eedbdab9 | 18 | |
bcff661d | 19 | static void __iomem *intc_baseaddr; |
eedbdab9 | 20 | |
eedbdab9 MS |
21 | /* No one else should require these constants, so define them locally here. */ |
22 | #define ISR 0x00 /* Interrupt Status Register */ | |
23 | #define IPR 0x04 /* Interrupt Pending Register */ | |
24 | #define IER 0x08 /* Interrupt Enable Register */ | |
25 | #define IAR 0x0c /* Interrupt Acknowledge Register */ | |
26 | #define SIE 0x10 /* Set Interrupt Enable bits */ | |
27 | #define CIE 0x14 /* Clear Interrupt Enable bits */ | |
28 | #define IVR 0x18 /* Interrupt Vector Register */ | |
29 | #define MER 0x1c /* Master Enable Register */ | |
30 | ||
31 | #define MER_ME (1<<0) | |
32 | #define MER_HIE (1<<1) | |
33 | ||
1aa1243c MS |
34 | static unsigned int (*read_fn)(void __iomem *); |
35 | static void (*write_fn)(u32, void __iomem *); | |
36 | ||
37 | static void intc_write32(u32 val, void __iomem *addr) | |
38 | { | |
39 | iowrite32(val, addr); | |
40 | } | |
41 | ||
42 | static unsigned int intc_read32(void __iomem *addr) | |
43 | { | |
44 | return ioread32(addr); | |
45 | } | |
46 | ||
47 | static void intc_write32_be(u32 val, void __iomem *addr) | |
48 | { | |
49 | iowrite32be(val, addr); | |
50 | } | |
51 | ||
52 | static unsigned int intc_read32_be(void __iomem *addr) | |
53 | { | |
54 | return ioread32be(addr); | |
55 | } | |
56 | ||
6f205a4c | 57 | static void intc_enable_or_unmask(struct irq_data *d) |
eedbdab9 | 58 | { |
6c7a2676 MS |
59 | unsigned long mask = 1 << d->hwirq; |
60 | ||
a5734de2 | 61 | pr_debug("irq-xilinx: enable_or_unmask: %ld\n", d->hwirq); |
33d9ff59 | 62 | |
63 | /* ack level irqs because they can't be acked during | |
64 | * ack function since the handle_level_irq function | |
65 | * acks the irq before calling the interrupt handler | |
66 | */ | |
4adc192e | 67 | if (irqd_is_level_type(d)) |
1aa1243c | 68 | write_fn(mask, intc_baseaddr + IAR); |
7958a689 | 69 | |
1aa1243c | 70 | write_fn(mask, intc_baseaddr + SIE); |
eedbdab9 MS |
71 | } |
72 | ||
6f205a4c | 73 | static void intc_disable_or_mask(struct irq_data *d) |
eedbdab9 | 74 | { |
a5734de2 | 75 | pr_debug("irq-xilinx: disable: %ld\n", d->hwirq); |
1aa1243c | 76 | write_fn(1 << d->hwirq, intc_baseaddr + CIE); |
eedbdab9 MS |
77 | } |
78 | ||
6f205a4c | 79 | static void intc_ack(struct irq_data *d) |
eedbdab9 | 80 | { |
a5734de2 | 81 | pr_debug("irq-xilinx: ack: %ld\n", d->hwirq); |
1aa1243c | 82 | write_fn(1 << d->hwirq, intc_baseaddr + IAR); |
eedbdab9 MS |
83 | } |
84 | ||
6f205a4c | 85 | static void intc_mask_ack(struct irq_data *d) |
eedbdab9 | 86 | { |
6c7a2676 MS |
87 | unsigned long mask = 1 << d->hwirq; |
88 | ||
a5734de2 | 89 | pr_debug("irq-xilinx: disable_and_ack: %ld\n", d->hwirq); |
1aa1243c MS |
90 | write_fn(mask, intc_baseaddr + CIE); |
91 | write_fn(mask, intc_baseaddr + IAR); | |
eedbdab9 MS |
92 | } |
93 | ||
eedbdab9 MS |
94 | static struct irq_chip intc_dev = { |
95 | .name = "Xilinx INTC", | |
6f205a4c TG |
96 | .irq_unmask = intc_enable_or_unmask, |
97 | .irq_mask = intc_disable_or_mask, | |
98 | .irq_ack = intc_ack, | |
99 | .irq_mask_ack = intc_mask_ack, | |
eedbdab9 MS |
100 | }; |
101 | ||
2462bacd GL |
102 | static struct irq_domain *root_domain; |
103 | ||
104 | unsigned int get_irq(void) | |
eedbdab9 | 105 | { |
2462bacd | 106 | unsigned int hwirq, irq = -1; |
eedbdab9 | 107 | |
1aa1243c | 108 | hwirq = read_fn(intc_baseaddr + IVR); |
2462bacd GL |
109 | if (hwirq != -1U) |
110 | irq = irq_find_mapping(root_domain, hwirq); | |
111 | ||
a5734de2 | 112 | pr_debug("irq-xilinx: hwirq=%d, irq=%d\n", hwirq, irq); |
eedbdab9 MS |
113 | |
114 | return irq; | |
115 | } | |
116 | ||
c0d997fb | 117 | static int xintc_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw) |
2462bacd GL |
118 | { |
119 | u32 intr_mask = (u32)d->host_data; | |
120 | ||
121 | if (intr_mask & (1 << hw)) { | |
122 | irq_set_chip_and_handler_name(irq, &intc_dev, | |
123 | handle_edge_irq, "edge"); | |
124 | irq_clear_status_flags(irq, IRQ_LEVEL); | |
125 | } else { | |
126 | irq_set_chip_and_handler_name(irq, &intc_dev, | |
127 | handle_level_irq, "level"); | |
128 | irq_set_status_flags(irq, IRQ_LEVEL); | |
129 | } | |
130 | return 0; | |
131 | } | |
132 | ||
133 | static const struct irq_domain_ops xintc_irq_domain_ops = { | |
134 | .xlate = irq_domain_xlate_onetwocell, | |
135 | .map = xintc_map, | |
136 | }; | |
137 | ||
8a9e90a1 MS |
138 | static int __init xilinx_intc_of_init(struct device_node *intc, |
139 | struct device_node *parent) | |
eedbdab9 | 140 | { |
2462bacd | 141 | u32 nr_irq, intr_mask; |
bcff661d | 142 | int ret; |
eedbdab9 | 143 | |
bcff661d MS |
144 | intc_baseaddr = of_iomap(intc, 0); |
145 | BUG_ON(!intc_baseaddr); | |
146 | ||
147 | ret = of_property_read_u32(intc, "xlnx,num-intr-inputs", &nr_irq); | |
148 | if (ret < 0) { | |
a5734de2 | 149 | pr_err("irq-xilinx: unable to read xlnx,num-intr-inputs\n"); |
2c80a072 | 150 | return ret; |
bcff661d MS |
151 | } |
152 | ||
153 | ret = of_property_read_u32(intc, "xlnx,kind-of-intr", &intr_mask); | |
154 | if (ret < 0) { | |
a5734de2 | 155 | pr_err("irq-xilinx: unable to read xlnx,kind-of-intr\n"); |
2c80a072 | 156 | return ret; |
bcff661d | 157 | } |
eedbdab9 | 158 | |
d50466c9 | 159 | if (intr_mask >> nr_irq) |
a5734de2 | 160 | pr_warn("irq-xilinx: mismatch in kind-of-intr param\n"); |
eedbdab9 | 161 | |
a5734de2 | 162 | pr_info("irq-xilinx: %s: num_irq=%d, edge=0x%x\n", |
bcff661d | 163 | intc->full_name, nr_irq, intr_mask); |
eedbdab9 | 164 | |
1aa1243c MS |
165 | write_fn = intc_write32; |
166 | read_fn = intc_read32; | |
167 | ||
eedbdab9 MS |
168 | /* |
169 | * Disable all external interrupts until they are | |
170 | * explicity requested. | |
171 | */ | |
1aa1243c | 172 | write_fn(0, intc_baseaddr + IER); |
eedbdab9 MS |
173 | |
174 | /* Acknowledge any pending interrupts just in case. */ | |
1aa1243c | 175 | write_fn(0xffffffff, intc_baseaddr + IAR); |
eedbdab9 MS |
176 | |
177 | /* Turn on the Master Enable. */ | |
1aa1243c MS |
178 | write_fn(MER_HIE | MER_ME, intc_baseaddr + MER); |
179 | if (!(read_fn(intc_baseaddr + MER) & (MER_HIE | MER_ME))) { | |
180 | write_fn = intc_write32_be; | |
181 | read_fn = intc_read32_be; | |
182 | write_fn(MER_HIE | MER_ME, intc_baseaddr + MER); | |
183 | } | |
eedbdab9 | 184 | |
2462bacd GL |
185 | /* Yeah, okay, casting the intr_mask to a void* is butt-ugly, but I'm |
186 | * lazy and Michal can clean it up to something nicer when he tests | |
187 | * and commits this patch. ~~gcl */ | |
188 | root_domain = irq_domain_add_linear(intc, nr_irq, &xintc_irq_domain_ops, | |
189 | (void *)intr_mask); | |
7c2c8513 DC |
190 | |
191 | irq_set_default_host(root_domain); | |
8a9e90a1 MS |
192 | |
193 | return 0; | |
eedbdab9 | 194 | } |
8a9e90a1 MS |
195 | |
196 | IRQCHIP_DECLARE(xilinx_intc, "xlnx,xps-intc-1.00.a", xilinx_intc_of_init); |