Commit | Line | Data |
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eedbdab9 | 1 | /* |
968674bd MS |
2 | * Copyright (C) 2007-2013 Michal Simek <monstr@monstr.eu> |
3 | * Copyright (C) 2012-2013 Xilinx, Inc. | |
eedbdab9 MS |
4 | * Copyright (C) 2007-2009 PetaLogix |
5 | * Copyright (C) 2006 Atmark Techno, Inc. | |
6 | * | |
7 | * This file is subject to the terms and conditions of the GNU General Public | |
8 | * License. See the file "COPYING" in the main directory of this archive | |
9 | * for more details. | |
10 | */ | |
11 | ||
2462bacd | 12 | #include <linux/irqdomain.h> |
eedbdab9 | 13 | #include <linux/irq.h> |
fd4b267b | 14 | #include <linux/irqchip.h> |
9689c99e | 15 | #include <linux/irqchip/chained_irq.h> |
bcff661d | 16 | #include <linux/of_address.h> |
eedbdab9 | 17 | #include <linux/io.h> |
591db74b | 18 | #include <linux/jump_label.h> |
892ee92b | 19 | #include <linux/bug.h> |
9689c99e | 20 | #include <linux/of_irq.h> |
eedbdab9 | 21 | |
eedbdab9 MS |
22 | /* No one else should require these constants, so define them locally here. */ |
23 | #define ISR 0x00 /* Interrupt Status Register */ | |
24 | #define IPR 0x04 /* Interrupt Pending Register */ | |
25 | #define IER 0x08 /* Interrupt Enable Register */ | |
26 | #define IAR 0x0c /* Interrupt Acknowledge Register */ | |
27 | #define SIE 0x10 /* Set Interrupt Enable bits */ | |
28 | #define CIE 0x14 /* Clear Interrupt Enable bits */ | |
29 | #define IVR 0x18 /* Interrupt Vector Register */ | |
30 | #define MER 0x1c /* Master Enable Register */ | |
31 | ||
32 | #define MER_ME (1<<0) | |
33 | #define MER_HIE (1<<1) | |
34 | ||
591db74b | 35 | static DEFINE_STATIC_KEY_FALSE(xintc_is_be); |
1aa1243c | 36 | |
591db74b ZLK |
37 | struct xintc_irq_chip { |
38 | void __iomem *base; | |
39 | struct irq_domain *root_domain; | |
40 | u32 intr_mask; | |
67862a3c | 41 | u32 nr_irq; |
591db74b | 42 | }; |
1aa1243c | 43 | |
67862a3c | 44 | static struct xintc_irq_chip *primary_intc; |
1aa1243c | 45 | |
67862a3c | 46 | static void xintc_write(struct xintc_irq_chip *irqc, int reg, u32 data) |
1aa1243c | 47 | { |
591db74b | 48 | if (static_branch_unlikely(&xintc_is_be)) |
67862a3c | 49 | iowrite32be(data, irqc->base + reg); |
591db74b | 50 | else |
67862a3c | 51 | iowrite32(data, irqc->base + reg); |
1aa1243c MS |
52 | } |
53 | ||
67862a3c | 54 | static u32 xintc_read(struct xintc_irq_chip *irqc, int reg) |
1aa1243c | 55 | { |
591db74b | 56 | if (static_branch_unlikely(&xintc_is_be)) |
67862a3c | 57 | return ioread32be(irqc->base + reg); |
591db74b | 58 | else |
67862a3c | 59 | return ioread32(irqc->base + reg); |
1aa1243c MS |
60 | } |
61 | ||
6f205a4c | 62 | static void intc_enable_or_unmask(struct irq_data *d) |
eedbdab9 | 63 | { |
67862a3c MS |
64 | struct xintc_irq_chip *irqc = irq_data_get_irq_chip_data(d); |
65 | unsigned long mask = BIT(d->hwirq); | |
6c7a2676 | 66 | |
a5734de2 | 67 | pr_debug("irq-xilinx: enable_or_unmask: %ld\n", d->hwirq); |
33d9ff59 | 68 | |
69 | /* ack level irqs because they can't be acked during | |
70 | * ack function since the handle_level_irq function | |
71 | * acks the irq before calling the interrupt handler | |
72 | */ | |
4adc192e | 73 | if (irqd_is_level_type(d)) |
67862a3c | 74 | xintc_write(irqc, IAR, mask); |
7958a689 | 75 | |
67862a3c | 76 | xintc_write(irqc, SIE, mask); |
eedbdab9 MS |
77 | } |
78 | ||
6f205a4c | 79 | static void intc_disable_or_mask(struct irq_data *d) |
eedbdab9 | 80 | { |
67862a3c MS |
81 | struct xintc_irq_chip *irqc = irq_data_get_irq_chip_data(d); |
82 | ||
a5734de2 | 83 | pr_debug("irq-xilinx: disable: %ld\n", d->hwirq); |
67862a3c | 84 | xintc_write(irqc, CIE, BIT(d->hwirq)); |
eedbdab9 MS |
85 | } |
86 | ||
6f205a4c | 87 | static void intc_ack(struct irq_data *d) |
eedbdab9 | 88 | { |
67862a3c MS |
89 | struct xintc_irq_chip *irqc = irq_data_get_irq_chip_data(d); |
90 | ||
a5734de2 | 91 | pr_debug("irq-xilinx: ack: %ld\n", d->hwirq); |
67862a3c | 92 | xintc_write(irqc, IAR, BIT(d->hwirq)); |
eedbdab9 MS |
93 | } |
94 | ||
6f205a4c | 95 | static void intc_mask_ack(struct irq_data *d) |
eedbdab9 | 96 | { |
67862a3c MS |
97 | struct xintc_irq_chip *irqc = irq_data_get_irq_chip_data(d); |
98 | unsigned long mask = BIT(d->hwirq); | |
6c7a2676 | 99 | |
a5734de2 | 100 | pr_debug("irq-xilinx: disable_and_ack: %ld\n", d->hwirq); |
67862a3c MS |
101 | xintc_write(irqc, CIE, mask); |
102 | xintc_write(irqc, IAR, mask); | |
eedbdab9 MS |
103 | } |
104 | ||
eedbdab9 MS |
105 | static struct irq_chip intc_dev = { |
106 | .name = "Xilinx INTC", | |
6f205a4c TG |
107 | .irq_unmask = intc_enable_or_unmask, |
108 | .irq_mask = intc_disable_or_mask, | |
109 | .irq_ack = intc_ack, | |
110 | .irq_mask_ack = intc_mask_ack, | |
eedbdab9 MS |
111 | }; |
112 | ||
67862a3c MS |
113 | static unsigned int xintc_get_irq_local(struct xintc_irq_chip *irqc) |
114 | { | |
115 | unsigned int irq = 0; | |
116 | u32 hwirq; | |
117 | ||
118 | hwirq = xintc_read(irqc, IVR); | |
119 | if (hwirq != -1U) | |
120 | irq = irq_find_mapping(irqc->root_domain, hwirq); | |
121 | ||
122 | pr_debug("irq-xilinx: hwirq=%d, irq=%d\n", hwirq, irq); | |
123 | ||
124 | return irq; | |
125 | } | |
126 | ||
c0d997fb | 127 | static int xintc_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw) |
2462bacd | 128 | { |
67862a3c MS |
129 | struct xintc_irq_chip *irqc = d->host_data; |
130 | ||
131 | if (irqc->intr_mask & BIT(hw)) { | |
2462bacd | 132 | irq_set_chip_and_handler_name(irq, &intc_dev, |
67862a3c | 133 | handle_edge_irq, "edge"); |
2462bacd GL |
134 | irq_clear_status_flags(irq, IRQ_LEVEL); |
135 | } else { | |
136 | irq_set_chip_and_handler_name(irq, &intc_dev, | |
67862a3c | 137 | handle_level_irq, "level"); |
2462bacd GL |
138 | irq_set_status_flags(irq, IRQ_LEVEL); |
139 | } | |
67862a3c | 140 | irq_set_chip_data(irq, irqc); |
2462bacd GL |
141 | return 0; |
142 | } | |
143 | ||
144 | static const struct irq_domain_ops xintc_irq_domain_ops = { | |
145 | .xlate = irq_domain_xlate_onetwocell, | |
146 | .map = xintc_map, | |
147 | }; | |
148 | ||
9689c99e ZLK |
149 | static void xil_intc_irq_handler(struct irq_desc *desc) |
150 | { | |
151 | struct irq_chip *chip = irq_desc_get_chip(desc); | |
67862a3c | 152 | struct xintc_irq_chip *irqc; |
9689c99e ZLK |
153 | u32 pending; |
154 | ||
67862a3c | 155 | irqc = irq_data_get_irq_handler_data(&desc->irq_data); |
9689c99e ZLK |
156 | chained_irq_enter(chip, desc); |
157 | do { | |
67862a3c MS |
158 | pending = xintc_get_irq_local(irqc); |
159 | if (pending == 0) | |
9689c99e ZLK |
160 | break; |
161 | generic_handle_irq(pending); | |
162 | } while (true); | |
163 | chained_irq_exit(chip, desc); | |
164 | } | |
165 | ||
a0789993 MS |
166 | static void xil_intc_handle_irq(struct pt_regs *regs) |
167 | { | |
168 | u32 hwirq; | |
169 | struct xintc_irq_chip *irqc = primary_intc; | |
170 | ||
171 | do { | |
172 | hwirq = xintc_read(irqc, IVR); | |
173 | if (likely(hwirq != -1U)) { | |
174 | int ret; | |
175 | ||
176 | ret = handle_domain_irq(irqc->root_domain, hwirq, regs); | |
177 | WARN_ONCE(ret, "Unhandled HWIRQ %d\n", hwirq); | |
178 | continue; | |
179 | } | |
180 | ||
181 | break; | |
182 | } while (1); | |
183 | } | |
184 | ||
8a9e90a1 MS |
185 | static int __init xilinx_intc_of_init(struct device_node *intc, |
186 | struct device_node *parent) | |
eedbdab9 | 187 | { |
591db74b | 188 | struct xintc_irq_chip *irqc; |
67862a3c | 189 | int ret, irq; |
591db74b ZLK |
190 | |
191 | irqc = kzalloc(sizeof(*irqc), GFP_KERNEL); | |
192 | if (!irqc) | |
193 | return -ENOMEM; | |
591db74b ZLK |
194 | irqc->base = of_iomap(intc, 0); |
195 | BUG_ON(!irqc->base); | |
bcff661d | 196 | |
67862a3c | 197 | ret = of_property_read_u32(intc, "xlnx,num-intr-inputs", &irqc->nr_irq); |
bcff661d | 198 | if (ret < 0) { |
a5734de2 | 199 | pr_err("irq-xilinx: unable to read xlnx,num-intr-inputs\n"); |
67862a3c | 200 | goto error; |
bcff661d MS |
201 | } |
202 | ||
591db74b | 203 | ret = of_property_read_u32(intc, "xlnx,kind-of-intr", &irqc->intr_mask); |
bcff661d | 204 | if (ret < 0) { |
8a11da59 ZLK |
205 | pr_warn("irq-xilinx: unable to read xlnx,kind-of-intr\n"); |
206 | irqc->intr_mask = 0; | |
bcff661d | 207 | } |
eedbdab9 | 208 | |
67862a3c | 209 | if (irqc->intr_mask >> irqc->nr_irq) |
a5734de2 | 210 | pr_warn("irq-xilinx: mismatch in kind-of-intr param\n"); |
eedbdab9 | 211 | |
e81f54c6 | 212 | pr_info("irq-xilinx: %pOF: num_irq=%d, edge=0x%x\n", |
67862a3c | 213 | intc, irqc->nr_irq, irqc->intr_mask); |
eedbdab9 | 214 | |
1aa1243c | 215 | |
eedbdab9 MS |
216 | /* |
217 | * Disable all external interrupts until they are | |
218 | * explicity requested. | |
219 | */ | |
67862a3c | 220 | xintc_write(irqc, IER, 0); |
eedbdab9 MS |
221 | |
222 | /* Acknowledge any pending interrupts just in case. */ | |
67862a3c | 223 | xintc_write(irqc, IAR, 0xffffffff); |
eedbdab9 MS |
224 | |
225 | /* Turn on the Master Enable. */ | |
67862a3c MS |
226 | xintc_write(irqc, MER, MER_HIE | MER_ME); |
227 | if (xintc_read(irqc, MER) != (MER_HIE | MER_ME)) { | |
591db74b | 228 | static_branch_enable(&xintc_is_be); |
67862a3c | 229 | xintc_write(irqc, MER, MER_HIE | MER_ME); |
1aa1243c | 230 | } |
eedbdab9 | 231 | |
67862a3c | 232 | irqc->root_domain = irq_domain_add_linear(intc, irqc->nr_irq, |
591db74b ZLK |
233 | &xintc_irq_domain_ops, irqc); |
234 | if (!irqc->root_domain) { | |
235 | pr_err("irq-xilinx: Unable to create IRQ domain\n"); | |
c74038ba | 236 | ret = -EINVAL; |
67862a3c | 237 | goto error; |
591db74b | 238 | } |
7c2c8513 | 239 | |
9689c99e ZLK |
240 | if (parent) { |
241 | irq = irq_of_parse_and_map(intc, 0); | |
242 | if (irq) { | |
243 | irq_set_chained_handler_and_data(irq, | |
244 | xil_intc_irq_handler, | |
245 | irqc); | |
246 | } else { | |
247 | pr_err("irq-xilinx: interrupts property not in DT\n"); | |
248 | ret = -EINVAL; | |
67862a3c | 249 | goto error; |
9689c99e ZLK |
250 | } |
251 | } else { | |
67862a3c | 252 | primary_intc = irqc; |
a0789993 | 253 | set_handle_irq(xil_intc_handle_irq); |
9689c99e | 254 | } |
8a9e90a1 MS |
255 | |
256 | return 0; | |
591db74b | 257 | |
67862a3c MS |
258 | error: |
259 | iounmap(irqc->base); | |
591db74b ZLK |
260 | kfree(irqc); |
261 | return ret; | |
262 | ||
eedbdab9 | 263 | } |
8a9e90a1 | 264 | |
8328255f ZLK |
265 | IRQCHIP_DECLARE(xilinx_intc_xps, "xlnx,xps-intc-1.00.a", xilinx_intc_of_init); |
266 | IRQCHIP_DECLARE(xilinx_intc_opb, "xlnx,opb-intc-1.00.c", xilinx_intc_of_init); |