Commit | Line | Data |
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eedbdab9 | 1 | /* |
968674bd MS |
2 | * Copyright (C) 2007-2013 Michal Simek <monstr@monstr.eu> |
3 | * Copyright (C) 2012-2013 Xilinx, Inc. | |
eedbdab9 MS |
4 | * Copyright (C) 2007-2009 PetaLogix |
5 | * Copyright (C) 2006 Atmark Techno, Inc. | |
6 | * | |
7 | * This file is subject to the terms and conditions of the GNU General Public | |
8 | * License. See the file "COPYING" in the main directory of this archive | |
9 | * for more details. | |
10 | */ | |
11 | ||
2462bacd | 12 | #include <linux/irqdomain.h> |
eedbdab9 | 13 | #include <linux/irq.h> |
fd4b267b | 14 | #include <linux/irqchip.h> |
9689c99e | 15 | #include <linux/irqchip/chained_irq.h> |
bcff661d | 16 | #include <linux/of_address.h> |
eedbdab9 | 17 | #include <linux/io.h> |
591db74b | 18 | #include <linux/jump_label.h> |
892ee92b | 19 | #include <linux/bug.h> |
9689c99e | 20 | #include <linux/of_irq.h> |
eedbdab9 | 21 | |
eedbdab9 MS |
22 | /* No one else should require these constants, so define them locally here. */ |
23 | #define ISR 0x00 /* Interrupt Status Register */ | |
24 | #define IPR 0x04 /* Interrupt Pending Register */ | |
25 | #define IER 0x08 /* Interrupt Enable Register */ | |
26 | #define IAR 0x0c /* Interrupt Acknowledge Register */ | |
27 | #define SIE 0x10 /* Set Interrupt Enable bits */ | |
28 | #define CIE 0x14 /* Clear Interrupt Enable bits */ | |
29 | #define IVR 0x18 /* Interrupt Vector Register */ | |
30 | #define MER 0x1c /* Master Enable Register */ | |
31 | ||
32 | #define MER_ME (1<<0) | |
33 | #define MER_HIE (1<<1) | |
34 | ||
1e364921 MS |
35 | #define SPURIOUS_IRQ (-1U) |
36 | ||
591db74b | 37 | static DEFINE_STATIC_KEY_FALSE(xintc_is_be); |
1aa1243c | 38 | |
591db74b ZLK |
39 | struct xintc_irq_chip { |
40 | void __iomem *base; | |
41 | struct irq_domain *root_domain; | |
42 | u32 intr_mask; | |
67862a3c | 43 | u32 nr_irq; |
591db74b | 44 | }; |
1aa1243c | 45 | |
67862a3c | 46 | static struct xintc_irq_chip *primary_intc; |
1aa1243c | 47 | |
67862a3c | 48 | static void xintc_write(struct xintc_irq_chip *irqc, int reg, u32 data) |
1aa1243c | 49 | { |
591db74b | 50 | if (static_branch_unlikely(&xintc_is_be)) |
67862a3c | 51 | iowrite32be(data, irqc->base + reg); |
591db74b | 52 | else |
67862a3c | 53 | iowrite32(data, irqc->base + reg); |
1aa1243c MS |
54 | } |
55 | ||
67862a3c | 56 | static u32 xintc_read(struct xintc_irq_chip *irqc, int reg) |
1aa1243c | 57 | { |
591db74b | 58 | if (static_branch_unlikely(&xintc_is_be)) |
67862a3c | 59 | return ioread32be(irqc->base + reg); |
591db74b | 60 | else |
67862a3c | 61 | return ioread32(irqc->base + reg); |
1aa1243c MS |
62 | } |
63 | ||
6f205a4c | 64 | static void intc_enable_or_unmask(struct irq_data *d) |
eedbdab9 | 65 | { |
67862a3c MS |
66 | struct xintc_irq_chip *irqc = irq_data_get_irq_chip_data(d); |
67 | unsigned long mask = BIT(d->hwirq); | |
6c7a2676 | 68 | |
a5734de2 | 69 | pr_debug("irq-xilinx: enable_or_unmask: %ld\n", d->hwirq); |
33d9ff59 | 70 | |
71 | /* ack level irqs because they can't be acked during | |
72 | * ack function since the handle_level_irq function | |
73 | * acks the irq before calling the interrupt handler | |
74 | */ | |
4adc192e | 75 | if (irqd_is_level_type(d)) |
67862a3c | 76 | xintc_write(irqc, IAR, mask); |
7958a689 | 77 | |
67862a3c | 78 | xintc_write(irqc, SIE, mask); |
eedbdab9 MS |
79 | } |
80 | ||
6f205a4c | 81 | static void intc_disable_or_mask(struct irq_data *d) |
eedbdab9 | 82 | { |
67862a3c MS |
83 | struct xintc_irq_chip *irqc = irq_data_get_irq_chip_data(d); |
84 | ||
a5734de2 | 85 | pr_debug("irq-xilinx: disable: %ld\n", d->hwirq); |
67862a3c | 86 | xintc_write(irqc, CIE, BIT(d->hwirq)); |
eedbdab9 MS |
87 | } |
88 | ||
6f205a4c | 89 | static void intc_ack(struct irq_data *d) |
eedbdab9 | 90 | { |
67862a3c MS |
91 | struct xintc_irq_chip *irqc = irq_data_get_irq_chip_data(d); |
92 | ||
a5734de2 | 93 | pr_debug("irq-xilinx: ack: %ld\n", d->hwirq); |
67862a3c | 94 | xintc_write(irqc, IAR, BIT(d->hwirq)); |
eedbdab9 MS |
95 | } |
96 | ||
6f205a4c | 97 | static void intc_mask_ack(struct irq_data *d) |
eedbdab9 | 98 | { |
67862a3c MS |
99 | struct xintc_irq_chip *irqc = irq_data_get_irq_chip_data(d); |
100 | unsigned long mask = BIT(d->hwirq); | |
6c7a2676 | 101 | |
a5734de2 | 102 | pr_debug("irq-xilinx: disable_and_ack: %ld\n", d->hwirq); |
67862a3c MS |
103 | xintc_write(irqc, CIE, mask); |
104 | xintc_write(irqc, IAR, mask); | |
eedbdab9 MS |
105 | } |
106 | ||
eedbdab9 MS |
107 | static struct irq_chip intc_dev = { |
108 | .name = "Xilinx INTC", | |
6f205a4c TG |
109 | .irq_unmask = intc_enable_or_unmask, |
110 | .irq_mask = intc_disable_or_mask, | |
111 | .irq_ack = intc_ack, | |
112 | .irq_mask_ack = intc_mask_ack, | |
eedbdab9 MS |
113 | }; |
114 | ||
c0d997fb | 115 | static int xintc_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw) |
2462bacd | 116 | { |
67862a3c MS |
117 | struct xintc_irq_chip *irqc = d->host_data; |
118 | ||
119 | if (irqc->intr_mask & BIT(hw)) { | |
2462bacd | 120 | irq_set_chip_and_handler_name(irq, &intc_dev, |
67862a3c | 121 | handle_edge_irq, "edge"); |
2462bacd GL |
122 | irq_clear_status_flags(irq, IRQ_LEVEL); |
123 | } else { | |
124 | irq_set_chip_and_handler_name(irq, &intc_dev, | |
67862a3c | 125 | handle_level_irq, "level"); |
2462bacd GL |
126 | irq_set_status_flags(irq, IRQ_LEVEL); |
127 | } | |
67862a3c | 128 | irq_set_chip_data(irq, irqc); |
2462bacd GL |
129 | return 0; |
130 | } | |
131 | ||
132 | static const struct irq_domain_ops xintc_irq_domain_ops = { | |
133 | .xlate = irq_domain_xlate_onetwocell, | |
134 | .map = xintc_map, | |
135 | }; | |
136 | ||
9689c99e ZLK |
137 | static void xil_intc_irq_handler(struct irq_desc *desc) |
138 | { | |
139 | struct irq_chip *chip = irq_desc_get_chip(desc); | |
67862a3c | 140 | struct xintc_irq_chip *irqc; |
9689c99e | 141 | |
67862a3c | 142 | irqc = irq_data_get_irq_handler_data(&desc->irq_data); |
9689c99e ZLK |
143 | chained_irq_enter(chip, desc); |
144 | do { | |
046a6ee2 MZ |
145 | u32 hwirq = xintc_read(irqc, IVR); |
146 | ||
147 | if (hwirq == -1U) | |
9689c99e | 148 | break; |
046a6ee2 MZ |
149 | |
150 | generic_handle_domain_irq(irqc->root_domain, hwirq); | |
9689c99e ZLK |
151 | } while (true); |
152 | chained_irq_exit(chip, desc); | |
153 | } | |
154 | ||
1e364921 MS |
155 | static void xil_intc_handle_irq(struct pt_regs *regs) |
156 | { | |
157 | u32 hwirq; | |
158 | ||
159 | do { | |
160 | hwirq = xintc_read(primary_intc, IVR); | |
161 | if (unlikely(hwirq == SPURIOUS_IRQ)) | |
162 | break; | |
163 | ||
164 | generic_handle_domain_irq(primary_intc->root_domain, hwirq); | |
165 | } while (true); | |
166 | } | |
167 | ||
8a9e90a1 MS |
168 | static int __init xilinx_intc_of_init(struct device_node *intc, |
169 | struct device_node *parent) | |
eedbdab9 | 170 | { |
591db74b | 171 | struct xintc_irq_chip *irqc; |
67862a3c | 172 | int ret, irq; |
591db74b ZLK |
173 | |
174 | irqc = kzalloc(sizeof(*irqc), GFP_KERNEL); | |
175 | if (!irqc) | |
176 | return -ENOMEM; | |
591db74b ZLK |
177 | irqc->base = of_iomap(intc, 0); |
178 | BUG_ON(!irqc->base); | |
bcff661d | 179 | |
67862a3c | 180 | ret = of_property_read_u32(intc, "xlnx,num-intr-inputs", &irqc->nr_irq); |
bcff661d | 181 | if (ret < 0) { |
a5734de2 | 182 | pr_err("irq-xilinx: unable to read xlnx,num-intr-inputs\n"); |
67862a3c | 183 | goto error; |
bcff661d MS |
184 | } |
185 | ||
591db74b | 186 | ret = of_property_read_u32(intc, "xlnx,kind-of-intr", &irqc->intr_mask); |
bcff661d | 187 | if (ret < 0) { |
8a11da59 ZLK |
188 | pr_warn("irq-xilinx: unable to read xlnx,kind-of-intr\n"); |
189 | irqc->intr_mask = 0; | |
bcff661d | 190 | } |
eedbdab9 | 191 | |
67862a3c | 192 | if (irqc->intr_mask >> irqc->nr_irq) |
a5734de2 | 193 | pr_warn("irq-xilinx: mismatch in kind-of-intr param\n"); |
eedbdab9 | 194 | |
e81f54c6 | 195 | pr_info("irq-xilinx: %pOF: num_irq=%d, edge=0x%x\n", |
67862a3c | 196 | intc, irqc->nr_irq, irqc->intr_mask); |
eedbdab9 | 197 | |
1aa1243c | 198 | |
eedbdab9 MS |
199 | /* |
200 | * Disable all external interrupts until they are | |
a359f757 | 201 | * explicitly requested. |
eedbdab9 | 202 | */ |
67862a3c | 203 | xintc_write(irqc, IER, 0); |
eedbdab9 MS |
204 | |
205 | /* Acknowledge any pending interrupts just in case. */ | |
67862a3c | 206 | xintc_write(irqc, IAR, 0xffffffff); |
eedbdab9 MS |
207 | |
208 | /* Turn on the Master Enable. */ | |
67862a3c MS |
209 | xintc_write(irqc, MER, MER_HIE | MER_ME); |
210 | if (xintc_read(irqc, MER) != (MER_HIE | MER_ME)) { | |
591db74b | 211 | static_branch_enable(&xintc_is_be); |
67862a3c | 212 | xintc_write(irqc, MER, MER_HIE | MER_ME); |
1aa1243c | 213 | } |
eedbdab9 | 214 | |
67862a3c | 215 | irqc->root_domain = irq_domain_add_linear(intc, irqc->nr_irq, |
591db74b ZLK |
216 | &xintc_irq_domain_ops, irqc); |
217 | if (!irqc->root_domain) { | |
218 | pr_err("irq-xilinx: Unable to create IRQ domain\n"); | |
c74038ba | 219 | ret = -EINVAL; |
67862a3c | 220 | goto error; |
591db74b | 221 | } |
7c2c8513 | 222 | |
9689c99e ZLK |
223 | if (parent) { |
224 | irq = irq_of_parse_and_map(intc, 0); | |
225 | if (irq) { | |
226 | irq_set_chained_handler_and_data(irq, | |
227 | xil_intc_irq_handler, | |
228 | irqc); | |
229 | } else { | |
230 | pr_err("irq-xilinx: interrupts property not in DT\n"); | |
231 | ret = -EINVAL; | |
67862a3c | 232 | goto error; |
9689c99e ZLK |
233 | } |
234 | } else { | |
67862a3c | 235 | primary_intc = irqc; |
e02f6c01 | 236 | irq_set_default_host(primary_intc->root_domain); |
1e364921 | 237 | set_handle_irq(xil_intc_handle_irq); |
9689c99e | 238 | } |
8a9e90a1 MS |
239 | |
240 | return 0; | |
591db74b | 241 | |
67862a3c MS |
242 | error: |
243 | iounmap(irqc->base); | |
591db74b ZLK |
244 | kfree(irqc); |
245 | return ret; | |
246 | ||
eedbdab9 | 247 | } |
8a9e90a1 | 248 | |
8328255f ZLK |
249 | IRQCHIP_DECLARE(xilinx_intc_xps, "xlnx,xps-intc-1.00.a", xilinx_intc_of_init); |
250 | IRQCHIP_DECLARE(xilinx_intc_opb, "xlnx,opb-intc-1.00.c", xilinx_intc_of_init); |