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1a59d1b8 | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
fa0fe48f RK |
2 | /* |
3 | * linux/arch/arm/common/vic.c | |
4 | * | |
5 | * Copyright (C) 1999 - 2003 ARM Limited | |
6 | * Copyright (C) 2000 Deep Blue Solutions Ltd | |
fa0fe48f | 7 | */ |
bb06b737 | 8 | |
f9b28ccb | 9 | #include <linux/export.h> |
fa0fe48f RK |
10 | #include <linux/init.h> |
11 | #include <linux/list.h> | |
fced80c7 | 12 | #include <linux/io.h> |
bc895b59 | 13 | #include <linux/irq.h> |
41a83e06 | 14 | #include <linux/irqchip.h> |
f6da9fe4 | 15 | #include <linux/irqchip/chained_irq.h> |
f9b28ccb JI |
16 | #include <linux/irqdomain.h> |
17 | #include <linux/of.h> | |
18 | #include <linux/of_address.h> | |
19 | #include <linux/of_irq.h> | |
328f5cc3 | 20 | #include <linux/syscore_ops.h> |
59fcf48f | 21 | #include <linux/device.h> |
f17a1f06 | 22 | #include <linux/amba/bus.h> |
9e47b8bf | 23 | #include <linux/irqchip/arm-vic.h> |
fa0fe48f | 24 | |
1558368e | 25 | #include <asm/exception.h> |
f36a3bb1 | 26 | #include <asm/irq.h> |
fa0fe48f | 27 | |
cf21af54 RH |
28 | #define VIC_IRQ_STATUS 0x00 |
29 | #define VIC_FIQ_STATUS 0x04 | |
b0b92ab6 | 30 | #define VIC_RAW_STATUS 0x08 |
cf21af54 | 31 | #define VIC_INT_SELECT 0x0c /* 1 = FIQ, 0 = IRQ */ |
b0b92ab6 LW |
32 | #define VIC_INT_ENABLE 0x10 /* 1 = enable, 0 = disable */ |
33 | #define VIC_INT_ENABLE_CLEAR 0x14 | |
cf21af54 RH |
34 | #define VIC_INT_SOFT 0x18 |
35 | #define VIC_INT_SOFT_CLEAR 0x1c | |
36 | #define VIC_PROTECT 0x20 | |
37 | #define VIC_PL190_VECT_ADDR 0x30 /* PL190 only */ | |
38 | #define VIC_PL190_DEF_VECT_ADDR 0x34 /* PL190 only */ | |
39 | ||
40 | #define VIC_VECT_ADDR0 0x100 /* 0 to 15 (0..31 PL192) */ | |
41 | #define VIC_VECT_CNTL0 0x200 /* 0 to 15 (0..31 PL192) */ | |
42 | #define VIC_ITCR 0x300 /* VIC test control register */ | |
43 | ||
44 | #define VIC_VECT_CNTL_ENABLE (1 << 5) | |
45 | ||
46 | #define VIC_PL192_VECT_ADDR 0xF00 | |
47 | ||
c07f87f2 BD |
48 | /** |
49 | * struct vic_device - VIC PM device | |
c07f87f2 | 50 | * @base: The register base for the VIC. |
eb0e1ebb | 51 | * @irq: The IRQ number for the base of the VIC. |
ce94df9c | 52 | * @valid_sources: A bitmask of valid interrupts |
c07f87f2 BD |
53 | * @resume_sources: A bitmask of interrupts for resume. |
54 | * @resume_irqs: The IRQs enabled for resume. | |
55 | * @int_select: Save for VIC_INT_SELECT. | |
56 | * @int_enable: Save for VIC_INT_ENABLE. | |
57 | * @soft_int: Save for VIC_INT_SOFT. | |
58 | * @protect: Save for VIC_PROTECT. | |
f9b28ccb | 59 | * @domain: The IRQ domain for the VIC. |
c07f87f2 BD |
60 | */ |
61 | struct vic_device { | |
c07f87f2 BD |
62 | void __iomem *base; |
63 | int irq; | |
ce94df9c | 64 | u32 valid_sources; |
c07f87f2 BD |
65 | u32 resume_sources; |
66 | u32 resume_irqs; | |
67 | u32 int_select; | |
68 | u32 int_enable; | |
69 | u32 soft_int; | |
70 | u32 protect; | |
75294957 | 71 | struct irq_domain *domain; |
c07f87f2 BD |
72 | }; |
73 | ||
74 | /* we cannot allocate memory when VICs are initially registered */ | |
75 | static struct vic_device vic_devices[CONFIG_ARM_VIC_NR]; | |
76 | ||
bb06b737 | 77 | static int vic_id; |
c07f87f2 | 78 | |
a0368029 RH |
79 | static void vic_handle_irq(struct pt_regs *regs); |
80 | ||
bb06b737 HS |
81 | /** |
82 | * vic_init2 - common initialisation code | |
83 | * @base: Base of the VIC. | |
84 | * | |
b595076a | 85 | * Common initialisation code for registration |
bb06b737 HS |
86 | * and resume. |
87 | */ | |
88 | static void vic_init2(void __iomem *base) | |
89 | { | |
90 | int i; | |
91 | ||
92 | for (i = 0; i < 16; i++) { | |
93 | void __iomem *reg = base + VIC_VECT_CNTL0 + (i * 4); | |
94 | writel(VIC_VECT_CNTL_ENABLE | i, reg); | |
95 | } | |
96 | ||
97 | writel(32, base + VIC_PL190_DEF_VECT_ADDR); | |
98 | } | |
c07f87f2 | 99 | |
328f5cc3 RW |
100 | #ifdef CONFIG_PM |
101 | static void resume_one_vic(struct vic_device *vic) | |
c07f87f2 | 102 | { |
c07f87f2 BD |
103 | void __iomem *base = vic->base; |
104 | ||
105 | printk(KERN_DEBUG "%s: resuming vic at %p\n", __func__, base); | |
106 | ||
107 | /* re-initialise static settings */ | |
108 | vic_init2(base); | |
109 | ||
110 | writel(vic->int_select, base + VIC_INT_SELECT); | |
111 | writel(vic->protect, base + VIC_PROTECT); | |
112 | ||
113 | /* set the enabled ints and then clear the non-enabled */ | |
114 | writel(vic->int_enable, base + VIC_INT_ENABLE); | |
115 | writel(~vic->int_enable, base + VIC_INT_ENABLE_CLEAR); | |
116 | ||
117 | /* and the same for the soft-int register */ | |
118 | ||
119 | writel(vic->soft_int, base + VIC_INT_SOFT); | |
120 | writel(~vic->soft_int, base + VIC_INT_SOFT_CLEAR); | |
328f5cc3 | 121 | } |
c07f87f2 | 122 | |
328f5cc3 RW |
123 | static void vic_resume(void) |
124 | { | |
125 | int id; | |
126 | ||
127 | for (id = vic_id - 1; id >= 0; id--) | |
128 | resume_one_vic(vic_devices + id); | |
c07f87f2 BD |
129 | } |
130 | ||
328f5cc3 | 131 | static void suspend_one_vic(struct vic_device *vic) |
c07f87f2 | 132 | { |
c07f87f2 BD |
133 | void __iomem *base = vic->base; |
134 | ||
135 | printk(KERN_DEBUG "%s: suspending vic at %p\n", __func__, base); | |
136 | ||
137 | vic->int_select = readl(base + VIC_INT_SELECT); | |
138 | vic->int_enable = readl(base + VIC_INT_ENABLE); | |
139 | vic->soft_int = readl(base + VIC_INT_SOFT); | |
140 | vic->protect = readl(base + VIC_PROTECT); | |
141 | ||
142 | /* set the interrupts (if any) that are used for | |
143 | * resuming the system */ | |
144 | ||
145 | writel(vic->resume_irqs, base + VIC_INT_ENABLE); | |
146 | writel(~vic->resume_irqs, base + VIC_INT_ENABLE_CLEAR); | |
328f5cc3 RW |
147 | } |
148 | ||
149 | static int vic_suspend(void) | |
150 | { | |
151 | int id; | |
152 | ||
153 | for (id = 0; id < vic_id; id++) | |
154 | suspend_one_vic(vic_devices + id); | |
c07f87f2 BD |
155 | |
156 | return 0; | |
157 | } | |
158 | ||
df042a5f | 159 | static struct syscore_ops vic_syscore_ops = { |
328f5cc3 RW |
160 | .suspend = vic_suspend, |
161 | .resume = vic_resume, | |
c07f87f2 BD |
162 | }; |
163 | ||
c07f87f2 | 164 | /** |
a359f757 | 165 | * vic_pm_init - initcall to register VIC pm |
c07f87f2 BD |
166 | * |
167 | * This is called via late_initcall() to register | |
168 | * the resources for the VICs due to the early | |
169 | * nature of the VIC's registration. | |
170 | */ | |
171 | static int __init vic_pm_init(void) | |
172 | { | |
328f5cc3 RW |
173 | if (vic_id > 0) |
174 | register_syscore_ops(&vic_syscore_ops); | |
c07f87f2 BD |
175 | |
176 | return 0; | |
177 | } | |
c07f87f2 | 178 | late_initcall(vic_pm_init); |
f9b28ccb | 179 | #endif /* CONFIG_PM */ |
c07f87f2 | 180 | |
ce94df9c LW |
181 | static struct irq_chip vic_chip; |
182 | ||
183 | static int vic_irqdomain_map(struct irq_domain *d, unsigned int irq, | |
184 | irq_hw_number_t hwirq) | |
185 | { | |
186 | struct vic_device *v = d->host_data; | |
187 | ||
188 | /* Skip invalid IRQs, only register handlers for the real ones */ | |
189 | if (!(v->valid_sources & (1 << hwirq))) | |
d94ea3f6 | 190 | return -EPERM; |
ce94df9c LW |
191 | irq_set_chip_and_handler(irq, &vic_chip, handle_level_irq); |
192 | irq_set_chip_data(irq, v->base); | |
d17cab44 | 193 | irq_set_probe(irq); |
ce94df9c LW |
194 | return 0; |
195 | } | |
196 | ||
a0368029 RH |
197 | /* |
198 | * Handle each interrupt in a single VIC. Returns non-zero if we've | |
199 | * handled at least one interrupt. This reads the status register | |
200 | * before handling each interrupt, which is necessary given that | |
201 | * handle_IRQ may briefly re-enable interrupts for soft IRQ handling. | |
202 | */ | |
203 | static int handle_one_vic(struct vic_device *vic, struct pt_regs *regs) | |
204 | { | |
205 | u32 stat, irq; | |
206 | int handled = 0; | |
207 | ||
208 | while ((stat = readl_relaxed(vic->base + VIC_IRQ_STATUS))) { | |
209 | irq = ffs(stat) - 1; | |
0953fb26 | 210 | generic_handle_domain_irq(vic->domain, irq); |
a0368029 RH |
211 | handled = 1; |
212 | } | |
213 | ||
214 | return handled; | |
215 | } | |
216 | ||
bd0b9ac4 | 217 | static void vic_handle_irq_cascaded(struct irq_desc *desc) |
e641b987 LW |
218 | { |
219 | u32 stat, hwirq; | |
f6da9fe4 | 220 | struct irq_chip *host_chip = irq_desc_get_chip(desc); |
e641b987 LW |
221 | struct vic_device *vic = irq_desc_get_handler_data(desc); |
222 | ||
f6da9fe4 LW |
223 | chained_irq_enter(host_chip, desc); |
224 | ||
e641b987 LW |
225 | while ((stat = readl_relaxed(vic->base + VIC_IRQ_STATUS))) { |
226 | hwirq = ffs(stat) - 1; | |
046a6ee2 | 227 | generic_handle_domain_irq(vic->domain, hwirq); |
e641b987 | 228 | } |
f6da9fe4 LW |
229 | |
230 | chained_irq_exit(host_chip, desc); | |
e641b987 LW |
231 | } |
232 | ||
a0368029 RH |
233 | /* |
234 | * Keep iterating over all registered VIC's until there are no pending | |
235 | * interrupts. | |
236 | */ | |
8783dd3a | 237 | static void __exception_irq_entry vic_handle_irq(struct pt_regs *regs) |
a0368029 RH |
238 | { |
239 | int i, handled; | |
240 | ||
241 | do { | |
242 | for (i = 0, handled = 0; i < vic_id; ++i) | |
243 | handled |= handle_one_vic(&vic_devices[i], regs); | |
244 | } while (handled); | |
245 | } | |
246 | ||
96009736 | 247 | static const struct irq_domain_ops vic_irqdomain_ops = { |
ce94df9c LW |
248 | .map = vic_irqdomain_map, |
249 | .xlate = irq_domain_xlate_onetwocell, | |
250 | }; | |
251 | ||
bb06b737 | 252 | /** |
f9b28ccb | 253 | * vic_register() - Register a VIC. |
bb06b737 | 254 | * @base: The base address of the VIC. |
e641b987 | 255 | * @parent_irq: The parent IRQ if cascaded, else 0. |
bb06b737 | 256 | * @irq: The base IRQ for the VIC. |
fa943bed | 257 | * @valid_sources: bitmask of valid interrupts |
bb06b737 | 258 | * @resume_sources: bitmask of interrupts allowed for resume sources. |
f9b28ccb | 259 | * @node: The device tree node associated with the VIC. |
bb06b737 HS |
260 | * |
261 | * Register the VIC with the system device tree so that it can be notified | |
262 | * of suspend and resume requests and ensure that the correct actions are | |
263 | * taken to re-instate the settings on resume. | |
f9b28ccb JI |
264 | * |
265 | * This also configures the IRQ domain for the VIC. | |
bb06b737 | 266 | */ |
e641b987 LW |
267 | static void __init vic_register(void __iomem *base, unsigned int parent_irq, |
268 | unsigned int irq, | |
fa943bed LW |
269 | u32 valid_sources, u32 resume_sources, |
270 | struct device_node *node) | |
bb06b737 HS |
271 | { |
272 | struct vic_device *v; | |
5ced33bc | 273 | int i; |
bb06b737 | 274 | |
f9b28ccb | 275 | if (vic_id >= ARRAY_SIZE(vic_devices)) { |
bb06b737 | 276 | printk(KERN_ERR "%s: too few VICs, increase CONFIG_ARM_VIC_NR\n", __func__); |
f9b28ccb | 277 | return; |
bb06b737 | 278 | } |
f9b28ccb JI |
279 | |
280 | v = &vic_devices[vic_id]; | |
281 | v->base = base; | |
ce94df9c | 282 | v->valid_sources = valid_sources; |
f9b28ccb | 283 | v->resume_sources = resume_sources; |
7fb7d8ae | 284 | set_handle_irq(vic_handle_irq); |
f9b28ccb | 285 | vic_id++; |
e641b987 LW |
286 | |
287 | if (parent_irq) { | |
9f213541 TG |
288 | irq_set_chained_handler_and_data(parent_irq, |
289 | vic_handle_irq_cascaded, v); | |
e641b987 LW |
290 | } |
291 | ||
07c9249f | 292 | v->domain = irq_domain_add_simple(node, fls(valid_sources), irq, |
fa943bed | 293 | &vic_irqdomain_ops, v); |
5ced33bc LW |
294 | /* create an IRQ mapping for each valid IRQ */ |
295 | for (i = 0; i < fls(valid_sources); i++) | |
296 | if (valid_sources & (1 << i)) | |
297 | irq_create_mapping(v->domain, i); | |
3b4df9db LW |
298 | /* If no base IRQ was passed, figure out our allocated base */ |
299 | if (irq) | |
300 | v->irq = irq; | |
301 | else | |
302 | v->irq = irq_find_mapping(v->domain, 0); | |
bb06b737 | 303 | } |
bb06b737 | 304 | |
f013c98d | 305 | static void vic_ack_irq(struct irq_data *d) |
bb06b737 | 306 | { |
f013c98d | 307 | void __iomem *base = irq_data_get_irq_chip_data(d); |
f9b28ccb | 308 | unsigned int irq = d->hwirq; |
bb06b737 HS |
309 | writel(1 << irq, base + VIC_INT_ENABLE_CLEAR); |
310 | /* moreover, clear the soft-triggered, in case it was the reason */ | |
311 | writel(1 << irq, base + VIC_INT_SOFT_CLEAR); | |
312 | } | |
313 | ||
f013c98d | 314 | static void vic_mask_irq(struct irq_data *d) |
bb06b737 | 315 | { |
f013c98d | 316 | void __iomem *base = irq_data_get_irq_chip_data(d); |
f9b28ccb | 317 | unsigned int irq = d->hwirq; |
bb06b737 HS |
318 | writel(1 << irq, base + VIC_INT_ENABLE_CLEAR); |
319 | } | |
320 | ||
f013c98d | 321 | static void vic_unmask_irq(struct irq_data *d) |
bb06b737 | 322 | { |
f013c98d | 323 | void __iomem *base = irq_data_get_irq_chip_data(d); |
f9b28ccb | 324 | unsigned int irq = d->hwirq; |
bb06b737 HS |
325 | writel(1 << irq, base + VIC_INT_ENABLE); |
326 | } | |
327 | ||
328 | #if defined(CONFIG_PM) | |
c07f87f2 BD |
329 | static struct vic_device *vic_from_irq(unsigned int irq) |
330 | { | |
331 | struct vic_device *v = vic_devices; | |
332 | unsigned int base_irq = irq & ~31; | |
333 | int id; | |
334 | ||
335 | for (id = 0; id < vic_id; id++, v++) { | |
336 | if (v->irq == base_irq) | |
337 | return v; | |
338 | } | |
339 | ||
340 | return NULL; | |
341 | } | |
342 | ||
f013c98d | 343 | static int vic_set_wake(struct irq_data *d, unsigned int on) |
c07f87f2 | 344 | { |
f013c98d | 345 | struct vic_device *v = vic_from_irq(d->irq); |
f9b28ccb | 346 | unsigned int off = d->hwirq; |
3f1a567d | 347 | u32 bit = 1 << off; |
c07f87f2 BD |
348 | |
349 | if (!v) | |
350 | return -EINVAL; | |
351 | ||
3f1a567d BD |
352 | if (!(bit & v->resume_sources)) |
353 | return -EINVAL; | |
354 | ||
c07f87f2 | 355 | if (on) |
3f1a567d | 356 | v->resume_irqs |= bit; |
c07f87f2 | 357 | else |
3f1a567d | 358 | v->resume_irqs &= ~bit; |
c07f87f2 BD |
359 | |
360 | return 0; | |
361 | } | |
c07f87f2 | 362 | #else |
c07f87f2 BD |
363 | #define vic_set_wake NULL |
364 | #endif /* CONFIG_PM */ | |
365 | ||
38c677cb | 366 | static struct irq_chip vic_chip = { |
b0c4c898 | 367 | .name = "VIC", |
f013c98d LB |
368 | .irq_ack = vic_ack_irq, |
369 | .irq_mask = vic_mask_irq, | |
370 | .irq_unmask = vic_unmask_irq, | |
371 | .irq_set_wake = vic_set_wake, | |
fa0fe48f RK |
372 | }; |
373 | ||
b0c4c898 HS |
374 | static void __init vic_disable(void __iomem *base) |
375 | { | |
376 | writel(0, base + VIC_INT_SELECT); | |
377 | writel(0, base + VIC_INT_ENABLE); | |
378 | writel(~0, base + VIC_INT_ENABLE_CLEAR); | |
b0c4c898 HS |
379 | writel(0, base + VIC_ITCR); |
380 | writel(~0, base + VIC_INT_SOFT_CLEAR); | |
381 | } | |
382 | ||
383 | static void __init vic_clear_interrupts(void __iomem *base) | |
384 | { | |
385 | unsigned int i; | |
386 | ||
387 | writel(0, base + VIC_PL190_VECT_ADDR); | |
388 | for (i = 0; i < 19; i++) { | |
389 | unsigned int value; | |
390 | ||
391 | value = readl(base + VIC_PL190_VECT_ADDR); | |
392 | writel(value, base + VIC_PL190_VECT_ADDR); | |
393 | } | |
394 | } | |
395 | ||
bb06b737 HS |
396 | /* |
397 | * The PL190 cell from ARM has been modified by ST to handle 64 interrupts. | |
398 | * The original cell has 32 interrupts, while the modified one has 64, | |
a359f757 | 399 | * replicating two blocks 0x00..0x1f in 0x20..0x3f. In that case |
bb06b737 HS |
400 | * the probe function is called twice, with base set to offset 000 |
401 | * and 020 within the page. We call this "second block". | |
402 | */ | |
403 | static void __init vic_init_st(void __iomem *base, unsigned int irq_start, | |
ad622671 | 404 | u32 vic_sources, struct device_node *node) |
bb06b737 HS |
405 | { |
406 | unsigned int i; | |
407 | int vic_2nd_block = ((unsigned long)base & ~PAGE_MASK) != 0; | |
408 | ||
409 | /* Disable all interrupts initially. */ | |
b0c4c898 | 410 | vic_disable(base); |
bb06b737 HS |
411 | |
412 | /* | |
413 | * Make sure we clear all existing interrupts. The vector registers | |
414 | * in this cell are after the second block of general registers, | |
415 | * so we can address them using standard offsets, but only from | |
416 | * the second base address, which is 0x20 in the page | |
417 | */ | |
418 | if (vic_2nd_block) { | |
b0c4c898 | 419 | vic_clear_interrupts(base); |
bb06b737 | 420 | |
bb06b737 HS |
421 | /* ST has 16 vectors as well, but we don't enable them by now */ |
422 | for (i = 0; i < 16; i++) { | |
423 | void __iomem *reg = base + VIC_VECT_CNTL0 + (i * 4); | |
424 | writel(0, reg); | |
425 | } | |
426 | ||
427 | writel(32, base + VIC_PL190_DEF_VECT_ADDR); | |
428 | } | |
429 | ||
e641b987 | 430 | vic_register(base, 0, irq_start, vic_sources, 0, node); |
bb06b737 | 431 | } |
87e8824b | 432 | |
b0b92ab6 | 433 | static void __init __vic_init(void __iomem *base, int parent_irq, int irq_start, |
f9b28ccb JI |
434 | u32 vic_sources, u32 resume_sources, |
435 | struct device_node *node) | |
fa0fe48f RK |
436 | { |
437 | unsigned int i; | |
87e8824b | 438 | u32 cellid = 0; |
f17a1f06 | 439 | enum amba_vendor vendor; |
87e8824b AR |
440 | |
441 | /* Identify which VIC cell this one is, by reading the ID */ | |
442 | for (i = 0; i < 4; i++) { | |
d4f3add2 AB |
443 | void __iomem *addr; |
444 | addr = (void __iomem *)((u32)base & PAGE_MASK) + 0xfe0 + (i * 4); | |
87e8824b AR |
445 | cellid |= (readl(addr) & 0xff) << (8 * i); |
446 | } | |
447 | vendor = (cellid >> 12) & 0xff; | |
448 | printk(KERN_INFO "VIC @%p: id 0x%08x, vendor 0x%02x\n", | |
449 | base, cellid, vendor); | |
450 | ||
451 | switch(vendor) { | |
f17a1f06 | 452 | case AMBA_VENDOR_ST: |
ad622671 | 453 | vic_init_st(base, irq_start, vic_sources, node); |
87e8824b AR |
454 | return; |
455 | default: | |
456 | printk(KERN_WARNING "VIC: unknown vendor, continuing anyways\n"); | |
df561f66 | 457 | fallthrough; |
f17a1f06 | 458 | case AMBA_VENDOR_ARM: |
87e8824b AR |
459 | break; |
460 | } | |
fa0fe48f | 461 | |
fa0fe48f | 462 | /* Disable all interrupts initially. */ |
b0c4c898 | 463 | vic_disable(base); |
fa0fe48f | 464 | |
b0c4c898 HS |
465 | /* Make sure we clear all existing interrupts */ |
466 | vic_clear_interrupts(base); | |
fa0fe48f | 467 | |
c07f87f2 | 468 | vic_init2(base); |
fa0fe48f | 469 | |
e641b987 | 470 | vic_register(base, parent_irq, irq_start, vic_sources, resume_sources, node); |
f9b28ccb JI |
471 | } |
472 | ||
473 | /** | |
474 | * vic_init() - initialise a vectored interrupt controller | |
475 | * @base: iomem base address | |
476 | * @irq_start: starting interrupt number, must be muliple of 32 | |
477 | * @vic_sources: bitmask of interrupt sources to allow | |
478 | * @resume_sources: bitmask of interrupt sources to allow for resume | |
479 | */ | |
480 | void __init vic_init(void __iomem *base, unsigned int irq_start, | |
481 | u32 vic_sources, u32 resume_sources) | |
482 | { | |
e641b987 LW |
483 | __vic_init(base, 0, irq_start, vic_sources, resume_sources, NULL); |
484 | } | |
485 | ||
f9b28ccb | 486 | #ifdef CONFIG_OF |
df042a5f BD |
487 | static int __init vic_of_init(struct device_node *node, |
488 | struct device_node *parent) | |
f9b28ccb JI |
489 | { |
490 | void __iomem *regs; | |
81e9c179 TF |
491 | u32 interrupt_mask = ~0; |
492 | u32 wakeup_mask = ~0; | |
a1511107 | 493 | int parent_irq; |
f9b28ccb JI |
494 | |
495 | regs = of_iomap(node, 0); | |
496 | if (WARN_ON(!regs)) | |
497 | return -EIO; | |
498 | ||
81e9c179 TF |
499 | of_property_read_u32(node, "valid-mask", &interrupt_mask); |
500 | of_property_read_u32(node, "valid-wakeup-mask", &wakeup_mask); | |
a1511107 LW |
501 | parent_irq = of_irq_get(node, 0); |
502 | if (parent_irq < 0) | |
503 | parent_irq = 0; | |
81e9c179 | 504 | |
07c9249f | 505 | /* |
5ced33bc | 506 | * Passing 0 as first IRQ makes the simple domain allocate descriptors |
07c9249f | 507 | */ |
a1511107 | 508 | __vic_init(regs, parent_irq, 0, interrupt_mask, wakeup_mask, node); |
f9b28ccb JI |
509 | |
510 | return 0; | |
fa0fe48f | 511 | } |
44430ec0 RH |
512 | IRQCHIP_DECLARE(arm_pl190_vic, "arm,pl190-vic", vic_of_init); |
513 | IRQCHIP_DECLARE(arm_pl192_vic, "arm,pl192-vic", vic_of_init); | |
514 | IRQCHIP_DECLARE(arm_versatile_vic, "arm,versatile-vic", vic_of_init); | |
f9b28ccb | 515 | #endif /* CONFIG OF */ |