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b2441318 | 1 | // SPDX-License-Identifier: GPL-2.0 |
c41b16f8 RK |
2 | /* |
3 | * Support for Versatile FPGA-based IRQ controllers | |
4 | */ | |
3a6ca8c5 | 5 | #include <linux/bitops.h> |
c41b16f8 RK |
6 | #include <linux/irq.h> |
7 | #include <linux/io.h> | |
41a83e06 | 8 | #include <linux/irqchip.h> |
486562da | 9 | #include <linux/irqchip/chained_irq.h> |
2389d501 | 10 | #include <linux/irqchip/versatile-fpga.h> |
3108e6ab LW |
11 | #include <linux/irqdomain.h> |
12 | #include <linux/module.h> | |
9bc15031 LW |
13 | #include <linux/of.h> |
14 | #include <linux/of_address.h> | |
bdd272cb | 15 | #include <linux/of_irq.h> |
c41b16f8 | 16 | |
3108e6ab | 17 | #include <asm/exception.h> |
c41b16f8 | 18 | #include <asm/mach/irq.h> |
c41b16f8 RK |
19 | |
20 | #define IRQ_STATUS 0x00 | |
21 | #define IRQ_RAW_STATUS 0x04 | |
22 | #define IRQ_ENABLE_SET 0x08 | |
23 | #define IRQ_ENABLE_CLEAR 0x0c | |
9bc15031 LW |
24 | #define INT_SOFT_SET 0x10 |
25 | #define INT_SOFT_CLEAR 0x14 | |
26 | #define FIQ_STATUS 0x20 | |
27 | #define FIQ_RAW_STATUS 0x24 | |
28 | #define FIQ_ENABLE 0x28 | |
29 | #define FIQ_ENABLE_SET 0x28 | |
30 | #define FIQ_ENABLE_CLEAR 0x2C | |
c41b16f8 | 31 | |
59318461 RH |
32 | #define PIC_ENABLES 0x20 /* set interrupt pass through bits */ |
33 | ||
3108e6ab LW |
34 | /** |
35 | * struct fpga_irq_data - irq data container for the FPGA IRQ controller | |
36 | * @base: memory offset in virtual memory | |
3108e6ab LW |
37 | * @chip: chip container for this instance |
38 | * @domain: IRQ domain for this instance | |
39 | * @valid: mask for valid IRQs on this controller | |
40 | * @used_irqs: number of active IRQs on this controller | |
41 | */ | |
42 | struct fpga_irq_data { | |
43 | void __iomem *base; | |
3108e6ab LW |
44 | struct irq_chip chip; |
45 | u32 valid; | |
46 | struct irq_domain *domain; | |
47 | u8 used_irqs; | |
48 | }; | |
49 | ||
50 | /* we cannot allocate memory when the controllers are initially registered */ | |
2389d501 | 51 | static struct fpga_irq_data fpga_irq_devices[CONFIG_VERSATILE_FPGA_IRQ_NR]; |
3108e6ab LW |
52 | static int fpga_irq_id; |
53 | ||
c41b16f8 RK |
54 | static void fpga_irq_mask(struct irq_data *d) |
55 | { | |
56 | struct fpga_irq_data *f = irq_data_get_irq_chip_data(d); | |
3108e6ab | 57 | u32 mask = 1 << d->hwirq; |
c41b16f8 RK |
58 | |
59 | writel(mask, f->base + IRQ_ENABLE_CLEAR); | |
60 | } | |
61 | ||
62 | static void fpga_irq_unmask(struct irq_data *d) | |
63 | { | |
64 | struct fpga_irq_data *f = irq_data_get_irq_chip_data(d); | |
3108e6ab | 65 | u32 mask = 1 << d->hwirq; |
c41b16f8 RK |
66 | |
67 | writel(mask, f->base + IRQ_ENABLE_SET); | |
68 | } | |
69 | ||
bd0b9ac4 | 70 | static void fpga_irq_handle(struct irq_desc *desc) |
c41b16f8 | 71 | { |
486562da | 72 | struct irq_chip *chip = irq_desc_get_chip(desc); |
6845664a | 73 | struct fpga_irq_data *f = irq_desc_get_handler_data(desc); |
486562da SE |
74 | u32 status; |
75 | ||
76 | chained_irq_enter(chip, desc); | |
c41b16f8 | 77 | |
486562da | 78 | status = readl(f->base + IRQ_STATUS); |
c41b16f8 | 79 | if (status == 0) { |
bd0b9ac4 | 80 | do_bad_IRQ(desc); |
486562da | 81 | goto out; |
c41b16f8 RK |
82 | } |
83 | ||
84 | do { | |
bd0b9ac4 TG |
85 | unsigned int irq = ffs(status) - 1; |
86 | ||
c41b16f8 | 87 | status &= ~(1 << irq); |
046a6ee2 | 88 | generic_handle_domain_irq(f->domain, irq); |
c41b16f8 | 89 | } while (status); |
486562da SE |
90 | |
91 | out: | |
92 | chained_irq_exit(chip, desc); | |
c41b16f8 RK |
93 | } |
94 | ||
3108e6ab LW |
95 | /* |
96 | * Handle each interrupt in a single FPGA IRQ controller. Returns non-zero | |
97 | * if we've handled at least one interrupt. This does a single read of the | |
98 | * status register and handles all interrupts in order from LSB first. | |
99 | */ | |
100 | static int handle_one_fpga(struct fpga_irq_data *f, struct pt_regs *regs) | |
101 | { | |
102 | int handled = 0; | |
103 | int irq; | |
104 | u32 status; | |
105 | ||
106 | while ((status = readl(f->base + IRQ_STATUS))) { | |
107 | irq = ffs(status) - 1; | |
84bc7399 | 108 | handle_domain_irq(f->domain, irq, regs); |
3108e6ab LW |
109 | handled = 1; |
110 | } | |
111 | ||
112 | return handled; | |
113 | } | |
114 | ||
115 | /* | |
116 | * Keep iterating over all registered FPGA IRQ controllers until there are | |
117 | * no pending interrupts. | |
118 | */ | |
119 | asmlinkage void __exception_irq_entry fpga_handle_irq(struct pt_regs *regs) | |
c41b16f8 | 120 | { |
3108e6ab | 121 | int i, handled; |
c41b16f8 | 122 | |
3108e6ab LW |
123 | do { |
124 | for (i = 0, handled = 0; i < fpga_irq_id; ++i) | |
125 | handled |= handle_one_fpga(&fpga_irq_devices[i], regs); | |
126 | } while (handled); | |
127 | } | |
128 | ||
129 | static int fpga_irqdomain_map(struct irq_domain *d, unsigned int irq, | |
130 | irq_hw_number_t hwirq) | |
131 | { | |
132 | struct fpga_irq_data *f = d->host_data; | |
133 | ||
134 | /* Skip invalid IRQs, only register handlers for the real ones */ | |
3a6ca8c5 | 135 | if (!(f->valid & BIT(hwirq))) |
d94ea3f6 | 136 | return -EPERM; |
3108e6ab LW |
137 | irq_set_chip_data(irq, f); |
138 | irq_set_chip_and_handler(irq, &f->chip, | |
139 | handle_level_irq); | |
d17cab44 | 140 | irq_set_probe(irq); |
3108e6ab LW |
141 | return 0; |
142 | } | |
143 | ||
96009736 | 144 | static const struct irq_domain_ops fpga_irqdomain_ops = { |
3108e6ab LW |
145 | .map = fpga_irqdomain_map, |
146 | .xlate = irq_domain_xlate_onetwocell, | |
147 | }; | |
148 | ||
3a6ca8c5 LW |
149 | void __init fpga_irq_init(void __iomem *base, const char *name, int irq_start, |
150 | int parent_irq, u32 valid, struct device_node *node) | |
151 | { | |
3108e6ab | 152 | struct fpga_irq_data *f; |
3a6ca8c5 | 153 | int i; |
3108e6ab LW |
154 | |
155 | if (fpga_irq_id >= ARRAY_SIZE(fpga_irq_devices)) { | |
e6423f8b | 156 | pr_err("%s: too few FPGA IRQ controllers, increase CONFIG_VERSATILE_FPGA_IRQ_NR\n", __func__); |
3a6ca8c5 | 157 | return; |
3108e6ab | 158 | } |
3108e6ab LW |
159 | f = &fpga_irq_devices[fpga_irq_id]; |
160 | f->base = base; | |
3108e6ab | 161 | f->chip.name = name; |
c41b16f8 RK |
162 | f->chip.irq_ack = fpga_irq_mask; |
163 | f->chip.irq_mask = fpga_irq_mask; | |
164 | f->chip.irq_unmask = fpga_irq_unmask; | |
3108e6ab | 165 | f->valid = valid; |
c41b16f8 RK |
166 | |
167 | if (parent_irq != -1) { | |
fcd3c5be TG |
168 | irq_set_chained_handler_and_data(parent_irq, fpga_irq_handle, |
169 | f); | |
c41b16f8 RK |
170 | } |
171 | ||
3a6ca8c5 LW |
172 | /* This will also allocate irq descriptors */ |
173 | f->domain = irq_domain_add_simple(node, fls(valid), irq_start, | |
3108e6ab | 174 | &fpga_irqdomain_ops, f); |
3a6ca8c5 LW |
175 | |
176 | /* This will allocate all valid descriptors in the linear case */ | |
177 | for (i = 0; i < fls(valid); i++) | |
178 | if (valid & BIT(i)) { | |
179 | if (!irq_start) | |
180 | irq_create_mapping(f->domain, i); | |
181 | f->used_irqs++; | |
182 | } | |
183 | ||
bdd272cb | 184 | pr_info("FPGA IRQ chip %d \"%s\" @ %p, %u irqs", |
3108e6ab | 185 | fpga_irq_id, name, base, f->used_irqs); |
bdd272cb LW |
186 | if (parent_irq != -1) |
187 | pr_cont(", parent IRQ: %d\n", parent_irq); | |
188 | else | |
189 | pr_cont("\n"); | |
3a6ca8c5 LW |
190 | |
191 | fpga_irq_id++; | |
9bc15031 | 192 | } |
c41b16f8 | 193 | |
9bc15031 LW |
194 | #ifdef CONFIG_OF |
195 | int __init fpga_irq_of_init(struct device_node *node, | |
196 | struct device_node *parent) | |
197 | { | |
9bc15031 LW |
198 | void __iomem *base; |
199 | u32 clear_mask; | |
200 | u32 valid_mask; | |
bdd272cb | 201 | int parent_irq; |
9bc15031 LW |
202 | |
203 | if (WARN_ON(!node)) | |
204 | return -ENODEV; | |
205 | ||
206 | base = of_iomap(node, 0); | |
207 | WARN(!base, "unable to map fpga irq registers\n"); | |
208 | ||
209 | if (of_property_read_u32(node, "clear-mask", &clear_mask)) | |
210 | clear_mask = 0; | |
211 | ||
212 | if (of_property_read_u32(node, "valid-mask", &valid_mask)) | |
213 | valid_mask = 0; | |
214 | ||
6a214a28 SE |
215 | writel(clear_mask, base + IRQ_ENABLE_CLEAR); |
216 | writel(clear_mask, base + FIQ_ENABLE_CLEAR); | |
217 | ||
bdd272cb LW |
218 | /* Some chips are cascaded from a parent IRQ */ |
219 | parent_irq = irq_of_parse_and_map(node, 0); | |
2920bc9a RH |
220 | if (!parent_irq) { |
221 | set_handle_irq(fpga_handle_irq); | |
bdd272cb | 222 | parent_irq = -1; |
2920bc9a | 223 | } |
bdd272cb LW |
224 | |
225 | fpga_irq_init(base, node->name, 0, parent_irq, valid_mask, node); | |
9bc15031 | 226 | |
59318461 RH |
227 | /* |
228 | * On Versatile AB/PB, some secondary interrupts have a direct | |
229 | * pass-thru to the primary controller for IRQs 20 and 22-31 which need | |
230 | * to be enabled. See section 3.10 of the Versatile AB user guide. | |
231 | */ | |
232 | if (of_device_is_compatible(node, "arm,versatile-sic")) | |
233 | writel(0xffd00000, base + PIC_ENABLES); | |
234 | ||
9bc15031 | 235 | return 0; |
c41b16f8 | 236 | } |
2920bc9a | 237 | IRQCHIP_DECLARE(arm_fpga, "arm,versatile-fpga-irq", fpga_irq_of_init); |
59318461 | 238 | IRQCHIP_DECLARE(arm_fpga_sic, "arm,versatile-sic", fpga_irq_of_init); |
1adea8b8 | 239 | IRQCHIP_DECLARE(ox810se_rps, "oxsemi,ox810se-rps-irq", fpga_irq_of_init); |
9bc15031 | 240 | #endif |