Commit | Line | Data |
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d7fbc6ca MR |
1 | /* |
2 | * Allwinner A1X SoCs IRQ chip driver. | |
3 | * | |
4 | * Copyright (C) 2012 Maxime Ripard | |
5 | * | |
6 | * Maxime Ripard <maxime.ripard@free-electrons.com> | |
7 | * | |
8 | * Based on code from | |
9 | * Allwinner Technology Co., Ltd. <www.allwinnertech.com> | |
10 | * Benn Huang <benn@allwinnertech.com> | |
11 | * | |
12 | * This file is licensed under the terms of the GNU General Public | |
13 | * License version 2. This program is licensed "as is" without any | |
14 | * warranty of any kind, whether express or implied. | |
15 | */ | |
16 | ||
17 | #include <linux/io.h> | |
18 | #include <linux/irq.h> | |
19 | #include <linux/of.h> | |
20 | #include <linux/of_address.h> | |
21 | #include <linux/of_irq.h> | |
22 | ||
23 | #include <asm/exception.h> | |
24 | #include <asm/mach/irq.h> | |
25 | ||
26 | #include "irqchip.h" | |
27 | ||
28 | #define SUN4I_IRQ_VECTOR_REG 0x00 | |
29 | #define SUN4I_IRQ_PROTECTION_REG 0x08 | |
30 | #define SUN4I_IRQ_NMI_CTRL_REG 0x0c | |
31 | #define SUN4I_IRQ_PENDING_REG(x) (0x10 + 0x4 * x) | |
32 | #define SUN4I_IRQ_FIQ_PENDING_REG(x) (0x20 + 0x4 * x) | |
33 | #define SUN4I_IRQ_ENABLE_REG(x) (0x40 + 0x4 * x) | |
34 | #define SUN4I_IRQ_MASK_REG(x) (0x50 + 0x4 * x) | |
35 | ||
36 | static void __iomem *sun4i_irq_base; | |
37 | static struct irq_domain *sun4i_irq_domain; | |
38 | ||
8783dd3a | 39 | static void __exception_irq_entry sun4i_handle_irq(struct pt_regs *regs); |
d7fbc6ca | 40 | |
baaecfa7 | 41 | static void sun4i_irq_ack(struct irq_data *irqd) |
d7fbc6ca MR |
42 | { |
43 | unsigned int irq = irqd_to_hwirq(irqd); | |
44 | unsigned int irq_off = irq % 32; | |
45 | int reg = irq / 32; | |
46 | u32 val; | |
47 | ||
915b78ce HG |
48 | if (irq != 0) |
49 | return; /* Only IRQ 0 / the ENMI needs to be acked */ | |
50 | ||
d7fbc6ca MR |
51 | val = readl(sun4i_irq_base + SUN4I_IRQ_PENDING_REG(reg)); |
52 | writel(val | (1 << irq_off), | |
53 | sun4i_irq_base + SUN4I_IRQ_PENDING_REG(reg)); | |
54 | } | |
55 | ||
56 | static void sun4i_irq_mask(struct irq_data *irqd) | |
57 | { | |
58 | unsigned int irq = irqd_to_hwirq(irqd); | |
59 | unsigned int irq_off = irq % 32; | |
60 | int reg = irq / 32; | |
61 | u32 val; | |
62 | ||
63 | val = readl(sun4i_irq_base + SUN4I_IRQ_ENABLE_REG(reg)); | |
64 | writel(val & ~(1 << irq_off), | |
65 | sun4i_irq_base + SUN4I_IRQ_ENABLE_REG(reg)); | |
66 | } | |
67 | ||
68 | static void sun4i_irq_unmask(struct irq_data *irqd) | |
69 | { | |
70 | unsigned int irq = irqd_to_hwirq(irqd); | |
71 | unsigned int irq_off = irq % 32; | |
72 | int reg = irq / 32; | |
73 | u32 val; | |
74 | ||
75 | val = readl(sun4i_irq_base + SUN4I_IRQ_ENABLE_REG(reg)); | |
76 | writel(val | (1 << irq_off), | |
77 | sun4i_irq_base + SUN4I_IRQ_ENABLE_REG(reg)); | |
78 | } | |
79 | ||
80 | static struct irq_chip sun4i_irq_chip = { | |
e9df9e22 HG |
81 | .name = "sun4i_irq", |
82 | .irq_eoi = sun4i_irq_ack, | |
83 | .irq_mask = sun4i_irq_mask, | |
84 | .irq_unmask = sun4i_irq_unmask, | |
85 | .flags = IRQCHIP_EOI_THREADED | IRQCHIP_EOI_IF_HANDLED, | |
86 | }; | |
87 | ||
d7fbc6ca MR |
88 | static int sun4i_irq_map(struct irq_domain *d, unsigned int virq, |
89 | irq_hw_number_t hw) | |
90 | { | |
915b78ce | 91 | irq_set_chip_and_handler(virq, &sun4i_irq_chip, handle_fasteoi_irq); |
d7fbc6ca MR |
92 | set_irq_flags(virq, IRQF_VALID | IRQF_PROBE); |
93 | ||
94 | return 0; | |
95 | } | |
96 | ||
97 | static struct irq_domain_ops sun4i_irq_ops = { | |
98 | .map = sun4i_irq_map, | |
99 | .xlate = irq_domain_xlate_onecell, | |
100 | }; | |
101 | ||
102 | static int __init sun4i_of_init(struct device_node *node, | |
103 | struct device_node *parent) | |
104 | { | |
105 | sun4i_irq_base = of_iomap(node, 0); | |
106 | if (!sun4i_irq_base) | |
107 | panic("%s: unable to map IC registers\n", | |
108 | node->full_name); | |
109 | ||
110 | /* Disable all interrupts */ | |
111 | writel(0, sun4i_irq_base + SUN4I_IRQ_ENABLE_REG(0)); | |
112 | writel(0, sun4i_irq_base + SUN4I_IRQ_ENABLE_REG(1)); | |
113 | writel(0, sun4i_irq_base + SUN4I_IRQ_ENABLE_REG(2)); | |
114 | ||
649ff46e | 115 | /* Unmask all the interrupts, ENABLE_REG(x) is used for masking */ |
d7fbc6ca MR |
116 | writel(0, sun4i_irq_base + SUN4I_IRQ_MASK_REG(0)); |
117 | writel(0, sun4i_irq_base + SUN4I_IRQ_MASK_REG(1)); | |
118 | writel(0, sun4i_irq_base + SUN4I_IRQ_MASK_REG(2)); | |
119 | ||
120 | /* Clear all the pending interrupts */ | |
121 | writel(0xffffffff, sun4i_irq_base + SUN4I_IRQ_PENDING_REG(0)); | |
122 | writel(0xffffffff, sun4i_irq_base + SUN4I_IRQ_PENDING_REG(1)); | |
123 | writel(0xffffffff, sun4i_irq_base + SUN4I_IRQ_PENDING_REG(2)); | |
124 | ||
125 | /* Enable protection mode */ | |
126 | writel(0x01, sun4i_irq_base + SUN4I_IRQ_PROTECTION_REG); | |
127 | ||
128 | /* Configure the external interrupt source type */ | |
129 | writel(0x00, sun4i_irq_base + SUN4I_IRQ_NMI_CTRL_REG); | |
130 | ||
131 | sun4i_irq_domain = irq_domain_add_linear(node, 3 * 32, | |
132 | &sun4i_irq_ops, NULL); | |
133 | if (!sun4i_irq_domain) | |
134 | panic("%s: unable to create IRQ domain\n", node->full_name); | |
135 | ||
136 | set_handle_irq(sun4i_handle_irq); | |
137 | ||
138 | return 0; | |
139 | } | |
a7e8b4b5 | 140 | IRQCHIP_DECLARE(allwinner_sun4i_ic, "allwinner,sun4i-a10-ic", sun4i_of_init); |
d7fbc6ca | 141 | |
8783dd3a | 142 | static void __exception_irq_entry sun4i_handle_irq(struct pt_regs *regs) |
d7fbc6ca MR |
143 | { |
144 | u32 irq, hwirq; | |
145 | ||
56af0416 HG |
146 | /* |
147 | * hwirq == 0 can mean one of 3 things: | |
148 | * 1) no more irqs pending | |
149 | * 2) irq 0 pending | |
150 | * 3) spurious irq | |
151 | * So if we immediately get a reading of 0, check the irq-pending reg | |
152 | * to differentiate between 2 and 3. We only do this once to avoid | |
153 | * the extra check in the common case of 1 hapening after having | |
154 | * read the vector-reg once. | |
155 | */ | |
d7fbc6ca | 156 | hwirq = readl(sun4i_irq_base + SUN4I_IRQ_VECTOR_REG) >> 2; |
56af0416 HG |
157 | if (hwirq == 0 && |
158 | !(readl(sun4i_irq_base + SUN4I_IRQ_PENDING_REG(0)) & BIT(0))) | |
159 | return; | |
160 | ||
161 | do { | |
d7fbc6ca MR |
162 | irq = irq_find_mapping(sun4i_irq_domain, hwirq); |
163 | handle_IRQ(irq, regs); | |
164 | hwirq = readl(sun4i_irq_base + SUN4I_IRQ_VECTOR_REG) >> 2; | |
56af0416 | 165 | } while (hwirq != 0); |
d7fbc6ca | 166 | } |