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8de50dc2 | 1 | // SPDX-License-Identifier: GPL-2.0 |
e0720416 AT |
2 | /* |
3 | * Copyright (C) Maxime Coquelin 2015 | |
8de50dc2 | 4 | * Copyright (C) STMicroelectronics 2017 |
e0720416 | 5 | * Author: Maxime Coquelin <mcoquelin.stm32@gmail.com> |
e0720416 AT |
6 | */ |
7 | ||
8 | #include <linux/bitops.h> | |
9 | #include <linux/interrupt.h> | |
10 | #include <linux/io.h> | |
11 | #include <linux/irq.h> | |
12 | #include <linux/irqchip.h> | |
13 | #include <linux/irqchip/chained_irq.h> | |
14 | #include <linux/irqdomain.h> | |
15 | #include <linux/of_address.h> | |
16 | #include <linux/of_irq.h> | |
73958b31 | 17 | #include <linux/syscore_ops.h> |
e0720416 | 18 | |
927abfc4 LB |
19 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
20 | ||
6dd64ee1 LB |
21 | #define IRQS_PER_BANK 32 |
22 | ||
23 | struct stm32_exti_bank { | |
24 | u32 imr_ofst; | |
25 | u32 emr_ofst; | |
26 | u32 rtsr_ofst; | |
27 | u32 ftsr_ofst; | |
28 | u32 swier_ofst; | |
be6230f0 LB |
29 | u32 rpr_ofst; |
30 | u32 fpr_ofst; | |
6dd64ee1 LB |
31 | }; |
32 | ||
be6230f0 LB |
33 | #define UNDEF_REG ~0 |
34 | ||
927abfc4 LB |
35 | struct stm32_desc_irq { |
36 | u32 exti; | |
37 | u32 irq_parent; | |
38 | }; | |
39 | ||
f9fc1745 LB |
40 | struct stm32_exti_drv_data { |
41 | const struct stm32_exti_bank **exti_banks; | |
927abfc4 | 42 | const struct stm32_desc_irq *desc_irqs; |
f9fc1745 | 43 | u32 bank_nr; |
927abfc4 | 44 | u32 irq_nr; |
f9fc1745 LB |
45 | }; |
46 | ||
d9e2b19b | 47 | struct stm32_exti_chip_data { |
f9fc1745 | 48 | struct stm32_exti_host_data *host_data; |
d9e2b19b | 49 | const struct stm32_exti_bank *reg_bank; |
927abfc4 LB |
50 | struct raw_spinlock rlock; |
51 | u32 wake_active; | |
52 | u32 mask_cache; | |
d9e2b19b LB |
53 | u32 rtsr_cache; |
54 | u32 ftsr_cache; | |
55 | }; | |
56 | ||
f9fc1745 LB |
57 | struct stm32_exti_host_data { |
58 | void __iomem *base; | |
59 | struct stm32_exti_chip_data *chips_data; | |
60 | const struct stm32_exti_drv_data *drv_data; | |
61 | }; | |
d9e2b19b | 62 | |
73958b31 LB |
63 | static struct stm32_exti_host_data *stm32_host_data; |
64 | ||
6dd64ee1 LB |
65 | static const struct stm32_exti_bank stm32f4xx_exti_b1 = { |
66 | .imr_ofst = 0x00, | |
67 | .emr_ofst = 0x04, | |
68 | .rtsr_ofst = 0x08, | |
69 | .ftsr_ofst = 0x0C, | |
70 | .swier_ofst = 0x10, | |
be6230f0 LB |
71 | .rpr_ofst = 0x14, |
72 | .fpr_ofst = UNDEF_REG, | |
6dd64ee1 LB |
73 | }; |
74 | ||
75 | static const struct stm32_exti_bank *stm32f4xx_exti_banks[] = { | |
76 | &stm32f4xx_exti_b1, | |
77 | }; | |
78 | ||
f9fc1745 LB |
79 | static const struct stm32_exti_drv_data stm32f4xx_drv_data = { |
80 | .exti_banks = stm32f4xx_exti_banks, | |
81 | .bank_nr = ARRAY_SIZE(stm32f4xx_exti_banks), | |
82 | }; | |
83 | ||
539c603e LB |
84 | static const struct stm32_exti_bank stm32h7xx_exti_b1 = { |
85 | .imr_ofst = 0x80, | |
86 | .emr_ofst = 0x84, | |
87 | .rtsr_ofst = 0x00, | |
88 | .ftsr_ofst = 0x04, | |
89 | .swier_ofst = 0x08, | |
be6230f0 LB |
90 | .rpr_ofst = 0x88, |
91 | .fpr_ofst = UNDEF_REG, | |
539c603e LB |
92 | }; |
93 | ||
94 | static const struct stm32_exti_bank stm32h7xx_exti_b2 = { | |
95 | .imr_ofst = 0x90, | |
96 | .emr_ofst = 0x94, | |
97 | .rtsr_ofst = 0x20, | |
98 | .ftsr_ofst = 0x24, | |
99 | .swier_ofst = 0x28, | |
be6230f0 LB |
100 | .rpr_ofst = 0x98, |
101 | .fpr_ofst = UNDEF_REG, | |
539c603e LB |
102 | }; |
103 | ||
104 | static const struct stm32_exti_bank stm32h7xx_exti_b3 = { | |
105 | .imr_ofst = 0xA0, | |
106 | .emr_ofst = 0xA4, | |
107 | .rtsr_ofst = 0x40, | |
108 | .ftsr_ofst = 0x44, | |
109 | .swier_ofst = 0x48, | |
be6230f0 LB |
110 | .rpr_ofst = 0xA8, |
111 | .fpr_ofst = UNDEF_REG, | |
539c603e LB |
112 | }; |
113 | ||
114 | static const struct stm32_exti_bank *stm32h7xx_exti_banks[] = { | |
115 | &stm32h7xx_exti_b1, | |
116 | &stm32h7xx_exti_b2, | |
117 | &stm32h7xx_exti_b3, | |
118 | }; | |
119 | ||
f9fc1745 LB |
120 | static const struct stm32_exti_drv_data stm32h7xx_drv_data = { |
121 | .exti_banks = stm32h7xx_exti_banks, | |
122 | .bank_nr = ARRAY_SIZE(stm32h7xx_exti_banks), | |
123 | }; | |
124 | ||
927abfc4 LB |
125 | static const struct stm32_exti_bank stm32mp1_exti_b1 = { |
126 | .imr_ofst = 0x80, | |
127 | .emr_ofst = 0x84, | |
128 | .rtsr_ofst = 0x00, | |
129 | .ftsr_ofst = 0x04, | |
130 | .swier_ofst = 0x08, | |
131 | .rpr_ofst = 0x0C, | |
132 | .fpr_ofst = 0x10, | |
133 | }; | |
134 | ||
135 | static const struct stm32_exti_bank stm32mp1_exti_b2 = { | |
136 | .imr_ofst = 0x90, | |
137 | .emr_ofst = 0x94, | |
138 | .rtsr_ofst = 0x20, | |
139 | .ftsr_ofst = 0x24, | |
140 | .swier_ofst = 0x28, | |
141 | .rpr_ofst = 0x2C, | |
142 | .fpr_ofst = 0x30, | |
143 | }; | |
144 | ||
145 | static const struct stm32_exti_bank stm32mp1_exti_b3 = { | |
146 | .imr_ofst = 0xA0, | |
147 | .emr_ofst = 0xA4, | |
148 | .rtsr_ofst = 0x40, | |
149 | .ftsr_ofst = 0x44, | |
150 | .swier_ofst = 0x48, | |
151 | .rpr_ofst = 0x4C, | |
152 | .fpr_ofst = 0x50, | |
153 | }; | |
154 | ||
155 | static const struct stm32_exti_bank *stm32mp1_exti_banks[] = { | |
156 | &stm32mp1_exti_b1, | |
157 | &stm32mp1_exti_b2, | |
158 | &stm32mp1_exti_b3, | |
159 | }; | |
160 | ||
161 | static const struct stm32_desc_irq stm32mp1_desc_irq[] = { | |
6bdd0299 | 162 | { .exti = 0, .irq_parent = 6 }, |
927abfc4 LB |
163 | { .exti = 1, .irq_parent = 7 }, |
164 | { .exti = 2, .irq_parent = 8 }, | |
165 | { .exti = 3, .irq_parent = 9 }, | |
166 | { .exti = 4, .irq_parent = 10 }, | |
167 | { .exti = 5, .irq_parent = 23 }, | |
168 | { .exti = 6, .irq_parent = 64 }, | |
169 | { .exti = 7, .irq_parent = 65 }, | |
170 | { .exti = 8, .irq_parent = 66 }, | |
171 | { .exti = 9, .irq_parent = 67 }, | |
172 | { .exti = 10, .irq_parent = 40 }, | |
173 | { .exti = 11, .irq_parent = 42 }, | |
174 | { .exti = 12, .irq_parent = 76 }, | |
175 | { .exti = 13, .irq_parent = 77 }, | |
176 | { .exti = 14, .irq_parent = 121 }, | |
177 | { .exti = 15, .irq_parent = 127 }, | |
178 | { .exti = 16, .irq_parent = 1 }, | |
179 | { .exti = 65, .irq_parent = 144 }, | |
180 | { .exti = 68, .irq_parent = 143 }, | |
181 | { .exti = 73, .irq_parent = 129 }, | |
182 | }; | |
183 | ||
184 | static const struct stm32_exti_drv_data stm32mp1_drv_data = { | |
185 | .exti_banks = stm32mp1_exti_banks, | |
186 | .bank_nr = ARRAY_SIZE(stm32mp1_exti_banks), | |
187 | .desc_irqs = stm32mp1_desc_irq, | |
188 | .irq_nr = ARRAY_SIZE(stm32mp1_desc_irq), | |
189 | }; | |
190 | ||
191 | static int stm32_exti_to_irq(const struct stm32_exti_drv_data *drv_data, | |
192 | irq_hw_number_t hwirq) | |
193 | { | |
194 | const struct stm32_desc_irq *desc_irq; | |
195 | int i; | |
196 | ||
197 | if (!drv_data->desc_irqs) | |
198 | return -EINVAL; | |
199 | ||
200 | for (i = 0; i < drv_data->irq_nr; i++) { | |
201 | desc_irq = &drv_data->desc_irqs[i]; | |
202 | if (desc_irq->exti == hwirq) | |
203 | return desc_irq->irq_parent; | |
204 | } | |
205 | ||
206 | return -EINVAL; | |
207 | } | |
208 | ||
6dd64ee1 LB |
209 | static unsigned long stm32_exti_pending(struct irq_chip_generic *gc) |
210 | { | |
d9e2b19b LB |
211 | struct stm32_exti_chip_data *chip_data = gc->private; |
212 | const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank; | |
be6230f0 LB |
213 | unsigned long pending; |
214 | ||
215 | pending = irq_reg_readl(gc, stm32_bank->rpr_ofst); | |
216 | if (stm32_bank->fpr_ofst != UNDEF_REG) | |
217 | pending |= irq_reg_readl(gc, stm32_bank->fpr_ofst); | |
6dd64ee1 | 218 | |
be6230f0 | 219 | return pending; |
6dd64ee1 LB |
220 | } |
221 | ||
e0720416 AT |
222 | static void stm32_irq_handler(struct irq_desc *desc) |
223 | { | |
224 | struct irq_domain *domain = irq_desc_get_handler_data(desc); | |
e0720416 | 225 | struct irq_chip *chip = irq_desc_get_chip(desc); |
6dd64ee1 LB |
226 | unsigned int virq, nbanks = domain->gc->num_chips; |
227 | struct irq_chip_generic *gc; | |
e0720416 | 228 | unsigned long pending; |
6dd64ee1 | 229 | int n, i, irq_base = 0; |
e0720416 AT |
230 | |
231 | chained_irq_enter(chip, desc); | |
232 | ||
6dd64ee1 LB |
233 | for (i = 0; i < nbanks; i++, irq_base += IRQS_PER_BANK) { |
234 | gc = irq_get_domain_generic_chip(domain, irq_base); | |
6dd64ee1 LB |
235 | |
236 | while ((pending = stm32_exti_pending(gc))) { | |
237 | for_each_set_bit(n, &pending, IRQS_PER_BANK) { | |
238 | virq = irq_find_mapping(domain, irq_base + n); | |
239 | generic_handle_irq(virq); | |
6dd64ee1 | 240 | } |
e0720416 AT |
241 | } |
242 | } | |
243 | ||
244 | chained_irq_exit(chip, desc); | |
245 | } | |
246 | ||
5a2490e0 LB |
247 | static int stm32_exti_set_type(struct irq_data *d, |
248 | unsigned int type, u32 *rtsr, u32 *ftsr) | |
e0720416 | 249 | { |
5a2490e0 | 250 | u32 mask = BIT(d->hwirq % IRQS_PER_BANK); |
e0720416 AT |
251 | |
252 | switch (type) { | |
253 | case IRQ_TYPE_EDGE_RISING: | |
5a2490e0 LB |
254 | *rtsr |= mask; |
255 | *ftsr &= ~mask; | |
e0720416 AT |
256 | break; |
257 | case IRQ_TYPE_EDGE_FALLING: | |
5a2490e0 LB |
258 | *rtsr &= ~mask; |
259 | *ftsr |= mask; | |
e0720416 AT |
260 | break; |
261 | case IRQ_TYPE_EDGE_BOTH: | |
5a2490e0 LB |
262 | *rtsr |= mask; |
263 | *ftsr |= mask; | |
e0720416 AT |
264 | break; |
265 | default: | |
e0720416 AT |
266 | return -EINVAL; |
267 | } | |
268 | ||
5a2490e0 LB |
269 | return 0; |
270 | } | |
271 | ||
272 | static int stm32_irq_set_type(struct irq_data *d, unsigned int type) | |
273 | { | |
274 | struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); | |
275 | struct stm32_exti_chip_data *chip_data = gc->private; | |
276 | const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank; | |
277 | u32 rtsr, ftsr; | |
278 | int err; | |
279 | ||
280 | irq_gc_lock(gc); | |
281 | ||
282 | rtsr = irq_reg_readl(gc, stm32_bank->rtsr_ofst); | |
283 | ftsr = irq_reg_readl(gc, stm32_bank->ftsr_ofst); | |
284 | ||
285 | err = stm32_exti_set_type(d, type, &rtsr, &ftsr); | |
286 | if (err) { | |
287 | irq_gc_unlock(gc); | |
288 | return err; | |
289 | } | |
290 | ||
6dd64ee1 LB |
291 | irq_reg_writel(gc, rtsr, stm32_bank->rtsr_ofst); |
292 | irq_reg_writel(gc, ftsr, stm32_bank->ftsr_ofst); | |
e0720416 AT |
293 | |
294 | irq_gc_unlock(gc); | |
295 | ||
296 | return 0; | |
297 | } | |
298 | ||
5a2490e0 LB |
299 | static void stm32_chip_suspend(struct stm32_exti_chip_data *chip_data, |
300 | u32 wake_active) | |
e0720416 | 301 | { |
d9e2b19b | 302 | const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank; |
5a2490e0 | 303 | void __iomem *base = chip_data->host_data->base; |
e0720416 | 304 | |
d9e2b19b | 305 | /* save rtsr, ftsr registers */ |
5a2490e0 LB |
306 | chip_data->rtsr_cache = readl_relaxed(base + stm32_bank->rtsr_ofst); |
307 | chip_data->ftsr_cache = readl_relaxed(base + stm32_bank->ftsr_ofst); | |
d9e2b19b | 308 | |
5a2490e0 LB |
309 | writel_relaxed(wake_active, base + stm32_bank->imr_ofst); |
310 | } | |
e0720416 | 311 | |
5a2490e0 LB |
312 | static void stm32_chip_resume(struct stm32_exti_chip_data *chip_data, |
313 | u32 mask_cache) | |
314 | { | |
315 | const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank; | |
316 | void __iomem *base = chip_data->host_data->base; | |
317 | ||
318 | /* restore rtsr, ftsr, registers */ | |
319 | writel_relaxed(chip_data->rtsr_cache, base + stm32_bank->rtsr_ofst); | |
320 | writel_relaxed(chip_data->ftsr_cache, base + stm32_bank->ftsr_ofst); | |
321 | ||
322 | writel_relaxed(mask_cache, base + stm32_bank->imr_ofst); | |
d9e2b19b | 323 | } |
e0720416 | 324 | |
5a2490e0 | 325 | static void stm32_irq_suspend(struct irq_chip_generic *gc) |
d9e2b19b LB |
326 | { |
327 | struct stm32_exti_chip_data *chip_data = gc->private; | |
d9e2b19b LB |
328 | |
329 | irq_gc_lock(gc); | |
5a2490e0 LB |
330 | stm32_chip_suspend(chip_data, gc->wake_active); |
331 | irq_gc_unlock(gc); | |
332 | } | |
d9e2b19b | 333 | |
5a2490e0 LB |
334 | static void stm32_irq_resume(struct irq_chip_generic *gc) |
335 | { | |
336 | struct stm32_exti_chip_data *chip_data = gc->private; | |
d9e2b19b | 337 | |
5a2490e0 LB |
338 | irq_gc_lock(gc); |
339 | stm32_chip_resume(chip_data, gc->mask_cache); | |
d9e2b19b | 340 | irq_gc_unlock(gc); |
e0720416 AT |
341 | } |
342 | ||
343 | static int stm32_exti_alloc(struct irq_domain *d, unsigned int virq, | |
344 | unsigned int nr_irqs, void *data) | |
345 | { | |
e0720416 AT |
346 | struct irq_fwspec *fwspec = data; |
347 | irq_hw_number_t hwirq; | |
348 | ||
349 | hwirq = fwspec->param[0]; | |
350 | ||
351 | irq_map_generic_chip(d, virq, hwirq); | |
e0720416 AT |
352 | |
353 | return 0; | |
354 | } | |
355 | ||
356 | static void stm32_exti_free(struct irq_domain *d, unsigned int virq, | |
357 | unsigned int nr_irqs) | |
358 | { | |
359 | struct irq_data *data = irq_domain_get_irq_data(d, virq); | |
360 | ||
361 | irq_domain_reset_irq_data(data); | |
362 | } | |
363 | ||
ea80aa2a | 364 | static const struct irq_domain_ops irq_exti_domain_ops = { |
e0720416 | 365 | .map = irq_map_generic_chip, |
e0720416 AT |
366 | .alloc = stm32_exti_alloc, |
367 | .free = stm32_exti_free, | |
368 | }; | |
369 | ||
be6230f0 LB |
370 | static void stm32_irq_ack(struct irq_data *d) |
371 | { | |
372 | struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); | |
d9e2b19b LB |
373 | struct stm32_exti_chip_data *chip_data = gc->private; |
374 | const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank; | |
be6230f0 LB |
375 | |
376 | irq_gc_lock(gc); | |
377 | ||
378 | irq_reg_writel(gc, d->mask, stm32_bank->rpr_ofst); | |
379 | if (stm32_bank->fpr_ofst != UNDEF_REG) | |
380 | irq_reg_writel(gc, d->mask, stm32_bank->fpr_ofst); | |
381 | ||
382 | irq_gc_unlock(gc); | |
383 | } | |
927abfc4 LB |
384 | |
385 | static inline u32 stm32_exti_set_bit(struct irq_data *d, u32 reg) | |
386 | { | |
387 | struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d); | |
388 | void __iomem *base = chip_data->host_data->base; | |
389 | u32 val; | |
390 | ||
391 | val = readl_relaxed(base + reg); | |
392 | val |= BIT(d->hwirq % IRQS_PER_BANK); | |
393 | writel_relaxed(val, base + reg); | |
394 | ||
395 | return val; | |
396 | } | |
397 | ||
398 | static inline u32 stm32_exti_clr_bit(struct irq_data *d, u32 reg) | |
399 | { | |
400 | struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d); | |
401 | void __iomem *base = chip_data->host_data->base; | |
402 | u32 val; | |
403 | ||
404 | val = readl_relaxed(base + reg); | |
405 | val &= ~BIT(d->hwirq % IRQS_PER_BANK); | |
406 | writel_relaxed(val, base + reg); | |
407 | ||
408 | return val; | |
409 | } | |
410 | ||
411 | static void stm32_exti_h_eoi(struct irq_data *d) | |
412 | { | |
413 | struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d); | |
414 | const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank; | |
415 | ||
416 | raw_spin_lock(&chip_data->rlock); | |
417 | ||
418 | stm32_exti_set_bit(d, stm32_bank->rpr_ofst); | |
419 | if (stm32_bank->fpr_ofst != UNDEF_REG) | |
420 | stm32_exti_set_bit(d, stm32_bank->fpr_ofst); | |
421 | ||
422 | raw_spin_unlock(&chip_data->rlock); | |
423 | ||
424 | if (d->parent_data->chip) | |
425 | irq_chip_eoi_parent(d); | |
426 | } | |
427 | ||
428 | static void stm32_exti_h_mask(struct irq_data *d) | |
429 | { | |
430 | struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d); | |
431 | const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank; | |
432 | ||
433 | raw_spin_lock(&chip_data->rlock); | |
434 | chip_data->mask_cache = stm32_exti_clr_bit(d, stm32_bank->imr_ofst); | |
435 | raw_spin_unlock(&chip_data->rlock); | |
436 | ||
437 | if (d->parent_data->chip) | |
438 | irq_chip_mask_parent(d); | |
439 | } | |
440 | ||
441 | static void stm32_exti_h_unmask(struct irq_data *d) | |
442 | { | |
443 | struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d); | |
444 | const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank; | |
445 | ||
446 | raw_spin_lock(&chip_data->rlock); | |
447 | chip_data->mask_cache = stm32_exti_set_bit(d, stm32_bank->imr_ofst); | |
448 | raw_spin_unlock(&chip_data->rlock); | |
449 | ||
450 | if (d->parent_data->chip) | |
451 | irq_chip_unmask_parent(d); | |
452 | } | |
453 | ||
454 | static int stm32_exti_h_set_type(struct irq_data *d, unsigned int type) | |
455 | { | |
456 | struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d); | |
457 | const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank; | |
458 | void __iomem *base = chip_data->host_data->base; | |
459 | u32 rtsr, ftsr; | |
460 | int err; | |
461 | ||
462 | raw_spin_lock(&chip_data->rlock); | |
463 | rtsr = readl_relaxed(base + stm32_bank->rtsr_ofst); | |
464 | ftsr = readl_relaxed(base + stm32_bank->ftsr_ofst); | |
465 | ||
466 | err = stm32_exti_set_type(d, type, &rtsr, &ftsr); | |
467 | if (err) { | |
468 | raw_spin_unlock(&chip_data->rlock); | |
469 | return err; | |
470 | } | |
471 | ||
472 | writel_relaxed(rtsr, base + stm32_bank->rtsr_ofst); | |
473 | writel_relaxed(ftsr, base + stm32_bank->ftsr_ofst); | |
474 | raw_spin_unlock(&chip_data->rlock); | |
475 | ||
476 | return 0; | |
477 | } | |
478 | ||
479 | static int stm32_exti_h_set_wake(struct irq_data *d, unsigned int on) | |
480 | { | |
481 | struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d); | |
482 | u32 mask = BIT(d->hwirq % IRQS_PER_BANK); | |
483 | ||
484 | raw_spin_lock(&chip_data->rlock); | |
485 | ||
486 | if (on) | |
487 | chip_data->wake_active |= mask; | |
488 | else | |
489 | chip_data->wake_active &= ~mask; | |
490 | ||
491 | raw_spin_unlock(&chip_data->rlock); | |
492 | ||
493 | return 0; | |
494 | } | |
495 | ||
496 | static int stm32_exti_h_set_affinity(struct irq_data *d, | |
497 | const struct cpumask *dest, bool force) | |
498 | { | |
499 | if (d->parent_data->chip) | |
500 | return irq_chip_set_affinity_parent(d, dest, force); | |
501 | ||
502 | return -EINVAL; | |
503 | } | |
504 | ||
73958b31 LB |
505 | #ifdef CONFIG_PM |
506 | static int stm32_exti_h_suspend(void) | |
507 | { | |
508 | struct stm32_exti_chip_data *chip_data; | |
509 | int i; | |
510 | ||
511 | for (i = 0; i < stm32_host_data->drv_data->bank_nr; i++) { | |
512 | chip_data = &stm32_host_data->chips_data[i]; | |
513 | raw_spin_lock(&chip_data->rlock); | |
514 | stm32_chip_suspend(chip_data, chip_data->wake_active); | |
515 | raw_spin_unlock(&chip_data->rlock); | |
516 | } | |
517 | ||
518 | return 0; | |
519 | } | |
520 | ||
521 | static void stm32_exti_h_resume(void) | |
522 | { | |
523 | struct stm32_exti_chip_data *chip_data; | |
524 | int i; | |
525 | ||
526 | for (i = 0; i < stm32_host_data->drv_data->bank_nr; i++) { | |
527 | chip_data = &stm32_host_data->chips_data[i]; | |
528 | raw_spin_lock(&chip_data->rlock); | |
529 | stm32_chip_resume(chip_data, chip_data->mask_cache); | |
530 | raw_spin_unlock(&chip_data->rlock); | |
531 | } | |
532 | } | |
533 | ||
534 | static struct syscore_ops stm32_exti_h_syscore_ops = { | |
535 | .suspend = stm32_exti_h_suspend, | |
536 | .resume = stm32_exti_h_resume, | |
537 | }; | |
538 | ||
539 | static void stm32_exti_h_syscore_init(void) | |
540 | { | |
541 | register_syscore_ops(&stm32_exti_h_syscore_ops); | |
542 | } | |
543 | #else | |
544 | static inline void stm32_exti_h_syscore_init(void) {} | |
545 | #endif | |
546 | ||
927abfc4 LB |
547 | static struct irq_chip stm32_exti_h_chip = { |
548 | .name = "stm32-exti-h", | |
549 | .irq_eoi = stm32_exti_h_eoi, | |
550 | .irq_mask = stm32_exti_h_mask, | |
551 | .irq_unmask = stm32_exti_h_unmask, | |
552 | .irq_retrigger = irq_chip_retrigger_hierarchy, | |
553 | .irq_set_type = stm32_exti_h_set_type, | |
554 | .irq_set_wake = stm32_exti_h_set_wake, | |
555 | .flags = IRQCHIP_MASK_ON_SUSPEND, | |
a84277bf | 556 | .irq_set_affinity = IS_ENABLED(CONFIG_SMP) ? stm32_exti_h_set_affinity : NULL, |
927abfc4 LB |
557 | }; |
558 | ||
559 | static int stm32_exti_h_domain_alloc(struct irq_domain *dm, | |
560 | unsigned int virq, | |
561 | unsigned int nr_irqs, void *data) | |
562 | { | |
563 | struct stm32_exti_host_data *host_data = dm->host_data; | |
564 | struct stm32_exti_chip_data *chip_data; | |
565 | struct irq_fwspec *fwspec = data; | |
566 | struct irq_fwspec p_fwspec; | |
567 | irq_hw_number_t hwirq; | |
568 | int p_irq, bank; | |
569 | ||
570 | hwirq = fwspec->param[0]; | |
571 | bank = hwirq / IRQS_PER_BANK; | |
572 | chip_data = &host_data->chips_data[bank]; | |
573 | ||
574 | irq_domain_set_hwirq_and_chip(dm, virq, hwirq, | |
575 | &stm32_exti_h_chip, chip_data); | |
576 | ||
577 | p_irq = stm32_exti_to_irq(host_data->drv_data, hwirq); | |
578 | if (p_irq >= 0) { | |
579 | p_fwspec.fwnode = dm->parent->fwnode; | |
580 | p_fwspec.param_count = 3; | |
581 | p_fwspec.param[0] = GIC_SPI; | |
582 | p_fwspec.param[1] = p_irq; | |
583 | p_fwspec.param[2] = IRQ_TYPE_LEVEL_HIGH; | |
584 | ||
585 | return irq_domain_alloc_irqs_parent(dm, virq, 1, &p_fwspec); | |
586 | } | |
587 | ||
588 | return 0; | |
589 | } | |
590 | ||
f9fc1745 LB |
591 | static struct |
592 | stm32_exti_host_data *stm32_exti_host_init(const struct stm32_exti_drv_data *dd, | |
593 | struct device_node *node) | |
594 | { | |
595 | struct stm32_exti_host_data *host_data; | |
596 | ||
597 | host_data = kzalloc(sizeof(*host_data), GFP_KERNEL); | |
598 | if (!host_data) | |
599 | return NULL; | |
600 | ||
601 | host_data->drv_data = dd; | |
602 | host_data->chips_data = kcalloc(dd->bank_nr, | |
603 | sizeof(struct stm32_exti_chip_data), | |
604 | GFP_KERNEL); | |
605 | if (!host_data->chips_data) | |
4096165d | 606 | goto free_host_data; |
f9fc1745 LB |
607 | |
608 | host_data->base = of_iomap(node, 0); | |
609 | if (!host_data->base) { | |
610 | pr_err("%pOF: Unable to map registers\n", node); | |
4096165d | 611 | goto free_chips_data; |
f9fc1745 | 612 | } |
be6230f0 | 613 | |
73958b31 LB |
614 | stm32_host_data = host_data; |
615 | ||
f9fc1745 | 616 | return host_data; |
4096165d DC |
617 | |
618 | free_chips_data: | |
619 | kfree(host_data->chips_data); | |
620 | free_host_data: | |
621 | kfree(host_data); | |
622 | ||
623 | return NULL; | |
f9fc1745 LB |
624 | } |
625 | ||
626 | static struct | |
627 | stm32_exti_chip_data *stm32_exti_chip_init(struct stm32_exti_host_data *h_data, | |
628 | u32 bank_idx, | |
629 | struct device_node *node) | |
630 | { | |
631 | const struct stm32_exti_bank *stm32_bank; | |
632 | struct stm32_exti_chip_data *chip_data; | |
633 | void __iomem *base = h_data->base; | |
634 | u32 irqs_mask; | |
635 | ||
636 | stm32_bank = h_data->drv_data->exti_banks[bank_idx]; | |
637 | chip_data = &h_data->chips_data[bank_idx]; | |
638 | chip_data->host_data = h_data; | |
639 | chip_data->reg_bank = stm32_bank; | |
640 | ||
927abfc4 LB |
641 | raw_spin_lock_init(&chip_data->rlock); |
642 | ||
f9fc1745 LB |
643 | /* Determine number of irqs supported */ |
644 | writel_relaxed(~0UL, base + stm32_bank->rtsr_ofst); | |
645 | irqs_mask = readl_relaxed(base + stm32_bank->rtsr_ofst); | |
646 | ||
647 | /* | |
648 | * This IP has no reset, so after hot reboot we should | |
649 | * clear registers to avoid residue | |
650 | */ | |
651 | writel_relaxed(0, base + stm32_bank->imr_ofst); | |
652 | writel_relaxed(0, base + stm32_bank->emr_ofst); | |
653 | writel_relaxed(0, base + stm32_bank->rtsr_ofst); | |
654 | writel_relaxed(0, base + stm32_bank->ftsr_ofst); | |
655 | writel_relaxed(~0UL, base + stm32_bank->rpr_ofst); | |
656 | if (stm32_bank->fpr_ofst != UNDEF_REG) | |
657 | writel_relaxed(~0UL, base + stm32_bank->fpr_ofst); | |
658 | ||
659 | pr_info("%s: bank%d, External IRQs available:%#x\n", | |
660 | node->full_name, bank_idx, irqs_mask); | |
661 | ||
662 | return chip_data; | |
663 | } | |
664 | ||
665 | static int __init stm32_exti_init(const struct stm32_exti_drv_data *drv_data, | |
666 | struct device_node *node) | |
e0720416 | 667 | { |
f9fc1745 | 668 | struct stm32_exti_host_data *host_data; |
e0720416 | 669 | unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN; |
f9fc1745 | 670 | int nr_irqs, ret, i; |
e0720416 AT |
671 | struct irq_chip_generic *gc; |
672 | struct irq_domain *domain; | |
e0720416 | 673 | |
f9fc1745 | 674 | host_data = stm32_exti_host_init(drv_data, node); |
4096165d DC |
675 | if (!host_data) |
676 | return -ENOMEM; | |
e0720416 | 677 | |
f9fc1745 | 678 | domain = irq_domain_add_linear(node, drv_data->bank_nr * IRQS_PER_BANK, |
e0720416 AT |
679 | &irq_exti_domain_ops, NULL); |
680 | if (!domain) { | |
681 | pr_err("%s: Could not register interrupt domain.\n", | |
6dd64ee1 | 682 | node->name); |
e0720416 AT |
683 | ret = -ENOMEM; |
684 | goto out_unmap; | |
685 | } | |
686 | ||
6dd64ee1 | 687 | ret = irq_alloc_domain_generic_chips(domain, IRQS_PER_BANK, 1, "exti", |
e0720416 AT |
688 | handle_edge_irq, clr, 0, 0); |
689 | if (ret) { | |
e81f54c6 | 690 | pr_err("%pOF: Could not allocate generic interrupt chip.\n", |
ea80aa2a | 691 | node); |
e0720416 AT |
692 | goto out_free_domain; |
693 | } | |
694 | ||
f9fc1745 LB |
695 | for (i = 0; i < drv_data->bank_nr; i++) { |
696 | const struct stm32_exti_bank *stm32_bank; | |
697 | struct stm32_exti_chip_data *chip_data; | |
6dd64ee1 | 698 | |
f9fc1745 LB |
699 | stm32_bank = drv_data->exti_banks[i]; |
700 | chip_data = stm32_exti_chip_init(host_data, i, node); | |
d9e2b19b | 701 | |
6dd64ee1 LB |
702 | gc = irq_get_domain_generic_chip(domain, i * IRQS_PER_BANK); |
703 | ||
f9fc1745 | 704 | gc->reg_base = host_data->base; |
6dd64ee1 | 705 | gc->chip_types->type = IRQ_TYPE_EDGE_BOTH; |
be6230f0 | 706 | gc->chip_types->chip.irq_ack = stm32_irq_ack; |
6dd64ee1 LB |
707 | gc->chip_types->chip.irq_mask = irq_gc_mask_clr_bit; |
708 | gc->chip_types->chip.irq_unmask = irq_gc_mask_set_bit; | |
709 | gc->chip_types->chip.irq_set_type = stm32_irq_set_type; | |
d9e2b19b LB |
710 | gc->chip_types->chip.irq_set_wake = irq_gc_set_wake; |
711 | gc->suspend = stm32_irq_suspend; | |
712 | gc->resume = stm32_irq_resume; | |
713 | gc->wake_enabled = IRQ_MSK(IRQS_PER_BANK); | |
714 | ||
6dd64ee1 | 715 | gc->chip_types->regs.mask = stm32_bank->imr_ofst; |
d9e2b19b | 716 | gc->private = (void *)chip_data; |
6dd64ee1 | 717 | } |
e0720416 AT |
718 | |
719 | nr_irqs = of_irq_count(node); | |
720 | for (i = 0; i < nr_irqs; i++) { | |
721 | unsigned int irq = irq_of_parse_and_map(node, i); | |
722 | ||
723 | irq_set_handler_data(irq, domain); | |
724 | irq_set_chained_handler(irq, stm32_irq_handler); | |
725 | } | |
726 | ||
727 | return 0; | |
728 | ||
729 | out_free_domain: | |
730 | irq_domain_remove(domain); | |
731 | out_unmap: | |
f9fc1745 | 732 | iounmap(host_data->base); |
f9fc1745 LB |
733 | kfree(host_data->chips_data); |
734 | kfree(host_data); | |
e0720416 AT |
735 | return ret; |
736 | } | |
737 | ||
927abfc4 LB |
738 | static const struct irq_domain_ops stm32_exti_h_domain_ops = { |
739 | .alloc = stm32_exti_h_domain_alloc, | |
740 | .free = irq_domain_free_irqs_common, | |
741 | }; | |
742 | ||
743 | static int | |
744 | __init stm32_exti_hierarchy_init(const struct stm32_exti_drv_data *drv_data, | |
745 | struct device_node *node, | |
746 | struct device_node *parent) | |
747 | { | |
748 | struct irq_domain *parent_domain, *domain; | |
749 | struct stm32_exti_host_data *host_data; | |
750 | int ret, i; | |
751 | ||
752 | parent_domain = irq_find_host(parent); | |
753 | if (!parent_domain) { | |
754 | pr_err("interrupt-parent not found\n"); | |
755 | return -EINVAL; | |
756 | } | |
757 | ||
758 | host_data = stm32_exti_host_init(drv_data, node); | |
4096165d DC |
759 | if (!host_data) |
760 | return -ENOMEM; | |
927abfc4 LB |
761 | |
762 | for (i = 0; i < drv_data->bank_nr; i++) | |
763 | stm32_exti_chip_init(host_data, i, node); | |
764 | ||
765 | domain = irq_domain_add_hierarchy(parent_domain, 0, | |
766 | drv_data->bank_nr * IRQS_PER_BANK, | |
767 | node, &stm32_exti_h_domain_ops, | |
768 | host_data); | |
769 | ||
770 | if (!domain) { | |
771 | pr_err("%s: Could not register exti domain.\n", node->name); | |
772 | ret = -ENOMEM; | |
773 | goto out_unmap; | |
774 | } | |
775 | ||
73958b31 LB |
776 | stm32_exti_h_syscore_init(); |
777 | ||
927abfc4 LB |
778 | return 0; |
779 | ||
780 | out_unmap: | |
781 | iounmap(host_data->base); | |
927abfc4 LB |
782 | kfree(host_data->chips_data); |
783 | kfree(host_data); | |
784 | return ret; | |
785 | } | |
786 | ||
6dd64ee1 LB |
787 | static int __init stm32f4_exti_of_init(struct device_node *np, |
788 | struct device_node *parent) | |
789 | { | |
f9fc1745 | 790 | return stm32_exti_init(&stm32f4xx_drv_data, np); |
6dd64ee1 LB |
791 | } |
792 | ||
793 | IRQCHIP_DECLARE(stm32f4_exti, "st,stm32-exti", stm32f4_exti_of_init); | |
539c603e LB |
794 | |
795 | static int __init stm32h7_exti_of_init(struct device_node *np, | |
796 | struct device_node *parent) | |
797 | { | |
f9fc1745 | 798 | return stm32_exti_init(&stm32h7xx_drv_data, np); |
539c603e LB |
799 | } |
800 | ||
801 | IRQCHIP_DECLARE(stm32h7_exti, "st,stm32h7-exti", stm32h7_exti_of_init); | |
927abfc4 LB |
802 | |
803 | static int __init stm32mp1_exti_of_init(struct device_node *np, | |
804 | struct device_node *parent) | |
805 | { | |
806 | return stm32_exti_hierarchy_init(&stm32mp1_drv_data, np, parent); | |
807 | } | |
808 | ||
809 | IRQCHIP_DECLARE(stm32mp1_exti, "st,stm32mp1-exti", stm32mp1_exti_of_init); |