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8de50dc2 | 1 | // SPDX-License-Identifier: GPL-2.0 |
e0720416 AT |
2 | /* |
3 | * Copyright (C) Maxime Coquelin 2015 | |
8de50dc2 | 4 | * Copyright (C) STMicroelectronics 2017 |
e0720416 | 5 | * Author: Maxime Coquelin <mcoquelin.stm32@gmail.com> |
e0720416 AT |
6 | */ |
7 | ||
8 | #include <linux/bitops.h> | |
9 | #include <linux/interrupt.h> | |
10 | #include <linux/io.h> | |
11 | #include <linux/irq.h> | |
12 | #include <linux/irqchip.h> | |
13 | #include <linux/irqchip/chained_irq.h> | |
14 | #include <linux/irqdomain.h> | |
15 | #include <linux/of_address.h> | |
16 | #include <linux/of_irq.h> | |
17 | ||
927abfc4 LB |
18 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
19 | ||
6dd64ee1 LB |
20 | #define IRQS_PER_BANK 32 |
21 | ||
22 | struct stm32_exti_bank { | |
23 | u32 imr_ofst; | |
24 | u32 emr_ofst; | |
25 | u32 rtsr_ofst; | |
26 | u32 ftsr_ofst; | |
27 | u32 swier_ofst; | |
be6230f0 LB |
28 | u32 rpr_ofst; |
29 | u32 fpr_ofst; | |
6dd64ee1 LB |
30 | }; |
31 | ||
be6230f0 LB |
32 | #define UNDEF_REG ~0 |
33 | ||
927abfc4 LB |
34 | struct stm32_desc_irq { |
35 | u32 exti; | |
36 | u32 irq_parent; | |
37 | }; | |
38 | ||
f9fc1745 LB |
39 | struct stm32_exti_drv_data { |
40 | const struct stm32_exti_bank **exti_banks; | |
927abfc4 | 41 | const struct stm32_desc_irq *desc_irqs; |
f9fc1745 | 42 | u32 bank_nr; |
927abfc4 | 43 | u32 irq_nr; |
f9fc1745 LB |
44 | }; |
45 | ||
d9e2b19b | 46 | struct stm32_exti_chip_data { |
f9fc1745 | 47 | struct stm32_exti_host_data *host_data; |
d9e2b19b | 48 | const struct stm32_exti_bank *reg_bank; |
927abfc4 LB |
49 | struct raw_spinlock rlock; |
50 | u32 wake_active; | |
51 | u32 mask_cache; | |
d9e2b19b LB |
52 | u32 rtsr_cache; |
53 | u32 ftsr_cache; | |
54 | }; | |
55 | ||
f9fc1745 LB |
56 | struct stm32_exti_host_data { |
57 | void __iomem *base; | |
58 | struct stm32_exti_chip_data *chips_data; | |
59 | const struct stm32_exti_drv_data *drv_data; | |
60 | }; | |
d9e2b19b | 61 | |
6dd64ee1 LB |
62 | static const struct stm32_exti_bank stm32f4xx_exti_b1 = { |
63 | .imr_ofst = 0x00, | |
64 | .emr_ofst = 0x04, | |
65 | .rtsr_ofst = 0x08, | |
66 | .ftsr_ofst = 0x0C, | |
67 | .swier_ofst = 0x10, | |
be6230f0 LB |
68 | .rpr_ofst = 0x14, |
69 | .fpr_ofst = UNDEF_REG, | |
6dd64ee1 LB |
70 | }; |
71 | ||
72 | static const struct stm32_exti_bank *stm32f4xx_exti_banks[] = { | |
73 | &stm32f4xx_exti_b1, | |
74 | }; | |
75 | ||
f9fc1745 LB |
76 | static const struct stm32_exti_drv_data stm32f4xx_drv_data = { |
77 | .exti_banks = stm32f4xx_exti_banks, | |
78 | .bank_nr = ARRAY_SIZE(stm32f4xx_exti_banks), | |
79 | }; | |
80 | ||
539c603e LB |
81 | static const struct stm32_exti_bank stm32h7xx_exti_b1 = { |
82 | .imr_ofst = 0x80, | |
83 | .emr_ofst = 0x84, | |
84 | .rtsr_ofst = 0x00, | |
85 | .ftsr_ofst = 0x04, | |
86 | .swier_ofst = 0x08, | |
be6230f0 LB |
87 | .rpr_ofst = 0x88, |
88 | .fpr_ofst = UNDEF_REG, | |
539c603e LB |
89 | }; |
90 | ||
91 | static const struct stm32_exti_bank stm32h7xx_exti_b2 = { | |
92 | .imr_ofst = 0x90, | |
93 | .emr_ofst = 0x94, | |
94 | .rtsr_ofst = 0x20, | |
95 | .ftsr_ofst = 0x24, | |
96 | .swier_ofst = 0x28, | |
be6230f0 LB |
97 | .rpr_ofst = 0x98, |
98 | .fpr_ofst = UNDEF_REG, | |
539c603e LB |
99 | }; |
100 | ||
101 | static const struct stm32_exti_bank stm32h7xx_exti_b3 = { | |
102 | .imr_ofst = 0xA0, | |
103 | .emr_ofst = 0xA4, | |
104 | .rtsr_ofst = 0x40, | |
105 | .ftsr_ofst = 0x44, | |
106 | .swier_ofst = 0x48, | |
be6230f0 LB |
107 | .rpr_ofst = 0xA8, |
108 | .fpr_ofst = UNDEF_REG, | |
539c603e LB |
109 | }; |
110 | ||
111 | static const struct stm32_exti_bank *stm32h7xx_exti_banks[] = { | |
112 | &stm32h7xx_exti_b1, | |
113 | &stm32h7xx_exti_b2, | |
114 | &stm32h7xx_exti_b3, | |
115 | }; | |
116 | ||
f9fc1745 LB |
117 | static const struct stm32_exti_drv_data stm32h7xx_drv_data = { |
118 | .exti_banks = stm32h7xx_exti_banks, | |
119 | .bank_nr = ARRAY_SIZE(stm32h7xx_exti_banks), | |
120 | }; | |
121 | ||
927abfc4 LB |
122 | static const struct stm32_exti_bank stm32mp1_exti_b1 = { |
123 | .imr_ofst = 0x80, | |
124 | .emr_ofst = 0x84, | |
125 | .rtsr_ofst = 0x00, | |
126 | .ftsr_ofst = 0x04, | |
127 | .swier_ofst = 0x08, | |
128 | .rpr_ofst = 0x0C, | |
129 | .fpr_ofst = 0x10, | |
130 | }; | |
131 | ||
132 | static const struct stm32_exti_bank stm32mp1_exti_b2 = { | |
133 | .imr_ofst = 0x90, | |
134 | .emr_ofst = 0x94, | |
135 | .rtsr_ofst = 0x20, | |
136 | .ftsr_ofst = 0x24, | |
137 | .swier_ofst = 0x28, | |
138 | .rpr_ofst = 0x2C, | |
139 | .fpr_ofst = 0x30, | |
140 | }; | |
141 | ||
142 | static const struct stm32_exti_bank stm32mp1_exti_b3 = { | |
143 | .imr_ofst = 0xA0, | |
144 | .emr_ofst = 0xA4, | |
145 | .rtsr_ofst = 0x40, | |
146 | .ftsr_ofst = 0x44, | |
147 | .swier_ofst = 0x48, | |
148 | .rpr_ofst = 0x4C, | |
149 | .fpr_ofst = 0x50, | |
150 | }; | |
151 | ||
152 | static const struct stm32_exti_bank *stm32mp1_exti_banks[] = { | |
153 | &stm32mp1_exti_b1, | |
154 | &stm32mp1_exti_b2, | |
155 | &stm32mp1_exti_b3, | |
156 | }; | |
157 | ||
158 | static const struct stm32_desc_irq stm32mp1_desc_irq[] = { | |
159 | { .exti = 1, .irq_parent = 7 }, | |
160 | { .exti = 2, .irq_parent = 8 }, | |
161 | { .exti = 3, .irq_parent = 9 }, | |
162 | { .exti = 4, .irq_parent = 10 }, | |
163 | { .exti = 5, .irq_parent = 23 }, | |
164 | { .exti = 6, .irq_parent = 64 }, | |
165 | { .exti = 7, .irq_parent = 65 }, | |
166 | { .exti = 8, .irq_parent = 66 }, | |
167 | { .exti = 9, .irq_parent = 67 }, | |
168 | { .exti = 10, .irq_parent = 40 }, | |
169 | { .exti = 11, .irq_parent = 42 }, | |
170 | { .exti = 12, .irq_parent = 76 }, | |
171 | { .exti = 13, .irq_parent = 77 }, | |
172 | { .exti = 14, .irq_parent = 121 }, | |
173 | { .exti = 15, .irq_parent = 127 }, | |
174 | { .exti = 16, .irq_parent = 1 }, | |
175 | { .exti = 65, .irq_parent = 144 }, | |
176 | { .exti = 68, .irq_parent = 143 }, | |
177 | { .exti = 73, .irq_parent = 129 }, | |
178 | }; | |
179 | ||
180 | static const struct stm32_exti_drv_data stm32mp1_drv_data = { | |
181 | .exti_banks = stm32mp1_exti_banks, | |
182 | .bank_nr = ARRAY_SIZE(stm32mp1_exti_banks), | |
183 | .desc_irqs = stm32mp1_desc_irq, | |
184 | .irq_nr = ARRAY_SIZE(stm32mp1_desc_irq), | |
185 | }; | |
186 | ||
187 | static int stm32_exti_to_irq(const struct stm32_exti_drv_data *drv_data, | |
188 | irq_hw_number_t hwirq) | |
189 | { | |
190 | const struct stm32_desc_irq *desc_irq; | |
191 | int i; | |
192 | ||
193 | if (!drv_data->desc_irqs) | |
194 | return -EINVAL; | |
195 | ||
196 | for (i = 0; i < drv_data->irq_nr; i++) { | |
197 | desc_irq = &drv_data->desc_irqs[i]; | |
198 | if (desc_irq->exti == hwirq) | |
199 | return desc_irq->irq_parent; | |
200 | } | |
201 | ||
202 | return -EINVAL; | |
203 | } | |
204 | ||
6dd64ee1 LB |
205 | static unsigned long stm32_exti_pending(struct irq_chip_generic *gc) |
206 | { | |
d9e2b19b LB |
207 | struct stm32_exti_chip_data *chip_data = gc->private; |
208 | const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank; | |
be6230f0 LB |
209 | unsigned long pending; |
210 | ||
211 | pending = irq_reg_readl(gc, stm32_bank->rpr_ofst); | |
212 | if (stm32_bank->fpr_ofst != UNDEF_REG) | |
213 | pending |= irq_reg_readl(gc, stm32_bank->fpr_ofst); | |
6dd64ee1 | 214 | |
be6230f0 | 215 | return pending; |
6dd64ee1 LB |
216 | } |
217 | ||
e0720416 AT |
218 | static void stm32_irq_handler(struct irq_desc *desc) |
219 | { | |
220 | struct irq_domain *domain = irq_desc_get_handler_data(desc); | |
e0720416 | 221 | struct irq_chip *chip = irq_desc_get_chip(desc); |
6dd64ee1 LB |
222 | unsigned int virq, nbanks = domain->gc->num_chips; |
223 | struct irq_chip_generic *gc; | |
e0720416 | 224 | unsigned long pending; |
6dd64ee1 | 225 | int n, i, irq_base = 0; |
e0720416 AT |
226 | |
227 | chained_irq_enter(chip, desc); | |
228 | ||
6dd64ee1 LB |
229 | for (i = 0; i < nbanks; i++, irq_base += IRQS_PER_BANK) { |
230 | gc = irq_get_domain_generic_chip(domain, irq_base); | |
6dd64ee1 LB |
231 | |
232 | while ((pending = stm32_exti_pending(gc))) { | |
233 | for_each_set_bit(n, &pending, IRQS_PER_BANK) { | |
234 | virq = irq_find_mapping(domain, irq_base + n); | |
235 | generic_handle_irq(virq); | |
6dd64ee1 | 236 | } |
e0720416 AT |
237 | } |
238 | } | |
239 | ||
240 | chained_irq_exit(chip, desc); | |
241 | } | |
242 | ||
5a2490e0 LB |
243 | static int stm32_exti_set_type(struct irq_data *d, |
244 | unsigned int type, u32 *rtsr, u32 *ftsr) | |
e0720416 | 245 | { |
5a2490e0 | 246 | u32 mask = BIT(d->hwirq % IRQS_PER_BANK); |
e0720416 AT |
247 | |
248 | switch (type) { | |
249 | case IRQ_TYPE_EDGE_RISING: | |
5a2490e0 LB |
250 | *rtsr |= mask; |
251 | *ftsr &= ~mask; | |
e0720416 AT |
252 | break; |
253 | case IRQ_TYPE_EDGE_FALLING: | |
5a2490e0 LB |
254 | *rtsr &= ~mask; |
255 | *ftsr |= mask; | |
e0720416 AT |
256 | break; |
257 | case IRQ_TYPE_EDGE_BOTH: | |
5a2490e0 LB |
258 | *rtsr |= mask; |
259 | *ftsr |= mask; | |
e0720416 AT |
260 | break; |
261 | default: | |
e0720416 AT |
262 | return -EINVAL; |
263 | } | |
264 | ||
5a2490e0 LB |
265 | return 0; |
266 | } | |
267 | ||
268 | static int stm32_irq_set_type(struct irq_data *d, unsigned int type) | |
269 | { | |
270 | struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); | |
271 | struct stm32_exti_chip_data *chip_data = gc->private; | |
272 | const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank; | |
273 | u32 rtsr, ftsr; | |
274 | int err; | |
275 | ||
276 | irq_gc_lock(gc); | |
277 | ||
278 | rtsr = irq_reg_readl(gc, stm32_bank->rtsr_ofst); | |
279 | ftsr = irq_reg_readl(gc, stm32_bank->ftsr_ofst); | |
280 | ||
281 | err = stm32_exti_set_type(d, type, &rtsr, &ftsr); | |
282 | if (err) { | |
283 | irq_gc_unlock(gc); | |
284 | return err; | |
285 | } | |
286 | ||
6dd64ee1 LB |
287 | irq_reg_writel(gc, rtsr, stm32_bank->rtsr_ofst); |
288 | irq_reg_writel(gc, ftsr, stm32_bank->ftsr_ofst); | |
e0720416 AT |
289 | |
290 | irq_gc_unlock(gc); | |
291 | ||
292 | return 0; | |
293 | } | |
294 | ||
5a2490e0 LB |
295 | static void stm32_chip_suspend(struct stm32_exti_chip_data *chip_data, |
296 | u32 wake_active) | |
e0720416 | 297 | { |
d9e2b19b | 298 | const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank; |
5a2490e0 | 299 | void __iomem *base = chip_data->host_data->base; |
e0720416 | 300 | |
d9e2b19b | 301 | /* save rtsr, ftsr registers */ |
5a2490e0 LB |
302 | chip_data->rtsr_cache = readl_relaxed(base + stm32_bank->rtsr_ofst); |
303 | chip_data->ftsr_cache = readl_relaxed(base + stm32_bank->ftsr_ofst); | |
d9e2b19b | 304 | |
5a2490e0 LB |
305 | writel_relaxed(wake_active, base + stm32_bank->imr_ofst); |
306 | } | |
e0720416 | 307 | |
5a2490e0 LB |
308 | static void stm32_chip_resume(struct stm32_exti_chip_data *chip_data, |
309 | u32 mask_cache) | |
310 | { | |
311 | const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank; | |
312 | void __iomem *base = chip_data->host_data->base; | |
313 | ||
314 | /* restore rtsr, ftsr, registers */ | |
315 | writel_relaxed(chip_data->rtsr_cache, base + stm32_bank->rtsr_ofst); | |
316 | writel_relaxed(chip_data->ftsr_cache, base + stm32_bank->ftsr_ofst); | |
317 | ||
318 | writel_relaxed(mask_cache, base + stm32_bank->imr_ofst); | |
d9e2b19b | 319 | } |
e0720416 | 320 | |
5a2490e0 | 321 | static void stm32_irq_suspend(struct irq_chip_generic *gc) |
d9e2b19b LB |
322 | { |
323 | struct stm32_exti_chip_data *chip_data = gc->private; | |
d9e2b19b LB |
324 | |
325 | irq_gc_lock(gc); | |
5a2490e0 LB |
326 | stm32_chip_suspend(chip_data, gc->wake_active); |
327 | irq_gc_unlock(gc); | |
328 | } | |
d9e2b19b | 329 | |
5a2490e0 LB |
330 | static void stm32_irq_resume(struct irq_chip_generic *gc) |
331 | { | |
332 | struct stm32_exti_chip_data *chip_data = gc->private; | |
d9e2b19b | 333 | |
5a2490e0 LB |
334 | irq_gc_lock(gc); |
335 | stm32_chip_resume(chip_data, gc->mask_cache); | |
d9e2b19b | 336 | irq_gc_unlock(gc); |
e0720416 AT |
337 | } |
338 | ||
339 | static int stm32_exti_alloc(struct irq_domain *d, unsigned int virq, | |
340 | unsigned int nr_irqs, void *data) | |
341 | { | |
e0720416 AT |
342 | struct irq_fwspec *fwspec = data; |
343 | irq_hw_number_t hwirq; | |
344 | ||
345 | hwirq = fwspec->param[0]; | |
346 | ||
347 | irq_map_generic_chip(d, virq, hwirq); | |
e0720416 AT |
348 | |
349 | return 0; | |
350 | } | |
351 | ||
352 | static void stm32_exti_free(struct irq_domain *d, unsigned int virq, | |
353 | unsigned int nr_irqs) | |
354 | { | |
355 | struct irq_data *data = irq_domain_get_irq_data(d, virq); | |
356 | ||
357 | irq_domain_reset_irq_data(data); | |
358 | } | |
359 | ||
ea80aa2a | 360 | static const struct irq_domain_ops irq_exti_domain_ops = { |
e0720416 | 361 | .map = irq_map_generic_chip, |
e0720416 AT |
362 | .alloc = stm32_exti_alloc, |
363 | .free = stm32_exti_free, | |
364 | }; | |
365 | ||
be6230f0 LB |
366 | static void stm32_irq_ack(struct irq_data *d) |
367 | { | |
368 | struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); | |
d9e2b19b LB |
369 | struct stm32_exti_chip_data *chip_data = gc->private; |
370 | const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank; | |
be6230f0 LB |
371 | |
372 | irq_gc_lock(gc); | |
373 | ||
374 | irq_reg_writel(gc, d->mask, stm32_bank->rpr_ofst); | |
375 | if (stm32_bank->fpr_ofst != UNDEF_REG) | |
376 | irq_reg_writel(gc, d->mask, stm32_bank->fpr_ofst); | |
377 | ||
378 | irq_gc_unlock(gc); | |
379 | } | |
927abfc4 LB |
380 | |
381 | static inline u32 stm32_exti_set_bit(struct irq_data *d, u32 reg) | |
382 | { | |
383 | struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d); | |
384 | void __iomem *base = chip_data->host_data->base; | |
385 | u32 val; | |
386 | ||
387 | val = readl_relaxed(base + reg); | |
388 | val |= BIT(d->hwirq % IRQS_PER_BANK); | |
389 | writel_relaxed(val, base + reg); | |
390 | ||
391 | return val; | |
392 | } | |
393 | ||
394 | static inline u32 stm32_exti_clr_bit(struct irq_data *d, u32 reg) | |
395 | { | |
396 | struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d); | |
397 | void __iomem *base = chip_data->host_data->base; | |
398 | u32 val; | |
399 | ||
400 | val = readl_relaxed(base + reg); | |
401 | val &= ~BIT(d->hwirq % IRQS_PER_BANK); | |
402 | writel_relaxed(val, base + reg); | |
403 | ||
404 | return val; | |
405 | } | |
406 | ||
407 | static void stm32_exti_h_eoi(struct irq_data *d) | |
408 | { | |
409 | struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d); | |
410 | const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank; | |
411 | ||
412 | raw_spin_lock(&chip_data->rlock); | |
413 | ||
414 | stm32_exti_set_bit(d, stm32_bank->rpr_ofst); | |
415 | if (stm32_bank->fpr_ofst != UNDEF_REG) | |
416 | stm32_exti_set_bit(d, stm32_bank->fpr_ofst); | |
417 | ||
418 | raw_spin_unlock(&chip_data->rlock); | |
419 | ||
420 | if (d->parent_data->chip) | |
421 | irq_chip_eoi_parent(d); | |
422 | } | |
423 | ||
424 | static void stm32_exti_h_mask(struct irq_data *d) | |
425 | { | |
426 | struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d); | |
427 | const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank; | |
428 | ||
429 | raw_spin_lock(&chip_data->rlock); | |
430 | chip_data->mask_cache = stm32_exti_clr_bit(d, stm32_bank->imr_ofst); | |
431 | raw_spin_unlock(&chip_data->rlock); | |
432 | ||
433 | if (d->parent_data->chip) | |
434 | irq_chip_mask_parent(d); | |
435 | } | |
436 | ||
437 | static void stm32_exti_h_unmask(struct irq_data *d) | |
438 | { | |
439 | struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d); | |
440 | const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank; | |
441 | ||
442 | raw_spin_lock(&chip_data->rlock); | |
443 | chip_data->mask_cache = stm32_exti_set_bit(d, stm32_bank->imr_ofst); | |
444 | raw_spin_unlock(&chip_data->rlock); | |
445 | ||
446 | if (d->parent_data->chip) | |
447 | irq_chip_unmask_parent(d); | |
448 | } | |
449 | ||
450 | static int stm32_exti_h_set_type(struct irq_data *d, unsigned int type) | |
451 | { | |
452 | struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d); | |
453 | const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank; | |
454 | void __iomem *base = chip_data->host_data->base; | |
455 | u32 rtsr, ftsr; | |
456 | int err; | |
457 | ||
458 | raw_spin_lock(&chip_data->rlock); | |
459 | rtsr = readl_relaxed(base + stm32_bank->rtsr_ofst); | |
460 | ftsr = readl_relaxed(base + stm32_bank->ftsr_ofst); | |
461 | ||
462 | err = stm32_exti_set_type(d, type, &rtsr, &ftsr); | |
463 | if (err) { | |
464 | raw_spin_unlock(&chip_data->rlock); | |
465 | return err; | |
466 | } | |
467 | ||
468 | writel_relaxed(rtsr, base + stm32_bank->rtsr_ofst); | |
469 | writel_relaxed(ftsr, base + stm32_bank->ftsr_ofst); | |
470 | raw_spin_unlock(&chip_data->rlock); | |
471 | ||
472 | return 0; | |
473 | } | |
474 | ||
475 | static int stm32_exti_h_set_wake(struct irq_data *d, unsigned int on) | |
476 | { | |
477 | struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d); | |
478 | u32 mask = BIT(d->hwirq % IRQS_PER_BANK); | |
479 | ||
480 | raw_spin_lock(&chip_data->rlock); | |
481 | ||
482 | if (on) | |
483 | chip_data->wake_active |= mask; | |
484 | else | |
485 | chip_data->wake_active &= ~mask; | |
486 | ||
487 | raw_spin_unlock(&chip_data->rlock); | |
488 | ||
489 | return 0; | |
490 | } | |
491 | ||
492 | static int stm32_exti_h_set_affinity(struct irq_data *d, | |
493 | const struct cpumask *dest, bool force) | |
494 | { | |
495 | if (d->parent_data->chip) | |
496 | return irq_chip_set_affinity_parent(d, dest, force); | |
497 | ||
498 | return -EINVAL; | |
499 | } | |
500 | ||
501 | static struct irq_chip stm32_exti_h_chip = { | |
502 | .name = "stm32-exti-h", | |
503 | .irq_eoi = stm32_exti_h_eoi, | |
504 | .irq_mask = stm32_exti_h_mask, | |
505 | .irq_unmask = stm32_exti_h_unmask, | |
506 | .irq_retrigger = irq_chip_retrigger_hierarchy, | |
507 | .irq_set_type = stm32_exti_h_set_type, | |
508 | .irq_set_wake = stm32_exti_h_set_wake, | |
509 | .flags = IRQCHIP_MASK_ON_SUSPEND, | |
510 | #ifdef CONFIG_SMP | |
511 | .irq_set_affinity = stm32_exti_h_set_affinity, | |
512 | #endif | |
513 | }; | |
514 | ||
515 | static int stm32_exti_h_domain_alloc(struct irq_domain *dm, | |
516 | unsigned int virq, | |
517 | unsigned int nr_irqs, void *data) | |
518 | { | |
519 | struct stm32_exti_host_data *host_data = dm->host_data; | |
520 | struct stm32_exti_chip_data *chip_data; | |
521 | struct irq_fwspec *fwspec = data; | |
522 | struct irq_fwspec p_fwspec; | |
523 | irq_hw_number_t hwirq; | |
524 | int p_irq, bank; | |
525 | ||
526 | hwirq = fwspec->param[0]; | |
527 | bank = hwirq / IRQS_PER_BANK; | |
528 | chip_data = &host_data->chips_data[bank]; | |
529 | ||
530 | irq_domain_set_hwirq_and_chip(dm, virq, hwirq, | |
531 | &stm32_exti_h_chip, chip_data); | |
532 | ||
533 | p_irq = stm32_exti_to_irq(host_data->drv_data, hwirq); | |
534 | if (p_irq >= 0) { | |
535 | p_fwspec.fwnode = dm->parent->fwnode; | |
536 | p_fwspec.param_count = 3; | |
537 | p_fwspec.param[0] = GIC_SPI; | |
538 | p_fwspec.param[1] = p_irq; | |
539 | p_fwspec.param[2] = IRQ_TYPE_LEVEL_HIGH; | |
540 | ||
541 | return irq_domain_alloc_irqs_parent(dm, virq, 1, &p_fwspec); | |
542 | } | |
543 | ||
544 | return 0; | |
545 | } | |
546 | ||
f9fc1745 LB |
547 | static struct |
548 | stm32_exti_host_data *stm32_exti_host_init(const struct stm32_exti_drv_data *dd, | |
549 | struct device_node *node) | |
550 | { | |
551 | struct stm32_exti_host_data *host_data; | |
552 | ||
553 | host_data = kzalloc(sizeof(*host_data), GFP_KERNEL); | |
554 | if (!host_data) | |
555 | return NULL; | |
556 | ||
557 | host_data->drv_data = dd; | |
558 | host_data->chips_data = kcalloc(dd->bank_nr, | |
559 | sizeof(struct stm32_exti_chip_data), | |
560 | GFP_KERNEL); | |
561 | if (!host_data->chips_data) | |
562 | return NULL; | |
563 | ||
564 | host_data->base = of_iomap(node, 0); | |
565 | if (!host_data->base) { | |
566 | pr_err("%pOF: Unable to map registers\n", node); | |
567 | return NULL; | |
568 | } | |
be6230f0 | 569 | |
f9fc1745 LB |
570 | return host_data; |
571 | } | |
572 | ||
573 | static struct | |
574 | stm32_exti_chip_data *stm32_exti_chip_init(struct stm32_exti_host_data *h_data, | |
575 | u32 bank_idx, | |
576 | struct device_node *node) | |
577 | { | |
578 | const struct stm32_exti_bank *stm32_bank; | |
579 | struct stm32_exti_chip_data *chip_data; | |
580 | void __iomem *base = h_data->base; | |
581 | u32 irqs_mask; | |
582 | ||
583 | stm32_bank = h_data->drv_data->exti_banks[bank_idx]; | |
584 | chip_data = &h_data->chips_data[bank_idx]; | |
585 | chip_data->host_data = h_data; | |
586 | chip_data->reg_bank = stm32_bank; | |
587 | ||
927abfc4 LB |
588 | raw_spin_lock_init(&chip_data->rlock); |
589 | ||
f9fc1745 LB |
590 | /* Determine number of irqs supported */ |
591 | writel_relaxed(~0UL, base + stm32_bank->rtsr_ofst); | |
592 | irqs_mask = readl_relaxed(base + stm32_bank->rtsr_ofst); | |
593 | ||
594 | /* | |
595 | * This IP has no reset, so after hot reboot we should | |
596 | * clear registers to avoid residue | |
597 | */ | |
598 | writel_relaxed(0, base + stm32_bank->imr_ofst); | |
599 | writel_relaxed(0, base + stm32_bank->emr_ofst); | |
600 | writel_relaxed(0, base + stm32_bank->rtsr_ofst); | |
601 | writel_relaxed(0, base + stm32_bank->ftsr_ofst); | |
602 | writel_relaxed(~0UL, base + stm32_bank->rpr_ofst); | |
603 | if (stm32_bank->fpr_ofst != UNDEF_REG) | |
604 | writel_relaxed(~0UL, base + stm32_bank->fpr_ofst); | |
605 | ||
606 | pr_info("%s: bank%d, External IRQs available:%#x\n", | |
607 | node->full_name, bank_idx, irqs_mask); | |
608 | ||
609 | return chip_data; | |
610 | } | |
611 | ||
612 | static int __init stm32_exti_init(const struct stm32_exti_drv_data *drv_data, | |
613 | struct device_node *node) | |
e0720416 | 614 | { |
f9fc1745 | 615 | struct stm32_exti_host_data *host_data; |
e0720416 | 616 | unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN; |
f9fc1745 | 617 | int nr_irqs, ret, i; |
e0720416 AT |
618 | struct irq_chip_generic *gc; |
619 | struct irq_domain *domain; | |
e0720416 | 620 | |
f9fc1745 LB |
621 | host_data = stm32_exti_host_init(drv_data, node); |
622 | if (!host_data) { | |
623 | ret = -ENOMEM; | |
624 | goto out_free_mem; | |
e0720416 AT |
625 | } |
626 | ||
f9fc1745 | 627 | domain = irq_domain_add_linear(node, drv_data->bank_nr * IRQS_PER_BANK, |
e0720416 AT |
628 | &irq_exti_domain_ops, NULL); |
629 | if (!domain) { | |
630 | pr_err("%s: Could not register interrupt domain.\n", | |
6dd64ee1 | 631 | node->name); |
e0720416 AT |
632 | ret = -ENOMEM; |
633 | goto out_unmap; | |
634 | } | |
635 | ||
6dd64ee1 | 636 | ret = irq_alloc_domain_generic_chips(domain, IRQS_PER_BANK, 1, "exti", |
e0720416 AT |
637 | handle_edge_irq, clr, 0, 0); |
638 | if (ret) { | |
e81f54c6 | 639 | pr_err("%pOF: Could not allocate generic interrupt chip.\n", |
ea80aa2a | 640 | node); |
e0720416 AT |
641 | goto out_free_domain; |
642 | } | |
643 | ||
f9fc1745 LB |
644 | for (i = 0; i < drv_data->bank_nr; i++) { |
645 | const struct stm32_exti_bank *stm32_bank; | |
646 | struct stm32_exti_chip_data *chip_data; | |
6dd64ee1 | 647 | |
f9fc1745 LB |
648 | stm32_bank = drv_data->exti_banks[i]; |
649 | chip_data = stm32_exti_chip_init(host_data, i, node); | |
d9e2b19b | 650 | |
6dd64ee1 LB |
651 | gc = irq_get_domain_generic_chip(domain, i * IRQS_PER_BANK); |
652 | ||
f9fc1745 | 653 | gc->reg_base = host_data->base; |
6dd64ee1 | 654 | gc->chip_types->type = IRQ_TYPE_EDGE_BOTH; |
be6230f0 | 655 | gc->chip_types->chip.irq_ack = stm32_irq_ack; |
6dd64ee1 LB |
656 | gc->chip_types->chip.irq_mask = irq_gc_mask_clr_bit; |
657 | gc->chip_types->chip.irq_unmask = irq_gc_mask_set_bit; | |
658 | gc->chip_types->chip.irq_set_type = stm32_irq_set_type; | |
d9e2b19b LB |
659 | gc->chip_types->chip.irq_set_wake = irq_gc_set_wake; |
660 | gc->suspend = stm32_irq_suspend; | |
661 | gc->resume = stm32_irq_resume; | |
662 | gc->wake_enabled = IRQ_MSK(IRQS_PER_BANK); | |
663 | ||
6dd64ee1 | 664 | gc->chip_types->regs.mask = stm32_bank->imr_ofst; |
d9e2b19b | 665 | gc->private = (void *)chip_data; |
6dd64ee1 | 666 | } |
e0720416 AT |
667 | |
668 | nr_irqs = of_irq_count(node); | |
669 | for (i = 0; i < nr_irqs; i++) { | |
670 | unsigned int irq = irq_of_parse_and_map(node, i); | |
671 | ||
672 | irq_set_handler_data(irq, domain); | |
673 | irq_set_chained_handler(irq, stm32_irq_handler); | |
674 | } | |
675 | ||
676 | return 0; | |
677 | ||
678 | out_free_domain: | |
679 | irq_domain_remove(domain); | |
680 | out_unmap: | |
f9fc1745 LB |
681 | iounmap(host_data->base); |
682 | out_free_mem: | |
683 | kfree(host_data->chips_data); | |
684 | kfree(host_data); | |
e0720416 AT |
685 | return ret; |
686 | } | |
687 | ||
927abfc4 LB |
688 | static const struct irq_domain_ops stm32_exti_h_domain_ops = { |
689 | .alloc = stm32_exti_h_domain_alloc, | |
690 | .free = irq_domain_free_irqs_common, | |
691 | }; | |
692 | ||
693 | static int | |
694 | __init stm32_exti_hierarchy_init(const struct stm32_exti_drv_data *drv_data, | |
695 | struct device_node *node, | |
696 | struct device_node *parent) | |
697 | { | |
698 | struct irq_domain *parent_domain, *domain; | |
699 | struct stm32_exti_host_data *host_data; | |
700 | int ret, i; | |
701 | ||
702 | parent_domain = irq_find_host(parent); | |
703 | if (!parent_domain) { | |
704 | pr_err("interrupt-parent not found\n"); | |
705 | return -EINVAL; | |
706 | } | |
707 | ||
708 | host_data = stm32_exti_host_init(drv_data, node); | |
709 | if (!host_data) { | |
710 | ret = -ENOMEM; | |
711 | goto out_free_mem; | |
712 | } | |
713 | ||
714 | for (i = 0; i < drv_data->bank_nr; i++) | |
715 | stm32_exti_chip_init(host_data, i, node); | |
716 | ||
717 | domain = irq_domain_add_hierarchy(parent_domain, 0, | |
718 | drv_data->bank_nr * IRQS_PER_BANK, | |
719 | node, &stm32_exti_h_domain_ops, | |
720 | host_data); | |
721 | ||
722 | if (!domain) { | |
723 | pr_err("%s: Could not register exti domain.\n", node->name); | |
724 | ret = -ENOMEM; | |
725 | goto out_unmap; | |
726 | } | |
727 | ||
728 | return 0; | |
729 | ||
730 | out_unmap: | |
731 | iounmap(host_data->base); | |
732 | out_free_mem: | |
733 | kfree(host_data->chips_data); | |
734 | kfree(host_data); | |
735 | return ret; | |
736 | } | |
737 | ||
6dd64ee1 LB |
738 | static int __init stm32f4_exti_of_init(struct device_node *np, |
739 | struct device_node *parent) | |
740 | { | |
f9fc1745 | 741 | return stm32_exti_init(&stm32f4xx_drv_data, np); |
6dd64ee1 LB |
742 | } |
743 | ||
744 | IRQCHIP_DECLARE(stm32f4_exti, "st,stm32-exti", stm32f4_exti_of_init); | |
539c603e LB |
745 | |
746 | static int __init stm32h7_exti_of_init(struct device_node *np, | |
747 | struct device_node *parent) | |
748 | { | |
f9fc1745 | 749 | return stm32_exti_init(&stm32h7xx_drv_data, np); |
539c603e LB |
750 | } |
751 | ||
752 | IRQCHIP_DECLARE(stm32h7_exti, "st,stm32h7-exti", stm32h7_exti_of_init); | |
927abfc4 LB |
753 | |
754 | static int __init stm32mp1_exti_of_init(struct device_node *np, | |
755 | struct device_node *parent) | |
756 | { | |
757 | return stm32_exti_hierarchy_init(&stm32mp1_drv_data, np, parent); | |
758 | } | |
759 | ||
760 | IRQCHIP_DECLARE(stm32mp1_exti, "st,stm32mp1-exti", stm32mp1_exti_of_init); |